dw-mipi-dsi.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   4 * Copyright (C) STMicroelectronics SA 2017
   5 *
   6 * Modified by Philippe Cornu <philippe.cornu@st.com>
   7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the
   8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
   9 */
  10
  11#include <linux/clk.h>
  12#include <linux/component.h>
  13#include <linux/debugfs.h>
  14#include <linux/export.h>
  15#include <linux/iopoll.h>
  16#include <linux/math64.h>
  17#include <linux/media-bus-format.h>
  18#include <linux/module.h>
  19#include <linux/platform_device.h>
  20#include <linux/pm_runtime.h>
  21#include <linux/reset.h>
  22
  23#include <video/mipi_display.h>
  24
  25#include <drm/bridge/dw_mipi_dsi.h>
  26#include <drm/drm_atomic_helper.h>
  27#include <drm/drm_bridge.h>
  28#include <drm/drm_connector.h>
  29#include <drm/drm_crtc.h>
  30#include <drm/drm_mipi_dsi.h>
  31#include <drm/drm_modes.h>
  32#include <drm/drm_of.h>
  33#include <drm/drm_print.h>
  34
  35#define HWVER_131			0x31333100	/* IP version 1.31 */
  36
  37#define DSI_VERSION			0x00
  38#define VERSION				GENMASK(31, 8)
  39
  40#define DSI_PWR_UP			0x04
  41#define RESET				0
  42#define POWERUP				BIT(0)
  43
  44#define DSI_CLKMGR_CFG			0x08
  45#define TO_CLK_DIVISION(div)		(((div) & 0xff) << 8)
  46#define TX_ESC_CLK_DIVISION(div)	((div) & 0xff)
  47
  48#define DSI_DPI_VCID			0x0c
  49#define DPI_VCID(vcid)			((vcid) & 0x3)
  50
  51#define DSI_DPI_COLOR_CODING		0x10
  52#define LOOSELY18_EN			BIT(8)
  53#define DPI_COLOR_CODING_16BIT_1	0x0
  54#define DPI_COLOR_CODING_16BIT_2	0x1
  55#define DPI_COLOR_CODING_16BIT_3	0x2
  56#define DPI_COLOR_CODING_18BIT_1	0x3
  57#define DPI_COLOR_CODING_18BIT_2	0x4
  58#define DPI_COLOR_CODING_24BIT		0x5
  59
  60#define DSI_DPI_CFG_POL			0x14
  61#define COLORM_ACTIVE_LOW		BIT(4)
  62#define SHUTD_ACTIVE_LOW		BIT(3)
  63#define HSYNC_ACTIVE_LOW		BIT(2)
  64#define VSYNC_ACTIVE_LOW		BIT(1)
  65#define DATAEN_ACTIVE_LOW		BIT(0)
  66
  67#define DSI_DPI_LP_CMD_TIM		0x18
  68#define OUTVACT_LPCMD_TIME(p)		(((p) & 0xff) << 16)
  69#define INVACT_LPCMD_TIME(p)		((p) & 0xff)
  70
  71#define DSI_DBI_VCID			0x1c
  72#define DSI_DBI_CFG			0x20
  73#define DSI_DBI_PARTITIONING_EN		0x24
  74#define DSI_DBI_CMDSIZE			0x28
  75
  76#define DSI_PCKHDL_CFG			0x2c
  77#define CRC_RX_EN			BIT(4)
  78#define ECC_RX_EN			BIT(3)
  79#define BTA_EN				BIT(2)
  80#define EOTP_RX_EN			BIT(1)
  81#define EOTP_TX_EN			BIT(0)
  82
  83#define DSI_GEN_VCID			0x30
  84
  85#define DSI_MODE_CFG			0x34
  86#define ENABLE_VIDEO_MODE		0
  87#define ENABLE_CMD_MODE			BIT(0)
  88
  89#define DSI_VID_MODE_CFG		0x38
  90#define ENABLE_LOW_POWER		(0x3f << 8)
  91#define ENABLE_LOW_POWER_MASK		(0x3f << 8)
  92#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES	0x0
  93#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS	0x1
  94#define VID_MODE_TYPE_BURST			0x2
  95#define VID_MODE_TYPE_MASK			0x3
  96#define ENABLE_LOW_POWER_CMD		BIT(15)
  97#define VID_MODE_VPG_ENABLE		BIT(16)
  98#define VID_MODE_VPG_MODE		BIT(20)
  99#define VID_MODE_VPG_HORIZONTAL		BIT(24)
 100
 101#define DSI_VID_PKT_SIZE		0x3c
 102#define VID_PKT_SIZE(p)			((p) & 0x3fff)
 103
 104#define DSI_VID_NUM_CHUNKS		0x40
 105#define VID_NUM_CHUNKS(c)		((c) & 0x1fff)
 106
 107#define DSI_VID_NULL_SIZE		0x44
 108#define VID_NULL_SIZE(b)		((b) & 0x1fff)
 109
 110#define DSI_VID_HSA_TIME		0x48
 111#define DSI_VID_HBP_TIME		0x4c
 112#define DSI_VID_HLINE_TIME		0x50
 113#define DSI_VID_VSA_LINES		0x54
 114#define DSI_VID_VBP_LINES		0x58
 115#define DSI_VID_VFP_LINES		0x5c
 116#define DSI_VID_VACTIVE_LINES		0x60
 117#define DSI_EDPI_CMD_SIZE		0x64
 118
 119#define DSI_CMD_MODE_CFG		0x68
 120#define MAX_RD_PKT_SIZE_LP		BIT(24)
 121#define DCS_LW_TX_LP			BIT(19)
 122#define DCS_SR_0P_TX_LP			BIT(18)
 123#define DCS_SW_1P_TX_LP			BIT(17)
 124#define DCS_SW_0P_TX_LP			BIT(16)
 125#define GEN_LW_TX_LP			BIT(14)
 126#define GEN_SR_2P_TX_LP			BIT(13)
 127#define GEN_SR_1P_TX_LP			BIT(12)
 128#define GEN_SR_0P_TX_LP			BIT(11)
 129#define GEN_SW_2P_TX_LP			BIT(10)
 130#define GEN_SW_1P_TX_LP			BIT(9)
 131#define GEN_SW_0P_TX_LP			BIT(8)
 132#define ACK_RQST_EN			BIT(1)
 133#define TEAR_FX_EN			BIT(0)
 134
 135#define CMD_MODE_ALL_LP			(MAX_RD_PKT_SIZE_LP | \
 136					 DCS_LW_TX_LP | \
 137					 DCS_SR_0P_TX_LP | \
 138					 DCS_SW_1P_TX_LP | \
 139					 DCS_SW_0P_TX_LP | \
 140					 GEN_LW_TX_LP | \
 141					 GEN_SR_2P_TX_LP | \
 142					 GEN_SR_1P_TX_LP | \
 143					 GEN_SR_0P_TX_LP | \
 144					 GEN_SW_2P_TX_LP | \
 145					 GEN_SW_1P_TX_LP | \
 146					 GEN_SW_0P_TX_LP)
 147
 148#define DSI_GEN_HDR			0x6c
 149#define DSI_GEN_PLD_DATA		0x70
 150
 151#define DSI_CMD_PKT_STATUS		0x74
 152#define GEN_RD_CMD_BUSY			BIT(6)
 153#define GEN_PLD_R_FULL			BIT(5)
 154#define GEN_PLD_R_EMPTY			BIT(4)
 155#define GEN_PLD_W_FULL			BIT(3)
 156#define GEN_PLD_W_EMPTY			BIT(2)
 157#define GEN_CMD_FULL			BIT(1)
 158#define GEN_CMD_EMPTY			BIT(0)
 159
 160#define DSI_TO_CNT_CFG			0x78
 161#define HSTX_TO_CNT(p)			(((p) & 0xffff) << 16)
 162#define LPRX_TO_CNT(p)			((p) & 0xffff)
 163
 164#define DSI_HS_RD_TO_CNT		0x7c
 165#define DSI_LP_RD_TO_CNT		0x80
 166#define DSI_HS_WR_TO_CNT		0x84
 167#define DSI_LP_WR_TO_CNT		0x88
 168#define DSI_BTA_TO_CNT			0x8c
 169
 170#define DSI_LPCLK_CTRL			0x94
 171#define AUTO_CLKLANE_CTRL		BIT(1)
 172#define PHY_TXREQUESTCLKHS		BIT(0)
 173
 174#define DSI_PHY_TMR_LPCLK_CFG		0x98
 175#define PHY_CLKHS2LP_TIME(lbcc)		(((lbcc) & 0x3ff) << 16)
 176#define PHY_CLKLP2HS_TIME(lbcc)		((lbcc) & 0x3ff)
 177
 178#define DSI_PHY_TMR_CFG			0x9c
 179#define PHY_HS2LP_TIME(lbcc)		(((lbcc) & 0xff) << 24)
 180#define PHY_LP2HS_TIME(lbcc)		(((lbcc) & 0xff) << 16)
 181#define MAX_RD_TIME(lbcc)		((lbcc) & 0x7fff)
 182#define PHY_HS2LP_TIME_V131(lbcc)	(((lbcc) & 0x3ff) << 16)
 183#define PHY_LP2HS_TIME_V131(lbcc)	((lbcc) & 0x3ff)
 184
 185#define DSI_PHY_RSTZ			0xa0
 186#define PHY_DISFORCEPLL			0
 187#define PHY_ENFORCEPLL			BIT(3)
 188#define PHY_DISABLECLK			0
 189#define PHY_ENABLECLK			BIT(2)
 190#define PHY_RSTZ			0
 191#define PHY_UNRSTZ			BIT(1)
 192#define PHY_SHUTDOWNZ			0
 193#define PHY_UNSHUTDOWNZ			BIT(0)
 194
 195#define DSI_PHY_IF_CFG			0xa4
 196#define PHY_STOP_WAIT_TIME(cycle)	(((cycle) & 0xff) << 8)
 197#define N_LANES(n)			(((n) - 1) & 0x3)
 198
 199#define DSI_PHY_ULPS_CTRL		0xa8
 200#define DSI_PHY_TX_TRIGGERS		0xac
 201
 202#define DSI_PHY_STATUS			0xb0
 203#define PHY_STOP_STATE_CLK_LANE		BIT(2)
 204#define PHY_LOCK			BIT(0)
 205
 206#define DSI_PHY_TST_CTRL0		0xb4
 207#define PHY_TESTCLK			BIT(1)
 208#define PHY_UNTESTCLK			0
 209#define PHY_TESTCLR			BIT(0)
 210#define PHY_UNTESTCLR			0
 211
 212#define DSI_PHY_TST_CTRL1		0xb8
 213#define PHY_TESTEN			BIT(16)
 214#define PHY_UNTESTEN			0
 215#define PHY_TESTDOUT(n)			(((n) & 0xff) << 8)
 216#define PHY_TESTDIN(n)			((n) & 0xff)
 217
 218#define DSI_INT_ST0			0xbc
 219#define DSI_INT_ST1			0xc0
 220#define DSI_INT_MSK0			0xc4
 221#define DSI_INT_MSK1			0xc8
 222
 223#define DSI_PHY_TMR_RD_CFG		0xf4
 224#define MAX_RD_TIME_V131(lbcc)		((lbcc) & 0x7fff)
 225
 226#define PHY_STATUS_TIMEOUT_US		10000
 227#define CMD_PKT_STATUS_TIMEOUT_US	20000
 228
 229#ifdef CONFIG_DEBUG_FS
 230#define VPG_DEFS(name, dsi) \
 231	((void __force *)&((*dsi).vpg_defs.name))
 232
 233#define REGISTER(name, mask, dsi) \
 234	{ #name, VPG_DEFS(name, dsi), mask, dsi }
 235
 236struct debugfs_entries {
 237	const char				*name;
 238	bool					*reg;
 239	u32					mask;
 240	struct dw_mipi_dsi			*dsi;
 241};
 242#endif /* CONFIG_DEBUG_FS */
 243
 244struct dw_mipi_dsi {
 245	struct drm_bridge bridge;
 246	struct mipi_dsi_host dsi_host;
 247	struct drm_bridge *panel_bridge;
 248	struct device *dev;
 249	void __iomem *base;
 250
 251	struct clk *pclk;
 252
 253	unsigned int lane_mbps; /* per lane */
 254	u32 channel;
 255	u32 lanes;
 256	u32 format;
 257	unsigned long mode_flags;
 258
 259#ifdef CONFIG_DEBUG_FS
 260	struct dentry *debugfs;
 261	struct debugfs_entries *debugfs_vpg;
 262	struct {
 263		bool vpg;
 264		bool vpg_horizontal;
 265		bool vpg_ber_pattern;
 266	} vpg_defs;
 267#endif /* CONFIG_DEBUG_FS */
 268
 269	struct dw_mipi_dsi *master; /* dual-dsi master ptr */
 270	struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */
 271
 272	struct drm_display_mode mode;
 273	const struct dw_mipi_dsi_plat_data *plat_data;
 274};
 275
 276/*
 277 * Check if either a link to a master or slave is present
 278 */
 279static inline bool dw_mipi_is_dual_mode(struct dw_mipi_dsi *dsi)
 280{
 281	return dsi->slave || dsi->master;
 282}
 283
 284/*
 285 * The controller should generate 2 frames before
 286 * preparing the peripheral.
 287 */
 288static void dw_mipi_dsi_wait_for_two_frames(const struct drm_display_mode *mode)
 289{
 290	int refresh, two_frames;
 291
 292	refresh = drm_mode_vrefresh(mode);
 293	two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
 294	msleep(two_frames);
 295}
 296
 297static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 298{
 299	return container_of(host, struct dw_mipi_dsi, dsi_host);
 300}
 301
 302static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge)
 303{
 304	return container_of(bridge, struct dw_mipi_dsi, bridge);
 305}
 306
 307static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 308{
 309	writel(val, dsi->base + reg);
 310}
 311
 312static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 313{
 314	return readl(dsi->base + reg);
 315}
 316
 317static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 318				   struct mipi_dsi_device *device)
 319{
 320	struct dw_mipi_dsi *dsi = host_to_dsi(host);
 321	const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
 322	struct drm_bridge *bridge;
 323	int ret;
 324
 325	if (device->lanes > dsi->plat_data->max_data_lanes) {
 326		dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
 327			device->lanes);
 328		return -EINVAL;
 329	}
 330
 331	dsi->lanes = device->lanes;
 332	dsi->channel = device->channel;
 333	dsi->format = device->format;
 334	dsi->mode_flags = device->mode_flags;
 335
 336	bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node, 1, 0);
 337	if (IS_ERR(bridge))
 338		return PTR_ERR(bridge);
 339
 340	bridge->pre_enable_prev_first = true;
 341	dsi->panel_bridge = bridge;
 342
 343	drm_bridge_add(&dsi->bridge);
 344
 345	if (pdata->host_ops && pdata->host_ops->attach) {
 346		ret = pdata->host_ops->attach(pdata->priv_data, device);
 347		if (ret < 0)
 348			return ret;
 349	}
 350
 351	return 0;
 352}
 353
 354static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 355				   struct mipi_dsi_device *device)
 356{
 357	struct dw_mipi_dsi *dsi = host_to_dsi(host);
 358	const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
 359	int ret;
 360
 361	if (pdata->host_ops && pdata->host_ops->detach) {
 362		ret = pdata->host_ops->detach(pdata->priv_data, device);
 363		if (ret < 0)
 364			return ret;
 365	}
 366
 367	drm_of_panel_bridge_remove(host->dev->of_node, 1, 0);
 368
 369	drm_bridge_remove(&dsi->bridge);
 370
 371	return 0;
 372}
 373
 374static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
 375				   const struct mipi_dsi_msg *msg)
 376{
 377	bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
 378	u32 val = 0;
 379
 380	/*
 381	 * TODO dw drv improvements
 382	 * largest packet sizes during hfp or during vsa/vpb/vfp
 383	 * should be computed according to byte lane, lane number and only
 384	 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
 385	 */
 386	dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(16)
 387		  | INVACT_LPCMD_TIME(4));
 388
 389	if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
 390		val |= ACK_RQST_EN;
 391	if (lpm)
 392		val |= CMD_MODE_ALL_LP;
 393
 394	dsi_write(dsi, DSI_CMD_MODE_CFG, val);
 395
 396	val = dsi_read(dsi, DSI_VID_MODE_CFG);
 397	if (lpm)
 398		val |= ENABLE_LOW_POWER_CMD;
 399	else
 400		val &= ~ENABLE_LOW_POWER_CMD;
 401	dsi_write(dsi, DSI_VID_MODE_CFG, val);
 402}
 403
 404static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
 405{
 406	int ret;
 407	u32 val, mask;
 408
 409	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 410				 val, !(val & GEN_CMD_FULL), 1000,
 411				 CMD_PKT_STATUS_TIMEOUT_US);
 412	if (ret) {
 413		dev_err(dsi->dev, "failed to get available command FIFO\n");
 414		return ret;
 415	}
 416
 417	dsi_write(dsi, DSI_GEN_HDR, hdr_val);
 418
 419	mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
 420	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 421				 val, (val & mask) == mask,
 422				 1000, CMD_PKT_STATUS_TIMEOUT_US);
 423	if (ret) {
 424		dev_err(dsi->dev, "failed to write command FIFO\n");
 425		return ret;
 426	}
 427
 428	return 0;
 429}
 430
 431static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
 432			     const struct mipi_dsi_packet *packet)
 433{
 434	const u8 *tx_buf = packet->payload;
 435	int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
 436	__le32 word;
 437	u32 val;
 438
 439	while (len) {
 440		if (len < pld_data_bytes) {
 441			word = 0;
 442			memcpy(&word, tx_buf, len);
 443			dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
 444			len = 0;
 445		} else {
 446			memcpy(&word, tx_buf, pld_data_bytes);
 447			dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
 448			tx_buf += pld_data_bytes;
 449			len -= pld_data_bytes;
 450		}
 451
 452		ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 453					 val, !(val & GEN_PLD_W_FULL), 1000,
 454					 CMD_PKT_STATUS_TIMEOUT_US);
 455		if (ret) {
 456			dev_err(dsi->dev,
 457				"failed to get available write payload FIFO\n");
 458			return ret;
 459		}
 460	}
 461
 462	word = 0;
 463	memcpy(&word, packet->header, sizeof(packet->header));
 464	return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
 465}
 466
 467static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
 468			    const struct mipi_dsi_msg *msg)
 469{
 470	int i, j, ret, len = msg->rx_len;
 471	u8 *buf = msg->rx_buf;
 472	u32 val;
 473
 474	/* Wait end of the read operation */
 475	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 476				 val, !(val & GEN_RD_CMD_BUSY),
 477				 1000, CMD_PKT_STATUS_TIMEOUT_US);
 478	if (ret) {
 479		dev_err(dsi->dev, "Timeout during read operation\n");
 480		return ret;
 481	}
 482
 483	for (i = 0; i < len; i += 4) {
 484		/* Read fifo must not be empty before all bytes are read */
 485		ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 486					 val, !(val & GEN_PLD_R_EMPTY),
 487					 1000, CMD_PKT_STATUS_TIMEOUT_US);
 488		if (ret) {
 489			dev_err(dsi->dev, "Read payload FIFO is empty\n");
 490			return ret;
 491		}
 492
 493		val = dsi_read(dsi, DSI_GEN_PLD_DATA);
 494		for (j = 0; j < 4 && j + i < len; j++)
 495			buf[i + j] = val >> (8 * j);
 496	}
 497
 498	return ret;
 499}
 500
 501static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 502					 const struct mipi_dsi_msg *msg)
 503{
 504	struct dw_mipi_dsi *dsi = host_to_dsi(host);
 505	struct mipi_dsi_packet packet;
 506	int ret, nb_bytes;
 507
 508	ret = mipi_dsi_create_packet(&packet, msg);
 509	if (ret) {
 510		dev_err(dsi->dev, "failed to create packet: %d\n", ret);
 511		return ret;
 512	}
 513
 514	dw_mipi_message_config(dsi, msg);
 515	if (dsi->slave)
 516		dw_mipi_message_config(dsi->slave, msg);
 517
 518	ret = dw_mipi_dsi_write(dsi, &packet);
 519	if (ret)
 520		return ret;
 521	if (dsi->slave) {
 522		ret = dw_mipi_dsi_write(dsi->slave, &packet);
 523		if (ret)
 524			return ret;
 525	}
 526
 527	if (msg->rx_buf && msg->rx_len) {
 528		ret = dw_mipi_dsi_read(dsi, msg);
 529		if (ret)
 530			return ret;
 531		nb_bytes = msg->rx_len;
 532	} else {
 533		nb_bytes = packet.size;
 534	}
 535
 536	return nb_bytes;
 537}
 538
 539static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 540	.attach = dw_mipi_dsi_host_attach,
 541	.detach = dw_mipi_dsi_host_detach,
 542	.transfer = dw_mipi_dsi_host_transfer,
 543};
 544
 545static u32 *
 546dw_mipi_dsi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
 547					     struct drm_bridge_state *bridge_state,
 548					     struct drm_crtc_state *crtc_state,
 549					     struct drm_connector_state *conn_state,
 550					     u32 output_fmt,
 551					     unsigned int *num_input_fmts)
 552{
 553	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
 554	const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
 555	u32 *input_fmts;
 556
 557	if (pdata->get_input_bus_fmts)
 558		return pdata->get_input_bus_fmts(pdata->priv_data,
 559						 bridge, bridge_state,
 560						 crtc_state, conn_state,
 561						 output_fmt, num_input_fmts);
 562
 563	/* Fall back to MEDIA_BUS_FMT_FIXED as the only input format. */
 564	input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
 565	if (!input_fmts)
 566		return NULL;
 567	input_fmts[0] = MEDIA_BUS_FMT_FIXED;
 568	*num_input_fmts = 1;
 569
 570	return input_fmts;
 571}
 572
 573static int dw_mipi_dsi_bridge_atomic_check(struct drm_bridge *bridge,
 574					   struct drm_bridge_state *bridge_state,
 575					   struct drm_crtc_state *crtc_state,
 576					   struct drm_connector_state *conn_state)
 577{
 578	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
 579	const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
 580	bool ret;
 581
 582	bridge_state->input_bus_cfg.flags =
 583		DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE;
 584
 585	if (pdata->mode_fixup) {
 586		ret = pdata->mode_fixup(pdata->priv_data, &crtc_state->mode,
 587					&crtc_state->adjusted_mode);
 588		if (!ret) {
 589			DRM_DEBUG_DRIVER("failed to fixup mode " DRM_MODE_FMT "\n",
 590					 DRM_MODE_ARG(&crtc_state->mode));
 591			return -EINVAL;
 592		}
 593	}
 594
 595	return 0;
 596}
 597
 598static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 599{
 600	u32 val;
 601
 602	/*
 603	 * TODO dw drv improvements
 604	 * enabling low power is panel-dependent, we should use the
 605	 * panel configuration here...
 606	 */
 607	val = ENABLE_LOW_POWER;
 608
 609	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 610		val |= VID_MODE_TYPE_BURST;
 611	else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 612		val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
 613	else
 614		val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
 615
 616#ifdef CONFIG_DEBUG_FS
 617	if (dsi->vpg_defs.vpg) {
 618		val |= VID_MODE_VPG_ENABLE;
 619		val |= dsi->vpg_defs.vpg_horizontal ?
 620		       VID_MODE_VPG_HORIZONTAL : 0;
 621		val |= dsi->vpg_defs.vpg_ber_pattern ? VID_MODE_VPG_MODE : 0;
 622	}
 623#endif /* CONFIG_DEBUG_FS */
 624
 625	dsi_write(dsi, DSI_VID_MODE_CFG, val);
 626}
 627
 628static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 629				 unsigned long mode_flags)
 630{
 631	u32 val;
 632
 633	dsi_write(dsi, DSI_PWR_UP, RESET);
 634
 635	if (mode_flags & MIPI_DSI_MODE_VIDEO) {
 636		dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 637		dw_mipi_dsi_video_mode_config(dsi);
 638	} else {
 639		dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 640	}
 641
 642	val = PHY_TXREQUESTCLKHS;
 643	if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
 644		val |= AUTO_CLKLANE_CTRL;
 645	dsi_write(dsi, DSI_LPCLK_CTRL, val);
 646
 647	dsi_write(dsi, DSI_PWR_UP, POWERUP);
 648}
 649
 650static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
 651{
 652	dsi_write(dsi, DSI_PWR_UP, RESET);
 653	dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
 654}
 655
 656static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 657{
 658	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
 659	unsigned int esc_rate; /* in MHz */
 660	u32 esc_clk_division;
 661	int ret;
 662
 663	/*
 664	 * The maximum permitted escape clock is 20MHz and it is derived from
 665	 * lanebyteclk, which is running at "lane_mbps / 8".
 666	 */
 667	if (phy_ops->get_esc_clk_rate) {
 668		ret = phy_ops->get_esc_clk_rate(dsi->plat_data->priv_data,
 669						&esc_rate);
 670		if (ret)
 671			DRM_DEBUG_DRIVER("Phy get_esc_clk_rate() failed\n");
 672	} else
 673		esc_rate = 20; /* Default to 20MHz */
 674
 675	/*
 676	 * We want :
 677	 *     (lane_mbps >> 3) / esc_clk_division < X
 678	 * which is:
 679	 *     (lane_mbps >> 3) / X > esc_clk_division
 680	 */
 681	esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1;
 682
 683	dsi_write(dsi, DSI_PWR_UP, RESET);
 684
 685	/*
 686	 * TODO dw drv improvements
 687	 * timeout clock division should be computed with the
 688	 * high speed transmission counter timeout and byte lane...
 689	 */
 690	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(0) |
 691		  TX_ESC_CLK_DIVISION(esc_clk_division));
 692}
 693
 694static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 695				   const struct drm_display_mode *mode)
 696{
 697	u32 val = 0, color = 0;
 698
 699	switch (dsi->format) {
 700	case MIPI_DSI_FMT_RGB888:
 701		color = DPI_COLOR_CODING_24BIT;
 702		break;
 703	case MIPI_DSI_FMT_RGB666:
 704		color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
 705		break;
 706	case MIPI_DSI_FMT_RGB666_PACKED:
 707		color = DPI_COLOR_CODING_18BIT_1;
 708		break;
 709	case MIPI_DSI_FMT_RGB565:
 710		color = DPI_COLOR_CODING_16BIT_1;
 711		break;
 712	}
 713
 714	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 715		val |= VSYNC_ACTIVE_LOW;
 716	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 717		val |= HSYNC_ACTIVE_LOW;
 718
 719	dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
 720	dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 721	dsi_write(dsi, DSI_DPI_CFG_POL, val);
 722}
 723
 724static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 725{
 726	u32 val = CRC_RX_EN | ECC_RX_EN | BTA_EN | EOTP_TX_EN;
 727
 728	if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
 729		val &= ~EOTP_TX_EN;
 730
 731	dsi_write(dsi, DSI_PCKHDL_CFG, val);
 732}
 733
 734static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 735					    const struct drm_display_mode *mode)
 736{
 737	/*
 738	 * TODO dw drv improvements
 739	 * only burst mode is supported here. For non-burst video modes,
 740	 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
 741	 * DSI_VNPCR.NPSIZE... especially because this driver supports
 742	 * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
 743	 */
 744
 745	dsi_write(dsi, DSI_VID_PKT_SIZE,
 746		       dw_mipi_is_dual_mode(dsi) ?
 747				VID_PKT_SIZE(mode->hdisplay / 2) :
 748				VID_PKT_SIZE(mode->hdisplay));
 749}
 750
 751static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 752{
 753	/*
 754	 * TODO dw drv improvements
 755	 * compute high speed transmission counter timeout according
 756	 * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
 757	 */
 758	dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(0) | LPRX_TO_CNT(0));
 759	/*
 760	 * TODO dw drv improvements
 761	 * the Bus-Turn-Around Timeout Counter should be computed
 762	 * according to byte lane...
 763	 */
 764	dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 765	dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 766}
 767
 768static const u32 minimum_lbccs[] = {10, 5, 4, 3};
 769
 770static inline u32 dw_mipi_dsi_get_minimum_lbcc(struct dw_mipi_dsi *dsi)
 771{
 772	return minimum_lbccs[dsi->lanes - 1];
 773}
 774
 775/* Get lane byte clock cycles. */
 776static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 777					   const struct drm_display_mode *mode,
 778					   u32 hcomponent)
 779{
 780	u32 frac, lbcc, minimum_lbcc;
 781	int bpp;
 782
 783	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
 784		/* lbcc based on lane_mbps */
 785		lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 786	} else {
 787		/* lbcc based on pixel clock rate */
 788		bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 789		if (bpp < 0) {
 790			dev_err(dsi->dev, "failed to get bpp\n");
 791			return 0;
 792		}
 793
 794		lbcc = div_u64((u64)hcomponent * mode->clock * bpp, dsi->lanes * 8);
 795	}
 796
 797	frac = lbcc % mode->clock;
 798	lbcc = lbcc / mode->clock;
 799	if (frac)
 800		lbcc++;
 801
 802	minimum_lbcc = dw_mipi_dsi_get_minimum_lbcc(dsi);
 803
 804	if (lbcc < minimum_lbcc)
 805		lbcc = minimum_lbcc;
 806
 807	return lbcc;
 808}
 809
 810static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
 811					  const struct drm_display_mode *mode)
 812{
 813	u32 htotal, hsa, hbp, lbcc;
 814
 815	htotal = mode->htotal;
 816	hsa = mode->hsync_end - mode->hsync_start;
 817	hbp = mode->htotal - mode->hsync_end;
 818
 819	/*
 820	 * TODO dw drv improvements
 821	 * computations below may be improved...
 822	 */
 823	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
 824	dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 825
 826	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
 827	dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 828
 829	lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
 830	dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 831}
 832
 833static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
 834					const struct drm_display_mode *mode)
 835{
 836	u32 vactive, vsa, vfp, vbp;
 837
 838	vactive = mode->vdisplay;
 839	vsa = mode->vsync_end - mode->vsync_start;
 840	vfp = mode->vsync_start - mode->vdisplay;
 841	vbp = mode->vtotal - mode->vsync_end;
 842
 843	dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 844	dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 845	dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 846	dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 847}
 848
 849static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 850{
 851	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
 852	struct dw_mipi_dsi_dphy_timing timing;
 853	u32 hw_version;
 854	int ret;
 855
 856	ret = phy_ops->get_timing(dsi->plat_data->priv_data,
 857				  dsi->lane_mbps, &timing);
 858	if (ret)
 859		DRM_DEV_ERROR(dsi->dev, "Retrieving phy timings failed\n");
 860
 861	/*
 862	 * TODO dw drv improvements
 863	 * data & clock lane timers should be computed according to panel
 864	 * blankings and to the automatic clock lane control mode...
 865	 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
 866	 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
 867	 */
 868
 869	hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
 870
 871	if (hw_version >= HWVER_131) {
 872		dsi_write(dsi, DSI_PHY_TMR_CFG,
 873			  PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
 874			  PHY_LP2HS_TIME_V131(timing.data_lp2hs));
 875		dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
 876	} else {
 877		dsi_write(dsi, DSI_PHY_TMR_CFG,
 878			  PHY_HS2LP_TIME(timing.data_hs2lp) |
 879			  PHY_LP2HS_TIME(timing.data_lp2hs) |
 880			  MAX_RD_TIME(10000));
 881	}
 882
 883	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG,
 884		  PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
 885		  PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
 886}
 887
 888static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 889{
 890	/*
 891	 * TODO dw drv improvements
 892	 * stop wait time should be the maximum between host dsi
 893	 * and panel stop wait times
 894	 */
 895	dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 896		  N_LANES(dsi->lanes));
 897}
 898
 899static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
 900{
 901	/* Clear PHY state */
 902	dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 903		  | PHY_RSTZ | PHY_SHUTDOWNZ);
 904	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
 905	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
 906	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
 907}
 908
 909static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
 910{
 911	u32 val;
 912	int ret;
 913
 914	dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 915		  PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 916
 917	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
 918				 val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 919	if (ret)
 920		DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
 921
 922	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
 923				 val, val & PHY_STOP_STATE_CLK_LANE, 1000,
 924				 PHY_STATUS_TIMEOUT_US);
 925	if (ret)
 926		DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
 927}
 928
 929static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 930{
 931	dsi_read(dsi, DSI_INT_ST0);
 932	dsi_read(dsi, DSI_INT_ST1);
 933	dsi_write(dsi, DSI_INT_MSK0, 0);
 934	dsi_write(dsi, DSI_INT_MSK1, 0);
 935}
 936
 937static void dw_mipi_dsi_bridge_post_atomic_disable(struct drm_bridge *bridge,
 938						   struct drm_atomic_state *state)
 939{
 940	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
 941	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
 942
 943	/*
 944	 * Switch to command mode before panel-bridge post_disable &
 945	 * panel unprepare.
 946	 * Note: panel-bridge disable & panel disable has been called
 947	 * before by the drm framework.
 948	 */
 949	dw_mipi_dsi_set_mode(dsi, 0);
 950
 951	if (phy_ops->power_off)
 952		phy_ops->power_off(dsi->plat_data->priv_data);
 953
 954	if (dsi->slave) {
 955		dw_mipi_dsi_disable(dsi->slave);
 956		clk_disable_unprepare(dsi->slave->pclk);
 957		pm_runtime_put(dsi->slave->dev);
 958	}
 959	dw_mipi_dsi_disable(dsi);
 960
 961	clk_disable_unprepare(dsi->pclk);
 962	pm_runtime_put(dsi->dev);
 963}
 964
 965static unsigned int dw_mipi_dsi_get_lanes(struct dw_mipi_dsi *dsi)
 966{
 967	/* this instance is the slave, so add the master's lanes */
 968	if (dsi->master)
 969		return dsi->master->lanes + dsi->lanes;
 970
 971	/* this instance is the master, so add the slave's lanes */
 972	if (dsi->slave)
 973		return dsi->lanes + dsi->slave->lanes;
 974
 975	/* single-dsi, so no other instance to consider */
 976	return dsi->lanes;
 977}
 978
 979static void dw_mipi_dsi_mode_set(struct dw_mipi_dsi *dsi,
 980				 const struct drm_display_mode *adjusted_mode)
 981{
 982	const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
 983	void *priv_data = dsi->plat_data->priv_data;
 984	int ret;
 985	u32 lanes = dw_mipi_dsi_get_lanes(dsi);
 986
 987	clk_prepare_enable(dsi->pclk);
 988
 989	ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi->mode_flags,
 990				     lanes, dsi->format, &dsi->lane_mbps);
 991	if (ret)
 992		DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
 993
 994	pm_runtime_get_sync(dsi->dev);
 995	dw_mipi_dsi_init(dsi);
 996	dw_mipi_dsi_dpi_config(dsi, adjusted_mode);
 997	dw_mipi_dsi_packet_handler_config(dsi);
 998	dw_mipi_dsi_video_mode_config(dsi);
 999	dw_mipi_dsi_video_packet_config(dsi, adjusted_mode);
1000	dw_mipi_dsi_command_mode_config(dsi);
1001	dw_mipi_dsi_line_timer_config(dsi, adjusted_mode);
1002	dw_mipi_dsi_vertical_timing_config(dsi, adjusted_mode);
1003
1004	dw_mipi_dsi_dphy_init(dsi);
1005	dw_mipi_dsi_dphy_timing_config(dsi);
1006	dw_mipi_dsi_dphy_interface_config(dsi);
1007
1008	dw_mipi_dsi_clear_err(dsi);
1009
1010	ret = phy_ops->init(priv_data);
1011	if (ret)
1012		DRM_DEBUG_DRIVER("Phy init() failed\n");
1013
1014	dw_mipi_dsi_dphy_enable(dsi);
1015
1016	dw_mipi_dsi_wait_for_two_frames(adjusted_mode);
1017
1018	/* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
1019	dw_mipi_dsi_set_mode(dsi, 0);
1020
1021	if (phy_ops->power_on)
1022		phy_ops->power_on(dsi->plat_data->priv_data);
1023}
1024
1025static void dw_mipi_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1026						 struct drm_atomic_state *state)
1027{
1028	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
1029
1030	/* Power up the dsi ctl into a command mode */
1031	dw_mipi_dsi_mode_set(dsi, &dsi->mode);
1032	if (dsi->slave)
1033		dw_mipi_dsi_mode_set(dsi->slave, &dsi->mode);
1034}
1035
1036static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
1037					const struct drm_display_mode *mode,
1038					const struct drm_display_mode *adjusted_mode)
1039{
1040	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
1041
1042	/* Store the display mode for later use in pre_enable callback */
1043	drm_mode_copy(&dsi->mode, adjusted_mode);
1044}
1045
1046static void dw_mipi_dsi_bridge_atomic_enable(struct drm_bridge *bridge,
1047					     struct drm_atomic_state *state)
1048{
1049	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
1050
1051	/* Switch to video mode for panel-bridge enable & panel enable */
1052	dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
1053	if (dsi->slave)
1054		dw_mipi_dsi_set_mode(dsi->slave, MIPI_DSI_MODE_VIDEO);
1055}
1056
1057static enum drm_mode_status
1058dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
1059			      const struct drm_display_info *info,
1060			      const struct drm_display_mode *mode)
1061{
1062	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
1063	const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
1064	enum drm_mode_status mode_status = MODE_OK;
1065
1066	if (pdata->mode_valid)
1067		mode_status = pdata->mode_valid(pdata->priv_data, mode,
1068						dsi->mode_flags,
1069						dw_mipi_dsi_get_lanes(dsi),
1070						dsi->format);
1071
1072	return mode_status;
1073}
1074
1075static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge,
1076				     struct drm_encoder *encoder,
1077				     enum drm_bridge_attach_flags flags)
1078{
1079	struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
1080
1081	/* Set the encoder type as caller does not know it */
1082	encoder->encoder_type = DRM_MODE_ENCODER_DSI;
1083
1084	/* Attach the panel-bridge to the dsi bridge */
1085	return drm_bridge_attach(encoder, dsi->panel_bridge, bridge,
1086				 flags);
1087}
1088
1089static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = {
1090	.atomic_duplicate_state	= drm_atomic_helper_bridge_duplicate_state,
1091	.atomic_destroy_state	= drm_atomic_helper_bridge_destroy_state,
1092	.atomic_get_input_bus_fmts = dw_mipi_dsi_bridge_atomic_get_input_bus_fmts,
1093	.atomic_check		= dw_mipi_dsi_bridge_atomic_check,
1094	.atomic_reset		= drm_atomic_helper_bridge_reset,
1095	.atomic_pre_enable	= dw_mipi_dsi_bridge_atomic_pre_enable,
1096	.atomic_enable		= dw_mipi_dsi_bridge_atomic_enable,
1097	.atomic_post_disable	= dw_mipi_dsi_bridge_post_atomic_disable,
1098	.mode_set		= dw_mipi_dsi_bridge_mode_set,
1099	.mode_valid		= dw_mipi_dsi_bridge_mode_valid,
1100	.attach			= dw_mipi_dsi_bridge_attach,
1101};
1102
1103#ifdef CONFIG_DEBUG_FS
1104
1105static int dw_mipi_dsi_debugfs_write(void *data, u64 val)
1106{
1107	struct debugfs_entries *vpg = data;
1108	struct dw_mipi_dsi *dsi;
1109	u32 mode_cfg;
1110
1111	if (!vpg)
1112		return -ENODEV;
1113
1114	dsi = vpg->dsi;
1115
1116	*vpg->reg = (bool)val;
1117
1118	mode_cfg = dsi_read(dsi, DSI_VID_MODE_CFG);
1119
1120	if (*vpg->reg)
1121		mode_cfg |= vpg->mask;
1122	else
1123		mode_cfg &= ~vpg->mask;
1124
1125	dsi_write(dsi, DSI_VID_MODE_CFG, mode_cfg);
1126
1127	return 0;
1128}
1129
1130static int dw_mipi_dsi_debugfs_show(void *data, u64 *val)
1131{
1132	struct debugfs_entries *vpg = data;
1133
1134	if (!vpg)
1135		return -ENODEV;
1136
1137	*val = *vpg->reg;
1138
1139	return 0;
1140}
1141
1142DEFINE_DEBUGFS_ATTRIBUTE(fops_x32, dw_mipi_dsi_debugfs_show,
1143			 dw_mipi_dsi_debugfs_write, "%llu\n");
1144
1145static void debugfs_create_files(void *data)
1146{
1147	struct dw_mipi_dsi *dsi = data;
1148	struct debugfs_entries debugfs[] = {
1149		REGISTER(vpg, VID_MODE_VPG_ENABLE, dsi),
1150		REGISTER(vpg_horizontal, VID_MODE_VPG_HORIZONTAL, dsi),
1151		REGISTER(vpg_ber_pattern, VID_MODE_VPG_MODE, dsi),
1152	};
1153	int i;
1154
1155	dsi->debugfs_vpg = kmemdup(debugfs, sizeof(debugfs), GFP_KERNEL);
1156	if (!dsi->debugfs_vpg)
1157		return;
1158
1159	for (i = 0; i < ARRAY_SIZE(debugfs); i++)
1160		debugfs_create_file(dsi->debugfs_vpg[i].name, 0644,
1161				    dsi->debugfs, &dsi->debugfs_vpg[i],
1162				    &fops_x32);
1163}
1164
1165static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi)
1166{
1167	dsi->debugfs = debugfs_create_dir(dev_name(dsi->dev), NULL);
1168	if (IS_ERR(dsi->debugfs)) {
1169		dev_err(dsi->dev, "failed to create debugfs root\n");
1170		return;
1171	}
1172
1173	debugfs_create_files(dsi);
1174}
1175
1176static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi)
1177{
1178	debugfs_remove_recursive(dsi->debugfs);
1179	kfree(dsi->debugfs_vpg);
1180}
1181
1182#else
1183
1184static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) { }
1185static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { }
1186
1187#endif /* CONFIG_DEBUG_FS */
1188
1189static struct dw_mipi_dsi *
1190__dw_mipi_dsi_probe(struct platform_device *pdev,
1191		    const struct dw_mipi_dsi_plat_data *plat_data)
1192{
1193	struct device *dev = &pdev->dev;
1194	struct reset_control *apb_rst;
1195	struct dw_mipi_dsi *dsi;
1196	int ret;
1197
1198	dsi = devm_drm_bridge_alloc(dev, struct dw_mipi_dsi, bridge,
1199				    &dw_mipi_dsi_bridge_funcs);
1200	if (IS_ERR(dsi))
1201		return ERR_CAST(dsi);
1202
1203	dsi->dev = dev;
1204	dsi->plat_data = plat_data;
1205
1206	if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps ||
1207	    !plat_data->phy_ops->get_timing) {
1208		DRM_ERROR("Phy not properly configured\n");
1209		return ERR_PTR(-ENODEV);
1210	}
1211
1212	if (!plat_data->base) {
1213		dsi->base = devm_platform_ioremap_resource(pdev, 0);
1214		if (IS_ERR(dsi->base))
1215			return ERR_PTR(-ENODEV);
1216
1217	} else {
1218		dsi->base = plat_data->base;
1219	}
1220
1221	dsi->pclk = devm_clk_get(dev, "pclk");
1222	if (IS_ERR(dsi->pclk)) {
1223		ret = PTR_ERR(dsi->pclk);
1224		dev_err(dev, "Unable to get pclk: %d\n", ret);
1225		return ERR_PTR(ret);
1226	}
1227
1228	/*
1229	 * Note that the reset was not defined in the initial device tree, so
1230	 * we have to be prepared for it not being found.
1231	 */
1232	apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb");
1233	if (IS_ERR(apb_rst)) {
1234		ret = PTR_ERR(apb_rst);
1235
1236		if (ret != -EPROBE_DEFER)
1237			dev_err(dev, "Unable to get reset control: %d\n", ret);
1238
1239		return ERR_PTR(ret);
1240	}
1241
1242	if (apb_rst) {
1243		ret = clk_prepare_enable(dsi->pclk);
1244		if (ret) {
1245			dev_err(dev, "%s: Failed to enable pclk\n", __func__);
1246			return ERR_PTR(ret);
1247		}
1248
1249		reset_control_assert(apb_rst);
1250		usleep_range(10, 20);
1251		reset_control_deassert(apb_rst);
1252
1253		clk_disable_unprepare(dsi->pclk);
1254	}
1255
1256	dw_mipi_dsi_debugfs_init(dsi);
1257	pm_runtime_enable(dev);
1258
1259	dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1260	dsi->dsi_host.dev = dev;
1261	ret = mipi_dsi_host_register(&dsi->dsi_host);
1262	if (ret) {
1263		dev_err(dev, "Failed to register MIPI host: %d\n", ret);
1264		pm_runtime_disable(dev);
1265		dw_mipi_dsi_debugfs_remove(dsi);
1266		return ERR_PTR(ret);
1267	}
1268
1269	dsi->bridge.driver_private = dsi;
1270	dsi->bridge.of_node = pdev->dev.of_node;
1271
1272	return dsi;
1273}
1274
1275static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
1276{
1277	mipi_dsi_host_unregister(&dsi->dsi_host);
1278
1279	pm_runtime_disable(dsi->dev);
1280	dw_mipi_dsi_debugfs_remove(dsi);
1281}
1282
1283void dw_mipi_dsi_set_slave(struct dw_mipi_dsi *dsi, struct dw_mipi_dsi *slave)
1284{
1285	/* introduce controllers to each other */
1286	dsi->slave = slave;
1287	dsi->slave->master = dsi;
1288
1289	/* migrate settings for already attached displays */
1290	dsi->slave->lanes = dsi->lanes;
1291	dsi->slave->channel = dsi->channel;
1292	dsi->slave->format = dsi->format;
1293	dsi->slave->mode_flags = dsi->mode_flags;
1294}
1295EXPORT_SYMBOL_GPL(dw_mipi_dsi_set_slave);
1296
1297struct drm_bridge *dw_mipi_dsi_get_bridge(struct dw_mipi_dsi *dsi)
1298{
1299	return &dsi->bridge;
1300}
1301EXPORT_SYMBOL_GPL(dw_mipi_dsi_get_bridge);
1302
1303/*
1304 * Probe/remove API, used from platforms based on the DRM bridge API.
1305 */
1306struct dw_mipi_dsi *
1307dw_mipi_dsi_probe(struct platform_device *pdev,
1308		  const struct dw_mipi_dsi_plat_data *plat_data)
1309{
1310	return __dw_mipi_dsi_probe(pdev, plat_data);
1311}
1312EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
1313
1314void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
1315{
1316	__dw_mipi_dsi_remove(dsi);
1317}
1318EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
1319
1320/*
1321 * Bind/unbind API, used from platforms based on the component framework.
1322 */
1323int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder)
1324{
1325	return drm_bridge_attach(encoder, &dsi->bridge, NULL, 0);
1326}
1327EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
1328
1329void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi)
1330{
1331}
1332EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
1333
1334MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1335MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
1336MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
1337MODULE_LICENSE("GPL");
1338MODULE_ALIAS("platform:dw-mipi-dsi");