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dw-hdmi-qp.h
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linux-6.19.14/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) Rockchip Electronics Co., Ltd. 4 * Author: 5 * Algea Cao <algea.cao@rock-chips.com> 6 */ 7#ifndef __DW_HDMI_QP_H__ 8#define __DW_HDMI_QP_H__ 9 10#include <linux/bits.h> 11 12/* Main Unit Registers */ 13#define CORE_ID 0x0 14#define VER_NUMBER 0x4 15#define VER_TYPE 0x8 16#define CONFIG_REG 0xc 17#define CONFIG_CEC BIT(28) 18#define CONFIG_AUD_UD BIT(23) 19#define CORE_TIMESTAMP_HHMM 0x14 20#define CORE_TIMESTAMP_MMDD 0x18 21#define CORE_TIMESTAMP_YYYY 0x1c 22/* Reset Manager Registers */ 23#define GLOBAL_SWRESET_REQUEST 0x40 24#define EARCRX_CMDC_SWINIT_P BIT(27) 25#define AVP_DATAPATH_PACKET_AUDIO_SWINIT_P BIT(10) 26#define GLOBAL_SWDISABLE 0x44 27#define CEC_SWDISABLE BIT(17) 28#define AVP_DATAPATH_PACKET_AUDIO_SWDISABLE BIT(10) 29#define AVP_DATAPATH_VIDEO_SWDISABLE BIT(6) 30#define RESET_MANAGER_CONFIG0 0x48 31#define RESET_MANAGER_STATUS0 0x50 32#define RESET_MANAGER_STATUS1 0x54 33#define RESET_MANAGER_STATUS2 0x58 34/* Timer Base Registers */ 35#define TIMER_BASE_CONFIG0 0x80 36#define TIMER_BASE_STATUS0 0x84 37/* CMU Registers */ 38#define CMU_CONFIG0 0xa0 39#define CMU_CONFIG1 0xa4 40#define CMU_CONFIG2 0xa8 41#define CMU_CONFIG3 0xac 42#define CMU_STATUS 0xb0 43#define DISPLAY_CLK_MONITOR 0x3f 44#define DISPLAY_CLK_LOCKED 0X15 45#define EARC_BPCLK_OFF BIT(9) 46#define AUDCLK_OFF BIT(7) 47#define LINKQPCLK_OFF BIT(5) 48#define VIDQPCLK_OFF BIT(3) 49#define IPI_CLK_OFF BIT(1) 50#define CMU_IPI_CLK_FREQ 0xb4 51#define CMU_VIDQPCLK_FREQ 0xb8 52#define CMU_LINKQPCLK_FREQ 0xbc 53#define CMU_AUDQPCLK_FREQ 0xc0 54#define CMU_EARC_BPCLK_FREQ 0xc4 55/* I2CM Registers */ 56#define I2CM_SM_SCL_CONFIG0 0xe0 57#define I2CM_FM_SCL_CONFIG0 0xe4 58#define I2CM_CONFIG0 0xe8 59#define I2CM_CONTROL0 0xec 60#define I2CM_STATUS0 0xf0 61#define I2CM_INTERFACE_CONTROL0 0xf4 62#define I2CM_ADDR 0xff000 63#define I2CM_SLVADDR 0xfe0 64#define I2CM_WR_MASK 0x1e 65#define I2CM_EXT_READ BIT(4) 66#define I2CM_SHORT_READ BIT(3) 67#define I2CM_FM_READ BIT(2) 68#define I2CM_FM_WRITE BIT(1) 69#define I2CM_FM_EN BIT(0) 70#define I2CM_INTERFACE_CONTROL1 0xf8 71#define I2CM_SEG_PTR 0x7f80 72#define I2CM_SEG_ADDR 0x7f 73#define I2CM_INTERFACE_WRDATA_0_3 0xfc 74#define I2CM_INTERFACE_WRDATA_4_7 0x100 75#define I2CM_INTERFACE_WRDATA_8_11 0x104 76#define I2CM_INTERFACE_WRDATA_12_15 0x108 77#define I2CM_INTERFACE_RDDATA_0_3 0x10c 78#define I2CM_INTERFACE_RDDATA_4_7 0x110 79#define I2CM_INTERFACE_RDDATA_8_11 0x114 80#define I2CM_INTERFACE_RDDATA_12_15 0x118 81/* SCDC Registers */ 82#define SCDC_CONFIG0 0x140 83#define SCDC_I2C_FM_EN BIT(12) 84#define SCDC_UPD_FLAGS_AUTO_CLR BIT(6) 85#define SCDC_UPD_FLAGS_POLL_EN BIT(4) 86#define SCDC_CONTROL0 0x148 87#define SCDC_STATUS0 0x150 88#define STATUS_UPDATE BIT(0) 89#define FRL_START BIT(4) 90#define FLT_UPDATE BIT(5) 91/* FLT Registers */ 92#define FLT_CONFIG0 0x160 93#define FLT_CONFIG1 0x164 94#define FLT_CONFIG2 0x168 95#define FLT_CONTROL0 0x170 96/* Main Unit 2 Registers */ 97#define MAINUNIT_STATUS0 0x180 98/* Video Interface Registers */ 99#define VIDEO_INTERFACE_CONFIG0 0x800 100#define VIDEO_INTERFACE_CONFIG1 0x804 101#define VIDEO_INTERFACE_CONFIG2 0x808 102#define VIDEO_INTERFACE_CONTROL0 0x80c 103#define VIDEO_INTERFACE_STATUS0 0x814 104/* Video Packing Registers */ 105#define VIDEO_PACKING_CONFIG0 0x81c 106/* Audio Interface Registers */ 107#define AUDIO_INTERFACE_CONFIG0 0x820 108#define AUD_IF_SEL_MSK 0x3 109#define AUD_IF_SPDIF 0x2 110#define AUD_IF_I2S 0x1 111#define AUD_IF_PAI 0x0 112#define AUD_FIFO_INIT_ON_OVF_MSK BIT(2) 113#define AUD_FIFO_INIT_ON_OVF_EN BIT(2) 114#define I2S_LINES_EN_MSK GENMASK(7, 4) 115#define I2S_LINES_EN(x) BIT((x) + 4) 116#define I2S_BPCUV_RCV_MSK BIT(12) 117#define I2S_BPCUV_RCV_EN BIT(12) 118#define I2S_BPCUV_RCV_DIS 0 119#define SPDIF_LINES_EN GENMASK(19, 16) 120#define AUD_FORMAT_MSK GENMASK(26, 24) 121#define AUD_3DOBA (0x7 << 24) 122#define AUD_3DASP (0x6 << 24) 123#define AUD_MSOBA (0x5 << 24) 124#define AUD_MSASP (0x4 << 24) 125#define AUD_HBR (0x3 << 24) 126#define AUD_DST (0x2 << 24) 127#define AUD_OBA (0x1 << 24) 128#define AUD_ASP (0x0 << 24) 129#define AUDIO_INTERFACE_CONFIG1 0x824 130#define AUDIO_INTERFACE_CONTROL0 0x82c 131#define AUDIO_FIFO_CLR_P BIT(0) 132#define AUDIO_INTERFACE_STATUS0 0x834 133/* Frame Composer Registers */ 134#define FRAME_COMPOSER_CONFIG0 0x840 135#define FRAME_COMPOSER_CONFIG1 0x844 136#define FRAME_COMPOSER_CONFIG2 0x848 137#define FRAME_COMPOSER_CONFIG3 0x84c 138#define FRAME_COMPOSER_CONFIG4 0x850 139#define FRAME_COMPOSER_CONFIG5 0x854 140#define FRAME_COMPOSER_CONFIG6 0x858 141#define FRAME_COMPOSER_CONFIG7 0x85c 142#define FRAME_COMPOSER_CONFIG8 0x860 143#define FRAME_COMPOSER_CONFIG9 0x864 144#define FRAME_COMPOSER_CONTROL0 0x86c 145/* Video Monitor Registers */ 146#define VIDEO_MONITOR_CONFIG0 0x880 147#define VIDEO_MONITOR_STATUS0 0x884 148#define VIDEO_MONITOR_STATUS1 0x888 149#define VIDEO_MONITOR_STATUS2 0x88c 150#define VIDEO_MONITOR_STATUS3 0x890 151#define VIDEO_MONITOR_STATUS4 0x894 152#define VIDEO_MONITOR_STATUS5 0x898 153#define VIDEO_MONITOR_STATUS6 0x89c 154/* HDCP2 Logic Registers */ 155#define HDCP2LOGIC_CONFIG0 0x8e0 156#define HDCP2_BYPASS BIT(0) 157#define HDCP2LOGIC_ESM_GPIO_IN 0x8e4 158#define HDCP2LOGIC_ESM_GPIO_OUT 0x8e8 159/* HDCP14 Registers */ 160#define HDCP14_CONFIG0 0x900 161#define HDCP14_CONFIG1 0x904 162#define HDCP14_CONFIG2 0x908 163#define HDCP14_CONFIG3 0x90c 164#define HDCP14_KEY_SEED 0x914 165#define HDCP14_KEY_H 0x918 166#define HDCP14_KEY_L 0x91c 167#define HDCP14_KEY_STATUS 0x920 168#define HDCP14_AKSV_H 0x924 169#define HDCP14_AKSV_L 0x928 170#define HDCP14_AN_H 0x92c 171#define HDCP14_AN_L 0x930 172#define HDCP14_STATUS0 0x934 173#define HDCP14_STATUS1 0x938 174/* Scrambler Registers */ 175#define SCRAMB_CONFIG0 0x960 176/* Video Configuration Registers */ 177#define LINK_CONFIG0 0x968 178#define OPMODE_FRL_4LANES BIT(8) 179#define OPMODE_DVI BIT(4) 180#define OPMODE_FRL BIT(0) 181/* TMDS FIFO Registers */ 182#define TMDS_FIFO_CONFIG0 0x970 183#define TMDS_FIFO_CONTROL0 0x974 184/* FRL RSFEC Registers */ 185#define FRL_RSFEC_CONFIG0 0xa20 186#define FRL_RSFEC_STATUS0 0xa30 187/* FRL Packetizer Registers */ 188#define FRL_PKTZ_CONFIG0 0xa40 189#define FRL_PKTZ_CONTROL0 0xa44 190#define FRL_PKTZ_CONTROL1 0xa50 191#define FRL_PKTZ_STATUS1 0xa54 192/* Packet Scheduler Registers */ 193#define PKTSCHED_CONFIG0 0xa80 194#define PKTSCHED_PRQUEUE0_CONFIG0 0xa84 195#define PKTSCHED_PRQUEUE1_CONFIG0 0xa88 196#define PKTSCHED_PRQUEUE2_CONFIG0 0xa8c 197#define PKTSCHED_PRQUEUE2_CONFIG1 0xa90 198#define PKTSCHED_PRQUEUE2_CONFIG2 0xa94 199#define PKTSCHED_PKT_CONFIG0 0xa98 200#define PKTSCHED_PKT_CONFIG1 0xa9c 201#define PKTSCHED_DRMI_FIELDRATE BIT(13) 202#define PKTSCHED_AVI_FIELDRATE BIT(12) 203#define PKTSCHED_PKT_CONFIG2 0xaa0 204#define PKTSCHED_PKT_CONFIG3 0xaa4 205#define PKTSCHED_PKT_EN 0xaa8 206#define PKTSCHED_DRMI_TX_EN BIT(17) 207#define PKTSCHED_AUDI_TX_EN BIT(15) 208#define PKTSCHED_AVI_TX_EN BIT(13) 209#define PKTSCHED_EMP_CVTEM_TX_EN BIT(10) 210#define PKTSCHED_AMD_TX_EN BIT(8) 211#define PKTSCHED_GCP_TX_EN BIT(3) 212#define PKTSCHED_AUDS_TX_EN BIT(2) 213#define PKTSCHED_ACR_TX_EN BIT(1) 214#define PKTSCHED_NULL_TX_EN BIT(0) 215#define PKTSCHED_PKT_CONTROL0 0xaac 216#define PKTSCHED_PKT_SEND 0xab0 217#define PKTSCHED_PKT_STATUS0 0xab4 218#define PKTSCHED_PKT_STATUS1 0xab8 219#define PKT_NULL_CONTENTS0 0xb00 220#define PKT_NULL_CONTENTS1 0xb04 221#define PKT_NULL_CONTENTS2 0xb08 222#define PKT_NULL_CONTENTS3 0xb0c 223#define PKT_NULL_CONTENTS4 0xb10 224#define PKT_NULL_CONTENTS5 0xb14 225#define PKT_NULL_CONTENTS6 0xb18 226#define PKT_NULL_CONTENTS7 0xb1c 227#define PKT_ACP_CONTENTS0 0xb20 228#define PKT_ACP_CONTENTS1 0xb24 229#define PKT_ACP_CONTENTS2 0xb28 230#define PKT_ACP_CONTENTS3 0xb2c 231#define PKT_ACP_CONTENTS4 0xb30 232#define PKT_ACP_CONTENTS5 0xb34 233#define PKT_ACP_CONTENTS6 0xb38 234#define PKT_ACP_CONTENTS7 0xb3c 235#define PKT_ISRC1_CONTENTS0 0xb40 236#define PKT_ISRC1_CONTENTS1 0xb44 237#define PKT_ISRC1_CONTENTS2 0xb48 238#define PKT_ISRC1_CONTENTS3 0xb4c 239#define PKT_ISRC1_CONTENTS4 0xb50 240#define PKT_ISRC1_CONTENTS5 0xb54 241#define PKT_ISRC1_CONTENTS6 0xb58 242#define PKT_ISRC1_CONTENTS7 0xb5c 243#define PKT_ISRC2_CONTENTS0 0xb60 244#define PKT_ISRC2_CONTENTS1 0xb64 245#define PKT_ISRC2_CONTENTS2 0xb68 246#define PKT_ISRC2_CONTENTS3 0xb6c 247#define PKT_ISRC2_CONTENTS4 0xb70 248#define PKT_ISRC2_CONTENTS5 0xb74 249#define PKT_ISRC2_CONTENTS6 0xb78 250#define PKT_ISRC2_CONTENTS7 0xb7c 251#define PKT_GMD_CONTENTS0 0xb80 252#define PKT_GMD_CONTENTS1 0xb84 253#define PKT_GMD_CONTENTS2 0xb88 254#define PKT_GMD_CONTENTS3 0xb8c 255#define PKT_GMD_CONTENTS4 0xb90 256#define PKT_GMD_CONTENTS5 0xb94 257#define PKT_GMD_CONTENTS6 0xb98 258#define PKT_GMD_CONTENTS7 0xb9c 259#define PKT_AMD_CONTENTS0 0xba0 260#define PKT_AMD_CONTENTS1 0xba4 261#define PKT_AMD_CONTENTS2 0xba8 262#define PKT_AMD_CONTENTS3 0xbac 263#define PKT_AMD_CONTENTS4 0xbb0 264#define PKT_AMD_CONTENTS5 0xbb4 265#define PKT_AMD_CONTENTS6 0xbb8 266#define PKT_AMD_CONTENTS7 0xbbc 267#define PKT_VSI_CONTENTS0 0xbc0 268#define PKT_VSI_CONTENTS1 0xbc4 269#define PKT_VSI_CONTENTS2 0xbc8 270#define PKT_VSI_CONTENTS3 0xbcc 271#define PKT_VSI_CONTENTS4 0xbd0 272#define PKT_VSI_CONTENTS5 0xbd4 273#define PKT_VSI_CONTENTS6 0xbd8 274#define PKT_VSI_CONTENTS7 0xbdc 275#define PKT_AVI_CONTENTS0 0xbe0 276#define HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT BIT(4) 277#define HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR 0x04 278#define HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR 0x08 279#define HDMI_FC_AVICONF2_IT_CONTENT_VALID 0x80 280#define PKT_AVI_CONTENTS1 0xbe4 281#define PKT_AVI_CONTENTS2 0xbe8 282#define PKT_AVI_CONTENTS3 0xbec 283#define PKT_AVI_CONTENTS4 0xbf0 284#define PKT_AVI_CONTENTS5 0xbf4 285#define PKT_AVI_CONTENTS6 0xbf8 286#define PKT_AVI_CONTENTS7 0xbfc 287#define PKT_SPDI_CONTENTS0 0xc00 288#define PKT_SPDI_CONTENTS1 0xc04 289#define PKT_SPDI_CONTENTS2 0xc08 290#define PKT_SPDI_CONTENTS3 0xc0c 291#define PKT_SPDI_CONTENTS4 0xc10 292#define PKT_SPDI_CONTENTS5 0xc14 293#define PKT_SPDI_CONTENTS6 0xc18 294#define PKT_SPDI_CONTENTS7 0xc1c 295#define PKT_AUDI_CONTENTS0 0xc20 296#define PKT_AUDI_CONTENTS1 0xc24 297#define PKT_AUDI_CONTENTS2 0xc28 298#define PKT_AUDI_CONTENTS3 0xc2c 299#define PKT_AUDI_CONTENTS4 0xc30 300#define PKT_AUDI_CONTENTS5 0xc34 301#define PKT_AUDI_CONTENTS6 0xc38 302#define PKT_AUDI_CONTENTS7 0xc3c 303#define PKT_NVI_CONTENTS0 0xc40 304#define PKT_NVI_CONTENTS1 0xc44 305#define PKT_NVI_CONTENTS2 0xc48 306#define PKT_NVI_CONTENTS3 0xc4c 307#define PKT_NVI_CONTENTS4 0xc50 308#define PKT_NVI_CONTENTS5 0xc54 309#define PKT_NVI_CONTENTS6 0xc58 310#define PKT_NVI_CONTENTS7 0xc5c 311#define PKT_DRMI_CONTENTS0 0xc60 312#define PKT_DRMI_CONTENTS1 0xc64 313#define PKT_DRMI_CONTENTS2 0xc68 314#define PKT_DRMI_CONTENTS3 0xc6c 315#define PKT_DRMI_CONTENTS4 0xc70 316#define PKT_DRMI_CONTENTS5 0xc74 317#define PKT_DRMI_CONTENTS6 0xc78 318#define PKT_DRMI_CONTENTS7 0xc7c 319#define PKT_GHDMI1_CONTENTS0 0xc80 320#define PKT_GHDMI1_CONTENTS1 0xc84 321#define PKT_GHDMI1_CONTENTS2 0xc88 322#define PKT_GHDMI1_CONTENTS3 0xc8c 323#define PKT_GHDMI1_CONTENTS4 0xc90 324#define PKT_GHDMI1_CONTENTS5 0xc94 325#define PKT_GHDMI1_CONTENTS6 0xc98 326#define PKT_GHDMI1_CONTENTS7 0xc9c 327#define PKT_GHDMI2_CONTENTS0 0xca0 328#define PKT_GHDMI2_CONTENTS1 0xca4 329#define PKT_GHDMI2_CONTENTS2 0xca8 330#define PKT_GHDMI2_CONTENTS3 0xcac 331#define PKT_GHDMI2_CONTENTS4 0xcb0 332#define PKT_GHDMI2_CONTENTS5 0xcb4 333#define PKT_GHDMI2_CONTENTS6 0xcb8 334#define PKT_GHDMI2_CONTENTS7 0xcbc 335/* EMP Packetizer Registers */ 336#define PKT_EMP_CONFIG0 0xce0 337#define PKT_EMP_CONTROL0 0xcec 338#define PKT_EMP_CONTROL1 0xcf0 339#define PKT_EMP_CONTROL2 0xcf4 340#define PKT_EMP_VTEM_CONTENTS0 0xd00 341#define PKT_EMP_VTEM_CONTENTS1 0xd04 342#define PKT_EMP_VTEM_CONTENTS2 0xd08 343#define PKT_EMP_VTEM_CONTENTS3 0xd0c 344#define PKT_EMP_VTEM_CONTENTS4 0xd10 345#define PKT_EMP_VTEM_CONTENTS5 0xd14 346#define PKT_EMP_VTEM_CONTENTS6 0xd18 347#define PKT_EMP_VTEM_CONTENTS7 0xd1c 348#define PKT0_EMP_CVTEM_CONTENTS0 0xd20 349#define PKT0_EMP_CVTEM_CONTENTS1 0xd24 350#define PKT0_EMP_CVTEM_CONTENTS2 0xd28 351#define PKT0_EMP_CVTEM_CONTENTS3 0xd2c 352#define PKT0_EMP_CVTEM_CONTENTS4 0xd30 353#define PKT0_EMP_CVTEM_CONTENTS5 0xd34 354#define PKT0_EMP_CVTEM_CONTENTS6 0xd38 355#define PKT0_EMP_CVTEM_CONTENTS7 0xd3c 356#define PKT1_EMP_CVTEM_CONTENTS0 0xd40 357#define PKT1_EMP_CVTEM_CONTENTS1 0xd44 358#define PKT1_EMP_CVTEM_CONTENTS2 0xd48 359#define PKT1_EMP_CVTEM_CONTENTS3 0xd4c 360#define PKT1_EMP_CVTEM_CONTENTS4 0xd50 361#define PKT1_EMP_CVTEM_CONTENTS5 0xd54 362#define PKT1_EMP_CVTEM_CONTENTS6 0xd58 363#define PKT1_EMP_CVTEM_CONTENTS7 0xd5c 364#define PKT2_EMP_CVTEM_CONTENTS0 0xd60 365#define PKT2_EMP_CVTEM_CONTENTS1 0xd64 366#define PKT2_EMP_CVTEM_CONTENTS2 0xd68 367#define PKT2_EMP_CVTEM_CONTENTS3 0xd6c 368#define PKT2_EMP_CVTEM_CONTENTS4 0xd70 369#define PKT2_EMP_CVTEM_CONTENTS5 0xd74 370#define PKT2_EMP_CVTEM_CONTENTS6 0xd78 371#define PKT2_EMP_CVTEM_CONTENTS7 0xd7c 372#define PKT3_EMP_CVTEM_CONTENTS0 0xd80 373#define PKT3_EMP_CVTEM_CONTENTS1 0xd84 374#define PKT3_EMP_CVTEM_CONTENTS2 0xd88 375#define PKT3_EMP_CVTEM_CONTENTS3 0xd8c 376#define PKT3_EMP_CVTEM_CONTENTS4 0xd90 377#define PKT3_EMP_CVTEM_CONTENTS5 0xd94 378#define PKT3_EMP_CVTEM_CONTENTS6 0xd98 379#define PKT3_EMP_CVTEM_CONTENTS7 0xd9c 380#define PKT4_EMP_CVTEM_CONTENTS0 0xda0 381#define PKT4_EMP_CVTEM_CONTENTS1 0xda4 382#define PKT4_EMP_CVTEM_CONTENTS2 0xda8 383#define PKT4_EMP_CVTEM_CONTENTS3 0xdac 384#define PKT4_EMP_CVTEM_CONTENTS4 0xdb0 385#define PKT4_EMP_CVTEM_CONTENTS5 0xdb4 386#define PKT4_EMP_CVTEM_CONTENTS6 0xdb8 387#define PKT4_EMP_CVTEM_CONTENTS7 0xdbc 388#define PKT5_EMP_CVTEM_CONTENTS0 0xdc0 389#define PKT5_EMP_CVTEM_CONTENTS1 0xdc4 390#define PKT5_EMP_CVTEM_CONTENTS2 0xdc8 391#define PKT5_EMP_CVTEM_CONTENTS3 0xdcc 392#define PKT5_EMP_CVTEM_CONTENTS4 0xdd0 393#define PKT5_EMP_CVTEM_CONTENTS5 0xdd4 394#define PKT5_EMP_CVTEM_CONTENTS6 0xdd8 395#define PKT5_EMP_CVTEM_CONTENTS7 0xddc 396/* Audio Packetizer Registers */ 397#define AUDPKT_CONTROL0 0xe20 398#define AUDPKT_PBIT_FORCE_EN_MASK BIT(12) 399#define AUDPKT_PBIT_FORCE_EN BIT(12) 400#define AUDPKT_CHSTATUS_OVR_EN_MASK BIT(0) 401#define AUDPKT_CHSTATUS_OVR_EN BIT(0) 402#define AUDPKT_CONTROL1 0xe24 403#define AUDPKT_ACR_CONTROL0 0xe40 404#define AUDPKT_ACR_N_VALUE 0xfffff 405#define AUDPKT_ACR_CONTROL1 0xe44 406#define AUDPKT_ACR_CTS_OVR_VAL_MSK GENMASK(23, 4) 407#define AUDPKT_ACR_CTS_OVR_VAL(x) ((x) << 4) 408#define AUDPKT_ACR_CTS_OVR_EN_MSK BIT(1) 409#define AUDPKT_ACR_CTS_OVR_EN BIT(1) 410#define AUDPKT_ACR_STATUS0 0xe4c 411#define AUDPKT_CHSTATUS_OVR0 0xe60 412#define AUDPKT_CHSTATUS_OVR1 0xe64 413/* IEC60958 Byte 3: Sampleing frenuency Bits 24 to 27 */ 414#define AUDPKT_CHSTATUS_SR_MASK GENMASK(3, 0) 415#define AUDPKT_CHSTATUS_SR_22050 0x4 416#define AUDPKT_CHSTATUS_SR_24000 0x6 417#define AUDPKT_CHSTATUS_SR_32000 0x3 418#define AUDPKT_CHSTATUS_SR_44100 0x0 419#define AUDPKT_CHSTATUS_SR_48000 0x2 420#define AUDPKT_CHSTATUS_SR_88200 0x8 421#define AUDPKT_CHSTATUS_SR_96000 0xa 422#define AUDPKT_CHSTATUS_SR_176400 0xc 423#define AUDPKT_CHSTATUS_SR_192000 0xe 424#define AUDPKT_CHSTATUS_SR_768000 0x9 425#define AUDPKT_CHSTATUS_SR_NOT_INDICATED 0x1 426/* IEC60958 Byte 4: Original Sampleing frenuency Bits 36 to 39 */ 427#define AUDPKT_CHSTATUS_0SR_MASK GENMASK(15, 12) 428#define AUDPKT_CHSTATUS_OSR_8000 0x6 429#define AUDPKT_CHSTATUS_OSR_11025 0xa 430#define AUDPKT_CHSTATUS_OSR_12000 0x2 431#define AUDPKT_CHSTATUS_OSR_16000 0x8 432#define AUDPKT_CHSTATUS_OSR_22050 0xb 433#define AUDPKT_CHSTATUS_OSR_24000 0x9 434#define AUDPKT_CHSTATUS_OSR_32000 0xc 435#define AUDPKT_CHSTATUS_OSR_44100 0xf 436#define AUDPKT_CHSTATUS_OSR_48000 0xd 437#define AUDPKT_CHSTATUS_OSR_88200 0x7 438#define AUDPKT_CHSTATUS_OSR_96000 0x5 439#define AUDPKT_CHSTATUS_OSR_176400 0x3 440#define AUDPKT_CHSTATUS_OSR_192000 0x1 441#define AUDPKT_CHSTATUS_OSR_NOT_INDICATED 0x0 442#define AUDPKT_CHSTATUS_OVR2 0xe68 443#define AUDPKT_CHSTATUS_OVR3 0xe6c 444#define AUDPKT_CHSTATUS_OVR4 0xe70 445#define AUDPKT_CHSTATUS_OVR5 0xe74 446#define AUDPKT_CHSTATUS_OVR6 0xe78 447#define AUDPKT_CHSTATUS_OVR7 0xe7c 448#define AUDPKT_CHSTATUS_OVR8 0xe80 449#define AUDPKT_CHSTATUS_OVR9 0xe84 450#define AUDPKT_CHSTATUS_OVR10 0xe88 451#define AUDPKT_CHSTATUS_OVR11 0xe8c 452#define AUDPKT_CHSTATUS_OVR12 0xe90 453#define AUDPKT_CHSTATUS_OVR13 0xe94 454#define AUDPKT_CHSTATUS_OVR14 0xe98 455#define AUDPKT_USRDATA_OVR_MSG_GENERIC0 0xea0 456#define AUDPKT_USRDATA_OVR_MSG_GENERIC1 0xea4 457#define AUDPKT_USRDATA_OVR_MSG_GENERIC2 0xea8 458#define AUDPKT_USRDATA_OVR_MSG_GENERIC3 0xeac 459#define AUDPKT_USRDATA_OVR_MSG_GENERIC4 0xeb0 460#define AUDPKT_USRDATA_OVR_MSG_GENERIC5 0xeb4 461#define AUDPKT_USRDATA_OVR_MSG_GENERIC6 0xeb8 462#define AUDPKT_USRDATA_OVR_MSG_GENERIC7 0xebc 463#define AUDPKT_USRDATA_OVR_MSG_GENERIC8 0xec0 464#define AUDPKT_USRDATA_OVR_MSG_GENERIC9 0xec4 465#define AUDPKT_USRDATA_OVR_MSG_GENERIC10 0xec8 466#define AUDPKT_USRDATA_OVR_MSG_GENERIC11 0xecc 467#define AUDPKT_USRDATA_OVR_MSG_GENERIC12 0xed0 468#define AUDPKT_USRDATA_OVR_MSG_GENERIC13 0xed4 469#define AUDPKT_USRDATA_OVR_MSG_GENERIC14 0xed8 470#define AUDPKT_USRDATA_OVR_MSG_GENERIC15 0xedc 471#define AUDPKT_USRDATA_OVR_MSG_GENERIC16 0xee0 472#define AUDPKT_USRDATA_OVR_MSG_GENERIC17 0xee4 473#define AUDPKT_USRDATA_OVR_MSG_GENERIC18 0xee8 474#define AUDPKT_USRDATA_OVR_MSG_GENERIC19 0xeec 475#define AUDPKT_USRDATA_OVR_MSG_GENERIC20 0xef0 476#define AUDPKT_USRDATA_OVR_MSG_GENERIC21 0xef4 477#define AUDPKT_USRDATA_OVR_MSG_GENERIC22 0xef8 478#define AUDPKT_USRDATA_OVR_MSG_GENERIC23 0xefc 479#define AUDPKT_USRDATA_OVR_MSG_GENERIC24 0xf00 480#define AUDPKT_USRDATA_OVR_MSG_GENERIC25 0xf04 481#define AUDPKT_USRDATA_OVR_MSG_GENERIC26 0xf08 482#define AUDPKT_USRDATA_OVR_MSG_GENERIC27 0xf0c 483#define AUDPKT_USRDATA_OVR_MSG_GENERIC28 0xf10 484#define AUDPKT_USRDATA_OVR_MSG_GENERIC29 0xf14 485#define AUDPKT_USRDATA_OVR_MSG_GENERIC30 0xf18 486#define AUDPKT_USRDATA_OVR_MSG_GENERIC31 0xf1c 487#define AUDPKT_USRDATA_OVR_MSG_GENERIC32 0xf20 488#define AUDPKT_VBIT_OVR0 0xf24 489/* CEC Registers */ 490#define CEC_TX_CONTROL 0x1000 491#define CEC_CTRL_CLEAR BIT(0) 492#define CEC_CTRL_START BIT(0) 493#define CEC_STATUS 0x1004 494#define CEC_STAT_DONE BIT(0) 495#define CEC_STAT_NACK BIT(1) 496#define CEC_STAT_ARBLOST BIT(2) 497#define CEC_STAT_LINE_ERR BIT(3) 498#define CEC_STAT_RETRANS_FAIL BIT(4) 499#define CEC_STAT_DISCARD BIT(5) 500#define CEC_STAT_TX_BUSY BIT(8) 501#define CEC_STAT_RX_BUSY BIT(9) 502#define CEC_STAT_DRIVE_ERR BIT(10) 503#define CEC_STAT_EOM BIT(11) 504#define CEC_STAT_NOTIFY_ERR BIT(12) 505#define CEC_CONFIG 0x1008 506#define CEC_ADDR 0x100c 507#define CEC_ADDR_BROADCAST BIT(15) 508#define CEC_TX_COUNT 0x1020 509#define CEC_TX_DATA3_0 0x1024 510#define CEC_TX_DATA7_4 0x1028 511#define CEC_TX_DATA11_8 0x102c 512#define CEC_TX_DATA15_12 0x1030 513#define CEC_RX_COUNT_STATUS 0x1040 514#define CEC_RX_DATA3_0 0x1044 515#define CEC_RX_DATA7_4 0x1048 516#define CEC_RX_DATA11_8 0x104c 517#define CEC_RX_DATA15_12 0x1050 518#define CEC_LOCK_CONTROL 0x1054 519#define CEC_RXQUAL_BITTIME_CONFIG 0x1060 520#define CEC_RX_BITTIME_CONFIG 0x1064 521#define CEC_TX_BITTIME_CONFIG 0x1068 522/* eARC RX CMDC Registers */ 523#define EARCRX_CMDC_CONFIG0 0x1800 524#define EARCRX_XACTREAD_STOP_CFG BIT(26) 525#define EARCRX_XACTREAD_RETRY_CFG BIT(25) 526#define EARCRX_CMDC_DSCVR_EARCVALID0_TO_DISC1 BIT(24) 527#define EARCRX_CMDC_XACT_RESTART_EN BIT(18) 528#define EARCRX_CMDC_CONFIG1 0x1804 529#define EARCRX_CMDC_CONTROL 0x1808 530#define EARCRX_CMDC_HEARTBEAT_LOSS_EN BIT(4) 531#define EARCRX_CMDC_DISCOVERY_EN BIT(3) 532#define EARCRX_CONNECTOR_HPD BIT(1) 533#define EARCRX_CMDC_WHITELIST0_CONFIG 0x180c 534#define EARCRX_CMDC_WHITELIST1_CONFIG 0x1810 535#define EARCRX_CMDC_WHITELIST2_CONFIG 0x1814 536#define EARCRX_CMDC_WHITELIST3_CONFIG 0x1818 537#define EARCRX_CMDC_STATUS 0x181c 538#define EARCRX_CMDC_XACT_INFO 0x1820 539#define EARCRX_CMDC_XACT_ACTION 0x1824 540#define EARCRX_CMDC_HEARTBEAT_RXSTAT_SE 0x1828 541#define EARCRX_CMDC_HEARTBEAT_STATUS 0x182c 542#define EARCRX_CMDC_XACT_WR0 0x1840 543#define EARCRX_CMDC_XACT_WR1 0x1844 544#define EARCRX_CMDC_XACT_WR2 0x1848 545#define EARCRX_CMDC_XACT_WR3 0x184c 546#define EARCRX_CMDC_XACT_WR4 0x1850 547#define EARCRX_CMDC_XACT_WR5 0x1854 548#define EARCRX_CMDC_XACT_WR6 0x1858 549#define EARCRX_CMDC_XACT_WR7 0x185c 550#define EARCRX_CMDC_XACT_WR8 0x1860 551#define EARCRX_CMDC_XACT_WR9 0x1864 552#define EARCRX_CMDC_XACT_WR10 0x1868 553#define EARCRX_CMDC_XACT_WR11 0x186c 554#define EARCRX_CMDC_XACT_WR12 0x1870 555#define EARCRX_CMDC_XACT_WR13 0x1874 556#define EARCRX_CMDC_XACT_WR14 0x1878 557#define EARCRX_CMDC_XACT_WR15 0x187c 558#define EARCRX_CMDC_XACT_WR16 0x1880 559#define EARCRX_CMDC_XACT_WR17 0x1884 560#define EARCRX_CMDC_XACT_WR18 0x1888 561#define EARCRX_CMDC_XACT_WR19 0x188c 562#define EARCRX_CMDC_XACT_WR20 0x1890 563#define EARCRX_CMDC_XACT_WR21 0x1894 564#define EARCRX_CMDC_XACT_WR22 0x1898 565#define EARCRX_CMDC_XACT_WR23 0x189c 566#define EARCRX_CMDC_XACT_WR24 0x18a0 567#define EARCRX_CMDC_XACT_WR25 0x18a4 568#define EARCRX_CMDC_XACT_WR26 0x18a8 569#define EARCRX_CMDC_XACT_WR27 0x18ac 570#define EARCRX_CMDC_XACT_WR28 0x18b0 571#define EARCRX_CMDC_XACT_WR29 0x18b4 572#define EARCRX_CMDC_XACT_WR30 0x18b8 573#define EARCRX_CMDC_XACT_WR31 0x18bc 574#define EARCRX_CMDC_XACT_WR32 0x18c0 575#define EARCRX_CMDC_XACT_WR33 0x18c4 576#define EARCRX_CMDC_XACT_WR34 0x18c8 577#define EARCRX_CMDC_XACT_WR35 0x18cc 578#define EARCRX_CMDC_XACT_WR36 0x18d0 579#define EARCRX_CMDC_XACT_WR37 0x18d4 580#define EARCRX_CMDC_XACT_WR38 0x18d8 581#define EARCRX_CMDC_XACT_WR39 0x18dc 582#define EARCRX_CMDC_XACT_WR40 0x18e0 583#define EARCRX_CMDC_XACT_WR41 0x18e4 584#define EARCRX_CMDC_XACT_WR42 0x18e8 585#define EARCRX_CMDC_XACT_WR43 0x18ec 586#define EARCRX_CMDC_XACT_WR44 0x18f0 587#define EARCRX_CMDC_XACT_WR45 0x18f4 588#define EARCRX_CMDC_XACT_WR46 0x18f8 589#define EARCRX_CMDC_XACT_WR47 0x18fc 590#define EARCRX_CMDC_XACT_WR48 0x1900 591#define EARCRX_CMDC_XACT_WR49 0x1904 592#define EARCRX_CMDC_XACT_WR50 0x1908 593#define EARCRX_CMDC_XACT_WR51 0x190c 594#define EARCRX_CMDC_XACT_WR52 0x1910 595#define EARCRX_CMDC_XACT_WR53 0x1914 596#define EARCRX_CMDC_XACT_WR54 0x1918 597#define EARCRX_CMDC_XACT_WR55 0x191c 598#define EARCRX_CMDC_XACT_WR56 0x1920 599#define EARCRX_CMDC_XACT_WR57 0x1924 600#define EARCRX_CMDC_XACT_WR58 0x1928 601#define EARCRX_CMDC_XACT_WR59 0x192c 602#define EARCRX_CMDC_XACT_WR60 0x1930 603#define EARCRX_CMDC_XACT_WR61 0x1934 604#define EARCRX_CMDC_XACT_WR62 0x1938 605#define EARCRX_CMDC_XACT_WR63 0x193c 606#define EARCRX_CMDC_XACT_WR64 0x1940 607#define EARCRX_CMDC_XACT_RD0 0x1960 608#define EARCRX_CMDC_XACT_RD1 0x1964 609#define EARCRX_CMDC_XACT_RD2 0x1968 610#define EARCRX_CMDC_XACT_RD3 0x196c 611#define EARCRX_CMDC_XACT_RD4 0x1970 612#define EARCRX_CMDC_XACT_RD5 0x1974 613#define EARCRX_CMDC_XACT_RD6 0x1978 614#define EARCRX_CMDC_XACT_RD7 0x197c 615#define EARCRX_CMDC_XACT_RD8 0x1980 616#define EARCRX_CMDC_XACT_RD9 0x1984 617#define EARCRX_CMDC_XACT_RD10 0x1988 618#define EARCRX_CMDC_XACT_RD11 0x198c 619#define EARCRX_CMDC_XACT_RD12 0x1990 620#define EARCRX_CMDC_XACT_RD13 0x1994 621#define EARCRX_CMDC_XACT_RD14 0x1998 622#define EARCRX_CMDC_XACT_RD15 0x199c 623#define EARCRX_CMDC_XACT_RD16 0x19a0 624#define EARCRX_CMDC_XACT_RD17 0x19a4 625#define EARCRX_CMDC_XACT_RD18 0x19a8 626#define EARCRX_CMDC_XACT_RD19 0x19ac 627#define EARCRX_CMDC_XACT_RD20 0x19b0 628#define EARCRX_CMDC_XACT_RD21 0x19b4 629#define EARCRX_CMDC_XACT_RD22 0x19b8 630#define EARCRX_CMDC_XACT_RD23 0x19bc 631#define EARCRX_CMDC_XACT_RD24 0x19c0 632#define EARCRX_CMDC_XACT_RD25 0x19c4 633#define EARCRX_CMDC_XACT_RD26 0x19c8 634#define EARCRX_CMDC_XACT_RD27 0x19cc 635#define EARCRX_CMDC_XACT_RD28 0x19d0 636#define EARCRX_CMDC_XACT_RD29 0x19d4 637#define EARCRX_CMDC_XACT_RD30 0x19d8 638#define EARCRX_CMDC_XACT_RD31 0x19dc 639#define EARCRX_CMDC_XACT_RD32 0x19e0 640#define EARCRX_CMDC_XACT_RD33 0x19e4 641#define EARCRX_CMDC_XACT_RD34 0x19e8 642#define EARCRX_CMDC_XACT_RD35 0x19ec 643#define EARCRX_CMDC_XACT_RD36 0x19f0 644#define EARCRX_CMDC_XACT_RD37 0x19f4 645#define EARCRX_CMDC_XACT_RD38 0x19f8 646#define EARCRX_CMDC_XACT_RD39 0x19fc 647#define EARCRX_CMDC_XACT_RD40 0x1a00 648#define EARCRX_CMDC_XACT_RD41 0x1a04 649#define EARCRX_CMDC_XACT_RD42 0x1a08 650#define EARCRX_CMDC_XACT_RD43 0x1a0c 651#define EARCRX_CMDC_XACT_RD44 0x1a10 652#define EARCRX_CMDC_XACT_RD45 0x1a14 653#define EARCRX_CMDC_XACT_RD46 0x1a18 654#define EARCRX_CMDC_XACT_RD47 0x1a1c 655#define EARCRX_CMDC_XACT_RD48 0x1a20 656#define EARCRX_CMDC_XACT_RD49 0x1a24 657#define EARCRX_CMDC_XACT_RD50 0x1a28 658#define EARCRX_CMDC_XACT_RD51 0x1a2c 659#define EARCRX_CMDC_XACT_RD52 0x1a30 660#define EARCRX_CMDC_XACT_RD53 0x1a34 661#define EARCRX_CMDC_XACT_RD54 0x1a38 662#define EARCRX_CMDC_XACT_RD55 0x1a3c 663#define EARCRX_CMDC_XACT_RD56 0x1a40 664#define EARCRX_CMDC_XACT_RD57 0x1a44 665#define EARCRX_CMDC_XACT_RD58 0x1a48 666#define EARCRX_CMDC_XACT_RD59 0x1a4c 667#define EARCRX_CMDC_XACT_RD60 0x1a50 668#define EARCRX_CMDC_XACT_RD61 0x1a54 669#define EARCRX_CMDC_XACT_RD62 0x1a58 670#define EARCRX_CMDC_XACT_RD63 0x1a5c 671#define EARCRX_CMDC_XACT_RD64 0x1a60 672#define EARCRX_CMDC_SYNC_CONFIG 0x1b00 673/* eARC RX DMAC Registers */ 674#define EARCRX_DMAC_PHY_CONTROL 0x1c00 675#define EARCRX_DMAC_CONFIG 0x1c08 676#define EARCRX_DMAC_CONTROL0 0x1c0c 677#define EARCRX_DMAC_AUDIO_EN BIT(1) 678#define EARCRX_DMAC_EN BIT(0) 679#define EARCRX_DMAC_CONTROL1 0x1c10 680#define EARCRX_DMAC_STATUS 0x1c14 681#define EARCRX_DMAC_CHSTATUS0 0x1c18 682#define EARCRX_DMAC_CHSTATUS1 0x1c1c 683#define EARCRX_DMAC_CHSTATUS2 0x1c20 684#define EARCRX_DMAC_CHSTATUS3 0x1c24 685#define EARCRX_DMAC_CHSTATUS4 0x1c28 686#define EARCRX_DMAC_CHSTATUS5 0x1c2c 687#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC0 0x1c30 688#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC1 0x1c34 689#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC2 0x1c38 690#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC3 0x1c3c 691#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC4 0x1c40 692#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC5 0x1c44 693#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC6 0x1c48 694#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC7 0x1c4c 695#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC8 0x1c50 696#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC9 0x1c54 697#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC10 0x1c58 698#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC11 0x1c5c 699#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT0 0x1c60 700#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT1 0x1c64 701#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT2 0x1c68 702#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT3 0x1c6c 703#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT4 0x1c70 704#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT5 0x1c74 705#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT6 0x1c78 706#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT7 0x1c7c 707#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT8 0x1c80 708#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT9 0x1c84 709#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT10 0x1c88 710#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT11 0x1c8c 711#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT0 0x1c90 712#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT1 0x1c94 713#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT2 0x1c98 714#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT3 0x1c9c 715#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT4 0x1ca0 716#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT5 0x1ca4 717#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT6 0x1ca8 718#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT7 0x1cac 719#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT8 0x1cb0 720#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT9 0x1cb4 721#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT10 0x1cb8 722#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT11 0x1cbc 723#define EARCRX_DMAC_USRDATA_MSG_GENERIC0 0x1cc0 724#define EARCRX_DMAC_USRDATA_MSG_GENERIC1 0x1cc4 725#define EARCRX_DMAC_USRDATA_MSG_GENERIC2 0x1cc8 726#define EARCRX_DMAC_USRDATA_MSG_GENERIC3 0x1ccc 727#define EARCRX_DMAC_USRDATA_MSG_GENERIC4 0x1cd0 728#define EARCRX_DMAC_USRDATA_MSG_GENERIC5 0x1cd4 729#define EARCRX_DMAC_USRDATA_MSG_GENERIC6 0x1cd8 730#define EARCRX_DMAC_USRDATA_MSG_GENERIC7 0x1cdc 731#define EARCRX_DMAC_USRDATA_MSG_GENERIC8 0x1ce0 732#define EARCRX_DMAC_USRDATA_MSG_GENERIC9 0x1ce4 733#define EARCRX_DMAC_USRDATA_MSG_GENERIC10 0x1ce8 734#define EARCRX_DMAC_USRDATA_MSG_GENERIC11 0x1cec 735#define EARCRX_DMAC_USRDATA_MSG_GENERIC12 0x1cf0 736#define EARCRX_DMAC_USRDATA_MSG_GENERIC13 0x1cf4 737#define EARCRX_DMAC_USRDATA_MSG_GENERIC14 0x1cf8 738#define EARCRX_DMAC_USRDATA_MSG_GENERIC15 0x1cfc 739#define EARCRX_DMAC_USRDATA_MSG_GENERIC16 0x1d00 740#define EARCRX_DMAC_USRDATA_MSG_GENERIC17 0x1d04 741#define EARCRX_DMAC_USRDATA_MSG_GENERIC18 0x1d08 742#define EARCRX_DMAC_USRDATA_MSG_GENERIC19 0x1d0c 743#define EARCRX_DMAC_USRDATA_MSG_GENERIC20 0x1d10 744#define EARCRX_DMAC_USRDATA_MSG_GENERIC21 0x1d14 745#define EARCRX_DMAC_USRDATA_MSG_GENERIC22 0x1d18 746#define EARCRX_DMAC_USRDATA_MSG_GENERIC23 0x1d1c 747#define EARCRX_DMAC_USRDATA_MSG_GENERIC24 0x1d20 748#define EARCRX_DMAC_USRDATA_MSG_GENERIC25 0x1d24 749#define EARCRX_DMAC_USRDATA_MSG_GENERIC26 0x1d28 750#define EARCRX_DMAC_USRDATA_MSG_GENERIC27 0x1d2c 751#define EARCRX_DMAC_USRDATA_MSG_GENERIC28 0x1d30 752#define EARCRX_DMAC_USRDATA_MSG_GENERIC29 0x1d34 753#define EARCRX_DMAC_USRDATA_MSG_GENERIC30 0x1d38 754#define EARCRX_DMAC_USRDATA_MSG_GENERIC31 0x1d3c 755#define EARCRX_DMAC_USRDATA_MSG_GENERIC32 0x1d40 756#define EARCRX_DMAC_CHSTATUS_STREAMER0 0x1d44 757#define EARCRX_DMAC_CHSTATUS_STREAMER1 0x1d48 758#define EARCRX_DMAC_CHSTATUS_STREAMER2 0x1d4c 759#define EARCRX_DMAC_CHSTATUS_STREAMER3 0x1d50 760#define EARCRX_DMAC_CHSTATUS_STREAMER4 0x1d54 761#define EARCRX_DMAC_CHSTATUS_STREAMER5 0x1d58 762#define EARCRX_DMAC_CHSTATUS_STREAMER6 0x1d5c 763#define EARCRX_DMAC_CHSTATUS_STREAMER7 0x1d60 764#define EARCRX_DMAC_CHSTATUS_STREAMER8 0x1d64 765#define EARCRX_DMAC_CHSTATUS_STREAMER9 0x1d68 766#define EARCRX_DMAC_CHSTATUS_STREAMER10 0x1d6c 767#define EARCRX_DMAC_CHSTATUS_STREAMER11 0x1d70 768#define EARCRX_DMAC_CHSTATUS_STREAMER12 0x1d74 769#define EARCRX_DMAC_CHSTATUS_STREAMER13 0x1d78 770#define EARCRX_DMAC_CHSTATUS_STREAMER14 0x1d7c 771#define EARCRX_DMAC_USRDATA_STREAMER0 0x1d80 772/* Main Unit Interrupt Registers */ 773#define MAIN_INTVEC_INDEX 0x3000 774#define MAINUNIT_0_INT_STATUS 0x3010 775#define MAINUNIT_0_INT_MASK_N 0x3014 776#define MAINUNIT_0_INT_CLEAR 0x3018 777#define MAINUNIT_0_INT_FORCE 0x301c 778#define MAINUNIT_1_INT_STATUS 0x3020 779#define FLT_EXIT_TO_LTSL_IRQ BIT(22) 780#define FLT_EXIT_TO_LTS4_IRQ BIT(21) 781#define FLT_EXIT_TO_LTSP_IRQ BIT(20) 782#define SCDC_NACK_RCVD_IRQ BIT(12) 783#define SCDC_RR_REPLY_STOP_IRQ BIT(11) 784#define SCDC_UPD_FLAGS_CLR_IRQ BIT(10) 785#define SCDC_UPD_FLAGS_CHG_IRQ BIT(9) 786#define SCDC_UPD_FLAGS_RD_IRQ BIT(8) 787#define I2CM_NACK_RCVD_IRQ BIT(2) 788#define I2CM_READ_REQUEST_IRQ BIT(1) 789#define I2CM_OP_DONE_IRQ BIT(0) 790#define MAINUNIT_1_INT_MASK_N 0x3024 791#define I2CM_NACK_RCVD_MASK_N BIT(2) 792#define I2CM_READ_REQUEST_MASK_N BIT(1) 793#define I2CM_OP_DONE_MASK_N BIT(0) 794#define MAINUNIT_1_INT_CLEAR 0x3028 795#define I2CM_NACK_RCVD_CLEAR BIT(2) 796#define I2CM_READ_REQUEST_CLEAR BIT(1) 797#define I2CM_OP_DONE_CLEAR BIT(0) 798#define MAINUNIT_1_INT_FORCE 0x302c 799/* AVPUNIT Interrupt Registers */ 800#define AVP_INTVEC_INDEX 0x3800 801#define AVP_0_INT_STATUS 0x3810 802#define AVP_0_INT_MASK_N 0x3814 803#define AVP_0_INT_CLEAR 0x3818 804#define AVP_0_INT_FORCE 0x381c 805#define AVP_1_INT_STATUS 0x3820 806#define AVP_1_INT_MASK_N 0x3824 807#define HDCP14_AUTH_CHG_MASK_N BIT(6) 808#define AVP_1_INT_CLEAR 0x3828 809#define AVP_1_INT_FORCE 0x382c 810#define AVP_2_INT_STATUS 0x3830 811#define AVP_2_INT_MASK_N 0x3834 812#define AVP_2_INT_CLEAR 0x3838 813#define AVP_2_INT_FORCE 0x383c 814#define AVP_3_INT_STATUS 0x3840 815#define AVP_3_INT_MASK_N 0x3844 816#define AVP_3_INT_CLEAR 0x3848 817#define AVP_3_INT_FORCE 0x384c 818#define AVP_4_INT_STATUS 0x3850 819#define AVP_4_INT_MASK_N 0x3854 820#define AVP_4_INT_CLEAR 0x3858 821#define AVP_4_INT_FORCE 0x385c 822#define AVP_5_INT_STATUS 0x3860 823#define AVP_5_INT_MASK_N 0x3864 824#define AVP_5_INT_CLEAR 0x3868 825#define AVP_5_INT_FORCE 0x386c 826#define AVP_6_INT_STATUS 0x3870 827#define AVP_6_INT_MASK_N 0x3874 828#define AVP_6_INT_CLEAR 0x3878 829#define AVP_6_INT_FORCE 0x387c 830/* CEC Interrupt Registers */ 831#define CEC_INT_STATUS 0x4000 832#define CEC_INT_MASK_N 0x4004 833#define CEC_INT_CLEAR 0x4008 834#define CEC_INT_FORCE 0x400c 835/* eARC RX Interrupt Registers */ 836#define EARCRX_INTVEC_INDEX 0x4800 837#define EARCRX_0_INT_STATUS 0x4810 838#define EARCRX_CMDC_DISCOVERY_TIMEOUT_IRQ BIT(9) 839#define EARCRX_CMDC_DISCOVERY_DONE_IRQ BIT(8) 840#define EARCRX_0_INT_MASK_N 0x4814 841#define EARCRX_0_INT_CLEAR 0x4818 842#define EARCRX_0_INT_FORCE 0x481c 843#define EARCRX_1_INT_STATUS 0x4820 844#define EARCRX_1_INT_MASK_N 0x4824 845#define EARCRX_1_INT_CLEAR 0x4828 846#define EARCRX_1_INT_FORCE 0x482c 847 848#endif /* __DW_HDMI_QP_H__ */
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