dw-hdmi-qp.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
   4 * Copyright (c) 2024 Collabora Ltd.
   5 *
   6 * Author: Algea Cao <algea.cao@rock-chips.com>
   7 * Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
   8 */
   9#include <linux/completion.h>
  10#include <linux/hdmi.h>
  11#include <linux/export.h>
  12#include <linux/i2c.h>
  13#include <linux/irq.h>
  14#include <linux/module.h>
  15#include <linux/mutex.h>
  16#include <linux/of.h>
  17#include <linux/workqueue.h>
  18
  19#include <drm/bridge/dw_hdmi_qp.h>
  20#include <drm/display/drm_hdmi_helper.h>
  21#include <drm/display/drm_hdmi_cec_helper.h>
  22#include <drm/display/drm_hdmi_state_helper.h>
  23#include <drm/drm_atomic.h>
  24#include <drm/drm_atomic_helper.h>
  25#include <drm/drm_bridge.h>
  26#include <drm/drm_connector.h>
  27#include <drm/drm_edid.h>
  28#include <drm/drm_modes.h>
  29
  30#include <media/cec.h>
  31
  32#include <sound/hdmi-codec.h>
  33
  34#include "dw-hdmi-qp.h"
  35
  36#define DDC_CI_ADDR		0x37
  37#define DDC_SEGMENT_ADDR	0x30
  38
  39#define HDMI14_MAX_TMDSCLK	340000000
  40
  41#define SCRAMB_POLL_DELAY_MS	3000
  42
  43/*
  44 * Unless otherwise noted, entries in this table are 100% optimization.
  45 * Values can be obtained from dw_hdmi_qp_compute_n() but that function is
  46 * slow so we pre-compute values we expect to see.
  47 *
  48 * The values for TMDS 25175, 25200, 27000, 54000, 74250 and 148500 kHz are
  49 * the recommended N values specified in the Audio chapter of the HDMI
  50 * specification.
  51 */
  52static const struct dw_hdmi_audio_tmds_n {
  53	unsigned long tmds;
  54	unsigned int n_32k;
  55	unsigned int n_44k1;
  56	unsigned int n_48k;
  57} common_tmds_n_table[] = {
  58	{ .tmds = 25175000,  .n_32k = 4576,  .n_44k1 = 7007,  .n_48k = 6864, },
  59	{ .tmds = 25200000,  .n_32k = 4096,  .n_44k1 = 6272,  .n_48k = 6144, },
  60	{ .tmds = 27000000,  .n_32k = 4096,  .n_44k1 = 6272,  .n_48k = 6144, },
  61	{ .tmds = 28320000,  .n_32k = 4096,  .n_44k1 = 5586,  .n_48k = 6144, },
  62	{ .tmds = 30240000,  .n_32k = 4096,  .n_44k1 = 5642,  .n_48k = 6144, },
  63	{ .tmds = 31500000,  .n_32k = 4096,  .n_44k1 = 5600,  .n_48k = 6144, },
  64	{ .tmds = 32000000,  .n_32k = 4096,  .n_44k1 = 5733,  .n_48k = 6144, },
  65	{ .tmds = 33750000,  .n_32k = 4096,  .n_44k1 = 6272,  .n_48k = 6144, },
  66	{ .tmds = 36000000,  .n_32k = 4096,  .n_44k1 = 5684,  .n_48k = 6144, },
  67	{ .tmds = 40000000,  .n_32k = 4096,  .n_44k1 = 5733,  .n_48k = 6144, },
  68	{ .tmds = 49500000,  .n_32k = 4096,  .n_44k1 = 5488,  .n_48k = 6144, },
  69	{ .tmds = 50000000,  .n_32k = 4096,  .n_44k1 = 5292,  .n_48k = 6144, },
  70	{ .tmds = 54000000,  .n_32k = 4096,  .n_44k1 = 6272,  .n_48k = 6144, },
  71	{ .tmds = 65000000,  .n_32k = 4096,  .n_44k1 = 7056,  .n_48k = 6144, },
  72	{ .tmds = 68250000,  .n_32k = 4096,  .n_44k1 = 5376,  .n_48k = 6144, },
  73	{ .tmds = 71000000,  .n_32k = 4096,  .n_44k1 = 7056,  .n_48k = 6144, },
  74	{ .tmds = 72000000,  .n_32k = 4096,  .n_44k1 = 5635,  .n_48k = 6144, },
  75	{ .tmds = 73250000,  .n_32k = 11648, .n_44k1 = 14112, .n_48k = 6144, },
  76	{ .tmds = 74250000,  .n_32k = 4096,  .n_44k1 = 6272,  .n_48k = 6144, },
  77	{ .tmds = 75000000,  .n_32k = 4096,  .n_44k1 = 5880,  .n_48k = 6144, },
  78	{ .tmds = 78750000,  .n_32k = 4096,  .n_44k1 = 5600,  .n_48k = 6144, },
  79	{ .tmds = 78800000,  .n_32k = 4096,  .n_44k1 = 5292,  .n_48k = 6144, },
  80	{ .tmds = 79500000,  .n_32k = 4096,  .n_44k1 = 4704,  .n_48k = 6144, },
  81	{ .tmds = 83500000,  .n_32k = 4096,  .n_44k1 = 7056,  .n_48k = 6144, },
  82	{ .tmds = 85500000,  .n_32k = 4096,  .n_44k1 = 5488,  .n_48k = 6144, },
  83	{ .tmds = 88750000,  .n_32k = 4096,  .n_44k1 = 14112, .n_48k = 6144, },
  84	{ .tmds = 97750000,  .n_32k = 4096,  .n_44k1 = 14112, .n_48k = 6144, },
  85	{ .tmds = 101000000, .n_32k = 4096,  .n_44k1 = 7056,  .n_48k = 6144, },
  86	{ .tmds = 106500000, .n_32k = 4096,  .n_44k1 = 4704,  .n_48k = 6144, },
  87	{ .tmds = 108000000, .n_32k = 4096,  .n_44k1 = 5684,  .n_48k = 6144, },
  88	{ .tmds = 115500000, .n_32k = 4096,  .n_44k1 = 5712,  .n_48k = 6144, },
  89	{ .tmds = 119000000, .n_32k = 4096,  .n_44k1 = 5544,  .n_48k = 6144, },
  90	{ .tmds = 135000000, .n_32k = 4096,  .n_44k1 = 5488,  .n_48k = 6144, },
  91	{ .tmds = 146250000, .n_32k = 11648, .n_44k1 = 6272,  .n_48k = 6144, },
  92	{ .tmds = 148500000, .n_32k = 4096,  .n_44k1 = 6272,  .n_48k = 6144, },
  93	{ .tmds = 154000000, .n_32k = 4096,  .n_44k1 = 5544,  .n_48k = 6144, },
  94	{ .tmds = 162000000, .n_32k = 4096,  .n_44k1 = 5684,  .n_48k = 6144, },
  95
  96	/* For 297 MHz+ HDMI spec have some other rule for setting N */
  97	{ .tmds = 297000000, .n_32k = 3073,  .n_44k1 = 4704,  .n_48k = 5120, },
  98	{ .tmds = 594000000, .n_32k = 3073,  .n_44k1 = 9408,  .n_48k = 10240,},
  99
 100	/* End of table */
 101	{ .tmds = 0,         .n_32k = 0,     .n_44k1 = 0,     .n_48k = 0,    },
 102};
 103
 104/*
 105 * These are the CTS values as recommended in the Audio chapter of the HDMI
 106 * specification.
 107 */
 108static const struct dw_hdmi_audio_tmds_cts {
 109	unsigned long tmds;
 110	unsigned int cts_32k;
 111	unsigned int cts_44k1;
 112	unsigned int cts_48k;
 113} common_tmds_cts_table[] = {
 114	{ .tmds = 25175000,  .cts_32k = 28125,  .cts_44k1 = 31250,  .cts_48k = 28125,  },
 115	{ .tmds = 25200000,  .cts_32k = 25200,  .cts_44k1 = 28000,  .cts_48k = 25200,  },
 116	{ .tmds = 27000000,  .cts_32k = 27000,  .cts_44k1 = 30000,  .cts_48k = 27000,  },
 117	{ .tmds = 54000000,  .cts_32k = 54000,  .cts_44k1 = 60000,  .cts_48k = 54000,  },
 118	{ .tmds = 74250000,  .cts_32k = 74250,  .cts_44k1 = 82500,  .cts_48k = 74250,  },
 119	{ .tmds = 148500000, .cts_32k = 148500, .cts_44k1 = 165000, .cts_48k = 148500, },
 120
 121	/* End of table */
 122	{ .tmds = 0,         .cts_32k = 0,      .cts_44k1 = 0,      .cts_48k = 0,      },
 123};
 124
 125struct dw_hdmi_qp_i2c {
 126	struct i2c_adapter	adap;
 127
 128	struct mutex		lock;	/* used to serialize data transfers */
 129	struct completion	cmp;
 130	u8			stat;
 131
 132	u8			slave_reg;
 133	bool			is_regaddr;
 134	bool			is_segment;
 135};
 136
 137#ifdef CONFIG_DRM_DW_HDMI_QP_CEC
 138struct dw_hdmi_qp_cec {
 139	struct drm_connector *connector;
 140	int irq;
 141	u32 addresses;
 142	struct cec_msg rx_msg;
 143	u8 tx_status;
 144	bool tx_done;
 145	bool rx_done;
 146};
 147#endif
 148
 149struct dw_hdmi_qp {
 150	struct drm_bridge bridge;
 151
 152	struct device *dev;
 153	struct dw_hdmi_qp_i2c *i2c;
 154
 155#ifdef CONFIG_DRM_DW_HDMI_QP_CEC
 156	struct dw_hdmi_qp_cec *cec;
 157#endif
 158
 159	struct {
 160		const struct dw_hdmi_qp_phy_ops *ops;
 161		void *data;
 162	} phy;
 163
 164	unsigned long ref_clk_rate;
 165	struct regmap *regm;
 166	int main_irq;
 167
 168	unsigned long tmds_char_rate;
 169};
 170
 171static void dw_hdmi_qp_write(struct dw_hdmi_qp *hdmi, unsigned int val,
 172			     int offset)
 173{
 174	regmap_write(hdmi->regm, offset, val);
 175}
 176
 177static unsigned int dw_hdmi_qp_read(struct dw_hdmi_qp *hdmi, int offset)
 178{
 179	unsigned int val = 0;
 180
 181	regmap_read(hdmi->regm, offset, &val);
 182
 183	return val;
 184}
 185
 186static void dw_hdmi_qp_mod(struct dw_hdmi_qp *hdmi, unsigned int data,
 187			   unsigned int mask, unsigned int reg)
 188{
 189	regmap_update_bits(hdmi->regm, reg, mask, data);
 190}
 191
 192static struct dw_hdmi_qp *dw_hdmi_qp_from_bridge(struct drm_bridge *bridge)
 193{
 194	return container_of(bridge, struct dw_hdmi_qp, bridge);
 195}
 196
 197static void dw_hdmi_qp_set_cts_n(struct dw_hdmi_qp *hdmi, unsigned int cts,
 198				 unsigned int n)
 199{
 200	/* Set N */
 201	dw_hdmi_qp_mod(hdmi, n, AUDPKT_ACR_N_VALUE, AUDPKT_ACR_CONTROL0);
 202
 203	/* Set CTS */
 204	if (cts)
 205		dw_hdmi_qp_mod(hdmi, AUDPKT_ACR_CTS_OVR_EN, AUDPKT_ACR_CTS_OVR_EN_MSK,
 206			       AUDPKT_ACR_CONTROL1);
 207	else
 208		dw_hdmi_qp_mod(hdmi, 0, AUDPKT_ACR_CTS_OVR_EN_MSK,
 209			       AUDPKT_ACR_CONTROL1);
 210
 211	dw_hdmi_qp_mod(hdmi, AUDPKT_ACR_CTS_OVR_VAL(cts), AUDPKT_ACR_CTS_OVR_VAL_MSK,
 212		       AUDPKT_ACR_CONTROL1);
 213}
 214
 215static int dw_hdmi_qp_match_tmds_n_table(struct dw_hdmi_qp *hdmi,
 216					 unsigned long pixel_clk,
 217					 unsigned long freq)
 218{
 219	const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
 220	int i;
 221
 222	for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
 223		if (pixel_clk == common_tmds_n_table[i].tmds) {
 224			tmds_n = &common_tmds_n_table[i];
 225			break;
 226		}
 227	}
 228
 229	if (!tmds_n)
 230		return -ENOENT;
 231
 232	switch (freq) {
 233	case 32000:
 234		return tmds_n->n_32k;
 235	case 44100:
 236	case 88200:
 237	case 176400:
 238		return (freq / 44100) * tmds_n->n_44k1;
 239	case 48000:
 240	case 96000:
 241	case 192000:
 242		return (freq / 48000) * tmds_n->n_48k;
 243	default:
 244		return -ENOENT;
 245	}
 246}
 247
 248static u32 dw_hdmi_qp_audio_math_diff(unsigned int freq, unsigned int n,
 249				      unsigned int pixel_clk)
 250{
 251	u64 cts = mul_u32_u32(pixel_clk, n);
 252
 253	return do_div(cts, 128 * freq);
 254}
 255
 256static unsigned int dw_hdmi_qp_compute_n(struct dw_hdmi_qp *hdmi,
 257					 unsigned long pixel_clk,
 258					 unsigned long freq)
 259{
 260	unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
 261	unsigned int max_n = (128 * freq) / 300;
 262	unsigned int ideal_n = (128 * freq) / 1000;
 263	unsigned int best_n_distance = ideal_n;
 264	unsigned int best_n = 0;
 265	u64 best_diff = U64_MAX;
 266	int n;
 267
 268	/* If the ideal N could satisfy the audio math, then just take it */
 269	if (dw_hdmi_qp_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
 270		return ideal_n;
 271
 272	for (n = min_n; n <= max_n; n++) {
 273		u64 diff = dw_hdmi_qp_audio_math_diff(freq, n, pixel_clk);
 274
 275		if (diff < best_diff ||
 276		    (diff == best_diff && abs(n - ideal_n) < best_n_distance)) {
 277			best_n = n;
 278			best_diff = diff;
 279			best_n_distance = abs(best_n - ideal_n);
 280		}
 281
 282		/*
 283		 * The best N already satisfy the audio math, and also be
 284		 * the closest value to ideal N, so just cut the loop.
 285		 */
 286		if (best_diff == 0 && (abs(n - ideal_n) > best_n_distance))
 287			break;
 288	}
 289
 290	return best_n;
 291}
 292
 293static unsigned int dw_hdmi_qp_find_n(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk,
 294				      unsigned long sample_rate)
 295{
 296	int n = dw_hdmi_qp_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
 297
 298	if (n > 0)
 299		return n;
 300
 301	dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
 302		 pixel_clk);
 303
 304	return dw_hdmi_qp_compute_n(hdmi, pixel_clk, sample_rate);
 305}
 306
 307static unsigned int dw_hdmi_qp_find_cts(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk,
 308					unsigned long sample_rate)
 309{
 310	const struct dw_hdmi_audio_tmds_cts *tmds_cts = NULL;
 311	int i;
 312
 313	for (i = 0; common_tmds_cts_table[i].tmds != 0; i++) {
 314		if (pixel_clk == common_tmds_cts_table[i].tmds) {
 315			tmds_cts = &common_tmds_cts_table[i];
 316			break;
 317		}
 318	}
 319
 320	if (!tmds_cts)
 321		return 0;
 322
 323	switch (sample_rate) {
 324	case 32000:
 325		return tmds_cts->cts_32k;
 326	case 44100:
 327	case 88200:
 328	case 176400:
 329		return tmds_cts->cts_44k1;
 330	case 48000:
 331	case 96000:
 332	case 192000:
 333		return tmds_cts->cts_48k;
 334	default:
 335		return -ENOENT;
 336	}
 337}
 338
 339static void dw_hdmi_qp_set_audio_interface(struct dw_hdmi_qp *hdmi,
 340					   struct hdmi_codec_daifmt *fmt,
 341					   struct hdmi_codec_params *hparms)
 342{
 343	u32 conf0 = 0;
 344
 345	/* Reset the audio data path of the AVP */
 346	dw_hdmi_qp_write(hdmi, AVP_DATAPATH_PACKET_AUDIO_SWINIT_P, GLOBAL_SWRESET_REQUEST);
 347
 348	/* Disable AUDS, ACR, AUDI */
 349	dw_hdmi_qp_mod(hdmi, 0,
 350		       PKTSCHED_ACR_TX_EN | PKTSCHED_AUDS_TX_EN | PKTSCHED_AUDI_TX_EN,
 351		       PKTSCHED_PKT_EN);
 352
 353	/* Clear the audio FIFO */
 354	dw_hdmi_qp_write(hdmi, AUDIO_FIFO_CLR_P, AUDIO_INTERFACE_CONTROL0);
 355
 356	/* Select I2S interface as the audio source */
 357	dw_hdmi_qp_mod(hdmi, AUD_IF_I2S, AUD_IF_SEL_MSK, AUDIO_INTERFACE_CONFIG0);
 358
 359	/* Enable the active i2s lanes */
 360	switch (hparms->channels) {
 361	case 7 ... 8:
 362		conf0 |= I2S_LINES_EN(3);
 363		fallthrough;
 364	case 5 ... 6:
 365		conf0 |= I2S_LINES_EN(2);
 366		fallthrough;
 367	case 3 ... 4:
 368		conf0 |= I2S_LINES_EN(1);
 369		fallthrough;
 370	default:
 371		conf0 |= I2S_LINES_EN(0);
 372		break;
 373	}
 374
 375	dw_hdmi_qp_mod(hdmi, conf0, I2S_LINES_EN_MSK, AUDIO_INTERFACE_CONFIG0);
 376
 377	/*
 378	 * Enable bpcuv generated internally for L-PCM, or received
 379	 * from stream for NLPCM/HBR.
 380	 */
 381	switch (fmt->bit_fmt) {
 382	case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
 383		conf0 = (hparms->channels == 8) ? AUD_HBR : AUD_ASP;
 384		conf0 |= I2S_BPCUV_RCV_EN;
 385		break;
 386	default:
 387		conf0 = AUD_ASP | I2S_BPCUV_RCV_DIS;
 388		break;
 389	}
 390
 391	dw_hdmi_qp_mod(hdmi, conf0, I2S_BPCUV_RCV_MSK | AUD_FORMAT_MSK,
 392		       AUDIO_INTERFACE_CONFIG0);
 393
 394	/* Enable audio FIFO auto clear when overflow */
 395	dw_hdmi_qp_mod(hdmi, AUD_FIFO_INIT_ON_OVF_EN, AUD_FIFO_INIT_ON_OVF_MSK,
 396		       AUDIO_INTERFACE_CONFIG0);
 397}
 398
 399/*
 400 * When transmitting IEC60958 linear PCM audio, these registers allow to
 401 * configure the channel status information of all the channel status
 402 * bits in the IEC60958 frame. For the moment this configuration is only
 403 * used when the I2S audio interface, General Purpose Audio (GPA),
 404 * or AHB audio DMA (AHBAUDDMA) interface is active
 405 * (for S/PDIF interface this information comes from the stream).
 406 */
 407static void dw_hdmi_qp_set_channel_status(struct dw_hdmi_qp *hdmi,
 408					  u8 *channel_status, bool ref2stream)
 409{
 410	/*
 411	 * AUDPKT_CHSTATUS_OVR0: { RSV, RSV, CS1, CS0 }
 412	 * AUDPKT_CHSTATUS_OVR1: { CS6, CS5, CS4, CS3 }
 413	 *
 414	 *      |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
 415	 * CS0: |   Mode    |        d        |  c  |  b  |  a  |
 416	 * CS1: |               Category Code                   |
 417	 * CS2: |    Channel Number     |     Source Number     |
 418	 * CS3: |    Clock Accuracy     |     Sample Freq       |
 419	 * CS4: |    Ori Sample Freq    |     Word Length       |
 420	 * CS5: |                                   |   CGMS-A  |
 421	 * CS6~CS23: Reserved
 422	 *
 423	 * a: use of channel status block
 424	 * b: linear PCM identification: 0 for lpcm, 1 for nlpcm
 425	 * c: copyright information
 426	 * d: additional format information
 427	 */
 428
 429	if (ref2stream)
 430		channel_status[0] |= IEC958_AES0_NONAUDIO;
 431
 432	if ((dw_hdmi_qp_read(hdmi, AUDIO_INTERFACE_CONFIG0) & GENMASK(25, 24)) == AUD_HBR) {
 433		/* fixup cs for HBR */
 434		channel_status[3] = (channel_status[3] & 0xf0) | IEC958_AES3_CON_FS_768000;
 435		channel_status[4] = (channel_status[4] & 0x0f) | IEC958_AES4_CON_ORIGFS_NOTID;
 436	}
 437
 438	dw_hdmi_qp_write(hdmi, channel_status[0] | (channel_status[1] << 8),
 439			 AUDPKT_CHSTATUS_OVR0);
 440
 441	regmap_bulk_write(hdmi->regm, AUDPKT_CHSTATUS_OVR1, &channel_status[3], 1);
 442
 443	if (ref2stream)
 444		dw_hdmi_qp_mod(hdmi, 0,
 445			       AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK,
 446			       AUDPKT_CONTROL0);
 447	else
 448		dw_hdmi_qp_mod(hdmi, AUDPKT_PBIT_FORCE_EN | AUDPKT_CHSTATUS_OVR_EN,
 449			       AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK,
 450			       AUDPKT_CONTROL0);
 451}
 452
 453static void dw_hdmi_qp_set_sample_rate(struct dw_hdmi_qp *hdmi, unsigned long long tmds_char_rate,
 454				       unsigned int sample_rate)
 455{
 456	unsigned int n, cts;
 457
 458	n = dw_hdmi_qp_find_n(hdmi, tmds_char_rate, sample_rate);
 459	cts = dw_hdmi_qp_find_cts(hdmi, tmds_char_rate, sample_rate);
 460
 461	dw_hdmi_qp_set_cts_n(hdmi, cts, n);
 462}
 463
 464static int dw_hdmi_qp_audio_enable(struct drm_bridge *bridge,
 465				   struct drm_connector *connector)
 466{
 467	struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge);
 468
 469	if (hdmi->tmds_char_rate)
 470		dw_hdmi_qp_mod(hdmi, 0, AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, GLOBAL_SWDISABLE);
 471
 472	return 0;
 473}
 474
 475static int dw_hdmi_qp_audio_prepare(struct drm_bridge *bridge,
 476				    struct drm_connector *connector,
 477				    struct hdmi_codec_daifmt *fmt,
 478				    struct hdmi_codec_params *hparms)
 479{
 480	struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge);
 481	bool ref2stream = false;
 482
 483	if (!hdmi->tmds_char_rate)
 484		return -ENODEV;
 485
 486	if (fmt->bit_clk_provider | fmt->frame_clk_provider) {
 487		dev_err(hdmi->dev, "unsupported clock settings\n");
 488		return -EINVAL;
 489	}
 490
 491	if (fmt->bit_fmt == SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE)
 492		ref2stream = true;
 493
 494	dw_hdmi_qp_set_audio_interface(hdmi, fmt, hparms);
 495	dw_hdmi_qp_set_sample_rate(hdmi, hdmi->tmds_char_rate, hparms->sample_rate);
 496	dw_hdmi_qp_set_channel_status(hdmi, hparms->iec.status, ref2stream);
 497	drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector, &hparms->cea);
 498
 499	return 0;
 500}
 501
 502static void dw_hdmi_qp_audio_disable_regs(struct dw_hdmi_qp *hdmi)
 503{
 504	/*
 505	 * Keep ACR, AUDI, AUDS packet always on to make SINK device
 506	 * active for better compatibility and user experience.
 507	 *
 508	 * This also fix POP sound on some SINK devices which wakeup
 509	 * from suspend to active.
 510	 */
 511	dw_hdmi_qp_mod(hdmi, I2S_BPCUV_RCV_DIS, I2S_BPCUV_RCV_MSK,
 512		       AUDIO_INTERFACE_CONFIG0);
 513	dw_hdmi_qp_mod(hdmi, AUDPKT_PBIT_FORCE_EN | AUDPKT_CHSTATUS_OVR_EN,
 514		       AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK,
 515		       AUDPKT_CONTROL0);
 516
 517	dw_hdmi_qp_mod(hdmi, AVP_DATAPATH_PACKET_AUDIO_SWDISABLE,
 518		       AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, GLOBAL_SWDISABLE);
 519}
 520
 521static void dw_hdmi_qp_audio_disable(struct drm_bridge *bridge,
 522				     struct drm_connector *connector)
 523{
 524	struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge);
 525
 526	drm_atomic_helper_connector_hdmi_clear_audio_infoframe(connector);
 527
 528	if (hdmi->tmds_char_rate)
 529		dw_hdmi_qp_audio_disable_regs(hdmi);
 530}
 531
 532static int dw_hdmi_qp_i2c_read(struct dw_hdmi_qp *hdmi,
 533			       unsigned char *buf, unsigned int length)
 534{
 535	struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
 536	int stat;
 537
 538	if (!i2c->is_regaddr) {
 539		dev_dbg(hdmi->dev, "set read register address to 0\n");
 540		i2c->slave_reg = 0x00;
 541		i2c->is_regaddr = true;
 542	}
 543
 544	while (length--) {
 545		reinit_completion(&i2c->cmp);
 546
 547		dw_hdmi_qp_mod(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR,
 548			       I2CM_INTERFACE_CONTROL0);
 549
 550		if (i2c->is_segment)
 551			dw_hdmi_qp_mod(hdmi, I2CM_EXT_READ, I2CM_WR_MASK,
 552				       I2CM_INTERFACE_CONTROL0);
 553		else
 554			dw_hdmi_qp_mod(hdmi, I2CM_FM_READ, I2CM_WR_MASK,
 555				       I2CM_INTERFACE_CONTROL0);
 556
 557		stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 558		if (!stat) {
 559			dev_err(hdmi->dev, "i2c read timed out\n");
 560			dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
 561			return -EAGAIN;
 562		}
 563
 564		/* Check for error condition on the bus */
 565		if (i2c->stat & I2CM_NACK_RCVD_IRQ) {
 566			dev_err(hdmi->dev, "i2c read error\n");
 567			dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
 568			return -EIO;
 569		}
 570
 571		*buf++ = dw_hdmi_qp_read(hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff;
 572		dw_hdmi_qp_mod(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);
 573	}
 574
 575	i2c->is_segment = false;
 576
 577	return 0;
 578}
 579
 580static int dw_hdmi_qp_i2c_write(struct dw_hdmi_qp *hdmi,
 581				unsigned char *buf, unsigned int length)
 582{
 583	struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
 584	int stat;
 585
 586	if (!i2c->is_regaddr) {
 587		/* Use the first write byte as register address */
 588		i2c->slave_reg = buf[0];
 589		length--;
 590		buf++;
 591		i2c->is_regaddr = true;
 592	}
 593
 594	while (length--) {
 595		reinit_completion(&i2c->cmp);
 596
 597		dw_hdmi_qp_write(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3);
 598		dw_hdmi_qp_mod(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR,
 599			       I2CM_INTERFACE_CONTROL0);
 600		dw_hdmi_qp_mod(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK,
 601			       I2CM_INTERFACE_CONTROL0);
 602
 603		stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 604		if (!stat) {
 605			dev_err(hdmi->dev, "i2c write time out!\n");
 606			dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
 607			return -EAGAIN;
 608		}
 609
 610		/* Check for error condition on the bus */
 611		if (i2c->stat & I2CM_NACK_RCVD_IRQ) {
 612			dev_err(hdmi->dev, "i2c write nack!\n");
 613			dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
 614			return -EIO;
 615		}
 616
 617		dw_hdmi_qp_mod(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);
 618	}
 619
 620	return 0;
 621}
 622
 623static int dw_hdmi_qp_i2c_xfer(struct i2c_adapter *adap,
 624			       struct i2c_msg *msgs, int num)
 625{
 626	struct dw_hdmi_qp *hdmi = i2c_get_adapdata(adap);
 627	struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
 628	u8 addr = msgs[0].addr;
 629	int i, ret = 0;
 630
 631	if (addr == DDC_CI_ADDR)
 632		/*
 633		 * The internal I2C controller does not support the multi-byte
 634		 * read and write operations needed for DDC/CI.
 635		 * FIXME: Blacklist the DDC/CI address until we filter out
 636		 * unsupported I2C operations.
 637		 */
 638		return -EOPNOTSUPP;
 639
 640	for (i = 0; i < num; i++) {
 641		if (msgs[i].len == 0) {
 642			dev_err(hdmi->dev,
 643				"unsupported transfer %d/%d, no data\n",
 644				i + 1, num);
 645			return -EOPNOTSUPP;
 646		}
 647	}
 648
 649	guard(mutex)(&i2c->lock);
 650
 651	/* Unmute DONE and ERROR interrupts */
 652	dw_hdmi_qp_mod(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N,
 653		       I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N,
 654		       MAINUNIT_1_INT_MASK_N);
 655
 656	/* Set slave device address taken from the first I2C message */
 657	if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1)
 658		addr = DDC_ADDR;
 659
 660	dw_hdmi_qp_mod(hdmi, addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0);
 661
 662	/* Set slave device register address on transfer */
 663	i2c->is_regaddr = false;
 664
 665	/* Set segment pointer for I2C extended read mode operation */
 666	i2c->is_segment = false;
 667
 668	for (i = 0; i < num; i++) {
 669		if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
 670			i2c->is_segment = true;
 671			dw_hdmi_qp_mod(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR,
 672				       I2CM_INTERFACE_CONTROL1);
 673			dw_hdmi_qp_mod(hdmi, *msgs[i].buf << 7, I2CM_SEG_PTR,
 674				       I2CM_INTERFACE_CONTROL1);
 675		} else {
 676			if (msgs[i].flags & I2C_M_RD)
 677				ret = dw_hdmi_qp_i2c_read(hdmi, msgs[i].buf,
 678							  msgs[i].len);
 679			else
 680				ret = dw_hdmi_qp_i2c_write(hdmi, msgs[i].buf,
 681							   msgs[i].len);
 682		}
 683		if (ret < 0)
 684			break;
 685	}
 686
 687	if (!ret)
 688		ret = num;
 689
 690	/* Mute DONE and ERROR interrupts */
 691	dw_hdmi_qp_mod(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N,
 692		       MAINUNIT_1_INT_MASK_N);
 693
 694	return ret;
 695}
 696
 697static u32 dw_hdmi_qp_i2c_func(struct i2c_adapter *adapter)
 698{
 699	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 700}
 701
 702static const struct i2c_algorithm dw_hdmi_qp_algorithm = {
 703	.master_xfer	= dw_hdmi_qp_i2c_xfer,
 704	.functionality	= dw_hdmi_qp_i2c_func,
 705};
 706
 707static struct i2c_adapter *dw_hdmi_qp_i2c_adapter(struct dw_hdmi_qp *hdmi)
 708{
 709	struct dw_hdmi_qp_i2c *i2c;
 710	struct i2c_adapter *adap;
 711	int ret;
 712
 713	i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 714	if (!i2c)
 715		return ERR_PTR(-ENOMEM);
 716
 717	mutex_init(&i2c->lock);
 718	init_completion(&i2c->cmp);
 719
 720	adap = &i2c->adap;
 721	adap->owner = THIS_MODULE;
 722	adap->dev.parent = hdmi->dev;
 723	adap->algo = &dw_hdmi_qp_algorithm;
 724	strscpy(adap->name, "DesignWare HDMI QP", sizeof(adap->name));
 725
 726	i2c_set_adapdata(adap, hdmi);
 727
 728	ret = devm_i2c_add_adapter(hdmi->dev, adap);
 729	if (ret) {
 730		dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
 731		devm_kfree(hdmi->dev, i2c);
 732		return ERR_PTR(ret);
 733	}
 734
 735	hdmi->i2c = i2c;
 736	dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 737
 738	return adap;
 739}
 740
 741static int dw_hdmi_qp_config_avi_infoframe(struct dw_hdmi_qp *hdmi,
 742					   const u8 *buffer, size_t len)
 743{
 744	u32 val, i, j;
 745
 746	if (len != HDMI_INFOFRAME_SIZE(AVI)) {
 747		dev_err(hdmi->dev, "failed to configure avi infoframe\n");
 748		return -EINVAL;
 749	}
 750
 751	/*
 752	 * DW HDMI QP IP uses a different byte format from standard AVI info
 753	 * frames, though generally the bits are in the correct bytes.
 754	 */
 755	val = buffer[1] << 8 | buffer[2] << 16;
 756	dw_hdmi_qp_write(hdmi, val, PKT_AVI_CONTENTS0);
 757
 758	for (i = 0; i < 4; i++) {
 759		for (j = 0; j < 4; j++) {
 760			if (i * 4 + j >= 14)
 761				break;
 762			if (!j)
 763				val = buffer[i * 4 + j + 3];
 764			val |= buffer[i * 4 + j + 3] << (8 * j);
 765		}
 766
 767		dw_hdmi_qp_write(hdmi, val, PKT_AVI_CONTENTS1 + i * 4);
 768	}
 769
 770	dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_AVI_FIELDRATE, PKTSCHED_PKT_CONFIG1);
 771
 772	dw_hdmi_qp_mod(hdmi, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN,
 773		       PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, PKTSCHED_PKT_EN);
 774
 775	return 0;
 776}
 777
 778static int dw_hdmi_qp_config_drm_infoframe(struct dw_hdmi_qp *hdmi,
 779					   const u8 *buffer, size_t len)
 780{
 781	u32 val, i;
 782
 783	if (len != HDMI_INFOFRAME_SIZE(DRM)) {
 784		dev_err(hdmi->dev, "failed to configure drm infoframe\n");
 785		return -EINVAL;
 786	}
 787
 788	dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN);
 789
 790	val = buffer[1] << 8 | buffer[2] << 16;
 791	dw_hdmi_qp_write(hdmi, val, PKT_DRMI_CONTENTS0);
 792
 793	for (i = 0; i <= buffer[2]; i++) {
 794		if (i % 4 == 0)
 795			val = buffer[3 + i];
 796		val |= buffer[3 + i] << ((i % 4) * 8);
 797
 798		if ((i % 4 == 3) || i == buffer[2])
 799			dw_hdmi_qp_write(hdmi, val,
 800					 PKT_DRMI_CONTENTS1 + ((i / 4) * 4));
 801	}
 802
 803	dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_FIELDRATE, PKTSCHED_PKT_CONFIG1);
 804	dw_hdmi_qp_mod(hdmi, PKTSCHED_DRMI_TX_EN, PKTSCHED_DRMI_TX_EN,
 805		       PKTSCHED_PKT_EN);
 806
 807	return 0;
 808}
 809
 810/*
 811 * Static values documented in the TRM
 812 * Different values are only used for debug purposes
 813 */
 814#define DW_HDMI_QP_AUDIO_INFOFRAME_HB1	0x1
 815#define DW_HDMI_QP_AUDIO_INFOFRAME_HB2	0xa
 816
 817static int dw_hdmi_qp_config_audio_infoframe(struct dw_hdmi_qp *hdmi,
 818					     const u8 *buffer, size_t len)
 819{
 820	/*
 821	 * AUDI_CONTENTS0: { RSV, HB2, HB1, RSV }
 822	 * AUDI_CONTENTS1: { PB3, PB2, PB1, PB0 }
 823	 * AUDI_CONTENTS2: { PB7, PB6, PB5, PB4 }
 824	 *
 825	 * PB0: CheckSum
 826	 * PB1: | CT3    | CT2  | CT1  | CT0  | F13  | CC2 | CC1 | CC0 |
 827	 * PB2: | F27    | F26  | F25  | SF2  | SF1  | SF0 | SS1 | SS0 |
 828	 * PB3: | F37    | F36  | F35  | F34  | F33  | F32 | F31 | F30 |
 829	 * PB4: | CA7    | CA6  | CA5  | CA4  | CA3  | CA2 | CA1 | CA0 |
 830	 * PB5: | DM_INH | LSV3 | LSV2 | LSV1 | LSV0 | F52 | F51 | F50 |
 831	 * PB6~PB10: Reserved
 832	 *
 833	 * AUDI_CONTENTS0 default value defined by HDMI specification,
 834	 * and shall only be changed for debug purposes.
 835	 */
 836	u32 header_bytes = (DW_HDMI_QP_AUDIO_INFOFRAME_HB1 << 8) |
 837			  (DW_HDMI_QP_AUDIO_INFOFRAME_HB2 << 16);
 838
 839	regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS0, &header_bytes, 1);
 840	regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS1, &buffer[3], 1);
 841	regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS2, &buffer[7], 1);
 842
 843	/* Enable ACR, AUDI, AMD */
 844	dw_hdmi_qp_mod(hdmi,
 845		       PKTSCHED_ACR_TX_EN | PKTSCHED_AUDI_TX_EN | PKTSCHED_AMD_TX_EN,
 846		       PKTSCHED_ACR_TX_EN | PKTSCHED_AUDI_TX_EN | PKTSCHED_AMD_TX_EN,
 847		       PKTSCHED_PKT_EN);
 848
 849	/* Enable AUDS */
 850	dw_hdmi_qp_mod(hdmi, PKTSCHED_AUDS_TX_EN, PKTSCHED_AUDS_TX_EN, PKTSCHED_PKT_EN);
 851
 852	return 0;
 853}
 854
 855static void dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge *bridge,
 856					    struct drm_atomic_state *state)
 857{
 858	struct dw_hdmi_qp *hdmi = bridge->driver_private;
 859	struct drm_connector_state *conn_state;
 860	struct drm_connector *connector;
 861	unsigned int op_mode;
 862
 863	connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
 864	if (WARN_ON(!connector))
 865		return;
 866
 867	conn_state = drm_atomic_get_new_connector_state(state, connector);
 868	if (WARN_ON(!conn_state))
 869		return;
 870
 871	if (connector->display_info.is_hdmi) {
 872		dev_dbg(hdmi->dev, "%s mode=HDMI %s rate=%llu bpc=%u\n", __func__,
 873			drm_hdmi_connector_get_output_format_name(conn_state->hdmi.output_format),
 874			conn_state->hdmi.tmds_char_rate, conn_state->hdmi.output_bpc);
 875		op_mode = 0;
 876		hdmi->tmds_char_rate = conn_state->hdmi.tmds_char_rate;
 877	} else {
 878		dev_dbg(hdmi->dev, "%s mode=DVI\n", __func__);
 879		op_mode = OPMODE_DVI;
 880	}
 881
 882	hdmi->phy.ops->init(hdmi, hdmi->phy.data);
 883
 884	dw_hdmi_qp_mod(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0);
 885	dw_hdmi_qp_mod(hdmi, op_mode, OPMODE_DVI, LINK_CONFIG0);
 886
 887	drm_atomic_helper_connector_hdmi_update_infoframes(connector, state);
 888}
 889
 890static void dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge *bridge,
 891					     struct drm_atomic_state *state)
 892{
 893	struct dw_hdmi_qp *hdmi = bridge->driver_private;
 894
 895	hdmi->tmds_char_rate = 0;
 896
 897	hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
 898}
 899
 900static enum drm_connector_status
 901dw_hdmi_qp_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector)
 902{
 903	struct dw_hdmi_qp *hdmi = bridge->driver_private;
 904
 905	return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
 906}
 907
 908static const struct drm_edid *
 909dw_hdmi_qp_bridge_edid_read(struct drm_bridge *bridge,
 910			    struct drm_connector *connector)
 911{
 912	struct dw_hdmi_qp *hdmi = bridge->driver_private;
 913	const struct drm_edid *drm_edid;
 914
 915	drm_edid = drm_edid_read_ddc(connector, bridge->ddc);
 916	if (!drm_edid)
 917		dev_dbg(hdmi->dev, "failed to get edid\n");
 918
 919	return drm_edid;
 920}
 921
 922static enum drm_mode_status
 923dw_hdmi_qp_bridge_tmds_char_rate_valid(const struct drm_bridge *bridge,
 924				       const struct drm_display_mode *mode,
 925				       unsigned long long rate)
 926{
 927	struct dw_hdmi_qp *hdmi = bridge->driver_private;
 928
 929	if (rate > HDMI14_MAX_TMDSCLK) {
 930		dev_dbg(hdmi->dev, "Unsupported TMDS char rate: %lld\n", rate);
 931		return MODE_CLOCK_HIGH;
 932	}
 933
 934	return MODE_OK;
 935}
 936
 937static int dw_hdmi_qp_bridge_clear_infoframe(struct drm_bridge *bridge,
 938					     enum hdmi_infoframe_type type)
 939{
 940	struct dw_hdmi_qp *hdmi = bridge->driver_private;
 941
 942	switch (type) {
 943	case HDMI_INFOFRAME_TYPE_AVI:
 944		dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN,
 945			       PKTSCHED_PKT_EN);
 946		break;
 947
 948	case HDMI_INFOFRAME_TYPE_DRM:
 949		dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN);
 950		break;
 951
 952	case HDMI_INFOFRAME_TYPE_AUDIO:
 953		dw_hdmi_qp_mod(hdmi, 0,
 954			       PKTSCHED_ACR_TX_EN |
 955			       PKTSCHED_AUDS_TX_EN |
 956			       PKTSCHED_AUDI_TX_EN,
 957			       PKTSCHED_PKT_EN);
 958		break;
 959	default:
 960		dev_dbg(hdmi->dev, "Unsupported infoframe type %x\n", type);
 961	}
 962
 963	return 0;
 964}
 965
 966static int dw_hdmi_qp_bridge_write_infoframe(struct drm_bridge *bridge,
 967					     enum hdmi_infoframe_type type,
 968					     const u8 *buffer, size_t len)
 969{
 970	struct dw_hdmi_qp *hdmi = bridge->driver_private;
 971
 972	dw_hdmi_qp_bridge_clear_infoframe(bridge, type);
 973
 974	switch (type) {
 975	case HDMI_INFOFRAME_TYPE_AVI:
 976		return dw_hdmi_qp_config_avi_infoframe(hdmi, buffer, len);
 977
 978	case HDMI_INFOFRAME_TYPE_DRM:
 979		return dw_hdmi_qp_config_drm_infoframe(hdmi, buffer, len);
 980
 981	case HDMI_INFOFRAME_TYPE_AUDIO:
 982		return dw_hdmi_qp_config_audio_infoframe(hdmi, buffer, len);
 983
 984	default:
 985		dev_dbg(hdmi->dev, "Unsupported infoframe type %x\n", type);
 986		return 0;
 987	}
 988}
 989
 990#ifdef CONFIG_DRM_DW_HDMI_QP_CEC
 991static irqreturn_t dw_hdmi_qp_cec_hardirq(int irq, void *dev_id)
 992{
 993	struct dw_hdmi_qp *hdmi = dev_id;
 994	struct dw_hdmi_qp_cec *cec = hdmi->cec;
 995	irqreturn_t ret = IRQ_HANDLED;
 996	u32 stat;
 997
 998	stat = dw_hdmi_qp_read(hdmi, CEC_INT_STATUS);
 999	if (stat == 0)
1000		return IRQ_NONE;
1001
1002	dw_hdmi_qp_write(hdmi, stat, CEC_INT_CLEAR);
1003
1004	if (stat & CEC_STAT_LINE_ERR) {
1005		cec->tx_status = CEC_TX_STATUS_ERROR;
1006		cec->tx_done = true;
1007		ret = IRQ_WAKE_THREAD;
1008	} else if (stat & CEC_STAT_DONE) {
1009		cec->tx_status = CEC_TX_STATUS_OK;
1010		cec->tx_done = true;
1011		ret = IRQ_WAKE_THREAD;
1012	} else if (stat & CEC_STAT_NACK) {
1013		cec->tx_status = CEC_TX_STATUS_NACK;
1014		cec->tx_done = true;
1015		ret = IRQ_WAKE_THREAD;
1016	}
1017
1018	if (stat & CEC_STAT_EOM) {
1019		unsigned int len, i, val;
1020
1021		val = dw_hdmi_qp_read(hdmi, CEC_RX_COUNT_STATUS);
1022		len = (val & 0xf) + 1;
1023
1024		if (len > sizeof(cec->rx_msg.msg))
1025			len = sizeof(cec->rx_msg.msg);
1026
1027		for (i = 0; i < 4; i++) {
1028			val = dw_hdmi_qp_read(hdmi, CEC_RX_DATA3_0 + i * 4);
1029			cec->rx_msg.msg[i * 4] = val & 0xff;
1030			cec->rx_msg.msg[i * 4 + 1] = (val >> 8) & 0xff;
1031			cec->rx_msg.msg[i * 4 + 2] = (val >> 16) & 0xff;
1032			cec->rx_msg.msg[i * 4 + 3] = (val >> 24) & 0xff;
1033		}
1034
1035		dw_hdmi_qp_write(hdmi, 1, CEC_LOCK_CONTROL);
1036
1037		cec->rx_msg.len = len;
1038		cec->rx_done = true;
1039
1040		ret = IRQ_WAKE_THREAD;
1041	}
1042
1043	return ret;
1044}
1045
1046static irqreturn_t dw_hdmi_qp_cec_thread(int irq, void *dev_id)
1047{
1048	struct dw_hdmi_qp *hdmi = dev_id;
1049	struct dw_hdmi_qp_cec *cec = hdmi->cec;
1050
1051	if (cec->tx_done) {
1052		cec->tx_done = false;
1053		drm_connector_hdmi_cec_transmit_attempt_done(cec->connector,
1054							     cec->tx_status);
1055	}
1056
1057	if (cec->rx_done) {
1058		cec->rx_done = false;
1059		drm_connector_hdmi_cec_received_msg(cec->connector, &cec->rx_msg);
1060	}
1061
1062	return IRQ_HANDLED;
1063}
1064
1065static int dw_hdmi_qp_cec_init(struct drm_bridge *bridge,
1066			       struct drm_connector *connector)
1067{
1068	struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge);
1069	struct dw_hdmi_qp_cec *cec = hdmi->cec;
1070
1071	cec->connector = connector;
1072
1073	dw_hdmi_qp_write(hdmi, 0, CEC_TX_COUNT);
1074	dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR);
1075	dw_hdmi_qp_write(hdmi, 0, CEC_INT_MASK_N);
1076
1077	return devm_request_threaded_irq(hdmi->dev, cec->irq,
1078					 dw_hdmi_qp_cec_hardirq,
1079					 dw_hdmi_qp_cec_thread, IRQF_SHARED,
1080					 dev_name(hdmi->dev), hdmi);
1081}
1082
1083static int dw_hdmi_qp_cec_log_addr(struct drm_bridge *bridge, u8 logical_addr)
1084{
1085	struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge);
1086	struct dw_hdmi_qp_cec *cec = hdmi->cec;
1087
1088	if (logical_addr == CEC_LOG_ADDR_INVALID)
1089		cec->addresses = 0;
1090	else
1091		cec->addresses |= BIT(logical_addr) | CEC_ADDR_BROADCAST;
1092
1093	dw_hdmi_qp_write(hdmi, cec->addresses, CEC_ADDR);
1094
1095	return 0;
1096}
1097
1098static int dw_hdmi_qp_cec_enable(struct drm_bridge *bridge, bool enable)
1099{
1100	struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge);
1101	unsigned int irqs;
1102	u32 swdisable;
1103
1104	if (!enable) {
1105		dw_hdmi_qp_write(hdmi, 0, CEC_INT_MASK_N);
1106		dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR);
1107
1108		swdisable = dw_hdmi_qp_read(hdmi, GLOBAL_SWDISABLE);
1109		swdisable = swdisable | CEC_SWDISABLE;
1110		dw_hdmi_qp_write(hdmi, swdisable, GLOBAL_SWDISABLE);
1111	} else {
1112		swdisable = dw_hdmi_qp_read(hdmi, GLOBAL_SWDISABLE);
1113		swdisable = swdisable & ~CEC_SWDISABLE;
1114		dw_hdmi_qp_write(hdmi, swdisable, GLOBAL_SWDISABLE);
1115
1116		dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR);
1117		dw_hdmi_qp_write(hdmi, 1, CEC_LOCK_CONTROL);
1118
1119		dw_hdmi_qp_cec_log_addr(bridge, CEC_LOG_ADDR_INVALID);
1120
1121		irqs = CEC_STAT_LINE_ERR | CEC_STAT_NACK | CEC_STAT_EOM |
1122		       CEC_STAT_DONE;
1123		dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR);
1124		dw_hdmi_qp_write(hdmi, irqs, CEC_INT_MASK_N);
1125	}
1126
1127	return 0;
1128}
1129
1130static int dw_hdmi_qp_cec_transmit(struct drm_bridge *bridge, u8 attempts,
1131				   u32 signal_free_time, struct cec_msg *msg)
1132{
1133	struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge);
1134	unsigned int i;
1135	u32 val;
1136
1137	for (i = 0; i < msg->len; i++) {
1138		if (!(i % 4))
1139			val = msg->msg[i];
1140		if ((i % 4) == 1)
1141			val |= msg->msg[i] << 8;
1142		if ((i % 4) == 2)
1143			val |= msg->msg[i] << 16;
1144		if ((i % 4) == 3)
1145			val |= msg->msg[i] << 24;
1146
1147		if (i == (msg->len - 1) || (i % 4) == 3)
1148			dw_hdmi_qp_write(hdmi, val, CEC_TX_DATA3_0 + (i / 4) * 4);
1149	}
1150
1151	dw_hdmi_qp_write(hdmi, msg->len - 1, CEC_TX_COUNT);
1152	dw_hdmi_qp_write(hdmi, CEC_CTRL_START, CEC_TX_CONTROL);
1153
1154	return 0;
1155}
1156#else
1157#define dw_hdmi_qp_cec_init NULL
1158#define dw_hdmi_qp_cec_enable NULL
1159#define dw_hdmi_qp_cec_log_addr NULL
1160#define dw_hdmi_qp_cec_transmit NULL
1161#endif /* CONFIG_DRM_DW_HDMI_QP_CEC */
1162
1163static const struct drm_bridge_funcs dw_hdmi_qp_bridge_funcs = {
1164	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1165	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1166	.atomic_reset = drm_atomic_helper_bridge_reset,
1167	.atomic_enable = dw_hdmi_qp_bridge_atomic_enable,
1168	.atomic_disable = dw_hdmi_qp_bridge_atomic_disable,
1169	.detect = dw_hdmi_qp_bridge_detect,
1170	.edid_read = dw_hdmi_qp_bridge_edid_read,
1171	.hdmi_tmds_char_rate_valid = dw_hdmi_qp_bridge_tmds_char_rate_valid,
1172	.hdmi_clear_infoframe = dw_hdmi_qp_bridge_clear_infoframe,
1173	.hdmi_write_infoframe = dw_hdmi_qp_bridge_write_infoframe,
1174	.hdmi_audio_startup = dw_hdmi_qp_audio_enable,
1175	.hdmi_audio_shutdown = dw_hdmi_qp_audio_disable,
1176	.hdmi_audio_prepare = dw_hdmi_qp_audio_prepare,
1177	.hdmi_cec_init = dw_hdmi_qp_cec_init,
1178	.hdmi_cec_enable = dw_hdmi_qp_cec_enable,
1179	.hdmi_cec_log_addr = dw_hdmi_qp_cec_log_addr,
1180	.hdmi_cec_transmit = dw_hdmi_qp_cec_transmit,
1181};
1182
1183static irqreturn_t dw_hdmi_qp_main_hardirq(int irq, void *dev_id)
1184{
1185	struct dw_hdmi_qp *hdmi = dev_id;
1186	struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
1187	u32 stat;
1188
1189	stat = dw_hdmi_qp_read(hdmi, MAINUNIT_1_INT_STATUS);
1190
1191	i2c->stat = stat & (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ |
1192			    I2CM_NACK_RCVD_IRQ);
1193
1194	if (i2c->stat) {
1195		dw_hdmi_qp_write(hdmi, i2c->stat, MAINUNIT_1_INT_CLEAR);
1196		complete(&i2c->cmp);
1197	}
1198
1199	if (stat)
1200		return IRQ_HANDLED;
1201
1202	return IRQ_NONE;
1203}
1204
1205static const struct regmap_config dw_hdmi_qp_regmap_config = {
1206	.reg_bits	= 32,
1207	.val_bits	= 32,
1208	.reg_stride	= 4,
1209	.max_register	= EARCRX_1_INT_FORCE,
1210};
1211
1212static void dw_hdmi_qp_init_hw(struct dw_hdmi_qp *hdmi)
1213{
1214	dw_hdmi_qp_write(hdmi, 0, MAINUNIT_0_INT_MASK_N);
1215	dw_hdmi_qp_write(hdmi, 0, MAINUNIT_1_INT_MASK_N);
1216	dw_hdmi_qp_write(hdmi, hdmi->ref_clk_rate, TIMER_BASE_CONFIG0);
1217
1218	/* Software reset */
1219	dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
1220	dw_hdmi_qp_write(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0);
1221	dw_hdmi_qp_mod(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0);
1222
1223	/* Clear DONE and ERROR interrupts */
1224	dw_hdmi_qp_write(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR,
1225			 MAINUNIT_1_INT_CLEAR);
1226
1227	if (hdmi->phy.ops->setup_hpd)
1228		hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
1229}
1230
1231struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev,
1232				   struct drm_encoder *encoder,
1233				   const struct dw_hdmi_qp_plat_data *plat_data)
1234{
1235	struct device *dev = &pdev->dev;
1236	struct dw_hdmi_qp *hdmi;
1237	void __iomem *regs;
1238	int ret;
1239
1240	if (!plat_data->phy_ops || !plat_data->phy_ops->init ||
1241	    !plat_data->phy_ops->disable || !plat_data->phy_ops->read_hpd) {
1242		dev_err(dev, "Missing platform PHY ops\n");
1243		return ERR_PTR(-ENODEV);
1244	}
1245
1246	hdmi = devm_drm_bridge_alloc(dev, struct dw_hdmi_qp, bridge,
1247				     &dw_hdmi_qp_bridge_funcs);
1248	if (IS_ERR(hdmi))
1249		return ERR_CAST(hdmi);
1250
1251	hdmi->dev = dev;
1252
1253	regs = devm_platform_ioremap_resource(pdev, 0);
1254	if (IS_ERR(regs))
1255		return ERR_CAST(regs);
1256
1257	hdmi->regm = devm_regmap_init_mmio(dev, regs, &dw_hdmi_qp_regmap_config);
1258	if (IS_ERR(hdmi->regm)) {
1259		dev_err(dev, "Failed to configure regmap\n");
1260		return ERR_CAST(hdmi->regm);
1261	}
1262
1263	hdmi->phy.ops = plat_data->phy_ops;
1264	hdmi->phy.data = plat_data->phy_data;
1265
1266	if (plat_data->ref_clk_rate) {
1267		hdmi->ref_clk_rate = plat_data->ref_clk_rate;
1268	} else {
1269		hdmi->ref_clk_rate = 428571429;
1270		dev_warn(dev, "Set ref_clk_rate to vendor default\n");
1271	}
1272
1273	dw_hdmi_qp_init_hw(hdmi);
1274
1275	hdmi->main_irq = plat_data->main_irq;
1276	ret = devm_request_threaded_irq(dev, plat_data->main_irq,
1277					dw_hdmi_qp_main_hardirq, NULL,
1278					IRQF_SHARED, dev_name(dev), hdmi);
1279	if (ret)
1280		return ERR_PTR(ret);
1281
1282	hdmi->bridge.driver_private = hdmi;
1283	hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT |
1284			   DRM_BRIDGE_OP_EDID |
1285			   DRM_BRIDGE_OP_HDMI |
1286			   DRM_BRIDGE_OP_HDMI_AUDIO |
1287			   DRM_BRIDGE_OP_HPD;
1288	hdmi->bridge.of_node = pdev->dev.of_node;
1289	hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
1290	hdmi->bridge.vendor = "Synopsys";
1291	hdmi->bridge.product = "DW HDMI QP TX";
1292
1293	if (plat_data->supported_formats)
1294		hdmi->bridge.supported_formats = plat_data->supported_formats;
1295
1296	if (plat_data->max_bpc)
1297		hdmi->bridge.max_bpc = plat_data->max_bpc;
1298
1299	hdmi->bridge.ddc = dw_hdmi_qp_i2c_adapter(hdmi);
1300	if (IS_ERR(hdmi->bridge.ddc))
1301		return ERR_CAST(hdmi->bridge.ddc);
1302
1303	hdmi->bridge.hdmi_audio_max_i2s_playback_channels = 8;
1304	hdmi->bridge.hdmi_audio_dev = dev;
1305	hdmi->bridge.hdmi_audio_dai_port = 1;
1306
1307#ifdef CONFIG_DRM_DW_HDMI_QP_CEC
1308	if (plat_data->cec_irq) {
1309		hdmi->bridge.ops |= DRM_BRIDGE_OP_HDMI_CEC_ADAPTER;
1310		hdmi->bridge.hdmi_cec_dev = dev;
1311		hdmi->bridge.hdmi_cec_adapter_name = dev_name(dev);
1312
1313		hdmi->cec = devm_kzalloc(hdmi->dev, sizeof(*hdmi->cec), GFP_KERNEL);
1314		if (!hdmi->cec)
1315			return ERR_PTR(-ENOMEM);
1316
1317		hdmi->cec->irq = plat_data->cec_irq;
1318	} else {
1319		dev_warn(dev, "Disabled CEC support due to missing IRQ\n");
1320	}
1321#endif
1322
1323	ret = devm_drm_bridge_add(dev, &hdmi->bridge);
1324	if (ret)
1325		return ERR_PTR(ret);
1326
1327	ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL,
1328				DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1329	if (ret)
1330		return ERR_PTR(ret);
1331
1332	return hdmi;
1333}
1334EXPORT_SYMBOL_GPL(dw_hdmi_qp_bind);
1335
1336void dw_hdmi_qp_suspend(struct device *dev, struct dw_hdmi_qp *hdmi)
1337{
1338	disable_irq(hdmi->main_irq);
1339}
1340EXPORT_SYMBOL_GPL(dw_hdmi_qp_suspend);
1341
1342void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi)
1343{
1344	dw_hdmi_qp_init_hw(hdmi);
1345	enable_irq(hdmi->main_irq);
1346}
1347EXPORT_SYMBOL_GPL(dw_hdmi_qp_resume);
1348
1349MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>");
1350MODULE_AUTHOR("Cristian Ciocaltea <cristian.ciocaltea@collabora.com>");
1351MODULE_DESCRIPTION("DW HDMI QP transmitter library");
1352MODULE_LICENSE("GPL");