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samsung-dsim.c
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linux-6.19.14/drivers/gpu/drm/bridge/samsung-dsim.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Samsung MIPI DSIM bridge driver. 4 * 5 * Copyright (C) 2021 Amarula Solutions(India) 6 * Copyright (c) 2014 Samsung Electronics Co., Ltd 7 * Author: Jagan Teki <jagan@amarulasolutions.com> 8 * 9 * Based on exynos_drm_dsi from 10 * Tomasz Figa <t.figa@samsung.com> 11 */ 12 13#include <linux/unaligned.h> 14 15#include <linux/clk.h> 16#include <linux/delay.h> 17#include <linux/export.h> 18#include <linux/irq.h> 19#include <linux/media-bus-format.h> 20#include <linux/of.h> 21#include <linux/phy/phy.h> 22#include <linux/platform_device.h> 23#include <linux/units.h> 24 25#include <video/mipi_display.h> 26 27#include <drm/bridge/samsung-dsim.h> 28#include <drm/drm_panel.h> 29#include <drm/drm_print.h> 30 31/* returns true iff both arguments logically differs */ 32#define NEQV(a, b) (!(a) ^ !(b)) 33 34/* DSIM_STATUS or DSIM_DPHY_STATUS */ 35#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) 36#define DSIM_STOP_STATE_CLK BIT(8) 37#define DSIM_TX_READY_HS_CLK BIT(10) 38 39/* DSIM_SWRST */ 40#define DSIM_FUNCRST BIT(16) 41#define DSIM_SWRST BIT(0) 42 43/* DSIM_TIMEOUT */ 44#define DSIM_LPDR_TIMEOUT(x) ((x) << 0) 45#define DSIM_BTA_TIMEOUT(x) ((x) << 16) 46 47/* DSIM_CLKCTRL */ 48#define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) 49#define DSIM_ESC_PRESCALER_MASK (0xffff << 0) 50#define DSIM_LANE_ESC_CLK_EN_DATA(x, offset) (((x) & 0xf) << offset) 51#define DSIM_LANE_ESC_CLK_EN_DATA_MASK(offset) (0xf << offset) 52#define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) 53#define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) 54#define DSIM_PLL_BYPASS BIT(27) 55 56/* DSIM_CONFIG */ 57#define DSIM_LANE_EN_CLK BIT(0) 58#define DSIM_LANE_EN(x) (((x) & 0xf) << 1) 59#define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) 60#define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) 61#define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) 62#define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) 63#define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) 64#define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) 65#define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) 66#define DSIM_SUB_VC (((x) & 0x3) << 16) 67#define DSIM_MAIN_VC (((x) & 0x3) << 18) 68#define DSIM_HSA_DISABLE_MODE BIT(20) 69#define DSIM_HBP_DISABLE_MODE BIT(21) 70#define DSIM_HFP_DISABLE_MODE BIT(22) 71/* 72 * The i.MX 8M Mini Applications Processor Reference Manual, 73 * Rev. 3, 11/2020 Page 4091 74 * The i.MX 8M Nano Applications Processor Reference Manual, 75 * Rev. 2, 07/2022 Page 3058 76 * The i.MX 8M Plus Applications Processor Reference Manual, 77 * Rev. 1, 06/2021 Page 5436 78 * all claims this bit is 'HseDisableMode' with the definition 79 * 0 = Disables transfer 80 * 1 = Enables transfer 81 * 82 * This clearly states that HSE is not a disabled bit. 83 * 84 * The naming convention follows as per the manual and the 85 * driver logic is based on the MIPI_DSI_MODE_VIDEO_HSE flag. 86 */ 87#define DSIM_HSE_DISABLE_MODE BIT(23) 88#define DSIM_AUTO_MODE BIT(24) 89#define DSIM_BURST_MODE BIT(26) 90#define DSIM_SYNC_INFORM BIT(27) 91#define DSIM_EOT_DISABLE BIT(28) 92#define DSIM_MFLUSH_VS BIT(29) 93/* This flag is valid only for exynos3250/3472/5260/5430 */ 94#define DSIM_CLKLANE_STOP BIT(30) 95#define DSIM_NON_CONTINUOUS_CLKLANE BIT(31) 96 97/* DSIM_ESCMODE */ 98#define DSIM_TX_TRIGGER_RST BIT(4) 99#define DSIM_TX_LPDT_LP BIT(6) 100#define DSIM_CMD_LPDT_LP BIT(7) 101#define DSIM_FORCE_BTA BIT(16) 102#define DSIM_FORCE_STOP_STATE BIT(20) 103#define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) 104#define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) 105 106/* DSIM_MDRESOL */ 107#define DSIM_MAIN_STAND_BY BIT(31) 108#define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16) 109#define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0) 110 111/* DSIM_MVPORCH */ 112#define DSIM_CMD_ALLOW(x) ((x) << 28) 113#define DSIM_STABLE_VFP(x) ((x) << 16) 114#define DSIM_MAIN_VBP(x) ((x) << 0) 115#define DSIM_CMD_ALLOW_MASK (0xf << 28) 116#define DSIM_STABLE_VFP_MASK (0x7ff << 16) 117#define DSIM_MAIN_VBP_MASK (0x7ff << 0) 118 119/* DSIM_MHPORCH */ 120#define DSIM_MAIN_HFP(x) ((x) << 16) 121#define DSIM_MAIN_HBP(x) ((x) << 0) 122#define DSIM_MAIN_HFP_MASK ((0xffff) << 16) 123#define DSIM_MAIN_HBP_MASK ((0xffff) << 0) 124 125/* DSIM_MSYNC */ 126#define DSIM_MAIN_VSA(x, offset) ((x) << offset) 127#define DSIM_MAIN_HSA(x) ((x) << 0) 128#define DSIM_MAIN_VSA_MASK(offset) ((0x3ff) << offset) 129#define DSIM_MAIN_HSA_MASK ((0xffff) << 0) 130 131/* DSIM_SDRESOL */ 132#define DSIM_SUB_STANDY(x) ((x) << 31) 133#define DSIM_SUB_VRESOL(x) ((x) << 16) 134#define DSIM_SUB_HRESOL(x) ((x) << 0) 135#define DSIM_SUB_STANDY_MASK ((0x1) << 31) 136#define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) 137#define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) 138 139/* DSIM_INTSRC */ 140#define DSIM_INT_PLL_STABLE BIT(31) 141#define DSIM_INT_SW_RST_RELEASE BIT(30) 142#define DSIM_INT_SFR_FIFO_EMPTY BIT(29) 143#define DSIM_INT_SFR_HDR_FIFO_EMPTY BIT(28) 144#define DSIM_INT_BTA BIT(25) 145#define DSIM_INT_FRAME_DONE BIT(24) 146#define DSIM_INT_RX_TIMEOUT BIT(21) 147#define DSIM_INT_BTA_TIMEOUT BIT(20) 148#define DSIM_INT_RX_DONE BIT(18) 149#define DSIM_INT_RX_TE BIT(17) 150#define DSIM_INT_RX_ACK BIT(16) 151#define DSIM_INT_RX_ECC_ERR BIT(15) 152#define DSIM_INT_RX_CRC_ERR BIT(14) 153 154/* DSIM_SFRCTRL */ 155#define DSIM_SFR_CTRL_STAND_BY BIT(4) 156#define DSIM_SFR_CTRL_SHADOW_UPDATE BIT(1) 157#define DSIM_SFR_CTRL_SHADOW_EN BIT(0) 158 159/* DSIM_FIFOCTRL */ 160#define DSIM_RX_DATA_FULL BIT(25) 161#define DSIM_RX_DATA_EMPTY BIT(24) 162#define DSIM_SFR_HEADER_FULL BIT(23) 163#define DSIM_SFR_HEADER_EMPTY BIT(22) 164#define DSIM_SFR_PAYLOAD_FULL BIT(21) 165#define DSIM_SFR_PAYLOAD_EMPTY BIT(20) 166#define DSIM_I80_HEADER_FULL BIT(19) 167#define DSIM_I80_HEADER_EMPTY BIT(18) 168#define DSIM_I80_PAYLOAD_FULL BIT(17) 169#define DSIM_I80_PAYLOAD_EMPTY BIT(16) 170#define DSIM_SD_HEADER_FULL BIT(15) 171#define DSIM_SD_HEADER_EMPTY BIT(14) 172#define DSIM_SD_PAYLOAD_FULL BIT(13) 173#define DSIM_SD_PAYLOAD_EMPTY BIT(12) 174#define DSIM_MD_HEADER_FULL BIT(11) 175#define DSIM_MD_HEADER_EMPTY BIT(10) 176#define DSIM_MD_PAYLOAD_FULL BIT(9) 177#define DSIM_MD_PAYLOAD_EMPTY BIT(8) 178#define DSIM_RX_FIFO BIT(4) 179#define DSIM_SFR_FIFO BIT(3) 180#define DSIM_I80_FIFO BIT(2) 181#define DSIM_SD_FIFO BIT(1) 182#define DSIM_MD_FIFO BIT(0) 183 184/* DSIM_PHYACCHR */ 185#define DSIM_AFC_EN BIT(14) 186#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) 187 188/* DSIM_PLLCTRL */ 189#define DSIM_PLL_DPDNSWAP_CLK (1 << 25) 190#define DSIM_PLL_DPDNSWAP_DAT (1 << 24) 191#define DSIM_FREQ_BAND(x) ((x) << 24) 192#define DSIM_PLL_EN BIT(23) 193#define DSIM_PLL(x, offset) ((x) << (offset)) 194 195/* DSIM_PHYCTRL */ 196#define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) 197#define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP BIT(30) 198#define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP BIT(14) 199 200/* DSIM_PHYTIMING */ 201#define DSIM_PHYTIMING_LPX(x) ((x) << 8) 202#define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) 203 204/* DSIM_PHYTIMING1 */ 205#define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) 206#define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) 207#define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) 208#define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) 209 210/* DSIM_PHYTIMING2 */ 211#define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) 212#define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) 213#define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) 214 215#define DSI_MAX_BUS_WIDTH 4 216#define DSI_NUM_VIRTUAL_CHANNELS 4 217#define DSI_TX_FIFO_SIZE 2048 218#define DSI_RX_FIFO_SIZE 256 219#define DSI_XFER_TIMEOUT_MS 100 220#define DSI_RX_FIFO_EMPTY 0x30800002 221 222#define PS_TO_CYCLE(ps, hz) DIV64_U64_ROUND_CLOSEST(((ps) * (hz)), 1000000000000ULL) 223 224enum samsung_dsim_transfer_type { 225 EXYNOS_DSI_TX, 226 EXYNOS_DSI_RX, 227}; 228 229static struct clk_bulk_data exynos3_clk_bulk_data[] = { 230 { .id = "bus_clk" }, 231 { .id = "pll_clk" }, 232}; 233 234static struct clk_bulk_data exynos4_clk_bulk_data[] = { 235 { .id = "bus_clk" }, 236 { .id = "sclk_mipi" }, 237}; 238 239static struct clk_bulk_data exynos5433_clk_bulk_data[] = { 240 { .id = "bus_clk" }, 241 { .id = "sclk_mipi" }, 242 { .id = "phyclk_mipidphy0_bitclkdiv8" }, 243 { .id = "phyclk_mipidphy0_rxclkesc0" }, 244 { .id = "sclk_rgb_vclk_to_dsim0" }, 245}; 246 247static struct clk_bulk_data exynos7870_clk_bulk_data[] = { 248 { .id = "bus" }, 249 { .id = "pll" }, 250 { .id = "byte" }, 251 { .id = "esc" }, 252}; 253 254enum reg_idx { 255 DSIM_STATUS_REG, /* Status register (legacy) */ 256 DSIM_LINK_STATUS_REG, /* Link status register */ 257 DSIM_DPHY_STATUS_REG, /* D-PHY status register */ 258 DSIM_SWRST_REG, /* Software reset register */ 259 DSIM_CLKCTRL_REG, /* Clock control register */ 260 DSIM_TIMEOUT_REG, /* Time out register */ 261 DSIM_CONFIG_REG, /* Configuration register */ 262 DSIM_ESCMODE_REG, /* Escape mode register */ 263 DSIM_MDRESOL_REG, 264 DSIM_MVPORCH_REG, /* Main display Vporch register */ 265 DSIM_MHPORCH_REG, /* Main display Hporch register */ 266 DSIM_MSYNC_REG, /* Main display sync area register */ 267 DSIM_INTSRC_REG, /* Interrupt source register */ 268 DSIM_INTMSK_REG, /* Interrupt mask register */ 269 DSIM_PKTHDR_REG, /* Packet Header FIFO register */ 270 DSIM_PAYLOAD_REG, /* Payload FIFO register */ 271 DSIM_RXFIFO_REG, /* Read FIFO register */ 272 DSIM_SFRCTRL_REG, /* SFR standby and shadow control register */ 273 DSIM_FIFOCTRL_REG, /* FIFO status and control register */ 274 DSIM_PLLCTRL_REG, /* PLL control register */ 275 DSIM_PHYCTRL_REG, 276 DSIM_PHYTIMING_REG, 277 DSIM_PHYTIMING1_REG, 278 DSIM_PHYTIMING2_REG, 279 NUM_REGS 280}; 281 282static const unsigned int exynos_reg_ofs[] = { 283 [DSIM_STATUS_REG] = 0x00, 284 [DSIM_SWRST_REG] = 0x04, 285 [DSIM_CLKCTRL_REG] = 0x08, 286 [DSIM_TIMEOUT_REG] = 0x0c, 287 [DSIM_CONFIG_REG] = 0x10, 288 [DSIM_ESCMODE_REG] = 0x14, 289 [DSIM_MDRESOL_REG] = 0x18, 290 [DSIM_MVPORCH_REG] = 0x1c, 291 [DSIM_MHPORCH_REG] = 0x20, 292 [DSIM_MSYNC_REG] = 0x24, 293 [DSIM_INTSRC_REG] = 0x2c, 294 [DSIM_INTMSK_REG] = 0x30, 295 [DSIM_PKTHDR_REG] = 0x34, 296 [DSIM_PAYLOAD_REG] = 0x38, 297 [DSIM_RXFIFO_REG] = 0x3c, 298 [DSIM_FIFOCTRL_REG] = 0x44, 299 [DSIM_PLLCTRL_REG] = 0x4c, 300 [DSIM_PHYCTRL_REG] = 0x5c, 301 [DSIM_PHYTIMING_REG] = 0x64, 302 [DSIM_PHYTIMING1_REG] = 0x68, 303 [DSIM_PHYTIMING2_REG] = 0x6c, 304}; 305 306static const unsigned int exynos5433_reg_ofs[] = { 307 [DSIM_STATUS_REG] = 0x04, 308 [DSIM_SWRST_REG] = 0x0C, 309 [DSIM_CLKCTRL_REG] = 0x10, 310 [DSIM_TIMEOUT_REG] = 0x14, 311 [DSIM_CONFIG_REG] = 0x18, 312 [DSIM_ESCMODE_REG] = 0x1C, 313 [DSIM_MDRESOL_REG] = 0x20, 314 [DSIM_MVPORCH_REG] = 0x24, 315 [DSIM_MHPORCH_REG] = 0x28, 316 [DSIM_MSYNC_REG] = 0x2C, 317 [DSIM_INTSRC_REG] = 0x34, 318 [DSIM_INTMSK_REG] = 0x38, 319 [DSIM_PKTHDR_REG] = 0x3C, 320 [DSIM_PAYLOAD_REG] = 0x40, 321 [DSIM_RXFIFO_REG] = 0x44, 322 [DSIM_FIFOCTRL_REG] = 0x4C, 323 [DSIM_PLLCTRL_REG] = 0x94, 324 [DSIM_PHYCTRL_REG] = 0xA4, 325 [DSIM_PHYTIMING_REG] = 0xB4, 326 [DSIM_PHYTIMING1_REG] = 0xB8, 327 [DSIM_PHYTIMING2_REG] = 0xBC, 328}; 329 330static const unsigned int exynos7870_reg_ofs[] = { 331 [DSIM_LINK_STATUS_REG] = 0x04, 332 [DSIM_DPHY_STATUS_REG] = 0x08, 333 [DSIM_SWRST_REG] = 0x0C, 334 [DSIM_CLKCTRL_REG] = 0x10, 335 [DSIM_TIMEOUT_REG] = 0x14, 336 [DSIM_ESCMODE_REG] = 0x1C, 337 [DSIM_MDRESOL_REG] = 0x20, 338 [DSIM_MVPORCH_REG] = 0x24, 339 [DSIM_MHPORCH_REG] = 0x28, 340 [DSIM_MSYNC_REG] = 0x2C, 341 [DSIM_CONFIG_REG] = 0x30, 342 [DSIM_INTSRC_REG] = 0x34, 343 [DSIM_INTMSK_REG] = 0x38, 344 [DSIM_PKTHDR_REG] = 0x3C, 345 [DSIM_PAYLOAD_REG] = 0x40, 346 [DSIM_RXFIFO_REG] = 0x44, 347 [DSIM_SFRCTRL_REG] = 0x48, 348 [DSIM_FIFOCTRL_REG] = 0x4C, 349 [DSIM_PLLCTRL_REG] = 0x94, 350 [DSIM_PHYCTRL_REG] = 0xA4, 351 [DSIM_PHYTIMING_REG] = 0xB4, 352 [DSIM_PHYTIMING1_REG] = 0xB8, 353 [DSIM_PHYTIMING2_REG] = 0xBC, 354}; 355 356enum reg_value_idx { 357 RESET_TYPE, 358 PLL_TIMER, 359 STOP_STATE_CNT, 360 PHYCTRL_ULPS_EXIT, 361 PHYCTRL_VREG_LP, 362 PHYCTRL_SLEW_UP, 363 PHYTIMING_LPX, 364 PHYTIMING_HS_EXIT, 365 PHYTIMING_CLK_PREPARE, 366 PHYTIMING_CLK_ZERO, 367 PHYTIMING_CLK_POST, 368 PHYTIMING_CLK_TRAIL, 369 PHYTIMING_HS_PREPARE, 370 PHYTIMING_HS_ZERO, 371 PHYTIMING_HS_TRAIL 372}; 373 374static const unsigned int reg_values[] = { 375 [RESET_TYPE] = DSIM_SWRST, 376 [PLL_TIMER] = 500, 377 [STOP_STATE_CNT] = 0xf, 378 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), 379 [PHYCTRL_VREG_LP] = 0, 380 [PHYCTRL_SLEW_UP] = 0, 381 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), 382 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), 383 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), 384 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), 385 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 386 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), 387 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), 388 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), 389 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), 390}; 391 392static const unsigned int exynos5422_reg_values[] = { 393 [RESET_TYPE] = DSIM_SWRST, 394 [PLL_TIMER] = 500, 395 [STOP_STATE_CNT] = 0xf, 396 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), 397 [PHYCTRL_VREG_LP] = 0, 398 [PHYCTRL_SLEW_UP] = 0, 399 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08), 400 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d), 401 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 402 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30), 403 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 404 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a), 405 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c), 406 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11), 407 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d), 408}; 409 410static const unsigned int exynos5433_reg_values[] = { 411 [RESET_TYPE] = DSIM_FUNCRST, 412 [PLL_TIMER] = 22200, 413 [STOP_STATE_CNT] = 0xa, 414 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), 415 [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, 416 [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, 417 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), 418 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), 419 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 420 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), 421 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 422 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), 423 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), 424 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), 425 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), 426}; 427 428static const unsigned int exynos7870_reg_values[] = { 429 [RESET_TYPE] = DSIM_SWRST, 430 [PLL_TIMER] = 80000, 431 [STOP_STATE_CNT] = 0xa, 432 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x177), 433 [PHYCTRL_VREG_LP] = 0, 434 [PHYCTRL_SLEW_UP] = 0, 435 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), 436 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), 437 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x08), 438 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2b), 439 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 440 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), 441 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), 442 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0f), 443 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), 444}; 445 446static const unsigned int imx8mm_dsim_reg_values[] = { 447 [RESET_TYPE] = DSIM_SWRST, 448 [PLL_TIMER] = 500, 449 [STOP_STATE_CNT] = 0xf, 450 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), 451 [PHYCTRL_VREG_LP] = 0, 452 [PHYCTRL_SLEW_UP] = 0, 453 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), 454 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), 455 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), 456 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x26), 457 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 458 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), 459 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x08), 460 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), 461 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), 462}; 463 464static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { 465 .reg_ofs = exynos_reg_ofs, 466 .plltmr_reg = 0x50, 467 .has_legacy_status_reg = 1, 468 .has_freqband = 1, 469 .has_clklane_stop = 1, 470 .clk_data = exynos3_clk_bulk_data, 471 .num_clks = ARRAY_SIZE(exynos3_clk_bulk_data), 472 .max_freq = 1000, 473 .wait_for_hdr_fifo = 1, 474 .wait_for_reset = 1, 475 .num_bits_resol = 11, 476 .video_mode_bit = 25, 477 .pll_stable_bit = 31, 478 .esc_clken_bit = 28, 479 .byte_clken_bit = 24, 480 .tx_req_hsclk_bit = 31, 481 .lane_esc_clk_bit = 19, 482 .lane_esc_data_offset = 20, 483 .pll_p_offset = 13, 484 .pll_m_offset = 4, 485 .pll_s_offset = 1, 486 .main_vsa_offset = 22, 487 .reg_values = reg_values, 488 .pll_fin_min = 6, 489 .pll_fin_max = 12, 490 .m_min = 41, 491 .m_max = 125, 492 .min_freq = 500, 493 .has_broken_fifoctrl_emptyhdr = 1, 494}; 495 496static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = { 497 .reg_ofs = exynos_reg_ofs, 498 .plltmr_reg = 0x50, 499 .has_legacy_status_reg = 1, 500 .has_freqband = 1, 501 .has_clklane_stop = 1, 502 .clk_data = exynos4_clk_bulk_data, 503 .num_clks = ARRAY_SIZE(exynos4_clk_bulk_data), 504 .max_freq = 1000, 505 .wait_for_hdr_fifo = 1, 506 .wait_for_reset = 1, 507 .num_bits_resol = 11, 508 .video_mode_bit = 25, 509 .pll_stable_bit = 31, 510 .esc_clken_bit = 28, 511 .byte_clken_bit = 24, 512 .tx_req_hsclk_bit = 31, 513 .lane_esc_clk_bit = 19, 514 .lane_esc_data_offset = 20, 515 .pll_p_offset = 13, 516 .pll_m_offset = 4, 517 .pll_s_offset = 1, 518 .main_vsa_offset = 22, 519 .reg_values = reg_values, 520 .pll_fin_min = 6, 521 .pll_fin_max = 12, 522 .m_min = 41, 523 .m_max = 125, 524 .min_freq = 500, 525 .has_broken_fifoctrl_emptyhdr = 1, 526}; 527 528static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = { 529 .reg_ofs = exynos_reg_ofs, 530 .plltmr_reg = 0x58, 531 .has_legacy_status_reg = 1, 532 .clk_data = exynos3_clk_bulk_data, 533 .num_clks = ARRAY_SIZE(exynos3_clk_bulk_data), 534 .max_freq = 1000, 535 .wait_for_hdr_fifo = 1, 536 .wait_for_reset = 1, 537 .num_bits_resol = 11, 538 .video_mode_bit = 25, 539 .pll_stable_bit = 31, 540 .esc_clken_bit = 28, 541 .byte_clken_bit = 24, 542 .tx_req_hsclk_bit = 31, 543 .lane_esc_clk_bit = 19, 544 .lane_esc_data_offset = 20, 545 .pll_p_offset = 13, 546 .pll_m_offset = 4, 547 .pll_s_offset = 1, 548 .main_vsa_offset = 22, 549 .reg_values = reg_values, 550 .pll_fin_min = 6, 551 .pll_fin_max = 12, 552 .m_min = 41, 553 .m_max = 125, 554 .min_freq = 500, 555}; 556 557static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = { 558 .reg_ofs = exynos5433_reg_ofs, 559 .plltmr_reg = 0xa0, 560 .has_legacy_status_reg = 1, 561 .has_clklane_stop = 1, 562 .clk_data = exynos5433_clk_bulk_data, 563 .num_clks = ARRAY_SIZE(exynos5433_clk_bulk_data), 564 .max_freq = 1500, 565 .wait_for_hdr_fifo = 1, 566 .wait_for_reset = 0, 567 .num_bits_resol = 12, 568 .video_mode_bit = 25, 569 .pll_stable_bit = 31, 570 .esc_clken_bit = 28, 571 .byte_clken_bit = 24, 572 .tx_req_hsclk_bit = 31, 573 .lane_esc_clk_bit = 19, 574 .lane_esc_data_offset = 20, 575 .pll_p_offset = 13, 576 .pll_m_offset = 4, 577 .pll_s_offset = 1, 578 .main_vsa_offset = 22, 579 .reg_values = exynos5433_reg_values, 580 .pll_fin_min = 6, 581 .pll_fin_max = 12, 582 .m_min = 41, 583 .m_max = 125, 584 .min_freq = 500, 585}; 586 587static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { 588 .reg_ofs = exynos5433_reg_ofs, 589 .plltmr_reg = 0xa0, 590 .has_legacy_status_reg = 1, 591 .has_clklane_stop = 1, 592 .clk_data = exynos3_clk_bulk_data, 593 .num_clks = ARRAY_SIZE(exynos3_clk_bulk_data), 594 .max_freq = 1500, 595 .wait_for_hdr_fifo = 1, 596 .wait_for_reset = 1, 597 .num_bits_resol = 12, 598 .video_mode_bit = 25, 599 .pll_stable_bit = 31, 600 .esc_clken_bit = 28, 601 .byte_clken_bit = 24, 602 .tx_req_hsclk_bit = 31, 603 .lane_esc_clk_bit = 19, 604 .lane_esc_data_offset = 20, 605 .pll_p_offset = 13, 606 .pll_m_offset = 4, 607 .pll_s_offset = 1, 608 .main_vsa_offset = 22, 609 .reg_values = exynos5422_reg_values, 610 .pll_fin_min = 6, 611 .pll_fin_max = 12, 612 .m_min = 41, 613 .m_max = 125, 614 .min_freq = 500, 615}; 616 617static const struct samsung_dsim_driver_data exynos7870_dsi_driver_data = { 618 .reg_ofs = exynos7870_reg_ofs, 619 .plltmr_reg = 0xa0, 620 .has_clklane_stop = 1, 621 .has_sfrctrl = 1, 622 .clk_data = exynos7870_clk_bulk_data, 623 .num_clks = ARRAY_SIZE(exynos7870_clk_bulk_data), 624 .max_freq = 1500, 625 .wait_for_hdr_fifo = 0, 626 .wait_for_reset = 1, 627 .num_bits_resol = 12, 628 .video_mode_bit = 18, 629 .pll_stable_bit = 24, 630 .esc_clken_bit = 16, 631 .byte_clken_bit = 17, 632 .tx_req_hsclk_bit = 20, 633 .lane_esc_clk_bit = 8, 634 .lane_esc_data_offset = 9, 635 .pll_p_offset = 13, 636 .pll_m_offset = 3, 637 .pll_s_offset = 0, 638 .main_vsa_offset = 16, 639 .reg_values = exynos7870_reg_values, 640 .pll_fin_min = 6, 641 .pll_fin_max = 12, 642 .m_min = 41, 643 .m_max = 125, 644 .min_freq = 500, 645}; 646 647static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = { 648 .reg_ofs = exynos5433_reg_ofs, 649 .plltmr_reg = 0xa0, 650 .has_legacy_status_reg = 1, 651 .has_clklane_stop = 1, 652 .clk_data = exynos4_clk_bulk_data, 653 .num_clks = ARRAY_SIZE(exynos4_clk_bulk_data), 654 .max_freq = 2100, 655 .wait_for_hdr_fifo = 1, 656 .wait_for_reset = 0, 657 .num_bits_resol = 12, 658 .video_mode_bit = 25, 659 .pll_stable_bit = 31, 660 .esc_clken_bit = 28, 661 .byte_clken_bit = 24, 662 .tx_req_hsclk_bit = 31, 663 .lane_esc_clk_bit = 19, 664 .lane_esc_data_offset = 20, 665 /* 666 * Unlike Exynos, PLL_P(PMS_P) offset 14 is used in i.MX8M Mini/Nano/Plus 667 * downstream driver - drivers/gpu/drm/bridge/sec-dsim.c 668 */ 669 .pll_p_offset = 14, 670 .pll_m_offset = 4, 671 .pll_s_offset = 1, 672 .main_vsa_offset = 22, 673 .reg_values = imx8mm_dsim_reg_values, 674 .pll_fin_min = 2, 675 .pll_fin_max = 30, 676 .m_min = 64, 677 .m_max = 1023, 678 .min_freq = 1050, 679}; 680 681static const struct samsung_dsim_driver_data * 682samsung_dsim_types[DSIM_TYPE_COUNT] = { 683 [DSIM_TYPE_EXYNOS3250] = &exynos3_dsi_driver_data, 684 [DSIM_TYPE_EXYNOS4210] = &exynos4_dsi_driver_data, 685 [DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data, 686 [DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data, 687 [DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data, 688 [DSIM_TYPE_EXYNOS7870] = &exynos7870_dsi_driver_data, 689 [DSIM_TYPE_IMX8MM] = &imx8mm_dsi_driver_data, 690 [DSIM_TYPE_IMX8MP] = &imx8mm_dsi_driver_data, 691}; 692 693static inline struct samsung_dsim *host_to_dsi(struct mipi_dsi_host *h) 694{ 695 return container_of(h, struct samsung_dsim, dsi_host); 696} 697 698static inline struct samsung_dsim *bridge_to_dsi(struct drm_bridge *b) 699{ 700 return container_of(b, struct samsung_dsim, bridge); 701} 702 703static inline void samsung_dsim_write(struct samsung_dsim *dsi, 704 enum reg_idx idx, u32 val) 705{ 706 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 707} 708 709static inline u32 samsung_dsim_read(struct samsung_dsim *dsi, enum reg_idx idx) 710{ 711 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 712} 713 714static void samsung_dsim_wait_for_reset(struct samsung_dsim *dsi) 715{ 716 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) 717 return; 718 719 dev_err(dsi->dev, "timeout waiting for reset\n"); 720} 721 722static void samsung_dsim_reset(struct samsung_dsim *dsi) 723{ 724 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; 725 726 reinit_completion(&dsi->completed); 727 samsung_dsim_write(dsi, DSIM_SWRST_REG, reset_val); 728} 729 730static unsigned long samsung_dsim_pll_find_pms(struct samsung_dsim *dsi, 731 unsigned long fin, 732 unsigned long fout, 733 u8 *p, u16 *m, u8 *s) 734{ 735 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 736 unsigned long best_freq = 0; 737 u32 min_delta = 0xffffffff; 738 u8 p_min, p_max; 739 u8 _p, best_p; 740 u16 _m, best_m; 741 u8 _s, best_s; 742 743 p_min = DIV_ROUND_UP(fin, (driver_data->pll_fin_max * HZ_PER_MHZ)); 744 p_max = fin / (driver_data->pll_fin_min * HZ_PER_MHZ); 745 746 for (_p = p_min; _p <= p_max; ++_p) { 747 for (_s = 0; _s <= 5; ++_s) { 748 u64 tmp; 749 u32 delta; 750 751 tmp = (u64)fout * (_p << _s); 752 do_div(tmp, fin); 753 _m = tmp; 754 if (_m < driver_data->m_min || _m > driver_data->m_max) 755 continue; 756 757 tmp = (u64)_m * fin; 758 do_div(tmp, _p); 759 if (tmp < driver_data->min_freq * HZ_PER_MHZ || 760 tmp > driver_data->max_freq * HZ_PER_MHZ) 761 continue; 762 763 tmp = (u64)_m * fin; 764 do_div(tmp, _p << _s); 765 766 delta = abs(fout - tmp); 767 if (delta < min_delta) { 768 best_p = _p; 769 best_m = _m; 770 best_s = _s; 771 min_delta = delta; 772 best_freq = tmp; 773 } 774 } 775 } 776 777 if (best_freq) { 778 *p = best_p; 779 *m = best_m; 780 *s = best_s; 781 } 782 783 return best_freq; 784} 785 786static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, 787 unsigned long freq) 788{ 789 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 790 unsigned long fin, fout; 791 int timeout; 792 u8 p, s; 793 u16 m; 794 u32 reg; 795 796 if (dsi->pll_clk) { 797 /* 798 * Ensure that the reference clock is generated with a power of 799 * two divider from its parent, but close to the PLLs upper 800 * limit. 801 */ 802 fin = clk_get_rate(clk_get_parent(dsi->pll_clk)); 803 while (fin > driver_data->pll_fin_max * HZ_PER_MHZ) 804 fin /= 2; 805 clk_set_rate(dsi->pll_clk, fin); 806 807 fin = clk_get_rate(dsi->pll_clk); 808 } else { 809 fin = dsi->pll_clk_rate; 810 } 811 dev_dbg(dsi->dev, "PLL ref clock freq %lu\n", fin); 812 813 fout = samsung_dsim_pll_find_pms(dsi, fin, freq, &p, &m, &s); 814 if (!fout) { 815 dev_err(dsi->dev, 816 "failed to find PLL PMS for requested frequency\n"); 817 return 0; 818 } 819 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); 820 821 writel(driver_data->reg_values[PLL_TIMER], 822 dsi->reg_base + driver_data->plltmr_reg); 823 824 reg = DSIM_PLL_EN | DSIM_PLL(p, driver_data->pll_p_offset) 825 | DSIM_PLL(m, driver_data->pll_m_offset) 826 | DSIM_PLL(s, driver_data->pll_s_offset); 827 828 if (driver_data->has_freqband) { 829 static const unsigned long freq_bands[] = { 830 100 * HZ_PER_MHZ, 120 * HZ_PER_MHZ, 160 * HZ_PER_MHZ, 831 200 * HZ_PER_MHZ, 270 * HZ_PER_MHZ, 320 * HZ_PER_MHZ, 832 390 * HZ_PER_MHZ, 450 * HZ_PER_MHZ, 510 * HZ_PER_MHZ, 833 560 * HZ_PER_MHZ, 640 * HZ_PER_MHZ, 690 * HZ_PER_MHZ, 834 770 * HZ_PER_MHZ, 870 * HZ_PER_MHZ, 950 * HZ_PER_MHZ, 835 }; 836 int band; 837 838 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) 839 if (fout < freq_bands[band]) 840 break; 841 842 dev_dbg(dsi->dev, "band %d\n", band); 843 844 reg |= DSIM_FREQ_BAND(band); 845 } 846 847 if (dsi->swap_dn_dp_clk) 848 reg |= DSIM_PLL_DPDNSWAP_CLK; 849 if (dsi->swap_dn_dp_data) 850 reg |= DSIM_PLL_DPDNSWAP_DAT; 851 852 samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg); 853 854 timeout = 3000; 855 do { 856 if (timeout-- == 0) { 857 dev_err(dsi->dev, "PLL failed to stabilize\n"); 858 return 0; 859 } 860 if (driver_data->has_legacy_status_reg) 861 reg = samsung_dsim_read(dsi, DSIM_STATUS_REG); 862 else 863 reg = samsung_dsim_read(dsi, DSIM_LINK_STATUS_REG); 864 } while ((reg & BIT(driver_data->pll_stable_bit)) == 0); 865 866 dsi->hs_clock = fout; 867 868 return fout; 869} 870 871static int samsung_dsim_enable_clock(struct samsung_dsim *dsi) 872{ 873 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 874 unsigned long hs_clk, byte_clk, esc_clk, pix_clk; 875 unsigned long esc_div; 876 u32 reg; 877 struct drm_display_mode *m = &dsi->mode; 878 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 879 880 /* m->clock is in KHz */ 881 pix_clk = m->clock * 1000; 882 883 /* Use burst_clk_rate if available, otherwise use the pix_clk */ 884 if (dsi->burst_clk_rate) 885 hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); 886 else 887 hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes)); 888 889 if (!hs_clk) { 890 dev_err(dsi->dev, "failed to configure DSI PLL\n"); 891 return -EFAULT; 892 } 893 894 byte_clk = hs_clk / 8; 895 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); 896 esc_clk = byte_clk / esc_div; 897 898 if (esc_clk > 20 * HZ_PER_MHZ) { 899 ++esc_div; 900 esc_clk = byte_clk / esc_div; 901 } 902 903 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", 904 hs_clk, byte_clk, esc_clk); 905 906 reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG); 907 reg &= ~(DSIM_ESC_PRESCALER_MASK | BIT(driver_data->lane_esc_clk_bit) 908 | DSIM_LANE_ESC_CLK_EN_DATA_MASK(driver_data->lane_esc_data_offset) 909 | DSIM_PLL_BYPASS 910 | DSIM_BYTE_CLK_SRC_MASK); 911 reg |= BIT(driver_data->esc_clken_bit) | BIT(driver_data->byte_clken_bit) 912 | DSIM_ESC_PRESCALER(esc_div) 913 | BIT(driver_data->lane_esc_clk_bit) 914 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1, 915 driver_data->lane_esc_data_offset) 916 | DSIM_BYTE_CLK_SRC(0) 917 | BIT(driver_data->tx_req_hsclk_bit); 918 samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg); 919 920 return 0; 921} 922 923static void samsung_dsim_set_phy_ctrl(struct samsung_dsim *dsi) 924{ 925 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 926 const unsigned int *reg_values = driver_data->reg_values; 927 u32 reg; 928 struct phy_configure_opts_mipi_dphy cfg; 929 int clk_prepare, lpx, clk_zero, clk_post, clk_trail; 930 int hs_exit, hs_prepare, hs_zero, hs_trail; 931 unsigned long long byte_clock = dsi->hs_clock / 8; 932 933 if (driver_data->has_freqband) 934 return; 935 936 phy_mipi_dphy_get_default_config_for_hsclk(dsi->hs_clock, 937 dsi->lanes, &cfg); 938 939 /* 940 * TODO: 941 * The tech Applications Processor manuals for i.MX8M Mini, Nano, 942 * and Plus don't state what the definition of the PHYTIMING 943 * bits are beyond their address and bit position. 944 * After reviewing NXP's downstream code, it appears 945 * that the various PHYTIMING registers take the number 946 * of cycles and use various dividers on them. This 947 * calculation does not result in an exact match to the 948 * downstream code, but it is very close to the values 949 * generated by their lookup table, and it appears 950 * to sync at a variety of resolutions. If someone 951 * can get a more accurate mathematical equation needed 952 * for these registers, this should be updated. 953 */ 954 955 lpx = PS_TO_CYCLE(cfg.lpx, byte_clock); 956 hs_exit = PS_TO_CYCLE(cfg.hs_exit, byte_clock); 957 clk_prepare = PS_TO_CYCLE(cfg.clk_prepare, byte_clock); 958 clk_zero = PS_TO_CYCLE(cfg.clk_zero, byte_clock); 959 clk_post = PS_TO_CYCLE(cfg.clk_post, byte_clock); 960 clk_trail = PS_TO_CYCLE(cfg.clk_trail, byte_clock); 961 hs_prepare = PS_TO_CYCLE(cfg.hs_prepare, byte_clock); 962 hs_zero = PS_TO_CYCLE(cfg.hs_zero, byte_clock); 963 hs_trail = PS_TO_CYCLE(cfg.hs_trail, byte_clock); 964 965 /* B D-PHY: D-PHY Master & Slave Analog Block control */ 966 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | 967 reg_values[PHYCTRL_SLEW_UP]; 968 969 samsung_dsim_write(dsi, DSIM_PHYCTRL_REG, reg); 970 971 /* 972 * T LPX: Transmitted length of any Low-Power state period 973 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS 974 * burst 975 */ 976 977 reg = DSIM_PHYTIMING_LPX(lpx) | DSIM_PHYTIMING_HS_EXIT(hs_exit); 978 979 samsung_dsim_write(dsi, DSIM_PHYTIMING_REG, reg); 980 981 /* 982 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 983 * Line state immediately before the HS-0 Line state starting the 984 * HS transmission 985 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to 986 * transmitting the Clock. 987 * T CLK_POST: Time that the transmitter continues to send HS clock 988 * after the last associated Data Lane has transitioned to LP Mode 989 * Interval is defined as the period from the end of T HS-TRAIL to 990 * the beginning of T CLK-TRAIL 991 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after 992 * the last payload clock bit of a HS transmission burst 993 */ 994 995 reg = DSIM_PHYTIMING1_CLK_PREPARE(clk_prepare) | 996 DSIM_PHYTIMING1_CLK_ZERO(clk_zero) | 997 DSIM_PHYTIMING1_CLK_POST(clk_post) | 998 DSIM_PHYTIMING1_CLK_TRAIL(clk_trail); 999 1000 samsung_dsim_write(dsi, DSIM_PHYTIMING1_REG, reg); 1001 1002 /* 1003 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 1004 * Line state immediately before the HS-0 Line state starting the 1005 * HS transmission 1006 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to 1007 * transmitting the Sync sequence. 1008 * T HS-TRAIL: Time that the transmitter drives the flipped differential 1009 * state after last payload data bit of a HS transmission burst 1010 */ 1011 1012 reg = DSIM_PHYTIMING2_HS_PREPARE(hs_prepare) | 1013 DSIM_PHYTIMING2_HS_ZERO(hs_zero) | 1014 DSIM_PHYTIMING2_HS_TRAIL(hs_trail); 1015 1016 samsung_dsim_write(dsi, DSIM_PHYTIMING2_REG, reg); 1017} 1018 1019static void samsung_dsim_disable_clock(struct samsung_dsim *dsi) 1020{ 1021 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 1022 u32 reg; 1023 1024 reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG); 1025 reg &= ~(BIT(driver_data->lane_esc_clk_bit) 1026 | DSIM_LANE_ESC_CLK_EN_DATA_MASK(driver_data->lane_esc_data_offset) 1027 | BIT(driver_data->esc_clken_bit) 1028 | BIT(driver_data->byte_clken_bit)); 1029 samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg); 1030 1031 reg = samsung_dsim_read(dsi, DSIM_PLLCTRL_REG); 1032 reg &= ~DSIM_PLL_EN; 1033 samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg); 1034} 1035 1036static void samsung_dsim_enable_lane(struct samsung_dsim *dsi, u32 lane) 1037{ 1038 u32 reg = samsung_dsim_read(dsi, DSIM_CONFIG_REG); 1039 1040 reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | 1041 DSIM_LANE_EN(lane)); 1042 samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg); 1043} 1044 1045static int samsung_dsim_init_link(struct samsung_dsim *dsi) 1046{ 1047 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 1048 int timeout; 1049 u32 reg; 1050 u32 lanes_mask; 1051 1052 /* Initialize FIFO pointers */ 1053 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG); 1054 reg &= ~0x1f; 1055 samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg); 1056 1057 usleep_range(9000, 11000); 1058 1059 reg |= 0x1f; 1060 samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg); 1061 usleep_range(9000, 11000); 1062 1063 /* DSI configuration */ 1064 reg = 0; 1065 1066 /* 1067 * The first bit of mode_flags specifies display configuration. 1068 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video 1069 * mode, otherwise it will support command mode. 1070 */ 1071 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 1072 reg |= BIT(driver_data->video_mode_bit); 1073 1074 /* 1075 * The user manual describes that following bits are ignored in 1076 * command mode. 1077 */ 1078 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 1079 reg |= DSIM_SYNC_INFORM; 1080 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 1081 reg |= DSIM_BURST_MODE; 1082 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) 1083 reg |= DSIM_AUTO_MODE; 1084 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) 1085 reg |= DSIM_HSE_DISABLE_MODE; 1086 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 1087 reg |= DSIM_HFP_DISABLE_MODE; 1088 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 1089 reg |= DSIM_HBP_DISABLE_MODE; 1090 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 1091 reg |= DSIM_HSA_DISABLE_MODE; 1092 } 1093 1094 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 1095 reg |= DSIM_EOT_DISABLE; 1096 1097 switch (dsi->format) { 1098 case MIPI_DSI_FMT_RGB888: 1099 reg |= DSIM_MAIN_PIX_FORMAT_RGB888; 1100 break; 1101 case MIPI_DSI_FMT_RGB666: 1102 reg |= DSIM_MAIN_PIX_FORMAT_RGB666; 1103 break; 1104 case MIPI_DSI_FMT_RGB666_PACKED: 1105 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; 1106 break; 1107 case MIPI_DSI_FMT_RGB565: 1108 reg |= DSIM_MAIN_PIX_FORMAT_RGB565; 1109 break; 1110 default: 1111 dev_err(dsi->dev, "invalid pixel format\n"); 1112 return -EINVAL; 1113 } 1114 1115 /* 1116 * Use non-continuous clock mode if the periparal wants and 1117 * host controller supports 1118 * 1119 * In non-continous clock mode, host controller will turn off 1120 * the HS clock between high-speed transmissions to reduce 1121 * power consumption. 1122 */ 1123 if (driver_data->has_clklane_stop && 1124 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 1125 if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) 1126 reg |= DSIM_NON_CONTINUOUS_CLKLANE; 1127 1128 reg |= DSIM_CLKLANE_STOP; 1129 } 1130 samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg); 1131 1132 lanes_mask = BIT(dsi->lanes) - 1; 1133 samsung_dsim_enable_lane(dsi, lanes_mask); 1134 1135 /* Check clock and data lane state are stop state */ 1136 timeout = 100; 1137 do { 1138 if (timeout-- == 0) { 1139 dev_err(dsi->dev, "waiting for bus lanes timed out\n"); 1140 return -EFAULT; 1141 } 1142 1143 if (driver_data->has_legacy_status_reg) 1144 reg = samsung_dsim_read(dsi, DSIM_STATUS_REG); 1145 else 1146 reg = samsung_dsim_read(dsi, DSIM_DPHY_STATUS_REG); 1147 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) 1148 != DSIM_STOP_STATE_DAT(lanes_mask)) 1149 continue; 1150 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); 1151 1152 reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG); 1153 reg &= ~DSIM_STOP_STATE_CNT_MASK; 1154 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); 1155 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg); 1156 1157 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); 1158 samsung_dsim_write(dsi, DSIM_TIMEOUT_REG, reg); 1159 1160 return 0; 1161} 1162 1163static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi) 1164{ 1165 struct drm_display_mode *m = &dsi->mode; 1166 unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; 1167 unsigned int main_vsa_offset = dsi->driver_data->main_vsa_offset; 1168 u32 reg; 1169 1170 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 1171 u64 byte_clk = dsi->hs_clock / 8; 1172 u64 pix_clk = m->clock * 1000; 1173 1174 int hfp = DIV64_U64_ROUND_UP((m->hsync_start - m->hdisplay) * byte_clk, pix_clk); 1175 int hbp = DIV64_U64_ROUND_UP((m->htotal - m->hsync_end) * byte_clk, pix_clk); 1176 int hsa = DIV64_U64_ROUND_UP((m->hsync_end - m->hsync_start) * byte_clk, pix_clk); 1177 1178 /* remove packet overhead when possible */ 1179 hfp = max(hfp - 6, 0); 1180 hbp = max(hbp - 6, 0); 1181 hsa = max(hsa - 6, 0); 1182 1183 dev_dbg(dsi->dev, "calculated hfp: %u, hbp: %u, hsa: %u", 1184 hfp, hbp, hsa); 1185 1186 reg = DSIM_CMD_ALLOW(0xf) 1187 | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay) 1188 | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); 1189 samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg); 1190 1191 reg = DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp); 1192 samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg); 1193 1194 reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start, main_vsa_offset) 1195 | DSIM_MAIN_HSA(hsa); 1196 samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg); 1197 } 1198 reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | 1199 DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol); 1200 1201 samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg); 1202 1203 dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay); 1204} 1205 1206static void samsung_dsim_set_display_enable(struct samsung_dsim *dsi, bool enable) 1207{ 1208 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 1209 u32 reg; 1210 1211 reg = samsung_dsim_read(dsi, DSIM_MDRESOL_REG); 1212 if (enable) 1213 reg |= DSIM_MAIN_STAND_BY; 1214 else 1215 reg &= ~DSIM_MAIN_STAND_BY; 1216 samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg); 1217 1218 if (driver_data->has_sfrctrl) { 1219 reg = samsung_dsim_read(dsi, DSIM_SFRCTRL_REG); 1220 if (enable) 1221 reg |= DSIM_SFR_CTRL_STAND_BY; 1222 else 1223 reg &= ~DSIM_SFR_CTRL_STAND_BY; 1224 samsung_dsim_write(dsi, DSIM_SFRCTRL_REG, reg); 1225 } 1226} 1227 1228static int samsung_dsim_wait_for_hdr_fifo(struct samsung_dsim *dsi) 1229{ 1230 int timeout = 2000; 1231 1232 do { 1233 u32 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG); 1234 1235 if (!dsi->driver_data->has_broken_fifoctrl_emptyhdr) { 1236 if (reg & DSIM_SFR_HEADER_EMPTY) 1237 return 0; 1238 } else { 1239 if (!(reg & DSIM_SFR_HEADER_FULL)) { 1240 /* 1241 * Wait a little bit, so the pending data can 1242 * actually leave the FIFO to avoid overflow. 1243 */ 1244 if (!cond_resched()) 1245 usleep_range(950, 1050); 1246 return 0; 1247 } 1248 } 1249 1250 if (!cond_resched()) 1251 usleep_range(950, 1050); 1252 } while (--timeout); 1253 1254 return -ETIMEDOUT; 1255} 1256 1257static void samsung_dsim_set_cmd_lpm(struct samsung_dsim *dsi, bool lpm) 1258{ 1259 u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG); 1260 1261 if (lpm) 1262 v |= DSIM_CMD_LPDT_LP; 1263 else 1264 v &= ~DSIM_CMD_LPDT_LP; 1265 1266 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v); 1267} 1268 1269static void samsung_dsim_force_bta(struct samsung_dsim *dsi) 1270{ 1271 u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG); 1272 1273 v |= DSIM_FORCE_BTA; 1274 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v); 1275} 1276 1277static void samsung_dsim_send_to_fifo(struct samsung_dsim *dsi, 1278 struct samsung_dsim_transfer *xfer) 1279{ 1280 struct device *dev = dsi->dev; 1281 struct mipi_dsi_packet *pkt = &xfer->packet; 1282 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 1283 const u8 *payload = pkt->payload + xfer->tx_done; 1284 u16 length = pkt->payload_length - xfer->tx_done; 1285 bool first = !xfer->tx_done; 1286 u32 reg; 1287 1288 dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n", 1289 xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done); 1290 1291 if (length > DSI_TX_FIFO_SIZE) 1292 length = DSI_TX_FIFO_SIZE; 1293 1294 xfer->tx_done += length; 1295 1296 /* Send payload */ 1297 while (length >= 4) { 1298 reg = get_unaligned_le32(payload); 1299 samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg); 1300 payload += 4; 1301 length -= 4; 1302 } 1303 1304 reg = 0; 1305 switch (length) { 1306 case 3: 1307 reg |= payload[2] << 16; 1308 fallthrough; 1309 case 2: 1310 reg |= payload[1] << 8; 1311 fallthrough; 1312 case 1: 1313 reg |= payload[0]; 1314 samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg); 1315 break; 1316 } 1317 1318 /* Send packet header */ 1319 if (!first) 1320 return; 1321 1322 reg = get_unaligned_le32(pkt->header); 1323 if (driver_data->wait_for_hdr_fifo) { 1324 if (samsung_dsim_wait_for_hdr_fifo(dsi)) { 1325 dev_err(dev, "waiting for header FIFO timed out\n"); 1326 return; 1327 } 1328 } 1329 1330 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, 1331 dsi->state & DSIM_STATE_CMD_LPM)) { 1332 samsung_dsim_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); 1333 dsi->state ^= DSIM_STATE_CMD_LPM; 1334 } 1335 1336 samsung_dsim_write(dsi, DSIM_PKTHDR_REG, reg); 1337 1338 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) 1339 samsung_dsim_force_bta(dsi); 1340} 1341 1342static void samsung_dsim_read_from_fifo(struct samsung_dsim *dsi, 1343 struct samsung_dsim_transfer *xfer) 1344{ 1345 u8 *payload = xfer->rx_payload + xfer->rx_done; 1346 bool first = !xfer->rx_done; 1347 struct device *dev = dsi->dev; 1348 u16 length; 1349 u32 reg; 1350 1351 if (first) { 1352 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG); 1353 1354 switch (reg & 0x3f) { 1355 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 1356 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1357 if (xfer->rx_len >= 2) { 1358 payload[1] = reg >> 16; 1359 ++xfer->rx_done; 1360 } 1361 fallthrough; 1362 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 1363 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1364 payload[0] = reg >> 8; 1365 ++xfer->rx_done; 1366 xfer->rx_len = xfer->rx_done; 1367 xfer->result = 0; 1368 goto clear_fifo; 1369 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1370 dev_err(dev, "DSI Error Report: 0x%04x\n", (reg >> 8) & 0xffff); 1371 xfer->result = 0; 1372 goto clear_fifo; 1373 } 1374 1375 length = (reg >> 8) & 0xffff; 1376 if (length > xfer->rx_len) { 1377 dev_err(dev, 1378 "response too long (%u > %u bytes), stripping\n", 1379 xfer->rx_len, length); 1380 length = xfer->rx_len; 1381 } else if (length < xfer->rx_len) { 1382 xfer->rx_len = length; 1383 } 1384 } 1385 1386 length = xfer->rx_len - xfer->rx_done; 1387 xfer->rx_done += length; 1388 1389 /* Receive payload */ 1390 while (length >= 4) { 1391 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG); 1392 payload[0] = (reg >> 0) & 0xff; 1393 payload[1] = (reg >> 8) & 0xff; 1394 payload[2] = (reg >> 16) & 0xff; 1395 payload[3] = (reg >> 24) & 0xff; 1396 payload += 4; 1397 length -= 4; 1398 } 1399 1400 if (length) { 1401 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG); 1402 switch (length) { 1403 case 3: 1404 payload[2] = (reg >> 16) & 0xff; 1405 fallthrough; 1406 case 2: 1407 payload[1] = (reg >> 8) & 0xff; 1408 fallthrough; 1409 case 1: 1410 payload[0] = reg & 0xff; 1411 } 1412 } 1413 1414 if (xfer->rx_done == xfer->rx_len) 1415 xfer->result = 0; 1416 1417clear_fifo: 1418 length = DSI_RX_FIFO_SIZE / 4; 1419 do { 1420 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG); 1421 if (reg == DSI_RX_FIFO_EMPTY) 1422 break; 1423 } while (--length); 1424} 1425 1426static void samsung_dsim_transfer_start(struct samsung_dsim *dsi) 1427{ 1428 unsigned long flags; 1429 struct samsung_dsim_transfer *xfer; 1430 1431 spin_lock_irqsave(&dsi->transfer_lock, flags); 1432 1433 while (!list_empty(&dsi->transfer_list)) { 1434 xfer = list_first_entry(&dsi->transfer_list, 1435 struct samsung_dsim_transfer, list); 1436 1437 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1438 1439 if (xfer->packet.payload_length && 1440 xfer->tx_done == xfer->packet.payload_length) 1441 /* waiting for RX */ 1442 return; 1443 1444 samsung_dsim_send_to_fifo(dsi, xfer); 1445 1446 if (xfer->packet.payload_length || xfer->rx_len) 1447 return; 1448 1449 xfer->result = 0; 1450 complete(&xfer->completed); 1451 1452 spin_lock_irqsave(&dsi->transfer_lock, flags); 1453 1454 list_del_init(&xfer->list); 1455 } 1456 1457 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1458} 1459 1460static bool samsung_dsim_transfer_finish(struct samsung_dsim *dsi) 1461{ 1462 struct samsung_dsim_transfer *xfer; 1463 unsigned long flags; 1464 bool start = true; 1465 1466 spin_lock_irqsave(&dsi->transfer_lock, flags); 1467 1468 if (list_empty(&dsi->transfer_list)) { 1469 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1470 return false; 1471 } 1472 1473 xfer = list_first_entry(&dsi->transfer_list, 1474 struct samsung_dsim_transfer, list); 1475 1476 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1477 1478 dev_dbg(dsi->dev, 1479 "> xfer %p, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n", 1480 xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len, 1481 xfer->rx_done); 1482 1483 if (xfer->tx_done != xfer->packet.payload_length) 1484 return true; 1485 1486 if (xfer->rx_done != xfer->rx_len) 1487 samsung_dsim_read_from_fifo(dsi, xfer); 1488 1489 if (xfer->rx_done != xfer->rx_len) 1490 return true; 1491 1492 spin_lock_irqsave(&dsi->transfer_lock, flags); 1493 1494 list_del_init(&xfer->list); 1495 start = !list_empty(&dsi->transfer_list); 1496 1497 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1498 1499 if (!xfer->rx_len) 1500 xfer->result = 0; 1501 complete(&xfer->completed); 1502 1503 return start; 1504} 1505 1506static void samsung_dsim_remove_transfer(struct samsung_dsim *dsi, 1507 struct samsung_dsim_transfer *xfer) 1508{ 1509 unsigned long flags; 1510 bool start; 1511 1512 spin_lock_irqsave(&dsi->transfer_lock, flags); 1513 1514 if (!list_empty(&dsi->transfer_list) && 1515 xfer == list_first_entry(&dsi->transfer_list, 1516 struct samsung_dsim_transfer, list)) { 1517 list_del_init(&xfer->list); 1518 start = !list_empty(&dsi->transfer_list); 1519 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1520 if (start) 1521 samsung_dsim_transfer_start(dsi); 1522 return; 1523 } 1524 1525 list_del_init(&xfer->list); 1526 1527 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1528} 1529 1530static int samsung_dsim_transfer(struct samsung_dsim *dsi, 1531 struct samsung_dsim_transfer *xfer) 1532{ 1533 unsigned long flags; 1534 bool stopped; 1535 1536 xfer->tx_done = 0; 1537 xfer->rx_done = 0; 1538 xfer->result = -ETIMEDOUT; 1539 init_completion(&xfer->completed); 1540 1541 spin_lock_irqsave(&dsi->transfer_lock, flags); 1542 1543 stopped = list_empty(&dsi->transfer_list); 1544 list_add_tail(&xfer->list, &dsi->transfer_list); 1545 1546 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1547 1548 if (stopped) 1549 samsung_dsim_transfer_start(dsi); 1550 1551 wait_for_completion_timeout(&xfer->completed, 1552 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); 1553 if (xfer->result == -ETIMEDOUT) { 1554 struct mipi_dsi_packet *pkt = &xfer->packet; 1555 1556 samsung_dsim_remove_transfer(dsi, xfer); 1557 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header, 1558 (int)pkt->payload_length, pkt->payload); 1559 return -ETIMEDOUT; 1560 } 1561 1562 /* Also covers hardware timeout condition */ 1563 return xfer->result; 1564} 1565 1566static irqreturn_t samsung_dsim_irq(int irq, void *dev_id) 1567{ 1568 struct samsung_dsim *dsi = dev_id; 1569 u32 status; 1570 1571 status = samsung_dsim_read(dsi, DSIM_INTSRC_REG); 1572 if (!status) { 1573 static unsigned long j; 1574 1575 if (printk_timed_ratelimit(&j, 500)) 1576 dev_warn(dsi->dev, "spurious interrupt\n"); 1577 return IRQ_HANDLED; 1578 } 1579 samsung_dsim_write(dsi, DSIM_INTSRC_REG, status); 1580 1581 if (status & DSIM_INT_SW_RST_RELEASE) { 1582 unsigned long mask = ~(DSIM_INT_RX_DONE | 1583 DSIM_INT_SFR_FIFO_EMPTY | 1584 DSIM_INT_SFR_HDR_FIFO_EMPTY | 1585 DSIM_INT_RX_ECC_ERR | 1586 DSIM_INT_SW_RST_RELEASE); 1587 samsung_dsim_write(dsi, DSIM_INTMSK_REG, mask); 1588 complete(&dsi->completed); 1589 return IRQ_HANDLED; 1590 } 1591 1592 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1593 DSIM_INT_PLL_STABLE))) 1594 return IRQ_HANDLED; 1595 1596 if (samsung_dsim_transfer_finish(dsi)) 1597 samsung_dsim_transfer_start(dsi); 1598 1599 return IRQ_HANDLED; 1600} 1601 1602static void samsung_dsim_enable_irq(struct samsung_dsim *dsi) 1603{ 1604 enable_irq(dsi->irq); 1605 1606 if (dsi->te_gpio) 1607 enable_irq(gpiod_to_irq(dsi->te_gpio)); 1608} 1609 1610static void samsung_dsim_disable_irq(struct samsung_dsim *dsi) 1611{ 1612 if (dsi->te_gpio) 1613 disable_irq(gpiod_to_irq(dsi->te_gpio)); 1614 1615 disable_irq(dsi->irq); 1616} 1617 1618static int samsung_dsim_init(struct samsung_dsim *dsi) 1619{ 1620 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 1621 1622 if (dsi->state & DSIM_STATE_INITIALIZED) 1623 return 0; 1624 1625 samsung_dsim_reset(dsi); 1626 samsung_dsim_enable_irq(dsi); 1627 1628 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) 1629 samsung_dsim_enable_lane(dsi, BIT(dsi->lanes) - 1); 1630 1631 samsung_dsim_enable_clock(dsi); 1632 if (driver_data->wait_for_reset) 1633 samsung_dsim_wait_for_reset(dsi); 1634 samsung_dsim_set_phy_ctrl(dsi); 1635 samsung_dsim_init_link(dsi); 1636 1637 dsi->state |= DSIM_STATE_INITIALIZED; 1638 1639 return 0; 1640} 1641 1642static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge, 1643 struct drm_atomic_state *state) 1644{ 1645 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1646 int ret; 1647 1648 if (dsi->state & DSIM_STATE_ENABLED) 1649 return; 1650 1651 ret = pm_runtime_resume_and_get(dsi->dev); 1652 if (ret < 0) { 1653 dev_err(dsi->dev, "failed to enable DSI device.\n"); 1654 return; 1655 } 1656 1657 dsi->state |= DSIM_STATE_ENABLED; 1658 1659 /* 1660 * For Exynos-DSIM the downstream bridge, or panel are expecting 1661 * the host initialization during DSI transfer. 1662 */ 1663 if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) { 1664 ret = samsung_dsim_init(dsi); 1665 if (ret) 1666 return; 1667 } 1668} 1669 1670static void samsung_dsim_atomic_enable(struct drm_bridge *bridge, 1671 struct drm_atomic_state *state) 1672{ 1673 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1674 1675 samsung_dsim_set_display_mode(dsi); 1676 samsung_dsim_set_display_enable(dsi, true); 1677 1678 dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; 1679} 1680 1681static void samsung_dsim_atomic_disable(struct drm_bridge *bridge, 1682 struct drm_atomic_state *state) 1683{ 1684 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1685 1686 if (!(dsi->state & DSIM_STATE_ENABLED)) 1687 return; 1688 1689 samsung_dsim_set_display_enable(dsi, false); 1690 dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; 1691} 1692 1693static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge, 1694 struct drm_atomic_state *state) 1695{ 1696 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1697 1698 dsi->state &= ~DSIM_STATE_ENABLED; 1699 pm_runtime_put_sync(dsi->dev); 1700} 1701 1702/* 1703 * This pixel output formats list referenced from, 1704 * AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022 1705 * 3.7.4 Pixel formats 1706 * Table 14. DSI pixel packing formats 1707 */ 1708static const u32 samsung_dsim_pixel_output_fmts[] = { 1709 MEDIA_BUS_FMT_YUYV10_1X20, 1710 MEDIA_BUS_FMT_YUYV12_1X24, 1711 MEDIA_BUS_FMT_UYVY8_1X16, 1712 MEDIA_BUS_FMT_RGB101010_1X30, 1713 MEDIA_BUS_FMT_RGB121212_1X36, 1714 MEDIA_BUS_FMT_RGB565_1X16, 1715 MEDIA_BUS_FMT_RGB666_1X18, 1716 MEDIA_BUS_FMT_RGB888_1X24, 1717}; 1718 1719static bool samsung_dsim_pixel_output_fmt_supported(u32 fmt) 1720{ 1721 int i; 1722 1723 if (fmt == MEDIA_BUS_FMT_FIXED) 1724 return false; 1725 1726 for (i = 0; i < ARRAY_SIZE(samsung_dsim_pixel_output_fmts); i++) { 1727 if (samsung_dsim_pixel_output_fmts[i] == fmt) 1728 return true; 1729 } 1730 1731 return false; 1732} 1733 1734static u32 * 1735samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 1736 struct drm_bridge_state *bridge_state, 1737 struct drm_crtc_state *crtc_state, 1738 struct drm_connector_state *conn_state, 1739 u32 output_fmt, 1740 unsigned int *num_input_fmts) 1741{ 1742 u32 *input_fmts; 1743 1744 input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); 1745 if (!input_fmts) 1746 return NULL; 1747 1748 if (!samsung_dsim_pixel_output_fmt_supported(output_fmt)) 1749 /* 1750 * Some bridge/display drivers are still not able to pass the 1751 * correct format, so handle those pipelines by falling back 1752 * to the default format till the supported formats finalized. 1753 */ 1754 output_fmt = MEDIA_BUS_FMT_RGB888_1X24; 1755 1756 input_fmts[0] = output_fmt; 1757 *num_input_fmts = 1; 1758 1759 return input_fmts; 1760} 1761 1762static int samsung_dsim_atomic_check(struct drm_bridge *bridge, 1763 struct drm_bridge_state *bridge_state, 1764 struct drm_crtc_state *crtc_state, 1765 struct drm_connector_state *conn_state) 1766{ 1767 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1768 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 1769 1770 /* 1771 * The i.MX8M Mini/Nano glue logic between LCDIF and DSIM 1772 * inverts HS/VS/DE sync signals polarity, therefore, while 1773 * i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 1774 * 13.6.3.5.2 RGB interface 1775 * i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 1776 * 13.6.2.7.2 RGB interface 1777 * both claim "Vsync, Hsync, and VDEN are active high signals.", the 1778 * LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. 1779 * 1780 * The i.MX8M Plus glue logic between LCDIFv3 and DSIM does not 1781 * implement the same behavior, therefore LCDIFv3 must generate 1782 * HS/VS/DE signals active HIGH. 1783 */ 1784 if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) { 1785 adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 1786 adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 1787 } else if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MP) { 1788 adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 1789 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 1790 } 1791 1792 /* 1793 * When using video sync pulses, the HFP, HBP, and HSA are divided between 1794 * the available lanes if there is more than one lane. For certain 1795 * timings and lane configurations, the HFP may not be evenly divisible. 1796 * If the HFP is rounded down, it ends up being too small which can cause 1797 * some monitors to not sync properly. In these instances, adjust htotal 1798 * and hsync to round the HFP up, and recalculate the htotal. Through trial 1799 * and error, it appears that the HBP and HSA do not appearto need the same 1800 * correction that HFP does. 1801 */ 1802 if (dsi->lanes > 1) { 1803 int hfp = adjusted_mode->hsync_start - adjusted_mode->hdisplay; 1804 int remainder = hfp % dsi->lanes; 1805 1806 if (remainder) { 1807 adjusted_mode->hsync_start += remainder; 1808 adjusted_mode->hsync_end += remainder; 1809 adjusted_mode->htotal += remainder; 1810 } 1811 } 1812 1813 return 0; 1814} 1815 1816static void samsung_dsim_mode_set(struct drm_bridge *bridge, 1817 const struct drm_display_mode *mode, 1818 const struct drm_display_mode *adjusted_mode) 1819{ 1820 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1821 1822 drm_mode_copy(&dsi->mode, adjusted_mode); 1823} 1824 1825static int samsung_dsim_attach(struct drm_bridge *bridge, 1826 struct drm_encoder *encoder, 1827 enum drm_bridge_attach_flags flags) 1828{ 1829 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1830 1831 return drm_bridge_attach(encoder, dsi->out_bridge, bridge, 1832 flags); 1833} 1834 1835static const struct drm_bridge_funcs samsung_dsim_bridge_funcs = { 1836 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1837 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1838 .atomic_reset = drm_atomic_helper_bridge_reset, 1839 .atomic_get_input_bus_fmts = samsung_dsim_atomic_get_input_bus_fmts, 1840 .atomic_check = samsung_dsim_atomic_check, 1841 .atomic_pre_enable = samsung_dsim_atomic_pre_enable, 1842 .atomic_enable = samsung_dsim_atomic_enable, 1843 .atomic_disable = samsung_dsim_atomic_disable, 1844 .atomic_post_disable = samsung_dsim_atomic_post_disable, 1845 .mode_set = samsung_dsim_mode_set, 1846 .attach = samsung_dsim_attach, 1847}; 1848 1849static irqreturn_t samsung_dsim_te_irq_handler(int irq, void *dev_id) 1850{ 1851 struct samsung_dsim *dsi = (struct samsung_dsim *)dev_id; 1852 const struct samsung_dsim_plat_data *pdata = dsi->plat_data; 1853 1854 if (pdata->host_ops && pdata->host_ops->te_irq_handler) 1855 return pdata->host_ops->te_irq_handler(dsi); 1856 1857 return IRQ_HANDLED; 1858} 1859 1860static int samsung_dsim_register_te_irq(struct samsung_dsim *dsi, struct device *dev) 1861{ 1862 int te_gpio_irq; 1863 int ret; 1864 1865 dsi->te_gpio = devm_gpiod_get_optional(dev, "te", GPIOD_IN); 1866 if (!dsi->te_gpio) 1867 return 0; 1868 else if (IS_ERR(dsi->te_gpio)) 1869 return dev_err_probe(dev, PTR_ERR(dsi->te_gpio), "failed to get te GPIO\n"); 1870 1871 te_gpio_irq = gpiod_to_irq(dsi->te_gpio); 1872 1873 ret = request_threaded_irq(te_gpio_irq, samsung_dsim_te_irq_handler, NULL, 1874 IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, "TE", dsi); 1875 if (ret) { 1876 dev_err(dsi->dev, "request interrupt failed with %d\n", ret); 1877 gpiod_put(dsi->te_gpio); 1878 return ret; 1879 } 1880 1881 return 0; 1882} 1883 1884static void samsung_dsim_unregister_te_irq(struct samsung_dsim *dsi) 1885{ 1886 if (dsi->te_gpio) { 1887 free_irq(gpiod_to_irq(dsi->te_gpio), dsi); 1888 gpiod_put(dsi->te_gpio); 1889 } 1890} 1891 1892static int samsung_dsim_host_attach(struct mipi_dsi_host *host, 1893 struct mipi_dsi_device *device) 1894{ 1895 struct samsung_dsim *dsi = host_to_dsi(host); 1896 const struct samsung_dsim_plat_data *pdata = dsi->plat_data; 1897 struct device *dev = dsi->dev; 1898 struct device_node *np = dev->of_node; 1899 struct device_node *remote; 1900 struct drm_panel *panel; 1901 int ret; 1902 1903 /* 1904 * Devices can also be child nodes when we also control that device 1905 * through the upstream device (ie, MIPI-DCS for a MIPI-DSI device). 1906 * 1907 * Lookup for a child node of the given parent that isn't either port 1908 * or ports. 1909 */ 1910 for_each_available_child_of_node(np, remote) { 1911 if (of_node_name_eq(remote, "port") || 1912 of_node_name_eq(remote, "ports")) 1913 continue; 1914 1915 goto of_find_panel_or_bridge; 1916 } 1917 1918 /* 1919 * of_graph_get_remote_node() produces a noisy error message if port 1920 * node isn't found and the absence of the port is a legit case here, 1921 * so at first we silently check whether graph presents in the 1922 * device-tree node. 1923 */ 1924 if (!of_graph_is_present(np)) 1925 return -ENODEV; 1926 1927 remote = of_graph_get_remote_node(np, 1, 0); 1928 1929of_find_panel_or_bridge: 1930 if (!remote) 1931 return -ENODEV; 1932 1933 panel = of_drm_find_panel(remote); 1934 if (!IS_ERR(panel)) { 1935 dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel); 1936 } else { 1937 dsi->out_bridge = of_drm_find_bridge(remote); 1938 if (!dsi->out_bridge) 1939 dsi->out_bridge = ERR_PTR(-EINVAL); 1940 } 1941 1942 of_node_put(remote); 1943 1944 if (IS_ERR(dsi->out_bridge)) { 1945 ret = PTR_ERR(dsi->out_bridge); 1946 DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret); 1947 return ret; 1948 } 1949 1950 DRM_DEV_INFO(dev, "Attached %s device (lanes:%d bpp:%d mode-flags:0x%lx)\n", 1951 device->name, device->lanes, 1952 mipi_dsi_pixel_format_to_bpp(device->format), 1953 device->mode_flags); 1954 1955 drm_bridge_add(&dsi->bridge); 1956 1957 /* 1958 * This is a temporary solution and should be made by more generic way. 1959 * 1960 * If attached panel device is for command mode one, dsi should register 1961 * TE interrupt handler. 1962 */ 1963 if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) { 1964 ret = samsung_dsim_register_te_irq(dsi, &device->dev); 1965 if (ret) 1966 goto err_remove_bridge; 1967 } 1968 1969 if (pdata->host_ops && pdata->host_ops->attach) { 1970 ret = pdata->host_ops->attach(dsi, device); 1971 if (ret) 1972 goto err_unregister_te_irq; 1973 } 1974 1975 dsi->lanes = device->lanes; 1976 dsi->format = device->format; 1977 dsi->mode_flags = device->mode_flags; 1978 1979 return 0; 1980 1981err_unregister_te_irq: 1982 if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) 1983 samsung_dsim_unregister_te_irq(dsi); 1984err_remove_bridge: 1985 drm_bridge_remove(&dsi->bridge); 1986 return ret; 1987} 1988 1989static int samsung_dsim_host_detach(struct mipi_dsi_host *host, 1990 struct mipi_dsi_device *device) 1991{ 1992 struct samsung_dsim *dsi = host_to_dsi(host); 1993 const struct samsung_dsim_plat_data *pdata = dsi->plat_data; 1994 1995 dsi->out_bridge = NULL; 1996 1997 if (pdata->host_ops && pdata->host_ops->detach) 1998 pdata->host_ops->detach(dsi, device); 1999 2000 samsung_dsim_unregister_te_irq(dsi); 2001 2002 drm_bridge_remove(&dsi->bridge); 2003 2004 return 0; 2005} 2006 2007static ssize_t samsung_dsim_host_transfer(struct mipi_dsi_host *host, 2008 const struct mipi_dsi_msg *msg) 2009{ 2010 struct samsung_dsim *dsi = host_to_dsi(host); 2011 struct samsung_dsim_transfer xfer; 2012 int ret; 2013 2014 if (!(dsi->state & DSIM_STATE_ENABLED)) 2015 return -EINVAL; 2016 2017 ret = samsung_dsim_init(dsi); 2018 if (ret) 2019 return ret; 2020 2021 ret = mipi_dsi_create_packet(&xfer.packet, msg); 2022 if (ret < 0) 2023 return ret; 2024 2025 xfer.rx_len = msg->rx_len; 2026 xfer.rx_payload = msg->rx_buf; 2027 xfer.flags = msg->flags; 2028 2029 ret = samsung_dsim_transfer(dsi, &xfer); 2030 return (ret < 0) ? ret : xfer.rx_done; 2031} 2032 2033static const struct mipi_dsi_host_ops samsung_dsim_ops = { 2034 .attach = samsung_dsim_host_attach, 2035 .detach = samsung_dsim_host_detach, 2036 .transfer = samsung_dsim_host_transfer, 2037}; 2038 2039static int samsung_dsim_of_read_u32(const struct device_node *np, 2040 const char *propname, u32 *out_value, bool optional) 2041{ 2042 int ret = of_property_read_u32(np, propname, out_value); 2043 2044 if (ret < 0 && !optional) 2045 pr_err("%pOF: failed to get '%s' property\n", np, propname); 2046 2047 return ret; 2048} 2049 2050static int samsung_dsim_parse_dt(struct samsung_dsim *dsi) 2051{ 2052 struct device *dev = dsi->dev; 2053 struct device_node *node = dev->of_node; 2054 u32 lane_polarities[5] = { 0 }; 2055 struct device_node *endpoint; 2056 int i, nr_lanes, ret; 2057 2058 ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency", 2059 &dsi->pll_clk_rate, 1); 2060 /* If it doesn't exist, read it from the clock instead of failing */ 2061 if (ret < 0) { 2062 dev_dbg(dev, "Using sclk_mipi for pll clock frequency\n"); 2063 dsi->pll_clk = devm_clk_get(dev, "sclk_mipi"); 2064 if (IS_ERR(dsi->pll_clk)) 2065 return PTR_ERR(dsi->pll_clk); 2066 } 2067 2068 /* If it doesn't exist, use pixel clock instead of failing */ 2069 ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency", 2070 &dsi->burst_clk_rate, 1); 2071 if (ret < 0) { 2072 dev_dbg(dev, "Using pixel clock for HS clock frequency\n"); 2073 dsi->burst_clk_rate = 0; 2074 } 2075 2076 ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency", 2077 &dsi->esc_clk_rate, 0); 2078 if (ret < 0) 2079 return ret; 2080 2081 endpoint = of_graph_get_endpoint_by_regs(node, 1, -1); 2082 nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes"); 2083 if (nr_lanes > 0 && nr_lanes <= 4) { 2084 /* Polarity 0 is clock lane, 1..4 are data lanes. */ 2085 of_property_read_u32_array(endpoint, "lane-polarities", 2086 lane_polarities, nr_lanes + 1); 2087 for (i = 1; i <= nr_lanes; i++) { 2088 if (lane_polarities[1] != lane_polarities[i]) 2089 DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match"); 2090 } 2091 if (lane_polarities[0]) 2092 dsi->swap_dn_dp_clk = true; 2093 if (lane_polarities[1]) 2094 dsi->swap_dn_dp_data = true; 2095 } 2096 2097 return 0; 2098} 2099 2100static int generic_dsim_register_host(struct samsung_dsim *dsi) 2101{ 2102 return mipi_dsi_host_register(&dsi->dsi_host); 2103} 2104 2105static void generic_dsim_unregister_host(struct samsung_dsim *dsi) 2106{ 2107 mipi_dsi_host_unregister(&dsi->dsi_host); 2108} 2109 2110static const struct samsung_dsim_host_ops generic_dsim_host_ops = { 2111 .register_host = generic_dsim_register_host, 2112 .unregister_host = generic_dsim_unregister_host, 2113}; 2114 2115static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_high = { 2116 .input_bus_flags = DRM_BUS_FLAG_DE_HIGH, 2117}; 2118 2119static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_low = { 2120 .input_bus_flags = DRM_BUS_FLAG_DE_LOW, 2121}; 2122 2123int samsung_dsim_probe(struct platform_device *pdev) 2124{ 2125 struct device *dev = &pdev->dev; 2126 struct samsung_dsim *dsi; 2127 int ret; 2128 2129 dsi = devm_drm_bridge_alloc(dev, struct samsung_dsim, bridge, &samsung_dsim_bridge_funcs); 2130 if (IS_ERR(dsi)) 2131 return PTR_ERR(dsi); 2132 2133 init_completion(&dsi->completed); 2134 spin_lock_init(&dsi->transfer_lock); 2135 INIT_LIST_HEAD(&dsi->transfer_list); 2136 2137 dsi->dsi_host.ops = &samsung_dsim_ops; 2138 dsi->dsi_host.dev = dev; 2139 2140 dsi->dev = dev; 2141 dsi->plat_data = of_device_get_match_data(dev); 2142 dsi->driver_data = samsung_dsim_types[dsi->plat_data->hw_type]; 2143 2144 dsi->supplies[0].supply = "vddcore"; 2145 dsi->supplies[1].supply = "vddio"; 2146 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), 2147 dsi->supplies); 2148 if (ret) 2149 return dev_err_probe(dev, ret, "failed to get regulators\n"); 2150 2151 ret = devm_clk_bulk_get(dev, dsi->driver_data->num_clks, 2152 dsi->driver_data->clk_data); 2153 if (ret) { 2154 dev_err(dev, "failed to get clocks in bulk (%d)\n", ret); 2155 return ret; 2156 } 2157 2158 dsi->reg_base = devm_platform_ioremap_resource(pdev, 0); 2159 if (IS_ERR(dsi->reg_base)) 2160 return PTR_ERR(dsi->reg_base); 2161 2162 dsi->phy = devm_phy_optional_get(dev, "dsim"); 2163 if (IS_ERR(dsi->phy)) { 2164 dev_info(dev, "failed to get dsim phy\n"); 2165 return PTR_ERR(dsi->phy); 2166 } 2167 2168 dsi->irq = platform_get_irq(pdev, 0); 2169 if (dsi->irq < 0) 2170 return dsi->irq; 2171 2172 ret = devm_request_threaded_irq(dev, dsi->irq, NULL, 2173 samsung_dsim_irq, 2174 IRQF_ONESHOT | IRQF_NO_AUTOEN, 2175 dev_name(dev), dsi); 2176 if (ret) { 2177 dev_err(dev, "failed to request dsi irq\n"); 2178 return ret; 2179 } 2180 2181 ret = samsung_dsim_parse_dt(dsi); 2182 if (ret) 2183 return ret; 2184 2185 platform_set_drvdata(pdev, dsi); 2186 2187 pm_runtime_enable(dev); 2188 2189 dsi->bridge.of_node = dev->of_node; 2190 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; 2191 2192 /* DE_LOW: i.MX8M Mini/Nano LCDIF-DSIM glue logic inverts HS/VS/DE */ 2193 if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) 2194 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_low; 2195 else 2196 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_high; 2197 2198 if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->register_host) { 2199 ret = dsi->plat_data->host_ops->register_host(dsi); 2200 if (ret) 2201 goto err_disable_runtime; 2202 } 2203 2204 return 0; 2205 2206err_disable_runtime: 2207 pm_runtime_disable(dev); 2208 2209 return ret; 2210} 2211EXPORT_SYMBOL_GPL(samsung_dsim_probe); 2212 2213void samsung_dsim_remove(struct platform_device *pdev) 2214{ 2215 struct samsung_dsim *dsi = platform_get_drvdata(pdev); 2216 2217 pm_runtime_disable(&pdev->dev); 2218 2219 if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->unregister_host) 2220 dsi->plat_data->host_ops->unregister_host(dsi); 2221} 2222EXPORT_SYMBOL_GPL(samsung_dsim_remove); 2223 2224static int samsung_dsim_suspend(struct device *dev) 2225{ 2226 struct samsung_dsim *dsi = dev_get_drvdata(dev); 2227 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 2228 int ret; 2229 2230 usleep_range(10000, 20000); 2231 2232 if (dsi->state & DSIM_STATE_INITIALIZED) { 2233 dsi->state &= ~DSIM_STATE_INITIALIZED; 2234 2235 samsung_dsim_disable_clock(dsi); 2236 2237 samsung_dsim_disable_irq(dsi); 2238 } 2239 2240 dsi->state &= ~DSIM_STATE_CMD_LPM; 2241 2242 phy_power_off(dsi->phy); 2243 2244 clk_bulk_disable_unprepare(driver_data->num_clks, driver_data->clk_data); 2245 2246 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 2247 if (ret < 0) 2248 dev_err(dsi->dev, "cannot disable regulators %d\n", ret); 2249 2250 return 0; 2251} 2252 2253static int samsung_dsim_resume(struct device *dev) 2254{ 2255 struct samsung_dsim *dsi = dev_get_drvdata(dev); 2256 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 2257 int ret; 2258 2259 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 2260 if (ret < 0) { 2261 dev_err(dsi->dev, "cannot enable regulators %d\n", ret); 2262 return ret; 2263 } 2264 2265 ret = clk_bulk_prepare_enable(driver_data->num_clks, driver_data->clk_data); 2266 if (ret < 0) 2267 goto err_clk; 2268 2269 ret = phy_power_on(dsi->phy); 2270 if (ret < 0) { 2271 dev_err(dsi->dev, "cannot enable phy %d\n", ret); 2272 goto err_clk; 2273 } 2274 2275 return 0; 2276 2277err_clk: 2278 clk_bulk_disable_unprepare(driver_data->num_clks, driver_data->clk_data); 2279 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 2280 2281 return ret; 2282} 2283 2284const struct dev_pm_ops samsung_dsim_pm_ops = { 2285 RUNTIME_PM_OPS(samsung_dsim_suspend, samsung_dsim_resume, NULL) 2286 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2287 pm_runtime_force_resume) 2288}; 2289EXPORT_SYMBOL_GPL(samsung_dsim_pm_ops); 2290 2291static const struct samsung_dsim_plat_data samsung_dsim_imx8mm_pdata = { 2292 .hw_type = DSIM_TYPE_IMX8MM, 2293 .host_ops = &generic_dsim_host_ops, 2294}; 2295 2296static const struct samsung_dsim_plat_data samsung_dsim_imx8mp_pdata = { 2297 .hw_type = DSIM_TYPE_IMX8MP, 2298 .host_ops = &generic_dsim_host_ops, 2299}; 2300 2301static const struct of_device_id samsung_dsim_of_match[] = { 2302 { 2303 .compatible = "fsl,imx8mm-mipi-dsim", 2304 .data = &samsung_dsim_imx8mm_pdata, 2305 }, 2306 { 2307 .compatible = "fsl,imx8mp-mipi-dsim", 2308 .data = &samsung_dsim_imx8mp_pdata, 2309 }, 2310 { /* sentinel. */ } 2311}; 2312MODULE_DEVICE_TABLE(of, samsung_dsim_of_match); 2313 2314static struct platform_driver samsung_dsim_driver = { 2315 .probe = samsung_dsim_probe, 2316 .remove = samsung_dsim_remove, 2317 .driver = { 2318 .name = "samsung-dsim", 2319 .pm = pm_ptr(&samsung_dsim_pm_ops), 2320 .of_match_table = samsung_dsim_of_match, 2321 }, 2322}; 2323 2324module_platform_driver(samsung_dsim_driver); 2325 2326MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>"); 2327MODULE_DESCRIPTION("Samsung MIPI DSIM controller bridge"); 2328MODULE_LICENSE("GPL");
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