ite-it66121.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) 2020 BayLibre, SAS
   4 * Author: Phong LE <ple@baylibre.com>
   5 * Copyright (C) 2018-2019, Artem Mygaiev
   6 * Copyright (C) 2017, Fresco Logic, Incorporated.
   7 *
   8 */
   9
  10#include <linux/media-bus-format.h>
  11#include <linux/module.h>
  12#include <linux/device.h>
  13#include <linux/interrupt.h>
  14#include <linux/i2c.h>
  15#include <linux/bitfield.h>
  16#include <linux/property.h>
  17#include <linux/regmap.h>
  18#include <linux/of_graph.h>
  19#include <linux/gpio/consumer.h>
  20#include <linux/pinctrl/consumer.h>
  21#include <linux/regulator/consumer.h>
  22
  23#include <drm/drm_atomic_helper.h>
  24#include <drm/drm_bridge.h>
  25#include <drm/drm_edid.h>
  26#include <drm/drm_modes.h>
  27#include <drm/drm_print.h>
  28#include <drm/drm_probe_helper.h>
  29
  30#include <sound/hdmi-codec.h>
  31
  32#define IT66121_VENDOR_ID0_REG			0x00
  33#define IT66121_VENDOR_ID1_REG			0x01
  34#define IT66121_DEVICE_ID0_REG			0x02
  35#define IT66121_DEVICE_ID1_REG			0x03
  36
  37#define IT66121_REVISION_MASK			GENMASK(7, 4)
  38#define IT66121_DEVICE_ID1_MASK			GENMASK(3, 0)
  39
  40#define IT66121_MASTER_SEL_REG			0x10
  41#define IT66121_MASTER_SEL_HOST			BIT(0)
  42
  43#define IT66121_AFE_DRV_REG			0x61
  44#define IT66121_AFE_DRV_RST			BIT(4)
  45#define IT66121_AFE_DRV_PWD			BIT(5)
  46
  47#define IT66121_INPUT_MODE_REG			0x70
  48#define IT66121_INPUT_MODE_RGB			(0 << 6)
  49#define IT66121_INPUT_MODE_YUV422		BIT(6)
  50#define IT66121_INPUT_MODE_YUV444		(2 << 6)
  51#define IT66121_INPUT_MODE_CCIR656		BIT(4)
  52#define IT66121_INPUT_MODE_SYNCEMB		BIT(3)
  53#define IT66121_INPUT_MODE_DDR			BIT(2)
  54
  55#define IT66121_INPUT_CSC_REG			0x72
  56#define IT66121_INPUT_CSC_ENDITHER		BIT(7)
  57#define IT66121_INPUT_CSC_ENUDFILTER		BIT(6)
  58#define IT66121_INPUT_CSC_DNFREE_GO		BIT(5)
  59#define IT66121_INPUT_CSC_RGB_TO_YUV		0x02
  60#define IT66121_INPUT_CSC_YUV_TO_RGB		0x03
  61#define IT66121_INPUT_CSC_NO_CONV		0x00
  62
  63#define IT66121_AFE_XP_REG			0x62
  64#define IT66121_AFE_XP_GAINBIT			BIT(7)
  65#define IT66121_AFE_XP_PWDPLL			BIT(6)
  66#define IT66121_AFE_XP_ENI			BIT(5)
  67#define IT66121_AFE_XP_ENO			BIT(4)
  68#define IT66121_AFE_XP_RESETB			BIT(3)
  69#define IT66121_AFE_XP_PWDI			BIT(2)
  70#define IT6610_AFE_XP_BYPASS			BIT(0)
  71
  72#define IT66121_AFE_IP_REG			0x64
  73#define IT66121_AFE_IP_GAINBIT			BIT(7)
  74#define IT66121_AFE_IP_PWDPLL			BIT(6)
  75#define IT66121_AFE_IP_CKSEL_05			(0 << 4)
  76#define IT66121_AFE_IP_CKSEL_1			BIT(4)
  77#define IT66121_AFE_IP_CKSEL_2			(2 << 4)
  78#define IT66121_AFE_IP_CKSEL_2OR4		(3 << 4)
  79#define IT66121_AFE_IP_ER0			BIT(3)
  80#define IT66121_AFE_IP_RESETB			BIT(2)
  81#define IT66121_AFE_IP_ENC			BIT(1)
  82#define IT66121_AFE_IP_EC1			BIT(0)
  83
  84#define IT66121_AFE_XP_EC1_REG			0x68
  85#define IT66121_AFE_XP_EC1_LOWCLK		BIT(4)
  86
  87#define IT66121_SW_RST_REG			0x04
  88#define IT66121_SW_RST_REF			BIT(5)
  89#define IT66121_SW_RST_AREF			BIT(4)
  90#define IT66121_SW_RST_VID			BIT(3)
  91#define IT66121_SW_RST_AUD			BIT(2)
  92#define IT66121_SW_RST_HDCP			BIT(0)
  93
  94#define IT66121_DDC_COMMAND_REG			0x15
  95#define IT66121_DDC_COMMAND_BURST_READ		0x0
  96#define IT66121_DDC_COMMAND_EDID_READ		0x3
  97#define IT66121_DDC_COMMAND_FIFO_CLR		0x9
  98#define IT66121_DDC_COMMAND_SCL_PULSE		0xA
  99#define IT66121_DDC_COMMAND_ABORT		0xF
 100
 101#define IT66121_HDCP_REG			0x20
 102#define IT66121_HDCP_CPDESIRED			BIT(0)
 103#define IT66121_HDCP_EN1P1FEAT			BIT(1)
 104
 105#define IT66121_INT_STATUS1_REG			0x06
 106#define IT66121_INT_STATUS1_AUD_OVF		BIT(7)
 107#define IT66121_INT_STATUS1_DDC_NOACK		BIT(5)
 108#define IT66121_INT_STATUS1_DDC_FIFOERR		BIT(4)
 109#define IT66121_INT_STATUS1_DDC_BUSHANG		BIT(2)
 110#define IT66121_INT_STATUS1_RX_SENS_STATUS	BIT(1)
 111#define IT66121_INT_STATUS1_HPD_STATUS		BIT(0)
 112
 113#define IT66121_DDC_HEADER_REG			0x11
 114#define IT66121_DDC_HEADER_HDCP			0x74
 115#define IT66121_DDC_HEADER_EDID			0xA0
 116
 117#define IT66121_DDC_OFFSET_REG			0x12
 118#define IT66121_DDC_BYTE_REG			0x13
 119#define IT66121_DDC_SEGMENT_REG			0x14
 120#define IT66121_DDC_RD_FIFO_REG			0x17
 121
 122#define IT66121_CLK_BANK_REG			0x0F
 123#define IT66121_CLK_BANK_PWROFF_RCLK		BIT(6)
 124#define IT66121_CLK_BANK_PWROFF_ACLK		BIT(5)
 125#define IT66121_CLK_BANK_PWROFF_TXCLK		BIT(4)
 126#define IT66121_CLK_BANK_PWROFF_CRCLK		BIT(3)
 127#define IT66121_CLK_BANK_0			0
 128#define IT66121_CLK_BANK_1			1
 129
 130#define IT66121_INT_REG				0x05
 131#define IT66121_INT_ACTIVE_HIGH			BIT(7)
 132#define IT66121_INT_OPEN_DRAIN			BIT(6)
 133#define IT66121_INT_TX_CLK_OFF			BIT(0)
 134
 135#define IT66121_INT_MASK1_REG			0x09
 136#define IT66121_INT_MASK1_AUD_OVF		BIT(7)
 137#define IT66121_INT_MASK1_DDC_NOACK		BIT(5)
 138#define IT66121_INT_MASK1_DDC_FIFOERR		BIT(4)
 139#define IT66121_INT_MASK1_DDC_BUSHANG		BIT(2)
 140#define IT66121_INT_MASK1_RX_SENS		BIT(1)
 141#define IT66121_INT_MASK1_HPD			BIT(0)
 142
 143#define IT66121_INT_CLR1_REG			0x0C
 144#define IT66121_INT_CLR1_PKTACP			BIT(7)
 145#define IT66121_INT_CLR1_PKTNULL		BIT(6)
 146#define IT66121_INT_CLR1_PKTGEN			BIT(5)
 147#define IT66121_INT_CLR1_KSVLISTCHK		BIT(4)
 148#define IT66121_INT_CLR1_AUTHDONE		BIT(3)
 149#define IT66121_INT_CLR1_AUTHFAIL		BIT(2)
 150#define IT66121_INT_CLR1_RX_SENS		BIT(1)
 151#define IT66121_INT_CLR1_HPD			BIT(0)
 152
 153#define IT66121_AV_MUTE_REG			0xC1
 154#define IT66121_AV_MUTE_ON			BIT(0)
 155#define IT66121_AV_MUTE_BLUESCR			BIT(1)
 156
 157#define IT66121_PKT_CTS_CTRL_REG		0xC5
 158#define IT66121_PKT_CTS_CTRL_SEL		BIT(1)
 159
 160#define IT66121_PKT_GEN_CTRL_REG		0xC6
 161#define IT66121_PKT_GEN_CTRL_ON			BIT(0)
 162#define IT66121_PKT_GEN_CTRL_RPT		BIT(1)
 163
 164#define IT66121_AVIINFO_DB1_REG			0x158
 165#define IT66121_AVIINFO_DB2_REG			0x159
 166#define IT66121_AVIINFO_DB3_REG			0x15A
 167#define IT66121_AVIINFO_DB4_REG			0x15B
 168#define IT66121_AVIINFO_DB5_REG			0x15C
 169#define IT66121_AVIINFO_CSUM_REG		0x15D
 170#define IT66121_AVIINFO_DB6_REG			0x15E
 171#define IT66121_AVIINFO_DB7_REG			0x15F
 172#define IT66121_AVIINFO_DB8_REG			0x160
 173#define IT66121_AVIINFO_DB9_REG			0x161
 174#define IT66121_AVIINFO_DB10_REG		0x162
 175#define IT66121_AVIINFO_DB11_REG		0x163
 176#define IT66121_AVIINFO_DB12_REG		0x164
 177#define IT66121_AVIINFO_DB13_REG		0x165
 178
 179#define IT66121_AVI_INFO_PKT_REG		0xCD
 180#define IT66121_AVI_INFO_PKT_ON			BIT(0)
 181#define IT66121_AVI_INFO_PKT_RPT		BIT(1)
 182
 183#define IT66121_HDMI_MODE_REG			0xC0
 184#define IT66121_HDMI_MODE_HDMI			BIT(0)
 185
 186#define IT66121_SYS_STATUS_REG			0x0E
 187#define IT66121_SYS_STATUS_ACTIVE_IRQ		BIT(7)
 188#define IT66121_SYS_STATUS_HPDETECT		BIT(6)
 189#define IT66121_SYS_STATUS_SENDECTECT		BIT(5)
 190#define IT66121_SYS_STATUS_VID_STABLE		BIT(4)
 191#define IT66121_SYS_STATUS_AUD_CTS_CLR		BIT(1)
 192#define IT66121_SYS_STATUS_CLEAR_IRQ		BIT(0)
 193
 194#define IT66121_DDC_STATUS_REG			0x16
 195#define IT66121_DDC_STATUS_TX_DONE		BIT(7)
 196#define IT66121_DDC_STATUS_ACTIVE		BIT(6)
 197#define IT66121_DDC_STATUS_NOACK		BIT(5)
 198#define IT66121_DDC_STATUS_WAIT_BUS		BIT(4)
 199#define IT66121_DDC_STATUS_ARBI_LOSE		BIT(3)
 200#define IT66121_DDC_STATUS_FIFO_FULL		BIT(2)
 201#define IT66121_DDC_STATUS_FIFO_EMPTY		BIT(1)
 202#define IT66121_DDC_STATUS_FIFO_VALID		BIT(0)
 203
 204#define IT66121_EDID_SLEEP_US			20000
 205#define IT66121_EDID_TIMEOUT_US			200000
 206#define IT66121_EDID_FIFO_SIZE			32
 207
 208#define IT66121_CLK_CTRL0_REG			0x58
 209#define IT66121_CLK_CTRL0_AUTO_OVER_SAMPLING	BIT(4)
 210#define IT66121_CLK_CTRL0_EXT_MCLK_MASK		GENMASK(3, 2)
 211#define IT66121_CLK_CTRL0_EXT_MCLK_128FS	(0 << 2)
 212#define IT66121_CLK_CTRL0_EXT_MCLK_256FS	BIT(2)
 213#define IT66121_CLK_CTRL0_EXT_MCLK_512FS	(2 << 2)
 214#define IT66121_CLK_CTRL0_EXT_MCLK_1024FS	(3 << 2)
 215#define IT66121_CLK_CTRL0_AUTO_IPCLK		BIT(0)
 216#define IT66121_CLK_STATUS1_REG			0x5E
 217#define IT66121_CLK_STATUS2_REG			0x5F
 218
 219#define IT66121_AUD_CTRL0_REG			0xE0
 220#define IT66121_AUD_SWL				(3 << 6)
 221#define IT66121_AUD_16BIT			(0 << 6)
 222#define IT66121_AUD_18BIT			BIT(6)
 223#define IT66121_AUD_20BIT			(2 << 6)
 224#define IT66121_AUD_24BIT			(3 << 6)
 225#define IT66121_AUD_SPDIFTC			BIT(5)
 226#define IT66121_AUD_SPDIF			BIT(4)
 227#define IT66121_AUD_I2S				(0 << 4)
 228#define IT66121_AUD_EN_I2S3			BIT(3)
 229#define IT66121_AUD_EN_I2S2			BIT(2)
 230#define IT66121_AUD_EN_I2S1			BIT(1)
 231#define IT66121_AUD_EN_I2S0			BIT(0)
 232#define IT66121_AUD_CTRL0_AUD_SEL		BIT(4)
 233
 234#define IT66121_AUD_CTRL1_REG			0xE1
 235#define IT66121_AUD_FIFOMAP_REG			0xE2
 236#define IT66121_AUD_CTRL3_REG			0xE3
 237#define IT66121_AUD_SRCVALID_FLAT_REG		0xE4
 238#define IT66121_AUD_FLAT_SRC0			BIT(4)
 239#define IT66121_AUD_FLAT_SRC1			BIT(5)
 240#define IT66121_AUD_FLAT_SRC2			BIT(6)
 241#define IT66121_AUD_FLAT_SRC3			BIT(7)
 242#define IT66121_AUD_HDAUDIO_REG			0xE5
 243
 244#define IT66121_AUD_PKT_CTS0_REG		0x130
 245#define IT66121_AUD_PKT_CTS1_REG		0x131
 246#define IT66121_AUD_PKT_CTS2_REG		0x132
 247#define IT66121_AUD_PKT_N0_REG			0x133
 248#define IT66121_AUD_PKT_N1_REG			0x134
 249#define IT66121_AUD_PKT_N2_REG			0x135
 250
 251#define IT66121_AUD_CHST_MODE_REG		0x191
 252#define IT66121_AUD_CHST_CAT_REG		0x192
 253#define IT66121_AUD_CHST_SRCNUM_REG		0x193
 254#define IT66121_AUD_CHST_CHTNUM_REG		0x194
 255#define IT66121_AUD_CHST_CA_FS_REG		0x198
 256#define IT66121_AUD_CHST_OFS_WL_REG		0x199
 257
 258#define IT66121_AUD_PKT_CTS_CNT0_REG		0x1A0
 259#define IT66121_AUD_PKT_CTS_CNT1_REG		0x1A1
 260#define IT66121_AUD_PKT_CTS_CNT2_REG		0x1A2
 261
 262#define IT66121_AUD_FS_22P05K			0x4
 263#define IT66121_AUD_FS_44P1K			0x0
 264#define IT66121_AUD_FS_88P2K			0x8
 265#define IT66121_AUD_FS_176P4K			0xC
 266#define IT66121_AUD_FS_24K			0x6
 267#define IT66121_AUD_FS_48K			0x2
 268#define IT66121_AUD_FS_96K			0xA
 269#define IT66121_AUD_FS_192K			0xE
 270#define IT66121_AUD_FS_768K			0x9
 271#define IT66121_AUD_FS_32K			0x3
 272#define IT66121_AUD_FS_OTHER			0x1
 273
 274#define IT66121_AUD_SWL_21BIT			0xD
 275#define IT66121_AUD_SWL_24BIT			0xB
 276#define IT66121_AUD_SWL_23BIT			0x9
 277#define IT66121_AUD_SWL_22BIT			0x5
 278#define IT66121_AUD_SWL_20BIT			0x3
 279#define IT66121_AUD_SWL_17BIT			0xC
 280#define IT66121_AUD_SWL_19BIT			0x8
 281#define IT66121_AUD_SWL_18BIT			0x4
 282#define IT66121_AUD_SWL_16BIT			0x2
 283#define IT66121_AUD_SWL_NOT_INDICATED		0x0
 284
 285#define IT66121_AFE_CLK_HIGH			80000 /* Khz */
 286
 287enum chip_id {
 288	ID_IT6610,
 289	ID_IT66121,
 290	ID_IT66122,
 291};
 292
 293struct it66121_chip_info {
 294	enum chip_id id;
 295	u16 vid, pid;
 296};
 297
 298struct it66121_ctx {
 299	struct regmap *regmap;
 300	struct drm_bridge bridge;
 301	struct drm_bridge *next_bridge;
 302	struct drm_connector *connector;
 303	struct device *dev;
 304	struct gpio_desc *gpio_reset;
 305	struct i2c_client *client;
 306	u32 bus_width;
 307	struct mutex lock; /* Protects fields below and device registers */
 308	struct hdmi_avi_infoframe hdmi_avi_infoframe;
 309	struct {
 310		struct platform_device *pdev;
 311		u8 ch_enable;
 312		u8 fs;
 313		u8 swl;
 314		bool auto_cts;
 315	} audio;
 316	enum chip_id id;
 317};
 318
 319static const struct regmap_range_cfg it66121_regmap_banks[] = {
 320	{
 321		.name = "it66121",
 322		.range_min = 0x00,
 323		.range_max = 0x1FF,
 324		.selector_reg = IT66121_CLK_BANK_REG,
 325		.selector_mask = 0x1,
 326		.selector_shift = 0,
 327		.window_start = 0x00,
 328		.window_len = 0x100,
 329	},
 330};
 331
 332static const struct regmap_config it66121_regmap_config = {
 333	.val_bits = 8,
 334	.reg_bits = 8,
 335	.max_register = 0x1FF,
 336	.ranges = it66121_regmap_banks,
 337	.num_ranges = ARRAY_SIZE(it66121_regmap_banks),
 338};
 339
 340static void it66121_hw_reset(struct it66121_ctx *ctx)
 341{
 342	gpiod_set_value(ctx->gpio_reset, 1);
 343	msleep(20);
 344	gpiod_set_value(ctx->gpio_reset, 0);
 345}
 346
 347static inline int it66121_preamble_ddc(struct it66121_ctx *ctx)
 348{
 349	return regmap_write(ctx->regmap, IT66121_MASTER_SEL_REG, IT66121_MASTER_SEL_HOST);
 350}
 351
 352static inline int it66121_fire_afe(struct it66121_ctx *ctx)
 353{
 354	return regmap_write(ctx->regmap, IT66121_AFE_DRV_REG, 0);
 355}
 356
 357/* TOFIX: Handle YCbCr Input & Output */
 358static int it66121_configure_input(struct it66121_ctx *ctx)
 359{
 360	int ret;
 361	u8 mode = IT66121_INPUT_MODE_RGB;
 362
 363	if (ctx->bus_width == 12)
 364		mode |= IT66121_INPUT_MODE_DDR;
 365
 366	ret = regmap_write(ctx->regmap, IT66121_INPUT_MODE_REG, mode);
 367	if (ret)
 368		return ret;
 369
 370	return regmap_write(ctx->regmap, IT66121_INPUT_CSC_REG, IT66121_INPUT_CSC_NO_CONV);
 371}
 372
 373/**
 374 * it66121_configure_afe() - Configure the analog front end
 375 * @ctx: it66121_ctx object
 376 * @mode: mode to configure
 377 *
 378 * RETURNS:
 379 * zero if success, a negative error code otherwise.
 380 */
 381static int it66121_configure_afe(struct it66121_ctx *ctx,
 382				 const struct drm_display_mode *mode)
 383{
 384	int ret;
 385
 386	ret = regmap_write(ctx->regmap, IT66121_AFE_DRV_REG,
 387			   IT66121_AFE_DRV_RST);
 388	if (ret)
 389		return ret;
 390
 391	if (mode->clock > IT66121_AFE_CLK_HIGH) {
 392		ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
 393					IT66121_AFE_XP_GAINBIT |
 394					IT66121_AFE_XP_ENO,
 395					IT66121_AFE_XP_GAINBIT);
 396		if (ret)
 397			return ret;
 398
 399		ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
 400					IT66121_AFE_IP_GAINBIT |
 401					IT66121_AFE_IP_ER0,
 402					IT66121_AFE_IP_GAINBIT);
 403		if (ret)
 404			return ret;
 405
 406		if (ctx->id == ID_IT66121 || ctx->id == ID_IT66122) {
 407			ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
 408						IT66121_AFE_IP_EC1, 0);
 409			if (ret)
 410				return ret;
 411
 412			ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG,
 413						IT66121_AFE_XP_EC1_LOWCLK, 0x80);
 414			if (ret)
 415				return ret;
 416		}
 417	} else {
 418		ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
 419					IT66121_AFE_XP_GAINBIT |
 420					IT66121_AFE_XP_ENO,
 421					IT66121_AFE_XP_ENO);
 422		if (ret)
 423			return ret;
 424
 425		ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
 426					IT66121_AFE_IP_GAINBIT |
 427					IT66121_AFE_IP_ER0,
 428					IT66121_AFE_IP_ER0);
 429		if (ret)
 430			return ret;
 431
 432		if (ctx->id == ID_IT66121 || ctx->id == ID_IT66122) {
 433			ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
 434						IT66121_AFE_IP_EC1,
 435						IT66121_AFE_IP_EC1);
 436			if (ret)
 437				return ret;
 438
 439			ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG,
 440						IT66121_AFE_XP_EC1_LOWCLK,
 441						IT66121_AFE_XP_EC1_LOWCLK);
 442			if (ret)
 443				return ret;
 444		}
 445	}
 446
 447	/* Clear reset flags */
 448	ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
 449				IT66121_SW_RST_REF | IT66121_SW_RST_VID, 0);
 450	if (ret)
 451		return ret;
 452
 453	if (ctx->id == ID_IT6610) {
 454		ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
 455					IT6610_AFE_XP_BYPASS,
 456					IT6610_AFE_XP_BYPASS);
 457		if (ret)
 458			return ret;
 459	}
 460
 461	return it66121_fire_afe(ctx);
 462}
 463
 464static inline int it66121_wait_ddc_ready(struct it66121_ctx *ctx)
 465{
 466	int ret, val;
 467	u32 error = IT66121_DDC_STATUS_NOACK | IT66121_DDC_STATUS_WAIT_BUS |
 468		    IT66121_DDC_STATUS_ARBI_LOSE;
 469	u32 done = IT66121_DDC_STATUS_TX_DONE;
 470
 471	ret = regmap_read_poll_timeout(ctx->regmap, IT66121_DDC_STATUS_REG, val,
 472				       val & (error | done), IT66121_EDID_SLEEP_US,
 473				       IT66121_EDID_TIMEOUT_US);
 474	if (ret)
 475		return ret;
 476
 477	if (val & error)
 478		return -EAGAIN;
 479
 480	return 0;
 481}
 482
 483static int it66121_abort_ddc_ops(struct it66121_ctx *ctx)
 484{
 485	int ret;
 486	unsigned int swreset, cpdesire;
 487
 488	ret = regmap_read(ctx->regmap, IT66121_SW_RST_REG, &swreset);
 489	if (ret)
 490		return ret;
 491
 492	ret = regmap_read(ctx->regmap, IT66121_HDCP_REG, &cpdesire);
 493	if (ret)
 494		return ret;
 495
 496	ret = regmap_write(ctx->regmap, IT66121_HDCP_REG,
 497			   cpdesire & (~IT66121_HDCP_CPDESIRED & 0xFF));
 498	if (ret)
 499		return ret;
 500
 501	ret = regmap_write(ctx->regmap, IT66121_SW_RST_REG,
 502			   (swreset | IT66121_SW_RST_HDCP));
 503	if (ret)
 504		return ret;
 505
 506	ret = it66121_preamble_ddc(ctx);
 507	if (ret)
 508		return ret;
 509
 510	ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
 511			   IT66121_DDC_COMMAND_ABORT);
 512	if (ret)
 513		return ret;
 514
 515	return it66121_wait_ddc_ready(ctx);
 516}
 517
 518static int it66121_get_edid_block(void *context, u8 *buf,
 519				  unsigned int block, size_t len)
 520{
 521	struct it66121_ctx *ctx = context;
 522	int remain = len;
 523	int offset = 0;
 524	int ret, cnt;
 525
 526	offset = (block % 2) * len;
 527	block = block / 2;
 528
 529	while (remain > 0) {
 530		cnt = (remain > IT66121_EDID_FIFO_SIZE) ?
 531				IT66121_EDID_FIFO_SIZE : remain;
 532
 533		ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
 534				   IT66121_DDC_COMMAND_FIFO_CLR);
 535		if (ret)
 536			return ret;
 537
 538		ret = it66121_wait_ddc_ready(ctx);
 539		if (ret)
 540			return ret;
 541
 542		ret = regmap_write(ctx->regmap, IT66121_DDC_OFFSET_REG, offset);
 543		if (ret)
 544			return ret;
 545
 546		ret = regmap_write(ctx->regmap, IT66121_DDC_BYTE_REG, cnt);
 547		if (ret)
 548			return ret;
 549
 550		ret = regmap_write(ctx->regmap, IT66121_DDC_SEGMENT_REG, block);
 551		if (ret)
 552			return ret;
 553
 554		ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
 555				   IT66121_DDC_COMMAND_EDID_READ);
 556		if (ret)
 557			return ret;
 558
 559		offset += cnt;
 560		remain -= cnt;
 561
 562		ret = it66121_wait_ddc_ready(ctx);
 563		if (ret) {
 564			it66121_abort_ddc_ops(ctx);
 565			return ret;
 566		}
 567
 568		ret = regmap_noinc_read(ctx->regmap, IT66121_DDC_RD_FIFO_REG,
 569					buf, cnt);
 570		if (ret)
 571			return ret;
 572
 573		buf += cnt;
 574	}
 575
 576	return 0;
 577}
 578
 579static bool it66121_is_hpd_detect(struct it66121_ctx *ctx)
 580{
 581	int val;
 582
 583	if (regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val))
 584		return false;
 585
 586	return val & IT66121_SYS_STATUS_HPDETECT;
 587}
 588
 589static int it66121_bridge_attach(struct drm_bridge *bridge,
 590				 struct drm_encoder *encoder,
 591				 enum drm_bridge_attach_flags flags)
 592{
 593	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 594	int ret;
 595
 596	if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
 597		return -EINVAL;
 598
 599	ret = drm_bridge_attach(encoder, ctx->next_bridge, bridge, flags);
 600	if (ret)
 601		return ret;
 602
 603	if (ctx->id == ID_IT66121 || ctx->id == ID_IT66122) {
 604		ret = regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG,
 605					IT66121_CLK_BANK_PWROFF_RCLK, 0);
 606		if (ret)
 607			return ret;
 608	}
 609
 610	ret = regmap_write_bits(ctx->regmap, IT66121_INT_REG,
 611				IT66121_INT_TX_CLK_OFF, 0);
 612	if (ret)
 613		return ret;
 614
 615	ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG,
 616				IT66121_AFE_DRV_PWD, 0);
 617	if (ret)
 618		return ret;
 619
 620	ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
 621				IT66121_AFE_XP_PWDI | IT66121_AFE_XP_PWDPLL, 0);
 622	if (ret)
 623		return ret;
 624
 625	ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
 626				IT66121_AFE_IP_PWDPLL, 0);
 627	if (ret)
 628		return ret;
 629
 630	ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG,
 631				IT66121_AFE_DRV_RST, 0);
 632	if (ret)
 633		return ret;
 634
 635	ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
 636				IT66121_AFE_XP_RESETB, IT66121_AFE_XP_RESETB);
 637	if (ret)
 638		return ret;
 639
 640	ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
 641				IT66121_AFE_IP_RESETB, IT66121_AFE_IP_RESETB);
 642	if (ret)
 643		return ret;
 644
 645	ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
 646				IT66121_SW_RST_REF,
 647				IT66121_SW_RST_REF);
 648	if (ret)
 649		return ret;
 650
 651	/* Per programming manual, sleep here for bridge to settle */
 652	msleep(50);
 653
 654	return 0;
 655}
 656
 657static int it66121_set_mute(struct it66121_ctx *ctx, bool mute)
 658{
 659	int ret;
 660	unsigned int val = 0;
 661
 662	if (mute)
 663		val = IT66121_AV_MUTE_ON;
 664
 665	ret = regmap_write_bits(ctx->regmap, IT66121_AV_MUTE_REG, IT66121_AV_MUTE_ON, val);
 666	if (ret)
 667		return ret;
 668
 669	return regmap_write(ctx->regmap, IT66121_PKT_GEN_CTRL_REG,
 670			    IT66121_PKT_GEN_CTRL_ON | IT66121_PKT_GEN_CTRL_RPT);
 671}
 672
 673#define MAX_OUTPUT_SEL_FORMATS	1
 674
 675static u32 *it66121_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
 676						      struct drm_bridge_state *bridge_state,
 677						      struct drm_crtc_state *crtc_state,
 678						      struct drm_connector_state *conn_state,
 679						      unsigned int *num_output_fmts)
 680{
 681	u32 *output_fmts;
 682
 683	output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
 684			      GFP_KERNEL);
 685	if (!output_fmts)
 686		return NULL;
 687
 688	/* TOFIX handle more than MEDIA_BUS_FMT_RGB888_1X24 as output format */
 689	output_fmts[0] =  MEDIA_BUS_FMT_RGB888_1X24;
 690	*num_output_fmts = 1;
 691
 692	return output_fmts;
 693}
 694
 695#define MAX_INPUT_SEL_FORMATS	1
 696
 697static u32 *it66121_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
 698						     struct drm_bridge_state *bridge_state,
 699						     struct drm_crtc_state *crtc_state,
 700						     struct drm_connector_state *conn_state,
 701						     u32 output_fmt,
 702						     unsigned int *num_input_fmts)
 703{
 704	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 705	u32 *input_fmts;
 706
 707	*num_input_fmts = 0;
 708
 709	input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
 710			     GFP_KERNEL);
 711	if (!input_fmts)
 712		return NULL;
 713
 714	if (ctx->bus_width == 12)
 715		/* IT66121FN Datasheet specifies Little-Endian ordering */
 716		input_fmts[0] = MEDIA_BUS_FMT_RGB888_2X12_LE;
 717	else
 718		/* TOFIX support more input bus formats in 24bit width */
 719		input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
 720	*num_input_fmts = 1;
 721
 722	return input_fmts;
 723}
 724
 725static void it66121_bridge_enable(struct drm_bridge *bridge,
 726				  struct drm_atomic_state *state)
 727{
 728	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 729
 730	ctx->connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
 731
 732	it66121_set_mute(ctx, false);
 733}
 734
 735static void it66121_bridge_disable(struct drm_bridge *bridge,
 736				   struct drm_atomic_state *state)
 737{
 738	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 739
 740	it66121_set_mute(ctx, true);
 741
 742	ctx->connector = NULL;
 743}
 744
 745static int it66121_bridge_check(struct drm_bridge *bridge,
 746				struct drm_bridge_state *bridge_state,
 747				struct drm_crtc_state *crtc_state,
 748				struct drm_connector_state *conn_state)
 749{
 750	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 751
 752	if (ctx->id == ID_IT6610) {
 753		/* The IT6610 only supports these settings */
 754		bridge_state->input_bus_cfg.flags |= DRM_BUS_FLAG_DE_HIGH |
 755			DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE;
 756		bridge_state->input_bus_cfg.flags &=
 757			~DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE;
 758	}
 759
 760	return 0;
 761}
 762
 763static
 764void it66121_bridge_mode_set(struct drm_bridge *bridge,
 765			     const struct drm_display_mode *mode,
 766			     const struct drm_display_mode *adjusted_mode)
 767{
 768	u8 buf[HDMI_INFOFRAME_SIZE(AVI)];
 769	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 770	int ret;
 771
 772	mutex_lock(&ctx->lock);
 773
 774	ret = drm_hdmi_avi_infoframe_from_display_mode(&ctx->hdmi_avi_infoframe, ctx->connector,
 775						       adjusted_mode);
 776	if (ret) {
 777		DRM_ERROR("Failed to setup AVI infoframe: %d\n", ret);
 778		goto unlock;
 779	}
 780
 781	ret = hdmi_avi_infoframe_pack(&ctx->hdmi_avi_infoframe, buf, sizeof(buf));
 782	if (ret < 0) {
 783		DRM_ERROR("Failed to pack infoframe: %d\n", ret);
 784		goto unlock;
 785	}
 786
 787	/* Write new AVI infoframe packet */
 788	ret = regmap_bulk_write(ctx->regmap, IT66121_AVIINFO_DB1_REG,
 789				&buf[HDMI_INFOFRAME_HEADER_SIZE],
 790				HDMI_AVI_INFOFRAME_SIZE);
 791	if (ret)
 792		goto unlock;
 793
 794	if (regmap_write(ctx->regmap, IT66121_AVIINFO_CSUM_REG, buf[3]))
 795		goto unlock;
 796
 797	/* Enable AVI infoframe */
 798	if (regmap_write(ctx->regmap, IT66121_AVI_INFO_PKT_REG,
 799			 IT66121_AVI_INFO_PKT_ON | IT66121_AVI_INFO_PKT_RPT))
 800		goto unlock;
 801
 802	/* Set TX mode to HDMI */
 803	if (regmap_write(ctx->regmap, IT66121_HDMI_MODE_REG, IT66121_HDMI_MODE_HDMI))
 804		goto unlock;
 805
 806	if ((ctx->id == ID_IT66121 || ctx->id == ID_IT66122) &&
 807	    regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG,
 808			      IT66121_CLK_BANK_PWROFF_TXCLK,
 809			      IT66121_CLK_BANK_PWROFF_TXCLK)) {
 810		goto unlock;
 811	}
 812
 813	if (it66121_configure_input(ctx))
 814		goto unlock;
 815
 816	if (it66121_configure_afe(ctx, adjusted_mode))
 817		goto unlock;
 818
 819	if ((ctx->id == ID_IT66121 || ctx->id == ID_IT66122) &&
 820	    regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG,
 821			      IT66121_CLK_BANK_PWROFF_TXCLK, 0)) {
 822		goto unlock;
 823	}
 824
 825unlock:
 826	mutex_unlock(&ctx->lock);
 827}
 828
 829static enum drm_mode_status it66121_bridge_mode_valid(struct drm_bridge *bridge,
 830						      const struct drm_display_info *info,
 831						      const struct drm_display_mode *mode)
 832{
 833	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 834	unsigned long max_clock;
 835
 836	max_clock = (ctx->bus_width == 12) ? 74250 : 148500;
 837
 838	if (mode->clock > max_clock)
 839		return MODE_CLOCK_HIGH;
 840
 841	if (mode->clock < 25000)
 842		return MODE_CLOCK_LOW;
 843
 844	return MODE_OK;
 845}
 846
 847static enum drm_connector_status
 848it66121_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector)
 849{
 850	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 851
 852	return it66121_is_hpd_detect(ctx) ? connector_status_connected
 853					  : connector_status_disconnected;
 854}
 855
 856static void it66121_bridge_hpd_enable(struct drm_bridge *bridge)
 857{
 858	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 859	int ret;
 860
 861	ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, IT66121_INT_MASK1_HPD, 0);
 862	if (ret)
 863		dev_err(ctx->dev, "failed to enable HPD IRQ\n");
 864}
 865
 866static void it66121_bridge_hpd_disable(struct drm_bridge *bridge)
 867{
 868	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 869	int ret;
 870
 871	ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG,
 872				IT66121_INT_MASK1_HPD, IT66121_INT_MASK1_HPD);
 873	if (ret)
 874		dev_err(ctx->dev, "failed to disable HPD IRQ\n");
 875}
 876
 877static const struct drm_edid *it66121_bridge_edid_read(struct drm_bridge *bridge,
 878						       struct drm_connector *connector)
 879{
 880	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
 881	const struct drm_edid *drm_edid;
 882	int ret;
 883
 884	mutex_lock(&ctx->lock);
 885	ret = it66121_preamble_ddc(ctx);
 886	if (ret) {
 887		drm_edid = NULL;
 888		goto out_unlock;
 889	}
 890
 891	ret = regmap_write(ctx->regmap, IT66121_DDC_HEADER_REG,
 892			   IT66121_DDC_HEADER_EDID);
 893	if (ret) {
 894		drm_edid = NULL;
 895		goto out_unlock;
 896	}
 897
 898	drm_edid = drm_edid_read_custom(connector, it66121_get_edid_block, ctx);
 899
 900out_unlock:
 901	mutex_unlock(&ctx->lock);
 902
 903	return drm_edid;
 904}
 905
 906static const struct drm_bridge_funcs it66121_bridge_funcs = {
 907	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
 908	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
 909	.atomic_reset = drm_atomic_helper_bridge_reset,
 910	.attach = it66121_bridge_attach,
 911	.atomic_get_output_bus_fmts = it66121_bridge_atomic_get_output_bus_fmts,
 912	.atomic_get_input_bus_fmts = it66121_bridge_atomic_get_input_bus_fmts,
 913	.atomic_enable = it66121_bridge_enable,
 914	.atomic_disable = it66121_bridge_disable,
 915	.atomic_check = it66121_bridge_check,
 916	.mode_set = it66121_bridge_mode_set,
 917	.mode_valid = it66121_bridge_mode_valid,
 918	.detect = it66121_bridge_detect,
 919	.edid_read = it66121_bridge_edid_read,
 920	.hpd_enable = it66121_bridge_hpd_enable,
 921	.hpd_disable = it66121_bridge_hpd_disable,
 922};
 923
 924static irqreturn_t it66121_irq_threaded_handler(int irq, void *dev_id)
 925{
 926	int ret;
 927	unsigned int val;
 928	struct it66121_ctx *ctx = dev_id;
 929	struct device *dev = ctx->dev;
 930	enum drm_connector_status status;
 931	bool event = false;
 932
 933	mutex_lock(&ctx->lock);
 934
 935	ret = regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val);
 936	if (ret)
 937		goto unlock;
 938
 939	if (!(val & IT66121_SYS_STATUS_ACTIVE_IRQ))
 940		goto unlock;
 941
 942	ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val);
 943	if (ret) {
 944		dev_err(dev, "Cannot read STATUS1_REG %d\n", ret);
 945	} else if (val & IT66121_INT_STATUS1_HPD_STATUS) {
 946		regmap_write_bits(ctx->regmap, IT66121_INT_CLR1_REG,
 947				  IT66121_INT_CLR1_HPD, IT66121_INT_CLR1_HPD);
 948
 949		status = it66121_is_hpd_detect(ctx) ? connector_status_connected
 950			: connector_status_disconnected;
 951
 952		event = true;
 953	}
 954
 955	regmap_write_bits(ctx->regmap, IT66121_SYS_STATUS_REG,
 956			  IT66121_SYS_STATUS_CLEAR_IRQ,
 957			  IT66121_SYS_STATUS_CLEAR_IRQ);
 958
 959unlock:
 960	mutex_unlock(&ctx->lock);
 961
 962	if (event)
 963		drm_bridge_hpd_notify(&ctx->bridge, status);
 964
 965	return IRQ_HANDLED;
 966}
 967
 968static int it661221_set_chstat(struct it66121_ctx *ctx, u8 iec60958_chstat[])
 969{
 970	int ret;
 971
 972	ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_MODE_REG, iec60958_chstat[0] & 0x7C);
 973	if (ret)
 974		return ret;
 975
 976	ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CAT_REG, iec60958_chstat[1]);
 977	if (ret)
 978		return ret;
 979
 980	ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_SRCNUM_REG, iec60958_chstat[2] & 0x0F);
 981	if (ret)
 982		return ret;
 983
 984	ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CHTNUM_REG,
 985			   (iec60958_chstat[2] >> 4) & 0x0F);
 986	if (ret)
 987		return ret;
 988
 989	ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CA_FS_REG, iec60958_chstat[3]);
 990	if (ret)
 991		return ret;
 992
 993	return regmap_write(ctx->regmap, IT66121_AUD_CHST_OFS_WL_REG, iec60958_chstat[4]);
 994}
 995
 996static int it661221_set_lpcm_audio(struct it66121_ctx *ctx, u8 audio_src_num, u8 audio_swl)
 997{
 998	int ret;
 999	unsigned int audio_enable = 0;
1000	unsigned int audio_format = 0;
1001
1002	switch (audio_swl) {
1003	case 16:
1004		audio_enable |= IT66121_AUD_16BIT;
1005		break;
1006	case 18:
1007		audio_enable |= IT66121_AUD_18BIT;
1008		break;
1009	case 20:
1010		audio_enable |= IT66121_AUD_20BIT;
1011		break;
1012	case 24:
1013	default:
1014		audio_enable |= IT66121_AUD_24BIT;
1015		break;
1016	}
1017
1018	audio_format |= 0x40;
1019	switch (audio_src_num) {
1020	case 4:
1021		audio_enable |= IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 |
1022				IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0;
1023		break;
1024	case 3:
1025		audio_enable |= IT66121_AUD_EN_I2S2 | IT66121_AUD_EN_I2S1 |
1026				IT66121_AUD_EN_I2S0;
1027		break;
1028	case 2:
1029		audio_enable |= IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0;
1030		break;
1031	case 1:
1032	default:
1033		audio_format &= ~0x40;
1034		audio_enable |= IT66121_AUD_EN_I2S0;
1035		break;
1036	}
1037
1038	audio_format |= 0x01;
1039	ctx->audio.ch_enable = audio_enable;
1040
1041	ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, audio_enable & 0xF0);
1042	if (ret)
1043		return ret;
1044
1045	ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL1_REG, audio_format);
1046	if (ret)
1047		return ret;
1048
1049	ret = regmap_write(ctx->regmap, IT66121_AUD_FIFOMAP_REG, 0xE4);
1050	if (ret)
1051		return ret;
1052
1053	ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL3_REG, 0x00);
1054	if (ret)
1055		return ret;
1056
1057	ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0x00);
1058	if (ret)
1059		return ret;
1060
1061	return regmap_write(ctx->regmap, IT66121_AUD_HDAUDIO_REG, 0x00);
1062}
1063
1064static int it661221_set_ncts(struct it66121_ctx *ctx, u8 fs)
1065{
1066	int ret;
1067	unsigned int n;
1068
1069	switch (fs) {
1070	case IT66121_AUD_FS_32K:
1071		n = 4096;
1072		break;
1073	case IT66121_AUD_FS_44P1K:
1074		n = 6272;
1075		break;
1076	case IT66121_AUD_FS_48K:
1077		n = 6144;
1078		break;
1079	case IT66121_AUD_FS_88P2K:
1080		n = 12544;
1081		break;
1082	case IT66121_AUD_FS_96K:
1083		n = 12288;
1084		break;
1085	case IT66121_AUD_FS_176P4K:
1086		n = 25088;
1087		break;
1088	case IT66121_AUD_FS_192K:
1089		n = 24576;
1090		break;
1091	case IT66121_AUD_FS_768K:
1092		n = 24576;
1093		break;
1094	default:
1095		n = 6144;
1096		break;
1097	}
1098
1099	ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N0_REG, (u8)((n) & 0xFF));
1100	if (ret)
1101		return ret;
1102
1103	ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N1_REG, (u8)((n >> 8) & 0xFF));
1104	if (ret)
1105		return ret;
1106
1107	ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N2_REG, (u8)((n >> 16) & 0xF));
1108	if (ret)
1109		return ret;
1110
1111	if (ctx->audio.auto_cts) {
1112		u8 loop_cnt = 255;
1113		u8 cts_stable_cnt = 0;
1114		unsigned int sum_cts = 0;
1115		unsigned int cts = 0;
1116		unsigned int last_cts = 0;
1117		unsigned int diff;
1118		unsigned int val;
1119
1120		while (loop_cnt--) {
1121			msleep(30);
1122			regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT2_REG, &val);
1123			cts = val << 12;
1124			regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT1_REG, &val);
1125			cts |= val << 4;
1126			regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT0_REG, &val);
1127			cts |= val >> 4;
1128			if (cts == 0) {
1129				continue;
1130			} else {
1131				if (last_cts > cts)
1132					diff = last_cts - cts;
1133				else
1134					diff = cts - last_cts;
1135				last_cts = cts;
1136				if (diff < 5) {
1137					cts_stable_cnt++;
1138					sum_cts += cts;
1139				} else {
1140					cts_stable_cnt = 0;
1141					sum_cts = 0;
1142					continue;
1143				}
1144
1145				if (cts_stable_cnt >= 32) {
1146					last_cts = (sum_cts >> 5);
1147					break;
1148				}
1149			}
1150		}
1151
1152		regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS0_REG, (u8)((last_cts) & 0xFF));
1153		regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS1_REG, (u8)((last_cts >> 8) & 0xFF));
1154		regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS2_REG, (u8)((last_cts >> 16) & 0x0F));
1155	}
1156
1157	ret = regmap_write(ctx->regmap, 0xF8, 0xC3);
1158	if (ret)
1159		return ret;
1160
1161	ret = regmap_write(ctx->regmap, 0xF8, 0xA5);
1162	if (ret)
1163		return ret;
1164
1165	if (ctx->audio.auto_cts) {
1166		ret = regmap_write_bits(ctx->regmap, IT66121_PKT_CTS_CTRL_REG,
1167					IT66121_PKT_CTS_CTRL_SEL,
1168					1);
1169	} else {
1170		ret = regmap_write_bits(ctx->regmap, IT66121_PKT_CTS_CTRL_REG,
1171					IT66121_PKT_CTS_CTRL_SEL,
1172					0);
1173	}
1174
1175	if (ret)
1176		return ret;
1177
1178	return regmap_write(ctx->regmap, 0xF8, 0xFF);
1179}
1180
1181static int it661221_audio_output_enable(struct it66121_ctx *ctx, bool enable)
1182{
1183	int ret;
1184
1185	if (enable) {
1186		ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
1187					IT66121_SW_RST_AUD | IT66121_SW_RST_AREF,
1188					0);
1189		if (ret)
1190			return ret;
1191
1192		ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG,
1193					IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 |
1194					IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0,
1195					ctx->audio.ch_enable);
1196	} else {
1197		ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG,
1198					IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 |
1199					IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0,
1200					ctx->audio.ch_enable & 0xF0);
1201		if (ret)
1202			return ret;
1203
1204		ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
1205					IT66121_SW_RST_AUD | IT66121_SW_RST_AREF,
1206					IT66121_SW_RST_AUD | IT66121_SW_RST_AREF);
1207	}
1208
1209	return ret;
1210}
1211
1212static int it661221_audio_ch_enable(struct it66121_ctx *ctx, bool enable)
1213{
1214	int ret;
1215
1216	if (enable) {
1217		ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0);
1218		if (ret)
1219			return ret;
1220
1221		ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, ctx->audio.ch_enable);
1222	} else {
1223		ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, ctx->audio.ch_enable & 0xF0);
1224	}
1225
1226	return ret;
1227}
1228
1229static int it66121_audio_hw_params(struct device *dev, void *data,
1230				   struct hdmi_codec_daifmt *daifmt,
1231				   struct hdmi_codec_params *params)
1232{
1233	u8 fs;
1234	u8 swl;
1235	int ret;
1236	struct it66121_ctx *ctx = dev_get_drvdata(dev);
1237	static u8 iec60958_chstat[5];
1238	unsigned int channels = params->channels;
1239	unsigned int sample_rate = params->sample_rate;
1240	unsigned int sample_width = params->sample_width;
1241
1242	mutex_lock(&ctx->lock);
1243	dev_dbg(dev, "%s: %u, %u, %u, %u\n", __func__,
1244		daifmt->fmt, sample_rate, sample_width, channels);
1245
1246	switch (daifmt->fmt) {
1247	case HDMI_I2S:
1248		dev_dbg(dev, "Using HDMI I2S\n");
1249		break;
1250	default:
1251		dev_err(dev, "Invalid or unsupported DAI format %d\n", daifmt->fmt);
1252		ret = -EINVAL;
1253		goto out;
1254	}
1255
1256	// Set audio clock recovery (N/CTS)
1257	ret = regmap_write(ctx->regmap, IT66121_CLK_CTRL0_REG,
1258			   IT66121_CLK_CTRL0_AUTO_OVER_SAMPLING |
1259			   IT66121_CLK_CTRL0_EXT_MCLK_256FS |
1260			   IT66121_CLK_CTRL0_AUTO_IPCLK);
1261	if (ret)
1262		goto out;
1263
1264	ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG,
1265				IT66121_AUD_CTRL0_AUD_SEL, 0); // remove spdif selection
1266	if (ret)
1267		goto out;
1268
1269	switch (sample_rate) {
1270	case 44100L:
1271		fs = IT66121_AUD_FS_44P1K;
1272		break;
1273	case 88200L:
1274		fs = IT66121_AUD_FS_88P2K;
1275		break;
1276	case 176400L:
1277		fs = IT66121_AUD_FS_176P4K;
1278		break;
1279	case 32000L:
1280		fs = IT66121_AUD_FS_32K;
1281		break;
1282	case 48000L:
1283		fs = IT66121_AUD_FS_48K;
1284		break;
1285	case 96000L:
1286		fs = IT66121_AUD_FS_96K;
1287		break;
1288	case 192000L:
1289		fs = IT66121_AUD_FS_192K;
1290		break;
1291	case 768000L:
1292		fs = IT66121_AUD_FS_768K;
1293		break;
1294	default:
1295		fs = IT66121_AUD_FS_48K;
1296		break;
1297	}
1298
1299	ctx->audio.fs = fs;
1300	ret = it661221_set_ncts(ctx, fs);
1301	if (ret) {
1302		dev_err(dev, "Failed to set N/CTS: %d\n", ret);
1303		goto out;
1304	}
1305
1306	// Set audio format register (except audio channel enable)
1307	ret = it661221_set_lpcm_audio(ctx, (channels + 1) / 2, sample_width);
1308	if (ret) {
1309		dev_err(dev, "Failed to set LPCM audio: %d\n", ret);
1310		goto out;
1311	}
1312
1313	// Set audio channel status
1314	iec60958_chstat[0] = 0;
1315	if ((channels + 1) / 2 == 1)
1316		iec60958_chstat[0] |= 0x1;
1317	iec60958_chstat[0] &= ~(1 << 1);
1318	iec60958_chstat[1] = 0;
1319	iec60958_chstat[2] = (channels + 1) / 2;
1320	iec60958_chstat[2] |= (channels << 4) & 0xF0;
1321	iec60958_chstat[3] = fs;
1322
1323	switch (sample_width) {
1324	case 21L:
1325		swl = IT66121_AUD_SWL_21BIT;
1326		break;
1327	case 24L:
1328		swl = IT66121_AUD_SWL_24BIT;
1329		break;
1330	case 23L:
1331		swl = IT66121_AUD_SWL_23BIT;
1332		break;
1333	case 22L:
1334		swl = IT66121_AUD_SWL_22BIT;
1335		break;
1336	case 20L:
1337		swl = IT66121_AUD_SWL_20BIT;
1338		break;
1339	case 17L:
1340		swl = IT66121_AUD_SWL_17BIT;
1341		break;
1342	case 19L:
1343		swl = IT66121_AUD_SWL_19BIT;
1344		break;
1345	case 18L:
1346		swl = IT66121_AUD_SWL_18BIT;
1347		break;
1348	case 16L:
1349		swl = IT66121_AUD_SWL_16BIT;
1350		break;
1351	default:
1352		swl = IT66121_AUD_SWL_NOT_INDICATED;
1353		break;
1354	}
1355
1356	iec60958_chstat[4] = (((~fs) << 4) & 0xF0) | swl;
1357	ret = it661221_set_chstat(ctx, iec60958_chstat);
1358	if (ret) {
1359		dev_err(dev, "Failed to set channel status: %d\n", ret);
1360		goto out;
1361	}
1362
1363	// Enable audio channel enable while input clock stable (if SPDIF).
1364	ret = it661221_audio_ch_enable(ctx, true);
1365	if (ret) {
1366		dev_err(dev, "Failed to enable audio channel: %d\n", ret);
1367		goto out;
1368	}
1369
1370	ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG,
1371				IT66121_INT_MASK1_AUD_OVF,
1372				0);
1373	if (ret)
1374		goto out;
1375
1376	dev_dbg(dev, "HDMI audio enabled.\n");
1377out:
1378	mutex_unlock(&ctx->lock);
1379
1380	return ret;
1381}
1382
1383static int it66121_audio_startup(struct device *dev, void *data)
1384{
1385	int ret;
1386	struct it66121_ctx *ctx = dev_get_drvdata(dev);
1387
1388	mutex_lock(&ctx->lock);
1389	ret = it661221_audio_output_enable(ctx, true);
1390	if (ret)
1391		dev_err(dev, "Failed to enable audio output: %d\n", ret);
1392
1393	mutex_unlock(&ctx->lock);
1394
1395	return ret;
1396}
1397
1398static void it66121_audio_shutdown(struct device *dev, void *data)
1399{
1400	int ret;
1401	struct it66121_ctx *ctx = dev_get_drvdata(dev);
1402
1403	mutex_lock(&ctx->lock);
1404	ret = it661221_audio_output_enable(ctx, false);
1405	if (ret)
1406		dev_err(dev, "Failed to disable audio output: %d\n", ret);
1407
1408	mutex_unlock(&ctx->lock);
1409}
1410
1411static int it66121_audio_mute(struct device *dev, void *data,
1412			      bool enable, int direction)
1413{
1414	int ret;
1415	struct it66121_ctx *ctx = dev_get_drvdata(dev);
1416
1417	dev_dbg(dev, "%s: enable=%s, direction=%d\n",
1418		__func__, enable ? "true" : "false", direction);
1419
1420	mutex_lock(&ctx->lock);
1421
1422	if (enable) {
1423		ret = regmap_write_bits(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG,
1424					IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 |
1425					IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3,
1426					IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 |
1427					IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3);
1428	} else {
1429		ret = regmap_write_bits(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG,
1430					IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 |
1431					IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3,
1432					0);
1433	}
1434
1435	mutex_unlock(&ctx->lock);
1436
1437	return ret;
1438}
1439
1440static int it66121_audio_get_eld(struct device *dev, void *data,
1441				 u8 *buf, size_t len)
1442{
1443	struct it66121_ctx *ctx = dev_get_drvdata(dev);
1444
1445	mutex_lock(&ctx->lock);
1446	if (!ctx->connector) {
1447		/* Pass en empty ELD if connector not available */
1448		dev_dbg(dev, "No connector present, passing empty EDID data");
1449		memset(buf, 0, len);
1450	} else {
1451		mutex_lock(&ctx->connector->eld_mutex);
1452		memcpy(buf, ctx->connector->eld,
1453		       min(sizeof(ctx->connector->eld), len));
1454		mutex_unlock(&ctx->connector->eld_mutex);
1455	}
1456	mutex_unlock(&ctx->lock);
1457
1458	return 0;
1459}
1460
1461static const struct hdmi_codec_ops it66121_audio_codec_ops = {
1462	.hw_params = it66121_audio_hw_params,
1463	.audio_startup = it66121_audio_startup,
1464	.audio_shutdown = it66121_audio_shutdown,
1465	.mute_stream = it66121_audio_mute,
1466	.get_eld = it66121_audio_get_eld,
1467};
1468
1469static int it66121_audio_codec_init(struct it66121_ctx *ctx, struct device *dev)
1470{
1471	struct hdmi_codec_pdata codec_data = {
1472		.ops = &it66121_audio_codec_ops,
1473		.i2s = 1, /* Only i2s support for now */
1474		.spdif = 0,
1475		.max_i2s_channels = 8,
1476		.no_capture_mute = 1,
1477	};
1478
1479	if (!of_property_present(dev->of_node, "#sound-dai-cells")) {
1480		dev_info(dev, "No \"#sound-dai-cells\", no audio\n");
1481		return 0;
1482	}
1483
1484	ctx->audio.pdev = platform_device_register_data(dev,
1485							HDMI_CODEC_DRV_NAME,
1486							PLATFORM_DEVID_AUTO,
1487							&codec_data,
1488							sizeof(codec_data));
1489
1490	if (IS_ERR(ctx->audio.pdev)) {
1491		dev_err(dev, "Failed to initialize HDMI audio codec: %d\n",
1492			PTR_ERR_OR_ZERO(ctx->audio.pdev));
1493	}
1494
1495	return PTR_ERR_OR_ZERO(ctx->audio.pdev);
1496}
1497
1498static const char * const it66121_supplies[] = {
1499	"vcn33", "vcn18", "vrf12"
1500};
1501
1502static const struct it66121_chip_info it66xx_chip_info[] = {
1503	{.id = ID_IT6610, .vid = 0xca00, .pid = 0x0611 },
1504	{.id = ID_IT66121, .vid = 0x4954, .pid = 0x0612 },
1505	{.id = ID_IT66122, .vid = 0x4954, .pid = 0x0622 },
1506};
1507
1508static int it66121_probe(struct i2c_client *client)
1509{
1510	u32 revision_id, vendor_ids[2] = { 0 }, device_ids[2] = { 0 };
1511	struct device_node *ep;
1512	int ret, i;
1513	struct it66121_ctx *ctx;
1514	struct device *dev = &client->dev;
1515	const struct it66121_chip_info *chip_info;
1516
1517	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1518		dev_err(dev, "I2C check functionality failed.\n");
1519		return -ENXIO;
1520	}
1521
1522	ctx = devm_drm_bridge_alloc(dev, struct it66121_ctx, bridge,
1523				    &it66121_bridge_funcs);
1524	if (IS_ERR(ctx))
1525		return PTR_ERR(ctx);
1526
1527	ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
1528	if (!ep)
1529		return -EINVAL;
1530
1531	ctx->dev = dev;
1532	ctx->client = client;
1533
1534	of_property_read_u32(ep, "bus-width", &ctx->bus_width);
1535	of_node_put(ep);
1536
1537	if (ctx->bus_width != 12 && ctx->bus_width != 24)
1538		return -EINVAL;
1539
1540	ep = of_graph_get_remote_node(dev->of_node, 1, -1);
1541	if (!ep) {
1542		dev_err(ctx->dev, "The endpoint is unconnected\n");
1543		return -EINVAL;
1544	}
1545
1546	ctx->next_bridge = of_drm_find_bridge(ep);
1547	of_node_put(ep);
1548	if (!ctx->next_bridge) {
1549		dev_dbg(ctx->dev, "Next bridge not found, deferring probe\n");
1550		return -EPROBE_DEFER;
1551	}
1552
1553	i2c_set_clientdata(client, ctx);
1554	mutex_init(&ctx->lock);
1555
1556	ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(it66121_supplies),
1557					     it66121_supplies);
1558	if (ret) {
1559		dev_err(dev, "Failed to enable power supplies\n");
1560		return ret;
1561	}
1562
1563	it66121_hw_reset(ctx);
1564
1565	ctx->regmap = devm_regmap_init_i2c(client, &it66121_regmap_config);
1566	if (IS_ERR(ctx->regmap))
1567		return PTR_ERR(ctx->regmap);
1568
1569	regmap_read(ctx->regmap, IT66121_VENDOR_ID0_REG, &vendor_ids[0]);
1570	regmap_read(ctx->regmap, IT66121_VENDOR_ID1_REG, &vendor_ids[1]);
1571	regmap_read(ctx->regmap, IT66121_DEVICE_ID0_REG, &device_ids[0]);
1572	regmap_read(ctx->regmap, IT66121_DEVICE_ID1_REG, &device_ids[1]);
1573
1574	/* Revision is shared with DEVICE_ID1 */
1575	revision_id = FIELD_GET(IT66121_REVISION_MASK, device_ids[1]);
1576	device_ids[1] &= IT66121_DEVICE_ID1_MASK;
1577
1578	for (i = 0; i < ARRAY_SIZE(it66xx_chip_info); i++) {
1579		chip_info = &it66xx_chip_info[i];
1580		if ((vendor_ids[1] << 8 | vendor_ids[0]) == chip_info->vid &&
1581		    (device_ids[1] << 8 | device_ids[0]) == chip_info->pid) {
1582			ctx->id = chip_info->id;
1583			break;
1584		}
1585	}
1586
1587	if (i == ARRAY_SIZE(it66xx_chip_info))
1588		return -ENODEV;
1589
1590	ctx->bridge.of_node = dev->of_node;
1591	ctx->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
1592	ctx->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID;
1593	if (client->irq > 0) {
1594		ctx->bridge.ops |= DRM_BRIDGE_OP_HPD;
1595
1596		ret = devm_request_threaded_irq(dev, client->irq, NULL,
1597						it66121_irq_threaded_handler,
1598						IRQF_ONESHOT, dev_name(dev),
1599						ctx);
1600		if (ret < 0) {
1601			dev_err(dev, "Failed to request irq %d:%d\n", client->irq, ret);
1602			return ret;
1603		}
1604	}
1605
1606	it66121_audio_codec_init(ctx, dev);
1607
1608	drm_bridge_add(&ctx->bridge);
1609
1610	dev_info(ctx->dev, "IT66121 revision %d probed\n", revision_id);
1611
1612	return 0;
1613}
1614
1615static void it66121_remove(struct i2c_client *client)
1616{
1617	struct it66121_ctx *ctx = i2c_get_clientdata(client);
1618
1619	drm_bridge_remove(&ctx->bridge);
1620	mutex_destroy(&ctx->lock);
1621}
1622
1623static const struct of_device_id it66121_dt_match[] = {
1624	{ .compatible = "ite,it6610" },
1625	{ .compatible = "ite,it66121" },
1626	{ .compatible = "ite,it66122" },
1627	{ }
1628};
1629MODULE_DEVICE_TABLE(of, it66121_dt_match);
1630
1631static const struct i2c_device_id it66121_id[] = {
1632	{ .name = "it6610" },
1633	{ .name = "it66121" },
1634	{ .name = "it66122" },
1635	{ }
1636};
1637MODULE_DEVICE_TABLE(i2c, it66121_id);
1638
1639static struct i2c_driver it66121_driver = {
1640	.driver = {
1641		.name	= "it66121",
1642		.of_match_table = it66121_dt_match,
1643	},
1644	.probe = it66121_probe,
1645	.remove = it66121_remove,
1646	.id_table = it66121_id,
1647};
1648
1649module_i2c_driver(it66121_driver);
1650
1651MODULE_AUTHOR("Phong LE");
1652MODULE_DESCRIPTION("IT66121 HDMI transmitter driver");
1653MODULE_LICENSE("GPL v2");