ite-it6263.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright 2024 NXP
  4 */
  5
  6#include <linux/bitfield.h>
  7#include <linux/bits.h>
  8#include <linux/delay.h>
  9#include <linux/gpio/consumer.h>
 10#include <linux/hdmi.h>
 11#include <linux/i2c.h>
 12#include <linux/media-bus-format.h>
 13#include <linux/module.h>
 14#include <linux/of.h>
 15#include <linux/regmap.h>
 16#include <linux/regulator/consumer.h>
 17
 18#include <drm/display/drm_hdmi_helper.h>
 19#include <drm/display/drm_hdmi_state_helper.h>
 20#include <drm/drm_atomic.h>
 21#include <drm/drm_atomic_helper.h>
 22#include <drm/drm_atomic_state_helper.h>
 23#include <drm/drm_bridge.h>
 24#include <drm/drm_bridge_connector.h>
 25#include <drm/drm_connector.h>
 26#include <drm/drm_crtc.h>
 27#include <drm/drm_edid.h>
 28#include <drm/drm_of.h>
 29#include <drm/drm_probe_helper.h>
 30
 31/* -----------------------------------------------------------------------------
 32 * LVDS registers
 33 */
 34
 35/* LVDS software reset registers */
 36#define LVDS_REG_05			0x05
 37#define  REG_SOFT_P_RST			BIT(1)
 38
 39/* LVDS system configuration registers */
 40/* 0x0b */
 41#define LVDS_REG_0B			0x0b
 42#define  REG_SSC_PCLK_RF		BIT(0)
 43#define  REG_LVDS_IN_SWAP		BIT(1)
 44
 45/* LVDS test pattern gen control registers */
 46/* 0x2c */
 47#define LVDS_REG_2C			0x2c
 48#define  REG_COL_DEP			GENMASK(1, 0)
 49#define  BIT8				FIELD_PREP(REG_COL_DEP, 1)
 50#define  OUT_MAP			BIT(4)
 51#define  VESA				BIT(4)
 52#define  JEIDA				0
 53#define  REG_DESSC_ENB			BIT(6)
 54#define  DMODE				BIT(7)
 55#define  DISO				BIT(7)
 56#define  SISO				0
 57
 58#define LVDS_REG_3C			0x3c
 59#define LVDS_REG_3F			0x3f
 60#define LVDS_REG_47			0x47
 61#define LVDS_REG_48			0x48
 62#define LVDS_REG_4F			0x4f
 63#define LVDS_REG_52			0x52
 64
 65/* -----------------------------------------------------------------------------
 66 * HDMI registers are separated into three banks:
 67 * 1) HDMI register common bank: 0x00 ~ 0x2f
 68 */
 69
 70/* HDMI genernal registers */
 71#define HDMI_REG_SW_RST			0x04
 72#define  SOFTREF_RST			BIT(5)
 73#define  SOFTA_RST			BIT(4)
 74#define  SOFTV_RST			BIT(3)
 75#define  AUD_RST			BIT(2)
 76#define  HDCP_RST			BIT(0)
 77#define  HDMI_RST_ALL			(SOFTREF_RST | SOFTA_RST | SOFTV_RST | \
 78					 AUD_RST | HDCP_RST)
 79
 80#define HDMI_REG_SYS_STATUS		0x0e
 81#define  HPDETECT			BIT(6)
 82#define  TXVIDSTABLE			BIT(4)
 83
 84#define HDMI_REG_BANK_CTRL		0x0f
 85#define  REG_BANK_SEL			BIT(0)
 86
 87/* HDMI System DDC control registers */
 88#define HDMI_REG_DDC_MASTER_CTRL	0x10
 89#define  MASTER_SEL_HOST		BIT(0)
 90
 91#define HDMI_REG_DDC_HEADER		0x11
 92
 93#define HDMI_REG_DDC_REQOFF		0x12
 94#define HDMI_REG_DDC_REQCOUNT		0x13
 95#define HDMI_REG_DDC_EDIDSEG		0x14
 96
 97#define HDMI_REG_DDC_CMD		0x15
 98#define  DDC_CMD_EDID_READ		0x3
 99#define  DDC_CMD_FIFO_CLR		0x9
100
101#define HDMI_REG_DDC_STATUS		0x16
102#define  DDC_DONE			BIT(7)
103#define  DDC_NOACK			BIT(5)
104#define  DDC_WAITBUS			BIT(4)
105#define  DDC_ARBILOSE			BIT(3)
106#define  DDC_ERROR			(DDC_NOACK | DDC_WAITBUS | DDC_ARBILOSE)
107
108#define HDMI_DDC_FIFO_BYTES		32
109#define HDMI_REG_DDC_READFIFO		0x17
110#define HDMI_REG_LVDS_PORT		0x1d /* LVDS input control I2C addr */
111#define HDMI_REG_LVDS_PORT_EN		0x1e
112#define LVDS_INPUT_CTRL_I2C_ADDR	0x33
113
114/* -----------------------------------------------------------------------------
115 * 2) HDMI register bank0: 0x30 ~ 0xff
116 */
117
118/* HDMI AFE registers */
119#define HDMI_REG_AFE_DRV_CTRL		0x61
120#define  AFE_DRV_PWD			BIT(5)
121#define  AFE_DRV_RST			BIT(4)
122
123#define HDMI_REG_AFE_XP_CTRL		0x62
124#define  AFE_XP_GAINBIT			BIT(7)
125#define  AFE_XP_ER0			BIT(4)
126#define  AFE_XP_RESETB			BIT(3)
127
128#define HDMI_REG_AFE_ISW_CTRL		0x63
129
130#define HDMI_REG_AFE_IP_CTRL		0x64
131#define  AFE_IP_GAINBIT			BIT(7)
132#define  AFE_IP_ER0			BIT(3)
133#define  AFE_IP_RESETB			BIT(2)
134
135/* HDMI input data format registers */
136#define HDMI_REG_INPUT_MODE		0x70
137#define  IN_RGB				0x00
138
139/* HDMI general control registers */
140#define HDMI_REG_HDMI_MODE		0xc0
141#define  TX_HDMI_MODE			BIT(0)
142
143#define HDMI_REG_GCP			0xc1
144#define  AVMUTE				BIT(0)
145#define  HDMI_COLOR_DEPTH		GENMASK(6, 4)
146#define  HDMI_COLOR_DEPTH_24		FIELD_PREP(HDMI_COLOR_DEPTH, 4)
147
148#define HDMI_REG_PKT_GENERAL_CTRL	0xc6
149#define HDMI_REG_PKT_NULL_CTRL		0xc9
150#define HDMI_REG_AVI_INFOFRM_CTRL	0xcd
151#define  ENABLE_PKT			BIT(0)
152#define  REPEAT_PKT			BIT(1)
153
154/* -----------------------------------------------------------------------------
155 * 3) HDMI register bank1: 0x130 ~ 0x1ff (HDMI packet registers)
156 */
157
158/* NULL packet registers */
159/* Header Byte(HB): n = 0 ~ 2 */
160#define HDMI_REG_PKT_HB(n)		(0x138 + (n))
161/* Packet Byte(PB): n = 0 ~ 27(HDMI_MAX_INFOFRAME_SIZE), n = 0 for checksum */
162#define HDMI_REG_PKT_PB(n)		(0x13b + (n))
163
164/* AVI packet registers */
165#define HDMI_REG_AVI_DB1		0x158
166#define HDMI_REG_AVI_DB2		0x159
167#define HDMI_REG_AVI_DB3		0x15a
168#define HDMI_REG_AVI_DB4		0x15b
169#define HDMI_REG_AVI_DB5		0x15c
170#define HDMI_REG_AVI_CSUM		0x15d
171#define HDMI_REG_AVI_DB6		0x15e
172#define HDMI_REG_AVI_DB7		0x15f
173#define HDMI_REG_AVI_DB8		0x160
174#define HDMI_REG_AVI_DB9		0x161
175#define HDMI_REG_AVI_DB10		0x162
176#define HDMI_REG_AVI_DB11		0x163
177#define HDMI_REG_AVI_DB12		0x164
178#define HDMI_REG_AVI_DB13		0x165
179
180#define HDMI_AVI_DB_CHUNK1_SIZE		(HDMI_REG_AVI_DB5 - HDMI_REG_AVI_DB1 + 1)
181#define HDMI_AVI_DB_CHUNK2_SIZE		(HDMI_REG_AVI_DB13 - HDMI_REG_AVI_DB6 + 1)
182
183/* IT6263 data sheet Rev0.8: LVDS RX supports input clock rate up to 150MHz. */
184#define MAX_PIXEL_CLOCK_KHZ		150000
185
186/* IT6263 programming guide Ver0.90: PCLK_HIGH for TMDS clock over 80MHz. */
187#define HIGH_PIXEL_CLOCK_KHZ		80000
188
189/*
190 * IT6263 data sheet Rev0.8: HDMI TX supports link speeds of up to 2.25Gbps
191 * (link clock rate of 225MHz).
192 */
193#define MAX_HDMI_TMDS_CHAR_RATE_HZ	225000000
194
195struct it6263 {
196	struct device *dev;
197	struct i2c_client *hdmi_i2c;
198	struct i2c_client *lvds_i2c;
199	struct regmap *hdmi_regmap;
200	struct regmap *lvds_regmap;
201	struct drm_bridge bridge;
202	struct drm_bridge *next_bridge;
203	int lvds_data_mapping;
204	bool lvds_dual_link;
205	bool lvds_link12_swap;
206};
207
208static inline struct it6263 *bridge_to_it6263(struct drm_bridge *bridge)
209{
210	return container_of(bridge, struct it6263, bridge);
211}
212
213static bool it6263_hdmi_writeable_reg(struct device *dev, unsigned int reg)
214{
215	switch (reg) {
216	case HDMI_REG_SW_RST:
217	case HDMI_REG_BANK_CTRL:
218	case HDMI_REG_DDC_MASTER_CTRL:
219	case HDMI_REG_DDC_HEADER:
220	case HDMI_REG_DDC_REQOFF:
221	case HDMI_REG_DDC_REQCOUNT:
222	case HDMI_REG_DDC_EDIDSEG:
223	case HDMI_REG_DDC_CMD:
224	case HDMI_REG_LVDS_PORT:
225	case HDMI_REG_LVDS_PORT_EN:
226	case HDMI_REG_AFE_DRV_CTRL:
227	case HDMI_REG_AFE_XP_CTRL:
228	case HDMI_REG_AFE_ISW_CTRL:
229	case HDMI_REG_AFE_IP_CTRL:
230	case HDMI_REG_INPUT_MODE:
231	case HDMI_REG_HDMI_MODE:
232	case HDMI_REG_GCP:
233	case HDMI_REG_PKT_GENERAL_CTRL:
234	case HDMI_REG_PKT_NULL_CTRL:
235	case HDMI_REG_AVI_INFOFRM_CTRL:
236	case HDMI_REG_PKT_HB(0) ... HDMI_REG_PKT_PB(HDMI_MAX_INFOFRAME_SIZE):
237	case HDMI_REG_AVI_DB1:
238	case HDMI_REG_AVI_DB2:
239	case HDMI_REG_AVI_DB3:
240	case HDMI_REG_AVI_DB4:
241	case HDMI_REG_AVI_DB5:
242	case HDMI_REG_AVI_CSUM:
243	case HDMI_REG_AVI_DB6:
244	case HDMI_REG_AVI_DB7:
245	case HDMI_REG_AVI_DB8:
246	case HDMI_REG_AVI_DB9:
247	case HDMI_REG_AVI_DB10:
248	case HDMI_REG_AVI_DB11:
249	case HDMI_REG_AVI_DB12:
250	case HDMI_REG_AVI_DB13:
251		return true;
252	default:
253		return false;
254	}
255}
256
257static bool it6263_hdmi_readable_reg(struct device *dev, unsigned int reg)
258{
259	if (it6263_hdmi_writeable_reg(dev, reg))
260		return true;
261
262	switch (reg) {
263	case HDMI_REG_SYS_STATUS:
264	case HDMI_REG_DDC_STATUS:
265	case HDMI_REG_DDC_READFIFO:
266		return true;
267	default:
268		return false;
269	}
270}
271
272static bool it6263_hdmi_volatile_reg(struct device *dev, unsigned int reg)
273{
274	switch (reg) {
275	case HDMI_REG_SW_RST:
276	case HDMI_REG_SYS_STATUS:
277	case HDMI_REG_DDC_STATUS:
278	case HDMI_REG_DDC_READFIFO:
279		return true;
280	default:
281		return false;
282	}
283}
284
285static const struct regmap_range_cfg it6263_hdmi_range_cfg = {
286	.range_min = 0x00,
287	.range_max = HDMI_REG_AVI_DB13,
288	.selector_reg = HDMI_REG_BANK_CTRL,
289	.selector_mask = REG_BANK_SEL,
290	.selector_shift = 0,
291	.window_start = 0x00,
292	.window_len = 0x100,
293};
294
295static const struct regmap_config it6263_hdmi_regmap_config = {
296	.name = "it6263-hdmi",
297	.reg_bits = 8,
298	.val_bits = 8,
299	.writeable_reg = it6263_hdmi_writeable_reg,
300	.readable_reg = it6263_hdmi_readable_reg,
301	.volatile_reg = it6263_hdmi_volatile_reg,
302	.max_register = HDMI_REG_AVI_DB13,
303	.ranges = &it6263_hdmi_range_cfg,
304	.num_ranges = 1,
305	.cache_type = REGCACHE_MAPLE,
306};
307
308static bool it6263_lvds_writeable_reg(struct device *dev, unsigned int reg)
309{
310	switch (reg) {
311	case LVDS_REG_05:
312	case LVDS_REG_0B:
313	case LVDS_REG_2C:
314	case LVDS_REG_3C:
315	case LVDS_REG_3F:
316	case LVDS_REG_47:
317	case LVDS_REG_48:
318	case LVDS_REG_4F:
319	case LVDS_REG_52:
320		return true;
321	default:
322		return false;
323	}
324}
325
326static bool it6263_lvds_readable_reg(struct device *dev, unsigned int reg)
327{
328	return it6263_lvds_writeable_reg(dev, reg);
329}
330
331static bool it6263_lvds_volatile_reg(struct device *dev, unsigned int reg)
332{
333	return reg == LVDS_REG_05;
334}
335
336static const struct regmap_config it6263_lvds_regmap_config = {
337	.name = "it6263-lvds",
338	.reg_bits = 8,
339	.val_bits = 8,
340	.writeable_reg = it6263_lvds_writeable_reg,
341	.readable_reg = it6263_lvds_readable_reg,
342	.volatile_reg = it6263_lvds_volatile_reg,
343	.max_register = LVDS_REG_52,
344	.cache_type = REGCACHE_MAPLE,
345};
346
347static const char * const it6263_supplies[] = {
348	"ivdd", "ovdd", "txavcc18", "txavcc33", "pvcc1", "pvcc2",
349	"avcc", "anvdd", "apvdd"
350};
351
352static int it6263_parse_dt(struct it6263 *it)
353{
354	struct device *dev = it->dev;
355	struct device_node *port0, *port1;
356	int ret = 0;
357
358	it->lvds_data_mapping = drm_of_lvds_get_data_mapping(dev->of_node);
359	if (it->lvds_data_mapping < 0) {
360		dev_err(dev, "%pOF: invalid or missing %s DT property: %d\n",
361			dev->of_node, "data-mapping", it->lvds_data_mapping);
362		return it->lvds_data_mapping;
363	}
364
365	it->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
366	if (IS_ERR(it->next_bridge))
367		return dev_err_probe(dev, PTR_ERR(it->next_bridge),
368				     "failed to get next bridge\n");
369
370	port0 = of_graph_get_port_by_id(dev->of_node, 0);
371	port1 = of_graph_get_port_by_id(dev->of_node, 1);
372	if (port0 && port1) {
373		int order;
374
375		it->lvds_dual_link = true;
376		order = drm_of_lvds_get_dual_link_pixel_order_sink(port0, port1);
377		if (order < 0) {
378			dev_err(dev,
379				"failed to get dual link pixel order: %d\n",
380				order);
381			ret = order;
382		} else if (order == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) {
383			it->lvds_link12_swap = true;
384		}
385	} else if (port1) {
386		ret = -EINVAL;
387		dev_err(dev, "single input LVDS port1 is not supported\n");
388	} else if (!port0) {
389		ret = -EINVAL;
390		dev_err(dev, "no input LVDS port\n");
391	}
392
393	of_node_put(port0);
394	of_node_put(port1);
395
396	return ret;
397}
398
399static inline void it6263_hw_reset(struct gpio_desc *reset_gpio)
400{
401	if (!reset_gpio)
402		return;
403
404	gpiod_set_value_cansleep(reset_gpio, 0);
405	fsleep(1000);
406	gpiod_set_value_cansleep(reset_gpio, 1);
407	/* The chip maker says the low pulse should be at least 40ms. */
408	fsleep(40000);
409	gpiod_set_value_cansleep(reset_gpio, 0);
410	/* addtional time to wait the high voltage to be stable */
411	fsleep(5000);
412}
413
414static inline int it6263_lvds_set_i2c_addr(struct it6263 *it)
415{
416	int ret;
417
418	ret = regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT,
419			   LVDS_INPUT_CTRL_I2C_ADDR << 1);
420	if (ret)
421		return ret;
422
423	return regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT_EN, BIT(0));
424}
425
426static inline void it6263_lvds_reset(struct it6263 *it)
427{
428	/* AFE PLL reset */
429	regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), 0x0);
430	fsleep(1000);
431	regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), BIT(0));
432
433	/* software pixel clock domain reset */
434	regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST,
435			  REG_SOFT_P_RST);
436	fsleep(1000);
437	regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST, 0x0);
438	fsleep(10000);
439}
440
441static inline bool it6263_is_input_bus_fmt_valid(int input_fmt)
442{
443	switch (input_fmt) {
444	case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
445	case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
446		return true;
447	}
448	return false;
449}
450
451static inline void it6263_lvds_set_interface(struct it6263 *it)
452{
453	u8 fmt;
454
455	/* color depth */
456	regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_COL_DEP, BIT8);
457
458	if (it->lvds_data_mapping == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG)
459		fmt = VESA;
460	else
461		fmt = JEIDA;
462
463	/* output mapping */
464	regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, OUT_MAP, fmt);
465
466	if (it->lvds_dual_link) {
467		regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, DISO);
468		regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), BIT(1));
469	} else {
470		regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, SISO);
471		regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), 0);
472	}
473}
474
475static inline void it6263_lvds_set_afe(struct it6263 *it)
476{
477	regmap_write(it->lvds_regmap, LVDS_REG_3C, 0xaa);
478	regmap_write(it->lvds_regmap, LVDS_REG_3F, 0x02);
479	regmap_write(it->lvds_regmap, LVDS_REG_47, 0xaa);
480	regmap_write(it->lvds_regmap, LVDS_REG_48, 0x02);
481	regmap_write(it->lvds_regmap, LVDS_REG_4F, 0x11);
482
483	regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_SSC_PCLK_RF,
484			  REG_SSC_PCLK_RF);
485	regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, 0x07, 0);
486	regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_DESSC_ENB,
487			  REG_DESSC_ENB);
488}
489
490static inline void it6263_lvds_sys_cfg(struct it6263 *it)
491{
492	regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_LVDS_IN_SWAP,
493			  it->lvds_link12_swap ? REG_LVDS_IN_SWAP : 0);
494}
495
496static inline void it6263_lvds_config(struct it6263 *it)
497{
498	it6263_lvds_reset(it);
499	it6263_lvds_set_interface(it);
500	it6263_lvds_set_afe(it);
501	it6263_lvds_sys_cfg(it);
502}
503
504static inline void it6263_hdmi_config(struct it6263 *it)
505{
506	regmap_write(it->hdmi_regmap, HDMI_REG_SW_RST, HDMI_RST_ALL);
507	regmap_write(it->hdmi_regmap, HDMI_REG_INPUT_MODE, IN_RGB);
508	regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, HDMI_COLOR_DEPTH,
509			  HDMI_COLOR_DEPTH_24);
510}
511
512static enum drm_connector_status it6263_detect(struct it6263 *it)
513{
514	unsigned int val;
515
516	regmap_read(it->hdmi_regmap, HDMI_REG_SYS_STATUS, &val);
517	if (val & HPDETECT)
518		return connector_status_connected;
519	else
520		return connector_status_disconnected;
521}
522
523static int it6263_read_edid(void *data, u8 *buf, unsigned int block, size_t len)
524{
525	struct it6263 *it = data;
526	struct regmap *regmap = it->hdmi_regmap;
527	unsigned int start = (block % 2) * EDID_LENGTH;
528	unsigned int segment = block >> 1;
529	unsigned int count, val;
530	int ret;
531
532	regmap_write(regmap, HDMI_REG_DDC_MASTER_CTRL, MASTER_SEL_HOST);
533	regmap_write(regmap, HDMI_REG_DDC_HEADER, DDC_ADDR << 1);
534	regmap_write(regmap, HDMI_REG_DDC_EDIDSEG, segment);
535
536	while (len) {
537		/* clear DDC FIFO */
538		regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_FIFO_CLR);
539
540		ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS,
541					       val, val & DDC_DONE,
542					       2000, 10000);
543		if (ret) {
544			dev_err(it->dev, "failed to clear DDC FIFO:%d\n", ret);
545			return ret;
546		}
547
548		count = len > HDMI_DDC_FIFO_BYTES ? HDMI_DDC_FIFO_BYTES : len;
549
550		/* fire the read command */
551		regmap_write(regmap, HDMI_REG_DDC_REQOFF, start);
552		regmap_write(regmap, HDMI_REG_DDC_REQCOUNT, count);
553		regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_EDID_READ);
554
555		start += count;
556		len -= count;
557
558		ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS, val,
559					       val & (DDC_DONE | DDC_ERROR),
560					       20000, 250000);
561		if (ret && !(val & DDC_ERROR)) {
562			dev_err(it->dev, "failed to read EDID:%d\n", ret);
563			return ret;
564		}
565
566		if (val & DDC_ERROR) {
567			dev_err(it->dev, "DDC error\n");
568			return -EIO;
569		}
570
571		/* cache to buffer */
572		for (; count > 0; count--) {
573			regmap_read(regmap, HDMI_REG_DDC_READFIFO, &val);
574			*(buf++) = val;
575		}
576	}
577
578	return 0;
579}
580
581static void it6263_bridge_atomic_disable(struct drm_bridge *bridge,
582					 struct drm_atomic_state *state)
583{
584	struct it6263 *it = bridge_to_it6263(bridge);
585
586	regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, AVMUTE, AVMUTE);
587	regmap_write(it->hdmi_regmap, HDMI_REG_PKT_GENERAL_CTRL, 0);
588	regmap_write(it->hdmi_regmap, HDMI_REG_AFE_DRV_CTRL,
589		     AFE_DRV_RST | AFE_DRV_PWD);
590}
591
592static void it6263_bridge_atomic_enable(struct drm_bridge *bridge,
593					struct drm_atomic_state *state)
594{
595	struct it6263 *it = bridge_to_it6263(bridge);
596	const struct drm_crtc_state *crtc_state;
597	struct regmap *regmap = it->hdmi_regmap;
598	const struct drm_display_mode *mode;
599	struct drm_connector *connector;
600	bool is_stable = false;
601	struct drm_crtc *crtc;
602	unsigned int val;
603	bool pclk_high;
604	int i, ret;
605
606	connector = drm_atomic_get_new_connector_for_encoder(state,
607							     bridge->encoder);
608	crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
609	crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
610	mode = &crtc_state->adjusted_mode;
611
612	regmap_write(regmap, HDMI_REG_HDMI_MODE, TX_HDMI_MODE);
613
614	drm_atomic_helper_connector_hdmi_update_infoframes(connector, state);
615
616	/* HDMI AFE setup */
617	pclk_high = mode->clock > HIGH_PIXEL_CLOCK_KHZ;
618	regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, AFE_DRV_RST);
619	if (pclk_high)
620		regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
621			     AFE_XP_GAINBIT | AFE_XP_RESETB);
622	else
623		regmap_write(regmap, HDMI_REG_AFE_XP_CTRL,
624			     AFE_XP_ER0 | AFE_XP_RESETB);
625	regmap_write(regmap, HDMI_REG_AFE_ISW_CTRL, 0x10);
626	if (pclk_high)
627		regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
628			     AFE_IP_GAINBIT | AFE_IP_RESETB);
629	else
630		regmap_write(regmap, HDMI_REG_AFE_IP_CTRL,
631			     AFE_IP_ER0 | AFE_IP_RESETB);
632
633	/* HDMI software video reset */
634	regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, SOFTV_RST);
635	fsleep(1000);
636	regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, 0);
637
638	/* reconfigure LVDS and retry several times in case video is instable */
639	for (i = 0; i < 3; i++) {
640		ret = regmap_read_poll_timeout(regmap, HDMI_REG_SYS_STATUS, val,
641					       val & TXVIDSTABLE,
642					       20000, 500000);
643		if (!ret) {
644			is_stable = true;
645			break;
646		}
647
648		it6263_lvds_config(it);
649	}
650
651	if (!is_stable)
652		dev_warn(it->dev, "failed to wait for video stable\n");
653
654	/* HDMI AFE reset release and power up */
655	regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, 0);
656
657	regmap_write_bits(regmap, HDMI_REG_GCP, AVMUTE, 0);
658
659	regmap_write(regmap, HDMI_REG_PKT_GENERAL_CTRL, ENABLE_PKT | REPEAT_PKT);
660}
661
662static enum drm_mode_status
663it6263_bridge_mode_valid(struct drm_bridge *bridge,
664			 const struct drm_display_info *info,
665			 const struct drm_display_mode *mode)
666{
667	unsigned long long rate;
668
669	rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
670	if (rate == 0)
671		return MODE_NOCLOCK;
672
673	return bridge->funcs->hdmi_tmds_char_rate_valid(bridge, mode, rate);
674}
675
676static int it6263_bridge_attach(struct drm_bridge *bridge,
677				struct drm_encoder *encoder,
678				enum drm_bridge_attach_flags flags)
679{
680	struct it6263 *it = bridge_to_it6263(bridge);
681	struct drm_connector *connector;
682	int ret;
683
684	ret = drm_bridge_attach(encoder, it->next_bridge, bridge,
685				flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
686	if (ret < 0)
687		return ret;
688
689	if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
690		return 0;
691
692	connector = drm_bridge_connector_init(bridge->dev, encoder);
693	if (IS_ERR(connector)) {
694		ret = PTR_ERR(connector);
695		dev_err(it->dev, "failed to initialize bridge connector: %d\n",
696			ret);
697		return ret;
698	}
699
700	drm_connector_attach_encoder(connector, encoder);
701
702	return 0;
703}
704
705static enum drm_connector_status
706it6263_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector)
707{
708	struct it6263 *it = bridge_to_it6263(bridge);
709
710	return it6263_detect(it);
711}
712
713static const struct drm_edid *
714it6263_bridge_edid_read(struct drm_bridge *bridge,
715			struct drm_connector *connector)
716{
717	struct it6263 *it = bridge_to_it6263(bridge);
718
719	return drm_edid_read_custom(connector, it6263_read_edid, it);
720}
721
722static u32 *
723it6263_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
724					struct drm_bridge_state *bridge_state,
725					struct drm_crtc_state *crtc_state,
726					struct drm_connector_state *conn_state,
727					u32 output_fmt,
728					unsigned int *num_input_fmts)
729{
730	struct it6263 *it = bridge_to_it6263(bridge);
731	u32 *input_fmts;
732
733	*num_input_fmts = 0;
734
735	if (!it6263_is_input_bus_fmt_valid(it->lvds_data_mapping))
736		return NULL;
737
738	input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
739	if (!input_fmts)
740		return NULL;
741
742	input_fmts[0] = it->lvds_data_mapping;
743	*num_input_fmts = 1;
744
745	return input_fmts;
746}
747
748static enum drm_mode_status
749it6263_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge,
750				 const struct drm_display_mode *mode,
751				 unsigned long long tmds_rate)
752{
753	if (mode->clock > MAX_PIXEL_CLOCK_KHZ)
754		return MODE_CLOCK_HIGH;
755
756	if (tmds_rate > MAX_HDMI_TMDS_CHAR_RATE_HZ)
757		return MODE_CLOCK_HIGH;
758
759	return MODE_OK;
760}
761
762static int it6263_hdmi_clear_infoframe(struct drm_bridge *bridge,
763				       enum hdmi_infoframe_type type)
764{
765	struct it6263 *it = bridge_to_it6263(bridge);
766
767	switch (type) {
768	case HDMI_INFOFRAME_TYPE_AVI:
769		regmap_write(it->hdmi_regmap, HDMI_REG_AVI_INFOFRM_CTRL, 0);
770		break;
771	case HDMI_INFOFRAME_TYPE_VENDOR:
772		regmap_write(it->hdmi_regmap, HDMI_REG_PKT_NULL_CTRL, 0);
773		break;
774	default:
775		dev_dbg(it->dev, "unsupported HDMI infoframe 0x%x\n", type);
776	}
777
778	return 0;
779}
780
781static int it6263_hdmi_write_infoframe(struct drm_bridge *bridge,
782				       enum hdmi_infoframe_type type,
783				       const u8 *buffer, size_t len)
784{
785	struct it6263 *it = bridge_to_it6263(bridge);
786	struct regmap *regmap = it->hdmi_regmap;
787
788	switch (type) {
789	case HDMI_INFOFRAME_TYPE_AVI:
790		/* write the first AVI infoframe data byte chunk(DB1-DB5) */
791		regmap_bulk_write(regmap, HDMI_REG_AVI_DB1,
792				  &buffer[HDMI_INFOFRAME_HEADER_SIZE],
793				  HDMI_AVI_DB_CHUNK1_SIZE);
794
795		/* write the second AVI infoframe data byte chunk(DB6-DB13) */
796		regmap_bulk_write(regmap, HDMI_REG_AVI_DB6,
797				  &buffer[HDMI_INFOFRAME_HEADER_SIZE +
798					  HDMI_AVI_DB_CHUNK1_SIZE],
799				  HDMI_AVI_DB_CHUNK2_SIZE);
800
801		/* write checksum */
802		regmap_write(regmap, HDMI_REG_AVI_CSUM, buffer[3]);
803
804		regmap_write(regmap, HDMI_REG_AVI_INFOFRM_CTRL,
805			     ENABLE_PKT | REPEAT_PKT);
806		break;
807	case HDMI_INFOFRAME_TYPE_VENDOR:
808		/* write header and payload */
809		regmap_bulk_write(regmap, HDMI_REG_PKT_HB(0), buffer, len);
810
811		regmap_write(regmap, HDMI_REG_PKT_NULL_CTRL,
812			     ENABLE_PKT | REPEAT_PKT);
813		break;
814	default:
815		dev_dbg(it->dev, "unsupported HDMI infoframe 0x%x\n", type);
816	}
817
818	return 0;
819}
820
821static const struct drm_bridge_funcs it6263_bridge_funcs = {
822	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
823	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
824	.atomic_reset = drm_atomic_helper_bridge_reset,
825	.attach = it6263_bridge_attach,
826	.mode_valid = it6263_bridge_mode_valid,
827	.atomic_disable = it6263_bridge_atomic_disable,
828	.atomic_enable = it6263_bridge_atomic_enable,
829	.detect = it6263_bridge_detect,
830	.edid_read = it6263_bridge_edid_read,
831	.atomic_get_input_bus_fmts = it6263_bridge_atomic_get_input_bus_fmts,
832	.hdmi_tmds_char_rate_valid = it6263_hdmi_tmds_char_rate_valid,
833	.hdmi_clear_infoframe = it6263_hdmi_clear_infoframe,
834	.hdmi_write_infoframe = it6263_hdmi_write_infoframe,
835};
836
837static int it6263_probe(struct i2c_client *client)
838{
839	struct device *dev = &client->dev;
840	struct gpio_desc *reset_gpio;
841	struct it6263 *it;
842	int ret;
843
844	it = devm_drm_bridge_alloc(dev, struct it6263, bridge,
845				   &it6263_bridge_funcs);
846	if (IS_ERR(it))
847		return PTR_ERR(it);
848
849	it->dev = dev;
850	it->hdmi_i2c = client;
851
852	it->hdmi_regmap = devm_regmap_init_i2c(client,
853					       &it6263_hdmi_regmap_config);
854	if (IS_ERR(it->hdmi_regmap))
855		return dev_err_probe(dev, PTR_ERR(it->hdmi_regmap),
856				     "failed to init I2C regmap for HDMI\n");
857
858	reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
859	if (IS_ERR(reset_gpio))
860		return dev_err_probe(dev, PTR_ERR(reset_gpio),
861				     "failed to get reset gpio\n");
862
863	ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(it6263_supplies),
864					     it6263_supplies);
865	if (ret)
866		return dev_err_probe(dev, ret, "failed to get power supplies\n");
867
868	ret = it6263_parse_dt(it);
869	if (ret)
870		return ret;
871
872	it6263_hw_reset(reset_gpio);
873
874	ret = it6263_lvds_set_i2c_addr(it);
875	if (ret)
876		return dev_err_probe(dev, ret, "failed to set I2C addr\n");
877
878	it->lvds_i2c = devm_i2c_new_dummy_device(dev, client->adapter,
879						 LVDS_INPUT_CTRL_I2C_ADDR);
880	if (IS_ERR(it->lvds_i2c))
881		return dev_err_probe(it->dev, PTR_ERR(it->lvds_i2c),
882				     "failed to allocate I2C device for LVDS\n");
883
884	it->lvds_regmap = devm_regmap_init_i2c(it->lvds_i2c,
885					       &it6263_lvds_regmap_config);
886	if (IS_ERR(it->lvds_regmap))
887		return dev_err_probe(dev, PTR_ERR(it->lvds_regmap),
888				     "failed to init I2C regmap for LVDS\n");
889
890	it6263_lvds_config(it);
891	it6263_hdmi_config(it);
892
893	i2c_set_clientdata(client, it);
894
895	it->bridge.of_node = dev->of_node;
896	/* IT6263 chip doesn't support HPD interrupt. */
897	it->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
898			 DRM_BRIDGE_OP_HDMI;
899	it->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
900	it->bridge.vendor = "ITE";
901	it->bridge.product = "IT6263";
902
903	return devm_drm_bridge_add(dev, &it->bridge);
904}
905
906static const struct of_device_id it6263_of_match[] = {
907	{ .compatible = "ite,it6263", },
908	{ }
909};
910MODULE_DEVICE_TABLE(of, it6263_of_match);
911
912static const struct i2c_device_id it6263_i2c_ids[] = {
913	{ "it6263" },
914	{ }
915};
916MODULE_DEVICE_TABLE(i2c, it6263_i2c_ids);
917
918static struct i2c_driver it6263_driver = {
919	.probe = it6263_probe,
920	.driver = {
921		.name = "it6263",
922		.of_match_table = it6263_of_match,
923	},
924	.id_table = it6263_i2c_ids,
925};
926module_i2c_driver(it6263_driver);
927
928MODULE_DESCRIPTION("ITE Tech. Inc. IT6263 LVDS/HDMI bridge");
929MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
930MODULE_LICENSE("GPL");