chipone-icn6211.c

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * Copyright (C) 2020 Amarula Solutions(India)
  4 * Author: Jagan Teki <jagan@amarulasolutions.com>
  5 */
  6
  7#include <drm/drm_atomic_helper.h>
  8#include <drm/drm_of.h>
  9#include <drm/drm_print.h>
 10#include <drm/drm_mipi_dsi.h>
 11
 12#include <linux/bitfield.h>
 13#include <linux/bits.h>
 14#include <linux/clk.h>
 15#include <linux/delay.h>
 16#include <linux/gpio/consumer.h>
 17#include <linux/i2c.h>
 18#include <linux/media-bus-format.h>
 19#include <linux/module.h>
 20#include <linux/of.h>
 21#include <linux/regmap.h>
 22#include <linux/regulator/consumer.h>
 23
 24#define VENDOR_ID		0x00
 25#define DEVICE_ID_H		0x01
 26#define DEVICE_ID_L		0x02
 27#define VERSION_ID		0x03
 28#define FIRMWARE_VERSION	0x08
 29#define CONFIG_FINISH		0x09
 30#define PD_CTRL(n)		(0x0a + ((n) & 0x3)) /* 0..3 */
 31#define RST_CTRL(n)		(0x0e + ((n) & 0x1)) /* 0..1 */
 32#define SYS_CTRL(n)		(0x10 + ((n) & 0x7)) /* 0..4 */
 33#define SYS_CTRL_1_CLK_PHASE_MSK	GENMASK(5, 4)
 34#define CLK_PHASE_0			0
 35#define CLK_PHASE_1_4			1
 36#define CLK_PHASE_1_2			2
 37#define CLK_PHASE_3_4			3
 38#define RGB_DRV(n)		(0x18 + ((n) & 0x3)) /* 0..3 */
 39#define RGB_DLY(n)		(0x1c + ((n) & 0x1)) /* 0..1 */
 40#define RGB_TEST_CTRL		0x1e
 41#define ATE_PLL_EN		0x1f
 42#define HACTIVE_LI		0x20
 43#define VACTIVE_LI		0x21
 44#define VACTIVE_HACTIVE_HI	0x22
 45#define HFP_LI			0x23
 46#define HSYNC_LI		0x24
 47#define HBP_LI			0x25
 48#define HFP_HSW_HBP_HI		0x26
 49#define HFP_HSW_HBP_HI_HFP(n)		(((n) & 0x300) >> 4)
 50#define HFP_HSW_HBP_HI_HS(n)		(((n) & 0x300) >> 6)
 51#define HFP_HSW_HBP_HI_HBP(n)		(((n) & 0x300) >> 8)
 52#define VFP			0x27
 53#define VSYNC			0x28
 54#define VBP			0x29
 55#define BIST_POL		0x2a
 56#define BIST_POL_BIST_MODE(n)		(((n) & 0xf) << 4)
 57#define BIST_POL_BIST_GEN		BIT(3)
 58#define BIST_POL_HSYNC_POL		BIT(2)
 59#define BIST_POL_VSYNC_POL		BIT(1)
 60#define BIST_POL_DE_POL			BIT(0)
 61#define BIST_RED		0x2b
 62#define BIST_GREEN		0x2c
 63#define BIST_BLUE		0x2d
 64#define BIST_CHESS_X		0x2e
 65#define BIST_CHESS_Y		0x2f
 66#define BIST_CHESS_XY_H		0x30
 67#define BIST_FRAME_TIME_L	0x31
 68#define BIST_FRAME_TIME_H	0x32
 69#define FIFO_MAX_ADDR_LOW	0x33
 70#define SYNC_EVENT_DLY		0x34
 71#define HSW_MIN			0x35
 72#define HFP_MIN			0x36
 73#define LOGIC_RST_NUM		0x37
 74#define OSC_CTRL(n)		(0x48 + ((n) & 0x7)) /* 0..5 */
 75#define BG_CTRL			0x4e
 76#define LDO_PLL			0x4f
 77#define PLL_CTRL(n)		(0x50 + ((n) & 0xf)) /* 0..15 */
 78#define PLL_CTRL_6_EXTERNAL		0x90
 79#define PLL_CTRL_6_MIPI_CLK		0x92
 80#define PLL_CTRL_6_INTERNAL		0x93
 81#define PLL_REM(n)		(0x60 + ((n) & 0x3)) /* 0..2 */
 82#define PLL_DIV(n)		(0x63 + ((n) & 0x3)) /* 0..2 */
 83#define PLL_FRAC(n)		(0x66 + ((n) & 0x3)) /* 0..2 */
 84#define PLL_INT(n)		(0x69 + ((n) & 0x1)) /* 0..1 */
 85#define PLL_REF_DIV		0x6b
 86#define PLL_REF_DIV_P(n)		((n) & 0xf)
 87#define PLL_REF_DIV_Pe			BIT(4)
 88#define PLL_REF_DIV_S(n)		(((n) & 0x7) << 5)
 89#define PLL_SSC_P(n)		(0x6c + ((n) & 0x3)) /* 0..2 */
 90#define PLL_SSC_STEP(n)		(0x6f + ((n) & 0x3)) /* 0..2 */
 91#define PLL_SSC_OFFSET(n)	(0x72 + ((n) & 0x3)) /* 0..3 */
 92#define GPIO_OEN		0x79
 93#define MIPI_CFG_PW		0x7a
 94#define MIPI_CFG_PW_CONFIG_DSI		0xc1
 95#define MIPI_CFG_PW_CONFIG_I2C		0x3e
 96#define GPIO_SEL(n)		(0x7b + ((n) & 0x1)) /* 0..1 */
 97#define IRQ_SEL			0x7d
 98#define DBG_SEL			0x7e
 99#define DBG_SIGNAL		0x7f
100#define MIPI_ERR_VECTOR_L	0x80
101#define MIPI_ERR_VECTOR_H	0x81
102#define MIPI_ERR_VECTOR_EN_L	0x82
103#define MIPI_ERR_VECTOR_EN_H	0x83
104#define MIPI_MAX_SIZE_L		0x84
105#define MIPI_MAX_SIZE_H		0x85
106#define DSI_CTRL		0x86
107#define DSI_CTRL_UNKNOWN		0x28
108#define DSI_CTRL_DSI_LANES(n)		((n) & 0x3)
109#define MIPI_PN_SWAP		0x87
110#define MIPI_PN_SWAP_CLK		BIT(4)
111#define MIPI_PN_SWAP_D(n)		BIT((n) & 0x3)
112#define MIPI_SOT_SYNC_BIT(n)	(0x88 + ((n) & 0x1)) /* 0..1 */
113#define MIPI_ULPS_CTRL		0x8a
114#define MIPI_CLK_CHK_VAR	0x8e
115#define MIPI_CLK_CHK_INI	0x8f
116#define MIPI_T_TERM_EN		0x90
117#define MIPI_T_HS_SETTLE	0x91
118#define MIPI_T_TA_SURE_PRE	0x92
119#define MIPI_T_LPX_SET		0x94
120#define MIPI_T_CLK_MISS		0x95
121#define MIPI_INIT_TIME_L	0x96
122#define MIPI_INIT_TIME_H	0x97
123#define MIPI_T_CLK_TERM_EN	0x99
124#define MIPI_T_CLK_SETTLE	0x9a
125#define MIPI_TO_HS_RX_L		0x9e
126#define MIPI_TO_HS_RX_H		0x9f
127#define MIPI_PHY(n)		(0xa0 + ((n) & 0x7)) /* 0..5 */
128#define MIPI_PD_RX		0xb0
129#define MIPI_PD_TERM		0xb1
130#define MIPI_PD_HSRX		0xb2
131#define MIPI_PD_LPTX		0xb3
132#define MIPI_PD_LPRX		0xb4
133#define MIPI_PD_CK_LANE		0xb5
134#define MIPI_FORCE_0		0xb6
135#define MIPI_RST_CTRL		0xb7
136#define MIPI_RST_NUM		0xb8
137#define MIPI_DBG_SET(n)		(0xc0 + ((n) & 0xf)) /* 0..9 */
138#define MIPI_DBG_SEL		0xe0
139#define MIPI_DBG_DATA		0xe1
140#define MIPI_ATE_TEST_SEL	0xe2
141#define MIPI_ATE_STATUS(n)	(0xe3 + ((n) & 0x1)) /* 0..1 */
142
143struct chipone {
144	struct device *dev;
145	struct regmap *regmap;
146	struct i2c_client *client;
147	struct drm_bridge bridge;
148	struct drm_display_mode mode;
149	struct drm_bridge *panel_bridge;
150	struct mipi_dsi_device *dsi;
151	struct gpio_desc *enable_gpio;
152	struct regulator *vdd1;
153	struct regulator *vdd2;
154	struct regulator *vdd3;
155	struct clk *refclk;
156	unsigned long refclk_rate;
157	bool interface_i2c;
158};
159
160static const struct regmap_range chipone_dsi_readable_ranges[] = {
161	regmap_reg_range(VENDOR_ID, VERSION_ID),
162	regmap_reg_range(FIRMWARE_VERSION, PLL_SSC_OFFSET(3)),
163	regmap_reg_range(GPIO_OEN, MIPI_ULPS_CTRL),
164	regmap_reg_range(MIPI_CLK_CHK_VAR, MIPI_T_TA_SURE_PRE),
165	regmap_reg_range(MIPI_T_LPX_SET, MIPI_INIT_TIME_H),
166	regmap_reg_range(MIPI_T_CLK_TERM_EN, MIPI_T_CLK_SETTLE),
167	regmap_reg_range(MIPI_TO_HS_RX_L, MIPI_PHY(5)),
168	regmap_reg_range(MIPI_PD_RX, MIPI_RST_NUM),
169	regmap_reg_range(MIPI_DBG_SET(0), MIPI_DBG_SET(9)),
170	regmap_reg_range(MIPI_DBG_SEL, MIPI_ATE_STATUS(1)),
171};
172
173static const struct regmap_access_table chipone_dsi_readable_table = {
174	.yes_ranges = chipone_dsi_readable_ranges,
175	.n_yes_ranges = ARRAY_SIZE(chipone_dsi_readable_ranges),
176};
177
178static const struct regmap_range chipone_dsi_writeable_ranges[] = {
179	regmap_reg_range(CONFIG_FINISH, PLL_SSC_OFFSET(3)),
180	regmap_reg_range(GPIO_OEN, MIPI_ULPS_CTRL),
181	regmap_reg_range(MIPI_CLK_CHK_VAR, MIPI_T_TA_SURE_PRE),
182	regmap_reg_range(MIPI_T_LPX_SET, MIPI_INIT_TIME_H),
183	regmap_reg_range(MIPI_T_CLK_TERM_EN, MIPI_T_CLK_SETTLE),
184	regmap_reg_range(MIPI_TO_HS_RX_L, MIPI_PHY(5)),
185	regmap_reg_range(MIPI_PD_RX, MIPI_RST_NUM),
186	regmap_reg_range(MIPI_DBG_SET(0), MIPI_DBG_SET(9)),
187	regmap_reg_range(MIPI_DBG_SEL, MIPI_ATE_STATUS(1)),
188};
189
190static const struct regmap_access_table chipone_dsi_writeable_table = {
191	.yes_ranges = chipone_dsi_writeable_ranges,
192	.n_yes_ranges = ARRAY_SIZE(chipone_dsi_writeable_ranges),
193};
194
195static const struct regmap_config chipone_regmap_config = {
196	.reg_bits = 8,
197	.val_bits = 8,
198	.rd_table = &chipone_dsi_readable_table,
199	.wr_table = &chipone_dsi_writeable_table,
200	.cache_type = REGCACHE_MAPLE,
201	.max_register = MIPI_ATE_STATUS(1),
202};
203
204static int chipone_dsi_read(void *context,
205			    const void *reg, size_t reg_size,
206			    void *val, size_t val_size)
207{
208	struct mipi_dsi_device *dsi = context;
209	const u16 reg16 = (val_size << 8) | *(u8 *)reg;
210	int ret;
211
212	ret = mipi_dsi_generic_read(dsi, &reg16, 2, val, val_size);
213
214	return ret == val_size ? 0 : -EINVAL;
215}
216
217static int chipone_dsi_write(void *context, const void *data, size_t count)
218{
219	struct mipi_dsi_device *dsi = context;
220
221	return mipi_dsi_generic_write(dsi, data, 2);
222}
223
224static const struct regmap_bus chipone_dsi_regmap_bus = {
225	.read				= chipone_dsi_read,
226	.write				= chipone_dsi_write,
227	.reg_format_endian_default	= REGMAP_ENDIAN_NATIVE,
228	.val_format_endian_default	= REGMAP_ENDIAN_NATIVE,
229};
230
231static inline struct chipone *bridge_to_chipone(struct drm_bridge *bridge)
232{
233	return container_of(bridge, struct chipone, bridge);
234}
235
236static void chipone_readb(struct chipone *icn, u8 reg, u8 *val)
237{
238	int ret, pval;
239
240	ret = regmap_read(icn->regmap, reg, &pval);
241
242	*val = ret ? 0 : pval & 0xff;
243}
244
245static int chipone_writeb(struct chipone *icn, u8 reg, u8 val)
246{
247	return regmap_write(icn->regmap, reg, val);
248}
249
250static void chipone_configure_pll(struct chipone *icn,
251				  const struct drm_display_mode *mode)
252{
253	unsigned int best_p = 0, best_m = 0, best_s = 0;
254	unsigned int mode_clock = mode->clock * 1000;
255	unsigned int delta, min_delta = 0xffffffff;
256	unsigned int freq_p, freq_s, freq_out;
257	unsigned int p_min, p_max;
258	unsigned int p, m, s;
259	unsigned int fin;
260	bool best_p_pot;
261	u8 ref_div;
262
263	/*
264	 * DSI byte clock frequency (input into PLL) is calculated as:
265	 *  DSI_CLK = HS clock / 4
266	 *
267	 * DPI pixel clock frequency (output from PLL) is mode clock.
268	 *
269	 * The chip contains fractional PLL which works as follows:
270	 *  DPI_CLK = ((DSI_CLK / P) * M) / S
271	 * P is pre-divider, register PLL_REF_DIV[3:0] is 1:n divider
272	 *                   register PLL_REF_DIV[4] is extra 1:2 divider
273	 * M is integer multiplier, register PLL_INT(0) is multiplier
274	 * S is post-divider, register PLL_REF_DIV[7:5] is 2^(n+1) divider
275	 *
276	 * It seems the PLL input clock after applying P pre-divider have
277	 * to be lower than 20 MHz.
278	 */
279	if (icn->refclk)
280		fin = icn->refclk_rate;
281	else
282		fin = icn->dsi->hs_rate / 4; /* in Hz */
283
284	/* Minimum value of P predivider for PLL input in 5..20 MHz */
285	p_min = clamp(DIV_ROUND_UP(fin, 20000000), 1U, 31U);
286	p_max = clamp(fin / 5000000, 1U, 31U);
287
288	for (p = p_min; p < p_max; p++) {	/* PLL_REF_DIV[4,3:0] */
289		if (p > 16 && p & 1)		/* P > 16 uses extra /2 */
290			continue;
291		freq_p = fin / p;
292		if (freq_p == 0)		/* Divider too high */
293			break;
294
295		for (s = 0; s < 0x7; s++) {	/* PLL_REF_DIV[7:5] */
296			freq_s = freq_p / BIT(s + 1);
297			if (freq_s == 0)	/* Divider too high */
298				break;
299
300			m = mode_clock / freq_s;
301
302			/* Multiplier is 8 bit */
303			if (m > 0xff)
304				continue;
305
306			/* Limit PLL VCO frequency to 1 GHz */
307			freq_out = (fin * m) / p;
308			if (freq_out > 1000000000)
309				continue;
310
311			/* Apply post-divider */
312			freq_out /= BIT(s + 1);
313
314			delta = abs(mode_clock - freq_out);
315			if (delta < min_delta) {
316				best_p = p;
317				best_m = m;
318				best_s = s;
319				min_delta = delta;
320			}
321		}
322	}
323
324	best_p_pot = !(best_p & 1);
325
326	dev_dbg(icn->dev,
327		"PLL: P[3:0]=%d P[4]=2*%d M=%d S[7:5]=2^%d delta=%d => DSI f_in(%s)=%d Hz ; DPI f_out=%d Hz\n",
328		best_p >> best_p_pot, best_p_pot, best_m, best_s + 1,
329		min_delta, icn->refclk ? "EXT" : "DSI", fin,
330		(fin * best_m) / (best_p << (best_s + 1)));
331
332	ref_div = PLL_REF_DIV_P(best_p >> best_p_pot) | PLL_REF_DIV_S(best_s);
333	if (best_p_pot)	/* Prefer /2 pre-divider */
334		ref_div |= PLL_REF_DIV_Pe;
335
336	/* Clock source selection either external clock or MIPI DSI clock lane */
337	chipone_writeb(icn, PLL_CTRL(6),
338		       icn->refclk ? PLL_CTRL_6_EXTERNAL : PLL_CTRL_6_MIPI_CLK);
339	chipone_writeb(icn, PLL_REF_DIV, ref_div);
340	chipone_writeb(icn, PLL_INT(0), best_m);
341}
342
343static void chipone_atomic_enable(struct drm_bridge *bridge,
344				  struct drm_atomic_state *state)
345{
346	struct chipone *icn = bridge_to_chipone(bridge);
347	struct drm_display_mode *mode = &icn->mode;
348	const struct drm_bridge_state *bridge_state;
349	u16 hfp, hbp, hsync;
350	u32 bus_flags;
351	u8 pol, sys_ctrl_1, id[4];
352
353	chipone_readb(icn, VENDOR_ID, id);
354	chipone_readb(icn, DEVICE_ID_H, id + 1);
355	chipone_readb(icn, DEVICE_ID_L, id + 2);
356	chipone_readb(icn, VERSION_ID, id + 3);
357
358	dev_dbg(icn->dev,
359		"Chip IDs: Vendor=0x%02x Device=0x%02x:0x%02x Version=0x%02x\n",
360		id[0], id[1], id[2], id[3]);
361
362	if (id[0] != 0xc1 || id[1] != 0x62 || id[2] != 0x11) {
363		dev_dbg(icn->dev, "Invalid Chip IDs, aborting configuration\n");
364		return;
365	}
366
367	/* Get the DPI flags from the bridge state. */
368	bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
369	bus_flags = bridge_state->output_bus_cfg.flags;
370
371	if (icn->interface_i2c)
372		chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_I2C);
373	else
374		chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_DSI);
375
376	chipone_writeb(icn, HACTIVE_LI, mode->hdisplay & 0xff);
377
378	chipone_writeb(icn, VACTIVE_LI, mode->vdisplay & 0xff);
379
380	/*
381	 * lsb nibble: 2nd nibble of hdisplay
382	 * msb nibble: 2nd nibble of vdisplay
383	 */
384	chipone_writeb(icn, VACTIVE_HACTIVE_HI,
385		       ((mode->hdisplay >> 8) & 0xf) |
386		       (((mode->vdisplay >> 8) & 0xf) << 4));
387
388	hfp = mode->hsync_start - mode->hdisplay;
389	hsync = mode->hsync_end - mode->hsync_start;
390	hbp = mode->htotal - mode->hsync_end;
391
392	chipone_writeb(icn, HFP_LI, hfp & 0xff);
393	chipone_writeb(icn, HSYNC_LI, hsync & 0xff);
394	chipone_writeb(icn, HBP_LI, hbp & 0xff);
395	/* Top two bits of Horizontal Front porch/Sync/Back porch */
396	chipone_writeb(icn, HFP_HSW_HBP_HI,
397		       HFP_HSW_HBP_HI_HFP(hfp) |
398		       HFP_HSW_HBP_HI_HS(hsync) |
399		       HFP_HSW_HBP_HI_HBP(hbp));
400
401	chipone_writeb(icn, VFP, mode->vsync_start - mode->vdisplay);
402
403	chipone_writeb(icn, VSYNC, mode->vsync_end - mode->vsync_start);
404
405	chipone_writeb(icn, VBP, mode->vtotal - mode->vsync_end);
406
407	/* dsi specific sequence */
408	chipone_writeb(icn, SYNC_EVENT_DLY, 0x80);
409	chipone_writeb(icn, HFP_MIN, hfp & 0xff);
410
411	/* DSI data lane count */
412	chipone_writeb(icn, DSI_CTRL,
413		       DSI_CTRL_UNKNOWN | DSI_CTRL_DSI_LANES(icn->dsi->lanes - 1));
414
415	chipone_writeb(icn, MIPI_PD_CK_LANE, 0xa0);
416	chipone_writeb(icn, PLL_CTRL(12), 0xff);
417	chipone_writeb(icn, MIPI_PN_SWAP, 0x00);
418
419	/* DPI HS/VS/DE polarity */
420	pol = ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIST_POL_HSYNC_POL : 0) |
421	      ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIST_POL_VSYNC_POL : 0) |
422	      ((bus_flags & DRM_BUS_FLAG_DE_HIGH) ? BIST_POL_DE_POL : 0);
423	chipone_writeb(icn, BIST_POL, pol);
424
425	/* Configure PLL settings */
426	chipone_configure_pll(icn, mode);
427
428	chipone_writeb(icn, SYS_CTRL(0), 0x40);
429	sys_ctrl_1 = 0x88;
430
431	if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE)
432		sys_ctrl_1 |= FIELD_PREP(SYS_CTRL_1_CLK_PHASE_MSK, CLK_PHASE_0);
433	else
434		sys_ctrl_1 |= FIELD_PREP(SYS_CTRL_1_CLK_PHASE_MSK, CLK_PHASE_1_2);
435
436	chipone_writeb(icn, SYS_CTRL(1), sys_ctrl_1);
437
438	/* icn6211 specific sequence */
439	chipone_writeb(icn, MIPI_FORCE_0, 0x20);
440	chipone_writeb(icn, PLL_CTRL(1), 0x20);
441	chipone_writeb(icn, CONFIG_FINISH, 0x10);
442
443	usleep_range(10000, 11000);
444}
445
446static void chipone_atomic_pre_enable(struct drm_bridge *bridge,
447				      struct drm_atomic_state *state)
448{
449	struct chipone *icn = bridge_to_chipone(bridge);
450	int ret;
451
452	if (icn->vdd1) {
453		ret = regulator_enable(icn->vdd1);
454		if (ret)
455			DRM_DEV_ERROR(icn->dev,
456				      "failed to enable VDD1 regulator: %d\n", ret);
457	}
458
459	if (icn->vdd2) {
460		ret = regulator_enable(icn->vdd2);
461		if (ret)
462			DRM_DEV_ERROR(icn->dev,
463				      "failed to enable VDD2 regulator: %d\n", ret);
464	}
465
466	if (icn->vdd3) {
467		ret = regulator_enable(icn->vdd3);
468		if (ret)
469			DRM_DEV_ERROR(icn->dev,
470				      "failed to enable VDD3 regulator: %d\n", ret);
471	}
472
473	ret = clk_prepare_enable(icn->refclk);
474	if (ret)
475		DRM_DEV_ERROR(icn->dev,
476			      "failed to enable RECLK clock: %d\n", ret);
477
478	gpiod_set_value(icn->enable_gpio, 1);
479
480	usleep_range(10000, 11000);
481}
482
483static void chipone_atomic_post_disable(struct drm_bridge *bridge,
484					struct drm_atomic_state *state)
485{
486	struct chipone *icn = bridge_to_chipone(bridge);
487
488	clk_disable_unprepare(icn->refclk);
489
490	if (icn->vdd1)
491		regulator_disable(icn->vdd1);
492
493	if (icn->vdd2)
494		regulator_disable(icn->vdd2);
495
496	if (icn->vdd3)
497		regulator_disable(icn->vdd3);
498
499	gpiod_set_value(icn->enable_gpio, 0);
500}
501
502static void chipone_mode_set(struct drm_bridge *bridge,
503			     const struct drm_display_mode *mode,
504			     const struct drm_display_mode *adjusted_mode)
505{
506	struct chipone *icn = bridge_to_chipone(bridge);
507
508	drm_mode_copy(&icn->mode, adjusted_mode);
509};
510
511static int chipone_dsi_attach(struct chipone *icn)
512{
513	struct mipi_dsi_device *dsi = icn->dsi;
514	struct device *dev = icn->dev;
515	int dsi_lanes, ret;
516
517	dsi_lanes = drm_of_get_data_lanes_count_ep(dev->of_node, 0, 0, 1, 4);
518
519	/*
520	 * If the 'data-lanes' property does not exist in DT or is invalid,
521	 * default to previously hard-coded behavior, which was 4 data lanes.
522	 */
523	if (dsi_lanes < 0)
524		icn->dsi->lanes = 4;
525	else
526		icn->dsi->lanes = dsi_lanes;
527
528	dsi->format = MIPI_DSI_FMT_RGB888;
529	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
530			  MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET;
531	dsi->hs_rate = 500000000;
532	dsi->lp_rate = 16000000;
533
534	ret = mipi_dsi_attach(dsi);
535	if (ret < 0)
536		dev_err(icn->dev, "failed to attach dsi\n");
537
538	return ret;
539}
540
541static int chipone_dsi_host_attach(struct chipone *icn)
542{
543	struct device *dev = icn->dev;
544	struct device_node *host_node;
545	struct device_node *endpoint;
546	struct mipi_dsi_device *dsi;
547	struct mipi_dsi_host *host;
548	int ret = 0;
549
550	const struct mipi_dsi_device_info info = {
551		.type = "chipone",
552		.channel = 0,
553		.node = NULL,
554	};
555
556	endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
557	host_node = of_graph_get_remote_port_parent(endpoint);
558	of_node_put(endpoint);
559
560	if (!host_node)
561		return -EINVAL;
562
563	host = of_find_mipi_dsi_host_by_node(host_node);
564	of_node_put(host_node);
565	if (!host)
566		return dev_err_probe(dev, -EPROBE_DEFER, "failed to find dsi host\n");
567
568	dsi = mipi_dsi_device_register_full(host, &info);
569	if (IS_ERR(dsi)) {
570		return dev_err_probe(dev, PTR_ERR(dsi),
571				     "failed to create dsi device\n");
572	}
573
574	icn->dsi = dsi;
575
576	ret = chipone_dsi_attach(icn);
577	if (ret < 0)
578		mipi_dsi_device_unregister(dsi);
579
580	return ret;
581}
582
583static int chipone_attach(struct drm_bridge *bridge,
584			  struct drm_encoder *encoder,
585			  enum drm_bridge_attach_flags flags)
586{
587	struct chipone *icn = bridge_to_chipone(bridge);
588
589	return drm_bridge_attach(encoder, icn->panel_bridge, bridge, flags);
590}
591
592#define MAX_INPUT_SEL_FORMATS	1
593
594static u32 *
595chipone_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
596				  struct drm_bridge_state *bridge_state,
597				  struct drm_crtc_state *crtc_state,
598				  struct drm_connector_state *conn_state,
599				  u32 output_fmt,
600				  unsigned int *num_input_fmts)
601{
602	u32 *input_fmts;
603
604	*num_input_fmts = 0;
605
606	input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
607			     GFP_KERNEL);
608	if (!input_fmts)
609		return NULL;
610
611	/* This is the DSI-end bus format */
612	input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
613	*num_input_fmts = 1;
614
615	return input_fmts;
616}
617
618static const struct drm_bridge_funcs chipone_bridge_funcs = {
619	.atomic_duplicate_state	= drm_atomic_helper_bridge_duplicate_state,
620	.atomic_destroy_state	= drm_atomic_helper_bridge_destroy_state,
621	.atomic_reset		= drm_atomic_helper_bridge_reset,
622	.atomic_pre_enable	= chipone_atomic_pre_enable,
623	.atomic_enable		= chipone_atomic_enable,
624	.atomic_post_disable	= chipone_atomic_post_disable,
625	.mode_set		= chipone_mode_set,
626	.attach			= chipone_attach,
627	.atomic_get_input_bus_fmts = chipone_atomic_get_input_bus_fmts,
628};
629
630static int chipone_parse_dt(struct chipone *icn)
631{
632	struct device *dev = icn->dev;
633	int ret;
634
635	icn->refclk = devm_clk_get_optional(dev, "refclk");
636	if (IS_ERR(icn->refclk)) {
637		ret = PTR_ERR(icn->refclk);
638		DRM_DEV_ERROR(dev, "failed to get REFCLK clock: %d\n", ret);
639		return ret;
640	} else if (icn->refclk) {
641		icn->refclk_rate = clk_get_rate(icn->refclk);
642		if (icn->refclk_rate < 10000000 || icn->refclk_rate > 154000000) {
643			DRM_DEV_ERROR(dev, "REFCLK out of range: %ld Hz\n",
644				      icn->refclk_rate);
645			return -EINVAL;
646		}
647	}
648
649	icn->vdd1 = devm_regulator_get_optional(dev, "vdd1");
650	if (IS_ERR(icn->vdd1)) {
651		ret = PTR_ERR(icn->vdd1);
652		if (ret == -EPROBE_DEFER)
653			return -EPROBE_DEFER;
654		icn->vdd1 = NULL;
655		DRM_DEV_DEBUG(dev, "failed to get VDD1 regulator: %d\n", ret);
656	}
657
658	icn->vdd2 = devm_regulator_get_optional(dev, "vdd2");
659	if (IS_ERR(icn->vdd2)) {
660		ret = PTR_ERR(icn->vdd2);
661		if (ret == -EPROBE_DEFER)
662			return -EPROBE_DEFER;
663		icn->vdd2 = NULL;
664		DRM_DEV_DEBUG(dev, "failed to get VDD2 regulator: %d\n", ret);
665	}
666
667	icn->vdd3 = devm_regulator_get_optional(dev, "vdd3");
668	if (IS_ERR(icn->vdd3)) {
669		ret = PTR_ERR(icn->vdd3);
670		if (ret == -EPROBE_DEFER)
671			return -EPROBE_DEFER;
672		icn->vdd3 = NULL;
673		DRM_DEV_DEBUG(dev, "failed to get VDD3 regulator: %d\n", ret);
674	}
675
676	icn->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
677	if (IS_ERR(icn->enable_gpio)) {
678		DRM_DEV_ERROR(dev, "failed to get enable GPIO\n");
679		return PTR_ERR(icn->enable_gpio);
680	}
681
682	icn->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
683	if (IS_ERR(icn->panel_bridge))
684		return PTR_ERR(icn->panel_bridge);
685
686	return 0;
687}
688
689static int chipone_common_probe(struct device *dev, struct chipone **icnr)
690{
691	struct chipone *icn;
692	int ret;
693
694	icn = devm_drm_bridge_alloc(dev, struct chipone, bridge,
695				    &chipone_bridge_funcs);
696	if (IS_ERR(icn))
697		return PTR_ERR(icn);
698
699	icn->dev = dev;
700
701	ret = chipone_parse_dt(icn);
702	if (ret)
703		return ret;
704
705	icn->bridge.type = DRM_MODE_CONNECTOR_DPI;
706	icn->bridge.of_node = dev->of_node;
707
708	*icnr = icn;
709
710	return ret;
711}
712
713static int chipone_dsi_probe(struct mipi_dsi_device *dsi)
714{
715	struct device *dev = &dsi->dev;
716	struct chipone *icn;
717	int ret;
718
719	ret = chipone_common_probe(dev, &icn);
720	if (ret)
721		return ret;
722
723	icn->regmap = devm_regmap_init(dev, &chipone_dsi_regmap_bus,
724				       dsi, &chipone_regmap_config);
725	if (IS_ERR(icn->regmap))
726		return PTR_ERR(icn->regmap);
727
728	icn->interface_i2c = false;
729	icn->dsi = dsi;
730
731	mipi_dsi_set_drvdata(dsi, icn);
732
733	drm_bridge_add(&icn->bridge);
734
735	ret = chipone_dsi_attach(icn);
736	if (ret)
737		drm_bridge_remove(&icn->bridge);
738
739	return ret;
740}
741
742static int chipone_i2c_probe(struct i2c_client *client)
743{
744	struct device *dev = &client->dev;
745	struct chipone *icn;
746	int ret;
747
748	ret = chipone_common_probe(dev, &icn);
749	if (ret)
750		return ret;
751
752	icn->regmap = devm_regmap_init_i2c(client, &chipone_regmap_config);
753	if (IS_ERR(icn->regmap))
754		return PTR_ERR(icn->regmap);
755
756	icn->interface_i2c = true;
757	icn->client = client;
758	dev_set_drvdata(dev, icn);
759	i2c_set_clientdata(client, icn);
760
761	drm_bridge_add(&icn->bridge);
762
763	return chipone_dsi_host_attach(icn);
764}
765
766static void chipone_dsi_remove(struct mipi_dsi_device *dsi)
767{
768	struct chipone *icn = mipi_dsi_get_drvdata(dsi);
769
770	mipi_dsi_detach(dsi);
771	drm_bridge_remove(&icn->bridge);
772}
773
774static const struct of_device_id chipone_of_match[] = {
775	{ .compatible = "chipone,icn6211", },
776	{ /* sentinel */ }
777};
778MODULE_DEVICE_TABLE(of, chipone_of_match);
779
780static struct mipi_dsi_driver chipone_dsi_driver = {
781	.probe = chipone_dsi_probe,
782	.remove = chipone_dsi_remove,
783	.driver = {
784		.name = "chipone-icn6211",
785		.of_match_table = chipone_of_match,
786	},
787};
788
789static const struct i2c_device_id chipone_i2c_id[] = {
790	{ "chipone,icn6211" },
791	{},
792};
793MODULE_DEVICE_TABLE(i2c, chipone_i2c_id);
794
795static struct i2c_driver chipone_i2c_driver = {
796	.probe = chipone_i2c_probe,
797	.id_table = chipone_i2c_id,
798	.driver = {
799		.name = "chipone-icn6211-i2c",
800		.of_match_table = chipone_of_match,
801	},
802};
803
804static int __init chipone_init(void)
805{
806	if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
807		mipi_dsi_driver_register(&chipone_dsi_driver);
808
809	return i2c_add_driver(&chipone_i2c_driver);
810}
811module_init(chipone_init);
812
813static void __exit chipone_exit(void)
814{
815	i2c_del_driver(&chipone_i2c_driver);
816
817	if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
818		mipi_dsi_driver_unregister(&chipone_dsi_driver);
819}
820module_exit(chipone_exit);
821
822MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
823MODULE_DESCRIPTION("Chipone ICN6211 MIPI-DSI to RGB Converter Bridge");
824MODULE_LICENSE("GPL");