analogix_dp_core.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3* Analogix DP (Display Port) core interface driver.
   4*
   5* Copyright (C) 2012 Samsung Electronics Co., Ltd.
   6* Author: Jingoo Han <jg1.han@samsung.com>
   7*/
   8
   9#include <linux/clk.h>
  10#include <linux/component.h>
  11#include <linux/err.h>
  12#include <linux/export.h>
  13#include <linux/gpio/consumer.h>
  14#include <linux/interrupt.h>
  15#include <linux/io.h>
  16#include <linux/iopoll.h>
  17#include <linux/module.h>
  18#include <linux/of.h>
  19#include <linux/phy/phy.h>
  20#include <linux/platform_device.h>
  21
  22#include <drm/bridge/analogix_dp.h>
  23#include <drm/drm_atomic.h>
  24#include <drm/drm_atomic_helper.h>
  25#include <drm/drm_bridge.h>
  26#include <drm/drm_crtc.h>
  27#include <drm/drm_device.h>
  28#include <drm/drm_edid.h>
  29#include <drm/drm_panel.h>
  30#include <drm/drm_print.h>
  31#include <drm/drm_probe_helper.h>
  32
  33#include "analogix_dp_core.h"
  34#include "analogix_dp_reg.h"
  35
  36#define to_dp(nm)	container_of(nm, struct analogix_dp_device, nm)
  37
  38static const bool verify_fast_training;
  39
  40static void analogix_dp_init_dp(struct analogix_dp_device *dp)
  41{
  42	analogix_dp_reset(dp);
  43
  44	analogix_dp_swreset(dp);
  45
  46	analogix_dp_init_analog_param(dp);
  47	analogix_dp_init_interrupt(dp);
  48
  49	/* SW defined function Normal operation */
  50	analogix_dp_enable_sw_function(dp);
  51
  52	analogix_dp_config_interrupt(dp);
  53
  54	analogix_dp_init_hpd(dp);
  55	analogix_dp_init_aux(dp);
  56}
  57
  58static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
  59{
  60	int timeout_loop = 0;
  61
  62	while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
  63		if (analogix_dp_get_plug_in_status(dp) == 0)
  64			return 0;
  65
  66		timeout_loop++;
  67		usleep_range(1000, 1100);
  68	}
  69
  70	/*
  71	 * Some edp screen do not have hpd signal, so we can't just
  72	 * return failed when hpd plug in detect failed, DT property
  73	 * "force-hpd" would indicate whether driver need this.
  74	 */
  75	if (!dp->force_hpd)
  76		return -ETIMEDOUT;
  77
  78	/*
  79	 * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
  80	 * will not work, so we need to give a force hpd action to
  81	 * set HPD_STATUS manually.
  82	 */
  83	dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
  84
  85	analogix_dp_force_hpd(dp);
  86
  87	if (analogix_dp_get_plug_in_status(dp) != 0) {
  88		dev_err(dp->dev, "failed to get hpd plug in status\n");
  89		return -EINVAL;
  90	}
  91
  92	dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
  93
  94	return 0;
  95}
  96
  97static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
  98{
  99	unsigned char psr_version;
 100	int ret;
 101
 102	ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
 103	if (ret != 1) {
 104		dev_err(dp->dev, "failed to get PSR version, disable it\n");
 105		return false;
 106	}
 107
 108	dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
 109	return psr_version & DP_PSR_IS_SUPPORTED;
 110}
 111
 112static int analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
 113{
 114	unsigned char psr_en;
 115	int ret;
 116
 117	/* Disable psr function */
 118	ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
 119	if (ret != 1) {
 120		dev_err(dp->dev, "failed to get psr config\n");
 121		goto end;
 122	}
 123
 124	psr_en &= ~DP_PSR_ENABLE;
 125	ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 126	if (ret != 1) {
 127		dev_err(dp->dev, "failed to disable panel psr\n");
 128		goto end;
 129	}
 130
 131	/* Main-Link transmitter remains active during PSR active states */
 132	psr_en = DP_PSR_CRC_VERIFICATION;
 133	ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 134	if (ret != 1) {
 135		dev_err(dp->dev, "failed to set panel psr\n");
 136		goto end;
 137	}
 138
 139	/* Enable psr function */
 140	psr_en = DP_PSR_ENABLE | DP_PSR_CRC_VERIFICATION;
 141	ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 142	if (ret != 1) {
 143		dev_err(dp->dev, "failed to set panel psr\n");
 144		goto end;
 145	}
 146
 147	analogix_dp_enable_psr_crc(dp);
 148
 149	dp->psr_supported = true;
 150
 151	return 0;
 152end:
 153	dev_err(dp->dev, "enable psr fail, force to disable psr\n");
 154
 155	return ret;
 156}
 157
 158static int
 159analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
 160				       bool enable)
 161{
 162	u8 data;
 163	int ret;
 164
 165	ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
 166	if (ret != 1)
 167		return ret;
 168
 169	if (enable)
 170		ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
 171					 DP_LANE_COUNT_ENHANCED_FRAME_EN |
 172					 DPCD_LANE_COUNT_SET(data));
 173	else
 174		ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
 175					 DPCD_LANE_COUNT_SET(data));
 176
 177	return ret < 0 ? ret : 0;
 178}
 179
 180static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp,
 181						  u8 *enhanced_mode_support)
 182{
 183	u8 data;
 184	int ret;
 185
 186	ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
 187	if (ret != 1) {
 188		*enhanced_mode_support = 0;
 189		return ret;
 190	}
 191
 192	*enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data);
 193
 194	return 0;
 195}
 196
 197static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
 198{
 199	u8 data;
 200	int ret;
 201
 202	ret = analogix_dp_is_enhanced_mode_available(dp, &data);
 203	if (ret < 0)
 204		return ret;
 205
 206	ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data);
 207	if (ret < 0)
 208		return ret;
 209
 210	analogix_dp_enable_enhanced_mode(dp, data);
 211
 212	return 0;
 213}
 214
 215static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 216{
 217	int ret;
 218
 219	analogix_dp_set_training_pattern(dp, DP_NONE);
 220
 221	ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 222				 DP_TRAINING_PATTERN_DISABLE);
 223
 224	return ret < 0 ? ret : 0;
 225}
 226
 227static int analogix_dp_link_start(struct analogix_dp_device *dp)
 228{
 229	u8 buf[4];
 230	int lane, lane_count, retval;
 231
 232	lane_count = dp->link_train.lane_count;
 233
 234	dp->link_train.lt_state = CLOCK_RECOVERY;
 235	dp->link_train.eq_loop = 0;
 236
 237	for (lane = 0; lane < lane_count; lane++)
 238		dp->link_train.cr_loop[lane] = 0;
 239
 240	/* Set link rate and count as you want to establish*/
 241	analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 242	retval = analogix_dp_wait_pll_locked(dp);
 243	if (retval) {
 244		DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", retval);
 245		return retval;
 246	}
 247	/*
 248	 * MACRO_RST must be applied after the PLL_LOCK to avoid
 249	 * the DP inter pair skew issue for at least 10 us
 250	 */
 251	analogix_dp_reset_macro(dp);
 252	analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 253
 254	/* Setup RX configuration */
 255	buf[0] = dp->link_train.link_rate;
 256	buf[1] = dp->link_train.lane_count;
 257	retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2);
 258	if (retval < 0)
 259		return retval;
 260	/* set enhanced mode if available */
 261	retval = analogix_dp_set_enhanced_mode(dp);
 262	if (retval < 0) {
 263		dev_err(dp->dev, "failed to set enhance mode\n");
 264		return retval;
 265	}
 266
 267	/* Set TX voltage-swing and pre-emphasis to minimum */
 268	for (lane = 0; lane < lane_count; lane++)
 269		dp->link_train.training_lane[lane] =
 270					DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
 271					DP_TRAIN_PRE_EMPH_LEVEL_0;
 272	analogix_dp_set_lane_link_training(dp);
 273
 274	/* Set training pattern 1 */
 275	analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 276
 277	/* Set RX training pattern */
 278	retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 279				    DP_LINK_SCRAMBLING_DISABLE |
 280					DP_TRAINING_PATTERN_1);
 281	if (retval < 0)
 282		return retval;
 283
 284	for (lane = 0; lane < lane_count; lane++)
 285		buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
 286			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 287
 288	retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf,
 289				   lane_count);
 290	if (retval < 0)
 291		return retval;
 292
 293	return 0;
 294}
 295
 296static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 297{
 298	int shift = (lane & 1) * 4;
 299	u8 link_value = link_status[lane >> 1];
 300
 301	return (link_value >> shift) & 0xf;
 302}
 303
 304static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 305{
 306	int lane;
 307	u8 lane_status;
 308
 309	for (lane = 0; lane < lane_count; lane++) {
 310		lane_status = analogix_dp_get_lane_status(link_status, lane);
 311		if ((lane_status & DP_LANE_CR_DONE) == 0)
 312			return -EINVAL;
 313	}
 314	return 0;
 315}
 316
 317static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 318				     int lane_count)
 319{
 320	int lane;
 321	u8 lane_status;
 322
 323	if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
 324		return -EINVAL;
 325
 326	for (lane = 0; lane < lane_count; lane++) {
 327		lane_status = analogix_dp_get_lane_status(link_status, lane);
 328		lane_status &= DP_CHANNEL_EQ_BITS;
 329		if (lane_status != DP_CHANNEL_EQ_BITS)
 330			return -EINVAL;
 331	}
 332
 333	return 0;
 334}
 335
 336static unsigned char
 337analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
 338{
 339	int shift = (lane & 1) * 4;
 340	u8 link_value = adjust_request[lane >> 1];
 341
 342	return (link_value >> shift) & 0x3;
 343}
 344
 345static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 346					u8 adjust_request[2],
 347					int lane)
 348{
 349	int shift = (lane & 1) * 4;
 350	u8 link_value = adjust_request[lane >> 1];
 351
 352	return ((link_value >> shift) & 0xc) >> 2;
 353}
 354
 355static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 356{
 357	analogix_dp_training_pattern_dis(dp);
 358	analogix_dp_set_enhanced_mode(dp);
 359
 360	dp->link_train.lt_state = FAILED;
 361}
 362
 363static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
 364						 u8 adjust_request[2])
 365{
 366	int lane, lane_count;
 367	u8 voltage_swing, pre_emphasis, training_lane;
 368
 369	lane_count = dp->link_train.lane_count;
 370	for (lane = 0; lane < lane_count; lane++) {
 371		voltage_swing = analogix_dp_get_adjust_request_voltage(
 372						adjust_request, lane);
 373		pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 374						adjust_request, lane);
 375		training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 376				DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 377
 378		if (voltage_swing == VOLTAGE_LEVEL_3)
 379			training_lane |= DP_TRAIN_MAX_SWING_REACHED;
 380		if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 381			training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 382
 383		dp->link_train.training_lane[lane] = training_lane;
 384	}
 385}
 386
 387static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
 388{
 389	int lane, lane_count, retval;
 390	u8 voltage_swing, pre_emphasis, training_lane;
 391	u8 link_status[2], adjust_request[2];
 392
 393	usleep_range(100, 101);
 394
 395	lane_count = dp->link_train.lane_count;
 396
 397	retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
 398	if (retval < 0)
 399		return retval;
 400
 401	if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 402		/* set training pattern 2 for EQ */
 403		analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 404
 405		retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 406					    DP_LINK_SCRAMBLING_DISABLE |
 407						DP_TRAINING_PATTERN_2);
 408		if (retval < 0)
 409			return retval;
 410
 411		dev_dbg(dp->dev, "Link Training Clock Recovery success\n");
 412		dp->link_train.lt_state = EQUALIZER_TRAINING;
 413
 414		return 0;
 415	}
 416
 417	retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
 418				  adjust_request, 2);
 419	if (retval < 0)
 420		return retval;
 421
 422	for (lane = 0; lane < lane_count; lane++) {
 423		training_lane = analogix_dp_get_lane_link_training(dp, lane);
 424		voltage_swing = analogix_dp_get_adjust_request_voltage(adjust_request, lane);
 425		pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(adjust_request, lane);
 426
 427		if (DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing &&
 428		    DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis)
 429			dp->link_train.cr_loop[lane]++;
 430
 431		if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
 432		    voltage_swing == VOLTAGE_LEVEL_3 ||
 433		    pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 434			dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
 435				dp->link_train.cr_loop[lane],
 436				voltage_swing, pre_emphasis);
 437			analogix_dp_reduce_link_rate(dp);
 438			return -EIO;
 439		}
 440	}
 441
 442	analogix_dp_get_adjust_training_lane(dp, adjust_request);
 443	analogix_dp_set_lane_link_training(dp);
 444
 445	retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
 446				   dp->link_train.training_lane, lane_count);
 447	if (retval < 0)
 448		return retval;
 449
 450	return 0;
 451}
 452
 453static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 454{
 455	int lane_count, retval;
 456	u32 reg;
 457	u8 link_align, link_status[2], adjust_request[2];
 458
 459	usleep_range(400, 401);
 460
 461	lane_count = dp->link_train.lane_count;
 462
 463	retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
 464	if (retval < 0)
 465		return retval;
 466
 467	if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
 468		analogix_dp_reduce_link_rate(dp);
 469		return -EIO;
 470	}
 471
 472	retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
 473				  adjust_request, 2);
 474	if (retval < 0)
 475		return retval;
 476
 477	retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
 478				   &link_align);
 479	if (retval < 0)
 480		return retval;
 481
 482	analogix_dp_get_adjust_training_lane(dp, adjust_request);
 483
 484	if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
 485		/* traing pattern Set to Normal */
 486		retval = analogix_dp_training_pattern_dis(dp);
 487		if (retval < 0)
 488			return retval;
 489
 490		dev_dbg(dp->dev, "Link Training success!\n");
 491		analogix_dp_get_link_bandwidth(dp, &reg);
 492		dp->link_train.link_rate = reg;
 493		dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 494			dp->link_train.link_rate);
 495
 496		analogix_dp_get_lane_count(dp, &reg);
 497		dp->link_train.lane_count = reg;
 498		dev_dbg(dp->dev, "final lane count = %.2x\n",
 499			dp->link_train.lane_count);
 500
 501		dp->link_train.lt_state = FINISHED;
 502
 503		return 0;
 504	}
 505
 506	/* not all locked */
 507	dp->link_train.eq_loop++;
 508
 509	if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 510		dev_err(dp->dev, "EQ Max loop\n");
 511		analogix_dp_reduce_link_rate(dp);
 512		return -EIO;
 513	}
 514
 515	analogix_dp_set_lane_link_training(dp);
 516
 517	retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
 518				   dp->link_train.training_lane, lane_count);
 519	if (retval < 0)
 520		return retval;
 521
 522	return 0;
 523}
 524
 525static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 526					     u8 *bandwidth)
 527{
 528	u8 data;
 529
 530	/*
 531	 * For DP rev.1.1, Maximum link rate of Main Link lanes
 532	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 533	 * For DP rev.1.2, Maximum link rate of Main Link lanes
 534	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
 535	 */
 536	drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);
 537	*bandwidth = data;
 538}
 539
 540static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 541					      u8 *lane_count)
 542{
 543	u8 data;
 544
 545	/*
 546	 * For DP rev.1.1, Maximum number of Main Link lanes
 547	 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 548	 */
 549	drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
 550	*lane_count = DPCD_MAX_LANE_COUNT(data);
 551}
 552
 553static int analogix_dp_full_link_train(struct analogix_dp_device *dp,
 554				       u32 max_lanes, u32 max_rate)
 555{
 556	int retval = 0;
 557	bool training_finished = false;
 558
 559	/* Initialize by reading RX's DPCD */
 560	analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 561	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 562
 563	if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&
 564	    (dp->link_train.link_rate != DP_LINK_BW_2_7) &&
 565	    (dp->link_train.link_rate != DP_LINK_BW_5_4)) {
 566		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 567			dp->link_train.link_rate);
 568		dp->link_train.link_rate = DP_LINK_BW_1_62;
 569	}
 570
 571	if (dp->link_train.lane_count == 0) {
 572		dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 573			dp->link_train.lane_count);
 574		dp->link_train.lane_count = (u8)LANE_COUNT1;
 575	}
 576
 577	/* Setup TX lane count & rate */
 578	if (dp->link_train.lane_count > max_lanes)
 579		dp->link_train.lane_count = max_lanes;
 580	if (dp->link_train.link_rate > max_rate)
 581		dp->link_train.link_rate = max_rate;
 582
 583	/* All DP analog module power up */
 584	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
 585
 586	dp->link_train.lt_state = START;
 587
 588	/* Process here */
 589	while (!retval && !training_finished) {
 590		switch (dp->link_train.lt_state) {
 591		case START:
 592			retval = analogix_dp_link_start(dp);
 593			if (retval)
 594				dev_err(dp->dev, "LT link start failed!\n");
 595			break;
 596		case CLOCK_RECOVERY:
 597			retval = analogix_dp_process_clock_recovery(dp);
 598			if (retval)
 599				dev_err(dp->dev, "LT CR failed!\n");
 600			break;
 601		case EQUALIZER_TRAINING:
 602			retval = analogix_dp_process_equalizer_training(dp);
 603			if (retval)
 604				dev_err(dp->dev, "LT EQ failed!\n");
 605			break;
 606		case FINISHED:
 607			training_finished = 1;
 608			break;
 609		case FAILED:
 610			return -EREMOTEIO;
 611		}
 612	}
 613	if (retval)
 614		dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
 615
 616	return retval;
 617}
 618
 619static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
 620{
 621	int ret;
 622	u8 link_align, link_status[2];
 623
 624	analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 625	ret = analogix_dp_wait_pll_locked(dp);
 626	if (ret) {
 627		DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", ret);
 628		return ret;
 629	}
 630
 631	/*
 632	 * MACRO_RST must be applied after the PLL_LOCK to avoid
 633	 * the DP inter pair skew issue for at least 10 us
 634	 */
 635	analogix_dp_reset_macro(dp);
 636	analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 637	analogix_dp_set_lane_link_training(dp);
 638
 639	/* source Set training pattern 1 */
 640	analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 641	/* From DP spec, pattern must be on-screen for a minimum 500us */
 642	usleep_range(500, 600);
 643
 644	analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 645	/* From DP spec, pattern must be on-screen for a minimum 500us */
 646	usleep_range(500, 600);
 647
 648	/* TODO: enhanced_mode?*/
 649	analogix_dp_set_training_pattern(dp, DP_NONE);
 650
 651	/*
 652	 * Useful for debugging issues with fast link training, disable for more
 653	 * speed
 654	 */
 655	if (verify_fast_training) {
 656		ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
 657					&link_align);
 658		if (ret < 0) {
 659			DRM_DEV_ERROR(dp->dev, "Read align status failed %d\n",
 660				      ret);
 661			return ret;
 662		}
 663
 664		ret = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status,
 665				       2);
 666		if (ret < 0) {
 667			DRM_DEV_ERROR(dp->dev, "Read link status failed %d\n",
 668				      ret);
 669			return ret;
 670		}
 671
 672		if (analogix_dp_clock_recovery_ok(link_status,
 673						  dp->link_train.lane_count)) {
 674			DRM_DEV_ERROR(dp->dev, "Clock recovery failed\n");
 675			analogix_dp_reduce_link_rate(dp);
 676			return -EIO;
 677		}
 678
 679		if (analogix_dp_channel_eq_ok(link_status, link_align,
 680					      dp->link_train.lane_count)) {
 681			DRM_DEV_ERROR(dp->dev, "Channel EQ failed\n");
 682			analogix_dp_reduce_link_rate(dp);
 683			return -EIO;
 684		}
 685	}
 686
 687	return 0;
 688}
 689
 690static int analogix_dp_train_link(struct analogix_dp_device *dp)
 691{
 692	if (dp->fast_train_enable)
 693		return analogix_dp_fast_link_train(dp);
 694
 695	return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,
 696					   dp->video_info.max_link_rate);
 697}
 698
 699static int analogix_dp_config_video(struct analogix_dp_device *dp)
 700{
 701	int timeout_loop = 0;
 702	int done_count = 0;
 703
 704	analogix_dp_config_video_slave_mode(dp);
 705
 706	analogix_dp_set_video_color_format(dp);
 707
 708	for (;;) {
 709		timeout_loop++;
 710		if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 711			break;
 712		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 713			dev_err(dp->dev, "Timeout of slave video streamclk ok\n");
 714			return -ETIMEDOUT;
 715		}
 716		usleep_range(1000, 1001);
 717	}
 718
 719	/* Set to use the register calculated M/N video */
 720	analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 721
 722	/* For video bist, Video timing must be generated by register */
 723	analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 724
 725	/* Disable video mute */
 726	analogix_dp_enable_video_mute(dp, 0);
 727
 728	/* Configure video slave mode */
 729	analogix_dp_enable_video_master(dp, 0);
 730
 731	/* Enable video */
 732	analogix_dp_start_video(dp);
 733
 734	timeout_loop = 0;
 735
 736	for (;;) {
 737		timeout_loop++;
 738		if (analogix_dp_is_video_stream_on(dp) == 0) {
 739			done_count++;
 740			if (done_count > 10)
 741				break;
 742		} else if (done_count) {
 743			done_count = 0;
 744		}
 745		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 746			dev_warn(dp->dev,
 747				 "Ignoring timeout of video streamclk ok\n");
 748			break;
 749		}
 750
 751		usleep_range(1000, 1001);
 752	}
 753
 754	return 0;
 755}
 756
 757static int analogix_dp_enable_scramble(struct analogix_dp_device *dp,
 758				       bool enable)
 759{
 760	u8 data;
 761	int ret;
 762
 763	if (enable) {
 764		analogix_dp_enable_scrambling(dp);
 765
 766		ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
 767					&data);
 768		if (ret != 1)
 769			return ret;
 770		ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 771				   (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 772	} else {
 773		analogix_dp_disable_scrambling(dp);
 774
 775		ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
 776					&data);
 777		if (ret != 1)
 778			return ret;
 779		ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 780				   (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
 781	}
 782	return ret < 0 ? ret : 0;
 783}
 784
 785static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
 786{
 787	struct analogix_dp_device *dp = arg;
 788	irqreturn_t ret = IRQ_NONE;
 789	enum dp_irq_type irq_type;
 790
 791	irq_type = analogix_dp_get_irq_type(dp);
 792	if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
 793		analogix_dp_mute_hpd_interrupt(dp);
 794		ret = IRQ_WAKE_THREAD;
 795	}
 796
 797	return ret;
 798}
 799
 800static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
 801{
 802	struct analogix_dp_device *dp = arg;
 803	enum dp_irq_type irq_type;
 804
 805	irq_type = analogix_dp_get_irq_type(dp);
 806	if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN ||
 807	    irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) {
 808		dev_dbg(dp->dev, "Detected cable status changed!\n");
 809		if (dp->drm_dev)
 810			drm_helper_hpd_irq_event(dp->drm_dev);
 811	}
 812
 813	if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
 814		analogix_dp_clear_hotplug_interrupts(dp);
 815		analogix_dp_unmute_hpd_interrupt(dp);
 816	}
 817
 818	return IRQ_HANDLED;
 819}
 820
 821static int analogix_dp_fast_link_train_detection(struct analogix_dp_device *dp)
 822{
 823	int ret;
 824	u8 spread;
 825
 826	ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
 827	if (ret != 1) {
 828		dev_err(dp->dev, "failed to read downspread %d\n", ret);
 829		return ret;
 830	}
 831	dp->fast_train_enable = !!(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
 832	dev_dbg(dp->dev, "fast link training %s\n",
 833		dp->fast_train_enable ? "supported" : "unsupported");
 834	return 0;
 835}
 836
 837static int analogix_dp_commit(struct analogix_dp_device *dp)
 838{
 839	int ret;
 840
 841	/* Keep the panel disabled while we configure video */
 842	drm_panel_disable(dp->plat_data->panel);
 843
 844	ret = analogix_dp_train_link(dp);
 845	if (ret) {
 846		dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
 847		return ret;
 848	}
 849
 850	ret = analogix_dp_enable_scramble(dp, 1);
 851	if (ret < 0) {
 852		dev_err(dp->dev, "can not enable scramble\n");
 853		return ret;
 854	}
 855
 856	analogix_dp_init_video(dp);
 857	ret = analogix_dp_config_video(dp);
 858	if (ret) {
 859		dev_err(dp->dev, "unable to config video\n");
 860		return ret;
 861	}
 862
 863	/* Safe to enable the panel now */
 864	drm_panel_enable(dp->plat_data->panel);
 865
 866	/* Check whether panel supports fast training */
 867	ret = analogix_dp_fast_link_train_detection(dp);
 868	if (ret)
 869		return ret;
 870
 871	if (analogix_dp_detect_sink_psr(dp)) {
 872		ret = analogix_dp_enable_sink_psr(dp);
 873		if (ret)
 874			return ret;
 875	}
 876
 877	return ret;
 878}
 879
 880static int analogix_dp_enable_psr(struct analogix_dp_device *dp)
 881{
 882	struct dp_sdp psr_vsc;
 883	int ret;
 884	u8 sink;
 885
 886	ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
 887	if (ret != 1)
 888		DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
 889	else if (sink == DP_PSR_SINK_ACTIVE_RFB)
 890		return 0;
 891
 892	/* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
 893	memset(&psr_vsc, 0, sizeof(psr_vsc));
 894	psr_vsc.sdp_header.HB0 = 0;
 895	psr_vsc.sdp_header.HB1 = 0x7;
 896	psr_vsc.sdp_header.HB2 = 0x2;
 897	psr_vsc.sdp_header.HB3 = 0x8;
 898	psr_vsc.db[0] = 0;
 899	psr_vsc.db[1] = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
 900
 901	ret = analogix_dp_send_psr_spd(dp, &psr_vsc, true);
 902	if (!ret)
 903		analogix_dp_set_analog_power_down(dp, POWER_ALL, true);
 904
 905	return ret;
 906}
 907
 908static int analogix_dp_disable_psr(struct analogix_dp_device *dp)
 909{
 910	struct dp_sdp psr_vsc;
 911	int ret;
 912	u8 sink;
 913
 914	analogix_dp_set_analog_power_down(dp, POWER_ALL, false);
 915
 916	ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
 917	if (ret != 1) {
 918		DRM_DEV_ERROR(dp->dev, "Failed to set DP Power0 %d\n", ret);
 919		return ret;
 920	}
 921
 922	ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
 923	if (ret != 1) {
 924		DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
 925		return ret;
 926	} else if (sink == DP_PSR_SINK_INACTIVE) {
 927		DRM_DEV_ERROR(dp->dev, "sink inactive, skip disable psr");
 928		return 0;
 929	}
 930
 931	ret = analogix_dp_train_link(dp);
 932	if (ret) {
 933		DRM_DEV_ERROR(dp->dev, "Failed to train the link %d\n", ret);
 934		return ret;
 935	}
 936
 937	/* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
 938	memset(&psr_vsc, 0, sizeof(psr_vsc));
 939	psr_vsc.sdp_header.HB0 = 0;
 940	psr_vsc.sdp_header.HB1 = 0x7;
 941	psr_vsc.sdp_header.HB2 = 0x2;
 942	psr_vsc.sdp_header.HB3 = 0x8;
 943
 944	psr_vsc.db[0] = 0;
 945	psr_vsc.db[1] = 0;
 946
 947	return analogix_dp_send_psr_spd(dp, &psr_vsc, true);
 948}
 949
 950static int analogix_dp_get_modes(struct drm_connector *connector)
 951{
 952	struct analogix_dp_device *dp = to_dp(connector);
 953	const struct drm_edid *drm_edid;
 954	int num_modes = 0;
 955
 956	if (dp->plat_data->panel) {
 957		num_modes += drm_panel_get_modes(dp->plat_data->panel, connector);
 958	} else {
 959		drm_edid = drm_edid_read_ddc(connector, &dp->aux.ddc);
 960
 961		drm_edid_connector_update(&dp->connector, drm_edid);
 962
 963		if (drm_edid) {
 964			num_modes += drm_edid_connector_add_modes(&dp->connector);
 965			drm_edid_free(drm_edid);
 966		}
 967	}
 968
 969	if (dp->plat_data->get_modes)
 970		num_modes += dp->plat_data->get_modes(dp->plat_data, connector);
 971
 972	return num_modes;
 973}
 974
 975static struct drm_encoder *
 976analogix_dp_best_encoder(struct drm_connector *connector)
 977{
 978	struct analogix_dp_device *dp = to_dp(connector);
 979
 980	return dp->encoder;
 981}
 982
 983
 984static int analogix_dp_atomic_check(struct drm_connector *connector,
 985				    struct drm_atomic_state *state)
 986{
 987	struct analogix_dp_device *dp = to_dp(connector);
 988	struct drm_connector_state *conn_state;
 989	struct drm_crtc_state *crtc_state;
 990
 991	conn_state = drm_atomic_get_new_connector_state(state, connector);
 992	if (WARN_ON(!conn_state))
 993		return -ENODEV;
 994
 995	conn_state->self_refresh_aware = true;
 996
 997	if (!conn_state->crtc)
 998		return 0;
 999
1000	crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
1001	if (!crtc_state)
1002		return 0;
1003
1004	if (crtc_state->self_refresh_active && !dp->psr_supported)
1005		return -EINVAL;
1006
1007	return 0;
1008}
1009
1010static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
1011	.get_modes = analogix_dp_get_modes,
1012	.best_encoder = analogix_dp_best_encoder,
1013	.atomic_check = analogix_dp_atomic_check,
1014};
1015
1016static enum drm_connector_status
1017analogix_dp_detect(struct drm_connector *connector, bool force)
1018{
1019	struct analogix_dp_device *dp = to_dp(connector);
1020	enum drm_connector_status status = connector_status_disconnected;
1021
1022	if (dp->plat_data->panel)
1023		return connector_status_connected;
1024
1025	if (!analogix_dp_detect_hpd(dp))
1026		status = connector_status_connected;
1027
1028	return status;
1029}
1030
1031static const struct drm_connector_funcs analogix_dp_connector_funcs = {
1032	.fill_modes = drm_helper_probe_single_connector_modes,
1033	.detect = analogix_dp_detect,
1034	.destroy = drm_connector_cleanup,
1035	.reset = drm_atomic_helper_connector_reset,
1036	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1037	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1038};
1039
1040static int analogix_dp_bridge_attach(struct drm_bridge *bridge,
1041				     struct drm_encoder *encoder,
1042				     enum drm_bridge_attach_flags flags)
1043{
1044	struct analogix_dp_device *dp = to_dp(bridge);
1045	struct drm_connector *connector = NULL;
1046	int ret = 0;
1047
1048	if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
1049		DRM_ERROR("Fix bridge driver to make connector optional!");
1050		return -EINVAL;
1051	}
1052
1053	if (!dp->plat_data->skip_connector) {
1054		connector = &dp->connector;
1055		connector->polled = DRM_CONNECTOR_POLL_HPD;
1056
1057		ret = drm_connector_init(dp->drm_dev, connector,
1058					 &analogix_dp_connector_funcs,
1059					 DRM_MODE_CONNECTOR_eDP);
1060		if (ret) {
1061			DRM_ERROR("Failed to initialize connector with drm\n");
1062			return ret;
1063		}
1064
1065		drm_connector_helper_add(connector,
1066					 &analogix_dp_connector_helper_funcs);
1067		drm_connector_attach_encoder(connector, encoder);
1068	}
1069
1070	/*
1071	 * NOTE: the connector registration is implemented in analogix
1072	 * platform driver, that to say connector would be exist after
1073	 * plat_data->attch return, that's why we record the connector
1074	 * point after plat attached.
1075	 */
1076	if (dp->plat_data->attach) {
1077		ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
1078		if (ret) {
1079			DRM_ERROR("Failed at platform attach func\n");
1080			return ret;
1081		}
1082	}
1083
1084	return 0;
1085}
1086
1087static
1088struct drm_crtc *analogix_dp_get_old_crtc(struct analogix_dp_device *dp,
1089					  struct drm_atomic_state *state)
1090{
1091	struct drm_encoder *encoder = dp->encoder;
1092	struct drm_connector *connector;
1093	struct drm_connector_state *conn_state;
1094
1095	connector = drm_atomic_get_old_connector_for_encoder(state, encoder);
1096	if (!connector)
1097		return NULL;
1098
1099	conn_state = drm_atomic_get_old_connector_state(state, connector);
1100	if (!conn_state)
1101		return NULL;
1102
1103	return conn_state->crtc;
1104}
1105
1106static
1107struct drm_crtc *analogix_dp_get_new_crtc(struct analogix_dp_device *dp,
1108					  struct drm_atomic_state *state)
1109{
1110	struct drm_encoder *encoder = dp->encoder;
1111	struct drm_connector *connector;
1112	struct drm_connector_state *conn_state;
1113
1114	connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
1115	if (!connector)
1116		return NULL;
1117
1118	conn_state = drm_atomic_get_new_connector_state(state, connector);
1119	if (!conn_state)
1120		return NULL;
1121
1122	return conn_state->crtc;
1123}
1124
1125static void analogix_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1126						 struct drm_atomic_state *old_state)
1127{
1128	struct analogix_dp_device *dp = to_dp(bridge);
1129	struct drm_crtc *crtc;
1130	struct drm_crtc_state *old_crtc_state;
1131
1132	crtc = analogix_dp_get_new_crtc(dp, old_state);
1133	if (!crtc)
1134		return;
1135
1136	old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc);
1137	/* Don't touch the panel if we're coming back from PSR */
1138	if (old_crtc_state && old_crtc_state->self_refresh_active)
1139		return;
1140
1141	drm_panel_prepare(dp->plat_data->panel);
1142}
1143
1144static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
1145{
1146	int ret;
1147
1148	pm_runtime_get_sync(dp->dev);
1149
1150	ret = analogix_dp_init_analog_func(dp);
1151	if (ret)
1152		return ret;
1153
1154	/*
1155	 * According to DP spec v1.3 chap 3.5.1.2 Link Training,
1156	 * We should first make sure the HPD signal is asserted high by device
1157	 * when we want to establish a link with it.
1158	 */
1159	ret = analogix_dp_detect_hpd(dp);
1160	if (ret) {
1161		DRM_ERROR("failed to get hpd single ret = %d\n", ret);
1162		goto out_dp_init;
1163	}
1164
1165	ret = analogix_dp_commit(dp);
1166	if (ret) {
1167		DRM_ERROR("dp commit error, ret = %d\n", ret);
1168		goto out_dp_init;
1169	}
1170
1171	enable_irq(dp->irq);
1172	return 0;
1173
1174out_dp_init:
1175	pm_runtime_put_sync(dp->dev);
1176
1177	return ret;
1178}
1179
1180static void analogix_dp_bridge_atomic_enable(struct drm_bridge *bridge,
1181					     struct drm_atomic_state *old_state)
1182{
1183	struct analogix_dp_device *dp = to_dp(bridge);
1184	struct drm_crtc *crtc;
1185	struct drm_crtc_state *old_crtc_state;
1186	int timeout_loop = 0;
1187	int ret;
1188
1189	crtc = analogix_dp_get_new_crtc(dp, old_state);
1190	if (!crtc)
1191		return;
1192
1193	old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc);
1194	/* Not a full enable, just disable PSR and continue */
1195	if (old_crtc_state && old_crtc_state->self_refresh_active) {
1196		ret = analogix_dp_disable_psr(dp);
1197		if (ret)
1198			DRM_ERROR("Failed to disable psr %d\n", ret);
1199		return;
1200	}
1201
1202	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1203		return;
1204
1205	while (timeout_loop < MAX_PLL_LOCK_LOOP) {
1206		if (analogix_dp_set_bridge(dp) == 0) {
1207			dp->dpms_mode = DRM_MODE_DPMS_ON;
1208			return;
1209		}
1210		dev_err(dp->dev, "failed to set bridge, retry: %d\n",
1211			timeout_loop);
1212		timeout_loop++;
1213		usleep_range(10, 11);
1214	}
1215	dev_err(dp->dev, "too many times retry set bridge, give it up\n");
1216}
1217
1218static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
1219{
1220	struct analogix_dp_device *dp = to_dp(bridge);
1221
1222	if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1223		return;
1224
1225	drm_panel_disable(dp->plat_data->panel);
1226
1227	disable_irq(dp->irq);
1228
1229	analogix_dp_set_analog_power_down(dp, POWER_ALL, 1);
1230
1231	pm_runtime_put_sync(dp->dev);
1232
1233	drm_panel_unprepare(dp->plat_data->panel);
1234
1235	dp->fast_train_enable = false;
1236	dp->psr_supported = false;
1237	dp->dpms_mode = DRM_MODE_DPMS_OFF;
1238}
1239
1240static void analogix_dp_bridge_atomic_disable(struct drm_bridge *bridge,
1241					      struct drm_atomic_state *old_state)
1242{
1243	struct analogix_dp_device *dp = to_dp(bridge);
1244	struct drm_crtc *old_crtc, *new_crtc;
1245	struct drm_crtc_state *old_crtc_state = NULL;
1246	struct drm_crtc_state *new_crtc_state = NULL;
1247	int ret;
1248
1249	new_crtc = analogix_dp_get_new_crtc(dp, old_state);
1250	if (!new_crtc)
1251		goto out;
1252
1253	new_crtc_state = drm_atomic_get_new_crtc_state(old_state, new_crtc);
1254	if (!new_crtc_state)
1255		goto out;
1256
1257	/* Don't do a full disable on PSR transitions */
1258	if (new_crtc_state->self_refresh_active)
1259		return;
1260
1261out:
1262	old_crtc = analogix_dp_get_old_crtc(dp, old_state);
1263	if (old_crtc) {
1264		old_crtc_state = drm_atomic_get_old_crtc_state(old_state,
1265							       old_crtc);
1266
1267		/* When moving from PSR to fully disabled, exit PSR first. */
1268		if (old_crtc_state && old_crtc_state->self_refresh_active) {
1269			ret = analogix_dp_disable_psr(dp);
1270			if (ret)
1271				DRM_ERROR("Failed to disable psr (%d)\n", ret);
1272		}
1273	}
1274
1275	analogix_dp_bridge_disable(bridge);
1276}
1277
1278static void analogix_dp_bridge_atomic_post_disable(struct drm_bridge *bridge,
1279						   struct drm_atomic_state *old_state)
1280{
1281	struct analogix_dp_device *dp = to_dp(bridge);
1282	struct drm_crtc *crtc;
1283	struct drm_crtc_state *new_crtc_state;
1284	int ret;
1285
1286	crtc = analogix_dp_get_new_crtc(dp, old_state);
1287	if (!crtc)
1288		return;
1289
1290	new_crtc_state = drm_atomic_get_new_crtc_state(old_state, crtc);
1291	if (!new_crtc_state || !new_crtc_state->self_refresh_active)
1292		return;
1293
1294	ret = analogix_dp_enable_psr(dp);
1295	if (ret)
1296		DRM_ERROR("Failed to enable psr (%d)\n", ret);
1297}
1298
1299static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
1300				const struct drm_display_mode *orig_mode,
1301				const struct drm_display_mode *mode)
1302{
1303	struct analogix_dp_device *dp = to_dp(bridge);
1304	struct drm_display_info *display_info = &dp->connector.display_info;
1305	struct video_info *video = &dp->video_info;
1306	struct device_node *dp_node = dp->dev->of_node;
1307	int vic;
1308
1309	/* Input video interlaces & hsync pol & vsync pol */
1310	video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1311	video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
1312	video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
1313
1314	/* Input video dynamic_range & colorimetry */
1315	vic = drm_match_cea_mode(mode);
1316	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
1317	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
1318		video->dynamic_range = CEA;
1319		video->ycbcr_coeff = COLOR_YCBCR601;
1320	} else if (vic) {
1321		video->dynamic_range = CEA;
1322		video->ycbcr_coeff = COLOR_YCBCR709;
1323	} else {
1324		video->dynamic_range = VESA;
1325		video->ycbcr_coeff = COLOR_YCBCR709;
1326	}
1327
1328	/* Input vide bpc and color_formats */
1329	switch (display_info->bpc) {
1330	case 12:
1331		video->color_depth = COLOR_12;
1332		break;
1333	case 10:
1334		video->color_depth = COLOR_10;
1335		break;
1336	case 8:
1337		video->color_depth = COLOR_8;
1338		break;
1339	case 6:
1340		video->color_depth = COLOR_6;
1341		break;
1342	default:
1343		video->color_depth = COLOR_8;
1344		break;
1345	}
1346	if (display_info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
1347		video->color_space = COLOR_YCBCR444;
1348	else if (display_info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
1349		video->color_space = COLOR_YCBCR422;
1350	else
1351		video->color_space = COLOR_RGB;
1352
1353	/*
1354	 * NOTE: those property parsing code is used for providing backward
1355	 * compatibility for samsung platform.
1356	 * Due to we used the "of_property_read_u32" interfaces, when this
1357	 * property isn't present, the "video_info" can keep the original
1358	 * values and wouldn't be modified.
1359	 */
1360	of_property_read_u32(dp_node, "samsung,color-space",
1361			     &video->color_space);
1362	of_property_read_u32(dp_node, "samsung,dynamic-range",
1363			     &video->dynamic_range);
1364	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1365			     &video->ycbcr_coeff);
1366	of_property_read_u32(dp_node, "samsung,color-depth",
1367			     &video->color_depth);
1368	if (of_property_read_bool(dp_node, "hsync-active-high"))
1369		video->h_sync_polarity = true;
1370	if (of_property_read_bool(dp_node, "vsync-active-high"))
1371		video->v_sync_polarity = true;
1372	if (of_property_read_bool(dp_node, "interlaced"))
1373		video->interlaced = true;
1374}
1375
1376static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
1377	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1378	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1379	.atomic_reset = drm_atomic_helper_bridge_reset,
1380	.atomic_pre_enable = analogix_dp_bridge_atomic_pre_enable,
1381	.atomic_enable = analogix_dp_bridge_atomic_enable,
1382	.atomic_disable = analogix_dp_bridge_atomic_disable,
1383	.atomic_post_disable = analogix_dp_bridge_atomic_post_disable,
1384	.mode_set = analogix_dp_bridge_mode_set,
1385	.attach = analogix_dp_bridge_attach,
1386};
1387
1388static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
1389{
1390	struct device_node *dp_node = dp->dev->of_node;
1391	struct video_info *video_info = &dp->video_info;
1392
1393	switch (dp->plat_data->dev_type) {
1394	case RK3288_DP:
1395	case RK3399_EDP:
1396		/*
1397		 * Like Rk3288 DisplayPort TRM indicate that "Main link
1398		 * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
1399		 */
1400		video_info->max_link_rate = 0x0A;
1401		video_info->max_lane_count = 0x04;
1402		break;
1403	case RK3588_EDP:
1404		video_info->max_link_rate = 0x14;
1405		video_info->max_lane_count = 0x04;
1406		break;
1407	case EXYNOS_DP:
1408		/*
1409		 * NOTE: those property parseing code is used for
1410		 * providing backward compatibility for samsung platform.
1411		 */
1412		of_property_read_u32(dp_node, "samsung,link-rate",
1413				     &video_info->max_link_rate);
1414		of_property_read_u32(dp_node, "samsung,lane-count",
1415				     &video_info->max_lane_count);
1416		break;
1417	}
1418
1419	return 0;
1420}
1421
1422static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux,
1423				       struct drm_dp_aux_msg *msg)
1424{
1425	struct analogix_dp_device *dp = to_dp(aux);
1426	int ret;
1427
1428	pm_runtime_get_sync(dp->dev);
1429
1430	ret = analogix_dp_detect_hpd(dp);
1431	if (ret)
1432		goto out;
1433
1434	ret = analogix_dp_transfer(dp, msg);
1435out:
1436	pm_runtime_mark_last_busy(dp->dev);
1437	pm_runtime_put_autosuspend(dp->dev);
1438
1439	return ret;
1440}
1441
1442static int analogix_dpaux_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
1443{
1444	struct analogix_dp_device *dp = to_dp(aux);
1445	int val;
1446	int ret;
1447
1448	if (dp->force_hpd)
1449		return 0;
1450
1451	pm_runtime_get_sync(dp->dev);
1452
1453	ret = readx_poll_timeout(analogix_dp_get_plug_in_status, dp, val, !val,
1454				 wait_us / 100, wait_us);
1455
1456	pm_runtime_mark_last_busy(dp->dev);
1457	pm_runtime_put_autosuspend(dp->dev);
1458
1459	return ret;
1460}
1461
1462struct analogix_dp_device *
1463analogix_dp_probe(struct device *dev, struct analogix_dp_plat_data *plat_data)
1464{
1465	struct platform_device *pdev = to_platform_device(dev);
1466	struct analogix_dp_device *dp;
1467	unsigned int irq_flags;
1468	int ret;
1469
1470	if (!plat_data) {
1471		dev_err(dev, "Invalided input plat_data\n");
1472		return ERR_PTR(-EINVAL);
1473	}
1474
1475	dp = devm_drm_bridge_alloc(dev, struct analogix_dp_device, bridge,
1476				   &analogix_dp_bridge_funcs);
1477	if (IS_ERR(dp))
1478		return ERR_CAST(dp);
1479
1480	dp->dev = &pdev->dev;
1481	dp->dpms_mode = DRM_MODE_DPMS_OFF;
1482
1483	/*
1484	 * platform dp driver need containor_of the plat_data to get
1485	 * the driver private data, so we need to store the point of
1486	 * plat_data, not the context of plat_data.
1487	 */
1488	dp->plat_data = plat_data;
1489
1490	ret = analogix_dp_dt_parse_pdata(dp);
1491	if (ret)
1492		return ERR_PTR(ret);
1493
1494	dp->phy = devm_phy_get(dp->dev, "dp");
1495	if (IS_ERR(dp->phy)) {
1496		dev_err(dp->dev, "no DP phy configured\n");
1497		ret = PTR_ERR(dp->phy);
1498		if (ret) {
1499			/*
1500			 * phy itself is not enabled, so we can move forward
1501			 * assigning NULL to phy pointer.
1502			 */
1503			if (ret == -ENOSYS || ret == -ENODEV)
1504				dp->phy = NULL;
1505			else
1506				return ERR_PTR(ret);
1507		}
1508	}
1509
1510	dp->clock = devm_clk_get(&pdev->dev, "dp");
1511	if (IS_ERR(dp->clock)) {
1512		dev_err(&pdev->dev, "failed to get clock\n");
1513		return ERR_CAST(dp->clock);
1514	}
1515
1516	dp->reg_base = devm_platform_ioremap_resource(pdev, 0);
1517	if (IS_ERR(dp->reg_base))
1518		return ERR_CAST(dp->reg_base);
1519
1520	dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd");
1521
1522	/* Try two different names */
1523	dp->hpd_gpiod = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
1524	if (!dp->hpd_gpiod)
1525		dp->hpd_gpiod = devm_gpiod_get_optional(dev, "samsung,hpd",
1526							GPIOD_IN);
1527	if (IS_ERR(dp->hpd_gpiod)) {
1528		dev_err(dev, "error getting HDP GPIO: %ld\n",
1529			PTR_ERR(dp->hpd_gpiod));
1530		return ERR_CAST(dp->hpd_gpiod);
1531	}
1532
1533	if (dp->hpd_gpiod) {
1534		/*
1535		 * Set up the hotplug GPIO from the device tree as an interrupt.
1536		 * Simply specifying a different interrupt in the device tree
1537		 * doesn't work since we handle hotplug rather differently when
1538		 * using a GPIO.  We also need the actual GPIO specifier so
1539		 * that we can get the current state of the GPIO.
1540		 */
1541		dp->irq = gpiod_to_irq(dp->hpd_gpiod);
1542		irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_NO_AUTOEN;
1543	} else {
1544		dp->irq = platform_get_irq(pdev, 0);
1545		irq_flags = IRQF_NO_AUTOEN;
1546	}
1547
1548	if (dp->irq == -ENXIO) {
1549		dev_err(&pdev->dev, "failed to get irq\n");
1550		return ERR_PTR(-ENODEV);
1551	}
1552
1553	ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
1554					analogix_dp_hardirq,
1555					analogix_dp_irq_thread,
1556					irq_flags, "analogix-dp", dp);
1557	if (ret) {
1558		dev_err(&pdev->dev, "failed to request irq\n");
1559		return ERR_PTR(ret);
1560	}
1561
1562	dp->aux.name = "DP-AUX";
1563	dp->aux.transfer = analogix_dpaux_transfer;
1564	dp->aux.wait_hpd_asserted = analogix_dpaux_wait_hpd_asserted;
1565	dp->aux.dev = dp->dev;
1566	drm_dp_aux_init(&dp->aux);
1567
1568	pm_runtime_use_autosuspend(dp->dev);
1569	pm_runtime_set_autosuspend_delay(dp->dev, 100);
1570	ret = devm_pm_runtime_enable(dp->dev);
1571	if (ret)
1572		return ERR_PTR(ret);
1573
1574	return dp;
1575}
1576EXPORT_SYMBOL_GPL(analogix_dp_probe);
1577
1578int analogix_dp_suspend(struct analogix_dp_device *dp)
1579{
1580	phy_power_off(dp->phy);
1581
1582	if (dp->plat_data->power_off)
1583		dp->plat_data->power_off(dp->plat_data);
1584
1585	clk_disable_unprepare(dp->clock);
1586
1587	return 0;
1588}
1589EXPORT_SYMBOL_GPL(analogix_dp_suspend);
1590
1591int analogix_dp_resume(struct analogix_dp_device *dp)
1592{
1593	int ret;
1594
1595	ret = clk_prepare_enable(dp->clock);
1596	if (ret < 0) {
1597		DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1598		return ret;
1599	}
1600
1601	if (dp->plat_data->power_on)
1602		dp->plat_data->power_on(dp->plat_data);
1603
1604	phy_set_mode(dp->phy, PHY_MODE_DP);
1605	phy_power_on(dp->phy);
1606
1607	analogix_dp_init_dp(dp);
1608
1609	return 0;
1610}
1611EXPORT_SYMBOL_GPL(analogix_dp_resume);
1612
1613int analogix_dp_bind(struct analogix_dp_device *dp, struct drm_device *drm_dev)
1614{
1615	int ret;
1616
1617	dp->drm_dev = drm_dev;
1618	dp->encoder = dp->plat_data->encoder;
1619
1620	dp->aux.drm_dev = drm_dev;
1621
1622	ret = drm_dp_aux_register(&dp->aux);
1623	if (ret) {
1624		DRM_ERROR("failed to register AUX (%d)\n", ret);
1625		return ret;
1626	}
1627
1628	ret = drm_bridge_attach(dp->encoder, &dp->bridge, NULL, 0);
1629	if (ret) {
1630		DRM_ERROR("failed to create bridge (%d)\n", ret);
1631		goto err_unregister_aux;
1632	}
1633
1634	return 0;
1635
1636err_unregister_aux:
1637	drm_dp_aux_unregister(&dp->aux);
1638
1639	return ret;
1640}
1641EXPORT_SYMBOL_GPL(analogix_dp_bind);
1642
1643void analogix_dp_unbind(struct analogix_dp_device *dp)
1644{
1645	analogix_dp_bridge_disable(&dp->bridge);
1646	dp->connector.funcs->destroy(&dp->connector);
1647
1648	drm_panel_unprepare(dp->plat_data->panel);
1649
1650	drm_dp_aux_unregister(&dp->aux);
1651}
1652EXPORT_SYMBOL_GPL(analogix_dp_unbind);
1653
1654int analogix_dp_start_crc(struct drm_connector *connector)
1655{
1656	struct analogix_dp_device *dp = to_dp(connector);
1657
1658	if (!connector->state->crtc) {
1659		DRM_ERROR("Connector %s doesn't currently have a CRTC.\n",
1660			  connector->name);
1661		return -EINVAL;
1662	}
1663
1664	return drm_dp_start_crc(&dp->aux, connector->state->crtc);
1665}
1666EXPORT_SYMBOL_GPL(analogix_dp_start_crc);
1667
1668int analogix_dp_stop_crc(struct drm_connector *connector)
1669{
1670	struct analogix_dp_device *dp = to_dp(connector);
1671
1672	return drm_dp_stop_crc(&dp->aux);
1673}
1674EXPORT_SYMBOL_GPL(analogix_dp_stop_crc);
1675
1676struct analogix_dp_plat_data *analogix_dp_aux_to_plat_data(struct drm_dp_aux *aux)
1677{
1678	struct analogix_dp_device *dp = to_dp(aux);
1679
1680	return dp->plat_data;
1681}
1682EXPORT_SYMBOL_GPL(analogix_dp_aux_to_plat_data);
1683
1684struct drm_dp_aux *analogix_dp_get_aux(struct analogix_dp_device *dp)
1685{
1686	return &dp->aux;
1687}
1688EXPORT_SYMBOL_GPL(analogix_dp_get_aux);
1689
1690MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1691MODULE_DESCRIPTION("Analogix DP Core Driver");
1692MODULE_LICENSE("GPL v2");