analogix-anx78xx.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright(c) 2016, Analogix Semiconductor.
   4 *
   5 * Based on anx7808 driver obtained from chromeos with copyright:
   6 * Copyright(c) 2013, Google Inc.
   7 */
   8#include <linux/delay.h>
   9#include <linux/err.h>
  10#include <linux/gpio/consumer.h>
  11#include <linux/i2c.h>
  12#include <linux/interrupt.h>
  13#include <linux/kernel.h>
  14#include <linux/module.h>
  15#include <linux/of_irq.h>
  16#include <linux/of_platform.h>
  17#include <linux/regmap.h>
  18#include <linux/regulator/consumer.h>
  19#include <linux/types.h>
  20
  21#include <drm/display/drm_dp_helper.h>
  22#include <drm/drm_atomic_helper.h>
  23#include <drm/drm_bridge.h>
  24#include <drm/drm_crtc.h>
  25#include <drm/drm_edid.h>
  26#include <drm/drm_print.h>
  27#include <drm/drm_probe_helper.h>
  28
  29#include "analogix-anx78xx.h"
  30
  31#define I2C_NUM_ADDRESSES	5
  32#define I2C_IDX_TX_P0		0
  33#define I2C_IDX_TX_P1		1
  34#define I2C_IDX_TX_P2		2
  35#define I2C_IDX_RX_P0		3
  36#define I2C_IDX_RX_P1		4
  37
  38#define XTAL_CLK		270 /* 27M */
  39
  40static const u8 anx7808_i2c_addresses[] = {
  41	[I2C_IDX_TX_P0] = 0x78,
  42	[I2C_IDX_TX_P1] = 0x7a,
  43	[I2C_IDX_TX_P2] = 0x72,
  44	[I2C_IDX_RX_P0] = 0x7e,
  45	[I2C_IDX_RX_P1] = 0x80,
  46};
  47
  48static const u8 anx781x_i2c_addresses[] = {
  49	[I2C_IDX_TX_P0] = 0x70,
  50	[I2C_IDX_TX_P1] = 0x7a,
  51	[I2C_IDX_TX_P2] = 0x72,
  52	[I2C_IDX_RX_P0] = 0x7e,
  53	[I2C_IDX_RX_P1] = 0x80,
  54};
  55
  56struct anx78xx_platform_data {
  57	struct regulator *dvdd10;
  58	struct gpio_desc *gpiod_hpd;
  59	struct gpio_desc *gpiod_pd;
  60	struct gpio_desc *gpiod_reset;
  61
  62	int hpd_irq;
  63	int intp_irq;
  64};
  65
  66struct anx78xx {
  67	struct drm_dp_aux aux;
  68	struct drm_bridge bridge;
  69	struct i2c_client *client;
  70	const struct drm_edid *drm_edid;
  71	struct drm_connector connector;
  72	struct anx78xx_platform_data pdata;
  73	struct mutex lock;
  74
  75	/*
  76	 * I2C Slave addresses of ANX7814 are mapped as TX_P0, TX_P1, TX_P2,
  77	 * RX_P0 and RX_P1.
  78	 */
  79	struct i2c_client *i2c_dummy[I2C_NUM_ADDRESSES];
  80	struct regmap *map[I2C_NUM_ADDRESSES];
  81
  82	u16 chipid;
  83	u8 dpcd[DP_RECEIVER_CAP_SIZE];
  84
  85	bool powered;
  86};
  87
  88static inline struct anx78xx *connector_to_anx78xx(struct drm_connector *c)
  89{
  90	return container_of(c, struct anx78xx, connector);
  91}
  92
  93static inline struct anx78xx *bridge_to_anx78xx(struct drm_bridge *bridge)
  94{
  95	return container_of(bridge, struct anx78xx, bridge);
  96}
  97
  98static int anx78xx_set_bits(struct regmap *map, u8 reg, u8 mask)
  99{
 100	return regmap_update_bits(map, reg, mask, mask);
 101}
 102
 103static int anx78xx_clear_bits(struct regmap *map, u8 reg, u8 mask)
 104{
 105	return regmap_update_bits(map, reg, mask, 0);
 106}
 107
 108static ssize_t anx78xx_aux_transfer(struct drm_dp_aux *aux,
 109				    struct drm_dp_aux_msg *msg)
 110{
 111	struct anx78xx *anx78xx = container_of(aux, struct anx78xx, aux);
 112	return anx_dp_aux_transfer(anx78xx->map[I2C_IDX_TX_P0], msg);
 113}
 114
 115static int anx78xx_set_hpd(struct anx78xx *anx78xx)
 116{
 117	int err;
 118
 119	err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
 120				 SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
 121	if (err)
 122		return err;
 123
 124	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
 125			       SP_HPD_OUT);
 126	if (err)
 127		return err;
 128
 129	return 0;
 130}
 131
 132static int anx78xx_clear_hpd(struct anx78xx *anx78xx)
 133{
 134	int err;
 135
 136	err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
 137				 SP_HPD_OUT);
 138	if (err)
 139		return err;
 140
 141	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
 142			       SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
 143	if (err)
 144		return err;
 145
 146	return 0;
 147}
 148
 149static const struct reg_sequence tmds_phy_initialization[] = {
 150	{ SP_TMDS_CTRL_BASE +  1, 0x90 },
 151	{ SP_TMDS_CTRL_BASE +  2, 0xa9 },
 152	{ SP_TMDS_CTRL_BASE +  6, 0x92 },
 153	{ SP_TMDS_CTRL_BASE +  7, 0x80 },
 154	{ SP_TMDS_CTRL_BASE + 20, 0xf2 },
 155	{ SP_TMDS_CTRL_BASE + 22, 0xc4 },
 156	{ SP_TMDS_CTRL_BASE + 23, 0x18 },
 157};
 158
 159static int anx78xx_rx_initialization(struct anx78xx *anx78xx)
 160{
 161	int err;
 162
 163	err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
 164			   SP_AUD_MUTE | SP_VID_MUTE);
 165	if (err)
 166		return err;
 167
 168	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_CHIP_CTRL_REG,
 169			       SP_MAN_HDMI5V_DET | SP_PLLLOCK_CKDT_EN |
 170			       SP_DIGITAL_CKDT_EN);
 171	if (err)
 172		return err;
 173
 174	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
 175			       SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
 176			       SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
 177	if (err)
 178		return err;
 179
 180	err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
 181				 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
 182				 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
 183	if (err)
 184		return err;
 185
 186	/* Sync detect change, GP set mute */
 187	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
 188			       SP_AUD_EXCEPTION_ENABLE_BASE + 1, BIT(5) |
 189			       BIT(6));
 190	if (err)
 191		return err;
 192
 193	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
 194			       SP_AUD_EXCEPTION_ENABLE_BASE + 3,
 195			       SP_AEC_EN21);
 196	if (err)
 197		return err;
 198
 199	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_AUDVID_CTRL_REG,
 200			       SP_AVC_EN | SP_AAC_OE | SP_AAC_EN);
 201	if (err)
 202		return err;
 203
 204	err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
 205				 SP_SYSTEM_POWER_DOWN1_REG, SP_PWDN_CTRL);
 206	if (err)
 207		return err;
 208
 209	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
 210			       SP_VID_DATA_RANGE_CTRL_REG, SP_R2Y_INPUT_LIMIT);
 211	if (err)
 212		return err;
 213
 214	/* Enable DDC stretch */
 215	err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
 216			   SP_DP_EXTRA_I2C_DEV_ADDR_REG, SP_I2C_EXTRA_ADDR);
 217	if (err)
 218		return err;
 219
 220	/* TMDS phy initialization */
 221	err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_RX_P0],
 222				     tmds_phy_initialization,
 223				     ARRAY_SIZE(tmds_phy_initialization));
 224	if (err)
 225		return err;
 226
 227	err = anx78xx_clear_hpd(anx78xx);
 228	if (err)
 229		return err;
 230
 231	return 0;
 232}
 233
 234static const u8 dp_tx_output_precise_tune_bits[20] = {
 235	0x01, 0x03, 0x07, 0x7f, 0x71, 0x6b, 0x7f,
 236	0x73, 0x7f, 0x7f, 0x00, 0x00, 0x00, 0x00,
 237	0x0c, 0x42, 0x1e, 0x3e, 0x72, 0x7e,
 238};
 239
 240static int anx78xx_link_phy_initialization(struct anx78xx *anx78xx)
 241{
 242	int err;
 243
 244	/*
 245	 * REVISIT : It is writing to a RESERVED bits in Analog Control 0
 246	 * register.
 247	 */
 248	err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_ANALOG_CTRL0_REG,
 249			   0x02);
 250	if (err)
 251		return err;
 252
 253	/*
 254	 * Write DP TX output emphasis precise tune bits.
 255	 */
 256	err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P1],
 257				SP_DP_TX_LT_CTRL0_REG,
 258				dp_tx_output_precise_tune_bits,
 259				ARRAY_SIZE(dp_tx_output_precise_tune_bits));
 260
 261	if (err)
 262		return err;
 263
 264	return 0;
 265}
 266
 267static int anx78xx_xtal_clk_sel(struct anx78xx *anx78xx)
 268{
 269	unsigned int value;
 270	int err;
 271
 272	err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P2],
 273				 SP_ANALOG_DEBUG2_REG,
 274				 SP_XTAL_FRQ | SP_FORCE_SW_OFF_BYPASS,
 275				 SP_XTAL_FRQ_27M);
 276	if (err)
 277		return err;
 278
 279	err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL3_REG,
 280			   XTAL_CLK & SP_WAIT_COUNTER_7_0_MASK);
 281	if (err)
 282		return err;
 283
 284	err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL4_REG,
 285			   ((XTAL_CLK & 0xff00) >> 2) | (XTAL_CLK / 10));
 286	if (err)
 287		return err;
 288
 289	err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
 290			   SP_I2C_GEN_10US_TIMER0_REG, XTAL_CLK & 0xff);
 291	if (err)
 292		return err;
 293
 294	err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
 295			   SP_I2C_GEN_10US_TIMER1_REG,
 296			   (XTAL_CLK & 0xff00) >> 8);
 297	if (err)
 298		return err;
 299
 300	err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_MISC_CTRL_REG,
 301			   XTAL_CLK / 10 - 1);
 302	if (err)
 303		return err;
 304
 305	err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
 306			  SP_HDMI_US_TIMER_CTRL_REG,
 307			  &value);
 308	if (err)
 309		return err;
 310
 311	err = regmap_write(anx78xx->map[I2C_IDX_RX_P0],
 312			   SP_HDMI_US_TIMER_CTRL_REG,
 313			   (value & SP_MS_TIMER_MARGIN_10_8_MASK) |
 314			   ((((XTAL_CLK / 10) >> 1) - 2) << 3));
 315	if (err)
 316		return err;
 317
 318	return 0;
 319}
 320
 321static const struct reg_sequence otp_key_protect[] = {
 322	{ SP_OTP_KEY_PROTECT1_REG, SP_OTP_PSW1 },
 323	{ SP_OTP_KEY_PROTECT2_REG, SP_OTP_PSW2 },
 324	{ SP_OTP_KEY_PROTECT3_REG, SP_OTP_PSW3 },
 325};
 326
 327static int anx78xx_tx_initialization(struct anx78xx *anx78xx)
 328{
 329	int err;
 330
 331	/* Set terminal resistor to 50 ohm */
 332	err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,
 333			   0x30);
 334	if (err)
 335		return err;
 336
 337	/* Enable aux double diff output */
 338	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
 339			       SP_DP_AUX_CH_CTRL2_REG, 0x08);
 340	if (err)
 341		return err;
 342
 343	err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
 344				 SP_DP_HDCP_CTRL_REG, SP_AUTO_EN |
 345				 SP_AUTO_START);
 346	if (err)
 347		return err;
 348
 349	err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_TX_P0],
 350				     otp_key_protect,
 351				     ARRAY_SIZE(otp_key_protect));
 352	if (err)
 353		return err;
 354
 355	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
 356			       SP_HDCP_KEY_COMMAND_REG, SP_DISABLE_SYNC_HDCP);
 357	if (err)
 358		return err;
 359
 360	err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL8_REG,
 361			   SP_VID_VRES_TH);
 362	if (err)
 363		return err;
 364
 365	/*
 366	 * DP HDCP auto authentication wait timer (when downstream starts to
 367	 * auth, DP side will wait for this period then do auth automatically)
 368	 */
 369	err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_HDCP_AUTO_TIMER_REG,
 370			   0x00);
 371	if (err)
 372		return err;
 373
 374	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
 375			       SP_DP_HDCP_CTRL_REG, SP_LINK_POLLING);
 376	if (err)
 377		return err;
 378
 379	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
 380			       SP_DP_LINK_DEBUG_CTRL_REG, SP_M_VID_DEBUG);
 381	if (err)
 382		return err;
 383
 384	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2],
 385			       SP_ANALOG_DEBUG2_REG, SP_POWERON_TIME_1P5MS);
 386	if (err)
 387		return err;
 388
 389	err = anx78xx_xtal_clk_sel(anx78xx);
 390	if (err)
 391		return err;
 392
 393	err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_DEFER_CTRL_REG,
 394			   SP_DEFER_CTRL_EN | 0x0c);
 395	if (err)
 396		return err;
 397
 398	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
 399			       SP_DP_POLLING_CTRL_REG,
 400			       SP_AUTO_POLLING_DISABLE);
 401	if (err)
 402		return err;
 403
 404	/*
 405	 * Short the link integrity check timer to speed up bstatus
 406	 * polling for HDCP CTS item 1A-07
 407	 */
 408	err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
 409			   SP_HDCP_LINK_CHECK_TIMER_REG, 0x1d);
 410	if (err)
 411		return err;
 412
 413	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
 414			       SP_DP_MISC_CTRL_REG, SP_EQ_TRAINING_LOOP);
 415	if (err)
 416		return err;
 417
 418	/* Power down the main link by default */
 419	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
 420			       SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
 421	if (err)
 422		return err;
 423
 424	err = anx78xx_link_phy_initialization(anx78xx);
 425	if (err)
 426		return err;
 427
 428	/* Gen m_clk with downspreading */
 429	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
 430			       SP_DP_M_CALCULATION_CTRL_REG, SP_M_GEN_CLK_SEL);
 431	if (err)
 432		return err;
 433
 434	return 0;
 435}
 436
 437static int anx78xx_enable_interrupts(struct anx78xx *anx78xx)
 438{
 439	int err;
 440
 441	/*
 442	 * BIT0: INT pin assertion polarity: 1 = assert high
 443	 * BIT1: INT pin output type: 0 = push/pull
 444	 */
 445	err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_INT_CTRL_REG, 0x01);
 446	if (err)
 447		return err;
 448
 449	err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
 450			   SP_COMMON_INT_MASK4_REG, SP_HPD_LOST | SP_HPD_PLUG);
 451	if (err)
 452		return err;
 453
 454	err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_MASK1_REG,
 455			   SP_TRAINING_FINISH);
 456	if (err)
 457		return err;
 458
 459	err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_MASK1_REG,
 460			   SP_CKDT_CHG | SP_SCDT_CHG);
 461	if (err)
 462		return err;
 463
 464	return 0;
 465}
 466
 467static void anx78xx_poweron(struct anx78xx *anx78xx)
 468{
 469	struct anx78xx_platform_data *pdata = &anx78xx->pdata;
 470	int err;
 471
 472	if (WARN_ON(anx78xx->powered))
 473		return;
 474
 475	if (pdata->dvdd10) {
 476		err = regulator_enable(pdata->dvdd10);
 477		if (err) {
 478			DRM_ERROR("Failed to enable DVDD10 regulator: %d\n",
 479				  err);
 480			return;
 481		}
 482
 483		usleep_range(1000, 2000);
 484	}
 485
 486	gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
 487	usleep_range(1000, 2000);
 488
 489	gpiod_set_value_cansleep(pdata->gpiod_pd, 0);
 490	usleep_range(1000, 2000);
 491
 492	gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
 493
 494	/* Power on registers module */
 495	anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
 496			 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
 497	anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
 498			   SP_REGISTER_PD | SP_TOTAL_PD);
 499
 500	anx78xx->powered = true;
 501}
 502
 503static void anx78xx_poweroff(struct anx78xx *anx78xx)
 504{
 505	struct anx78xx_platform_data *pdata = &anx78xx->pdata;
 506	int err;
 507
 508	if (WARN_ON(!anx78xx->powered))
 509		return;
 510
 511	gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
 512	usleep_range(1000, 2000);
 513
 514	gpiod_set_value_cansleep(pdata->gpiod_pd, 1);
 515	usleep_range(1000, 2000);
 516
 517	if (pdata->dvdd10) {
 518		err = regulator_disable(pdata->dvdd10);
 519		if (err) {
 520			DRM_ERROR("Failed to disable DVDD10 regulator: %d\n",
 521				  err);
 522			return;
 523		}
 524
 525		usleep_range(1000, 2000);
 526	}
 527
 528	anx78xx->powered = false;
 529}
 530
 531static int anx78xx_start(struct anx78xx *anx78xx)
 532{
 533	int err;
 534
 535	/* Power on all modules */
 536	err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
 537				 SP_POWERDOWN_CTRL_REG,
 538				 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD |
 539				 SP_LINK_PD);
 540
 541	err = anx78xx_enable_interrupts(anx78xx);
 542	if (err) {
 543		DRM_ERROR("Failed to enable interrupts: %d\n", err);
 544		goto err_poweroff;
 545	}
 546
 547	err = anx78xx_rx_initialization(anx78xx);
 548	if (err) {
 549		DRM_ERROR("Failed receiver initialization: %d\n", err);
 550		goto err_poweroff;
 551	}
 552
 553	err = anx78xx_tx_initialization(anx78xx);
 554	if (err) {
 555		DRM_ERROR("Failed transmitter initialization: %d\n", err);
 556		goto err_poweroff;
 557	}
 558
 559	/*
 560	 * This delay seems to help keep the hardware in a good state. Without
 561	 * it, there are times where it fails silently.
 562	 */
 563	usleep_range(10000, 15000);
 564
 565	return 0;
 566
 567err_poweroff:
 568	DRM_ERROR("Failed SlimPort transmitter initialization: %d\n", err);
 569	anx78xx_poweroff(anx78xx);
 570
 571	return err;
 572}
 573
 574static int anx78xx_init_pdata(struct anx78xx *anx78xx)
 575{
 576	struct anx78xx_platform_data *pdata = &anx78xx->pdata;
 577	struct device *dev = &anx78xx->client->dev;
 578
 579	/* 1.0V digital core power regulator  */
 580	pdata->dvdd10 = devm_regulator_get(dev, "dvdd10");
 581	if (IS_ERR(pdata->dvdd10)) {
 582		if (PTR_ERR(pdata->dvdd10) != -EPROBE_DEFER)
 583			DRM_ERROR("DVDD10 regulator not found\n");
 584
 585		return PTR_ERR(pdata->dvdd10);
 586	}
 587
 588	/* GPIO for HPD */
 589	pdata->gpiod_hpd = devm_gpiod_get(dev, "hpd", GPIOD_IN);
 590	if (IS_ERR(pdata->gpiod_hpd))
 591		return PTR_ERR(pdata->gpiod_hpd);
 592
 593	/* GPIO for chip power down */
 594	pdata->gpiod_pd = devm_gpiod_get(dev, "pd", GPIOD_OUT_HIGH);
 595	if (IS_ERR(pdata->gpiod_pd))
 596		return PTR_ERR(pdata->gpiod_pd);
 597
 598	/* GPIO for chip reset */
 599	pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
 600
 601	return PTR_ERR_OR_ZERO(pdata->gpiod_reset);
 602}
 603
 604static int anx78xx_dp_link_training(struct anx78xx *anx78xx)
 605{
 606	u8 dp_bw, dpcd[2];
 607	int err;
 608
 609	err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
 610			   0x0);
 611	if (err)
 612		return err;
 613
 614	err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
 615				 SP_POWERDOWN_CTRL_REG,
 616				 SP_TOTAL_PD);
 617	if (err)
 618		return err;
 619
 620	err = drm_dp_dpcd_readb(&anx78xx->aux, DP_MAX_LINK_RATE, &dp_bw);
 621	if (err < 0)
 622		return err;
 623
 624	switch (dp_bw) {
 625	case DP_LINK_BW_1_62:
 626	case DP_LINK_BW_2_7:
 627	case DP_LINK_BW_5_4:
 628		break;
 629
 630	default:
 631		DRM_DEBUG_KMS("DP bandwidth (%#02x) not supported\n", dp_bw);
 632		return -EINVAL;
 633	}
 634
 635	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
 636			       SP_VIDEO_MUTE);
 637	if (err)
 638		return err;
 639
 640	err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
 641				 SP_VID_CTRL1_REG, SP_VIDEO_EN);
 642	if (err)
 643		return err;
 644
 645	/* Get DPCD info */
 646	err = drm_dp_dpcd_read(&anx78xx->aux, DP_DPCD_REV,
 647			       &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE);
 648	if (err < 0) {
 649		DRM_ERROR("Failed to read DPCD: %d\n", err);
 650		return err;
 651	}
 652
 653	/* Clear channel x SERDES power down */
 654	err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
 655				 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
 656	if (err)
 657		return err;
 658
 659	drm_dp_link_power_up(&anx78xx->aux, anx78xx->dpcd[DP_DPCD_REV]);
 660
 661	/* Possibly enable downspread on the sink */
 662	err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
 663			   SP_DP_DOWNSPREAD_CTRL1_REG, 0);
 664	if (err)
 665		return err;
 666
 667	if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {
 668		DRM_DEBUG("Enable downspread on the sink\n");
 669		/* 4000PPM */
 670		err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
 671				   SP_DP_DOWNSPREAD_CTRL1_REG, 8);
 672		if (err)
 673			return err;
 674
 675		err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL,
 676					 DP_SPREAD_AMP_0_5);
 677		if (err < 0)
 678			return err;
 679	} else {
 680		err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL, 0);
 681		if (err < 0)
 682			return err;
 683	}
 684
 685	/* Set the lane count and the link rate on the sink */
 686	if (drm_dp_enhanced_frame_cap(anx78xx->dpcd))
 687		err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
 688				       SP_DP_SYSTEM_CTRL_BASE + 4,
 689				       SP_ENHANCED_MODE);
 690	else
 691		err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
 692					 SP_DP_SYSTEM_CTRL_BASE + 4,
 693					 SP_ENHANCED_MODE);
 694	if (err)
 695		return err;
 696
 697	err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
 698			   SP_DP_MAIN_LINK_BW_SET_REG,
 699			   anx78xx->dpcd[DP_MAX_LINK_RATE]);
 700	if (err)
 701		return err;
 702
 703	dpcd[1] = drm_dp_max_lane_count(anx78xx->dpcd);
 704
 705	if (drm_dp_enhanced_frame_cap(anx78xx->dpcd))
 706		dpcd[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 707
 708	err = drm_dp_dpcd_write(&anx78xx->aux, DP_LINK_BW_SET, dpcd,
 709				sizeof(dpcd));
 710	if (err < 0) {
 711		DRM_ERROR("Failed to configure link: %d\n", err);
 712		return err;
 713	}
 714
 715	/* Start training on the source */
 716	err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_LT_CTRL_REG,
 717			   SP_LT_EN);
 718	if (err)
 719		return err;
 720
 721	return 0;
 722}
 723
 724static int anx78xx_config_dp_output(struct anx78xx *anx78xx)
 725{
 726	int err;
 727
 728	err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
 729				 SP_VIDEO_MUTE);
 730	if (err)
 731		return err;
 732
 733	/* Enable DP output */
 734	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
 735			       SP_VIDEO_EN);
 736	if (err)
 737		return err;
 738
 739	return 0;
 740}
 741
 742static int anx78xx_send_video_infoframe(struct anx78xx *anx78xx,
 743					struct hdmi_avi_infoframe *frame)
 744{
 745	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
 746	int err;
 747
 748	err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));
 749	if (err < 0) {
 750		DRM_ERROR("Failed to pack AVI infoframe: %d\n", err);
 751		return err;
 752	}
 753
 754	err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
 755				 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
 756	if (err)
 757		return err;
 758
 759	err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P2],
 760				SP_INFOFRAME_AVI_DB1_REG, buffer,
 761				frame->length);
 762	if (err)
 763		return err;
 764
 765	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
 766			       SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_UD);
 767	if (err)
 768		return err;
 769
 770	err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
 771			       SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
 772	if (err)
 773		return err;
 774
 775	return 0;
 776}
 777
 778static int anx78xx_get_downstream_info(struct anx78xx *anx78xx)
 779{
 780	u8 value;
 781	int err;
 782
 783	err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SINK_COUNT, &value);
 784	if (err < 0) {
 785		DRM_ERROR("Get sink count failed %d\n", err);
 786		return err;
 787	}
 788
 789	if (!DP_GET_SINK_COUNT(value)) {
 790		DRM_ERROR("Downstream disconnected\n");
 791		return -EIO;
 792	}
 793
 794	return 0;
 795}
 796
 797static int anx78xx_get_modes(struct drm_connector *connector)
 798{
 799	struct anx78xx *anx78xx = connector_to_anx78xx(connector);
 800	int err, num_modes = 0;
 801
 802	if (WARN_ON(!anx78xx->powered))
 803		return 0;
 804
 805	if (anx78xx->drm_edid)
 806		return drm_edid_connector_add_modes(connector);
 807
 808	mutex_lock(&anx78xx->lock);
 809
 810	err = anx78xx_get_downstream_info(anx78xx);
 811	if (err) {
 812		DRM_ERROR("Failed to get downstream info: %d\n", err);
 813		goto unlock;
 814	}
 815
 816	anx78xx->drm_edid = drm_edid_read_ddc(connector, &anx78xx->aux.ddc);
 817
 818	err = drm_edid_connector_update(connector, anx78xx->drm_edid);
 819
 820	if (!anx78xx->drm_edid) {
 821		DRM_ERROR("Failed to read EDID\n");
 822		goto unlock;
 823	}
 824
 825	if (err) {
 826		DRM_ERROR("Failed to update EDID property: %d\n", err);
 827		goto unlock;
 828	}
 829
 830	num_modes = drm_edid_connector_add_modes(connector);
 831
 832unlock:
 833	mutex_unlock(&anx78xx->lock);
 834
 835	return num_modes;
 836}
 837
 838static const struct drm_connector_helper_funcs anx78xx_connector_helper_funcs = {
 839	.get_modes = anx78xx_get_modes,
 840};
 841
 842static enum drm_connector_status anx78xx_detect(struct drm_connector *connector,
 843						bool force)
 844{
 845	struct anx78xx *anx78xx = connector_to_anx78xx(connector);
 846
 847	if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
 848		return connector_status_disconnected;
 849
 850	return connector_status_connected;
 851}
 852
 853static const struct drm_connector_funcs anx78xx_connector_funcs = {
 854	.fill_modes = drm_helper_probe_single_connector_modes,
 855	.detect = anx78xx_detect,
 856	.destroy = drm_connector_cleanup,
 857	.reset = drm_atomic_helper_connector_reset,
 858	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 859	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 860};
 861
 862static int anx78xx_bridge_attach(struct drm_bridge *bridge,
 863				 struct drm_encoder *encoder,
 864				 enum drm_bridge_attach_flags flags)
 865{
 866	struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
 867	int err;
 868
 869	if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
 870		DRM_ERROR("Fix bridge driver to make connector optional!");
 871		return -EINVAL;
 872	}
 873
 874	/* Register aux channel */
 875	anx78xx->aux.name = "DP-AUX";
 876	anx78xx->aux.dev = &anx78xx->client->dev;
 877	anx78xx->aux.drm_dev = bridge->dev;
 878	anx78xx->aux.transfer = anx78xx_aux_transfer;
 879
 880	err = drm_dp_aux_register(&anx78xx->aux);
 881	if (err < 0) {
 882		DRM_ERROR("Failed to register aux channel: %d\n", err);
 883		return err;
 884	}
 885
 886	err = drm_connector_init(bridge->dev, &anx78xx->connector,
 887				 &anx78xx_connector_funcs,
 888				 DRM_MODE_CONNECTOR_DisplayPort);
 889	if (err) {
 890		DRM_ERROR("Failed to initialize connector: %d\n", err);
 891		goto aux_unregister;
 892	}
 893
 894	drm_connector_helper_add(&anx78xx->connector,
 895				 &anx78xx_connector_helper_funcs);
 896
 897	anx78xx->connector.polled = DRM_CONNECTOR_POLL_HPD;
 898
 899	err = drm_connector_attach_encoder(&anx78xx->connector,
 900					   encoder);
 901	if (err) {
 902		DRM_ERROR("Failed to link up connector to encoder: %d\n", err);
 903		goto connector_cleanup;
 904	}
 905
 906	err = drm_connector_register(&anx78xx->connector);
 907	if (err) {
 908		DRM_ERROR("Failed to register connector: %d\n", err);
 909		goto connector_cleanup;
 910	}
 911
 912	return 0;
 913connector_cleanup:
 914	drm_connector_cleanup(&anx78xx->connector);
 915aux_unregister:
 916	drm_dp_aux_unregister(&anx78xx->aux);
 917	return err;
 918}
 919
 920static void anx78xx_bridge_detach(struct drm_bridge *bridge)
 921{
 922	drm_dp_aux_unregister(&bridge_to_anx78xx(bridge)->aux);
 923}
 924
 925static enum drm_mode_status
 926anx78xx_bridge_mode_valid(struct drm_bridge *bridge,
 927			  const struct drm_display_info *info,
 928			  const struct drm_display_mode *mode)
 929{
 930	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 931		return MODE_NO_INTERLACE;
 932
 933	/* Max 1200p at 5.4 Ghz, one lane */
 934	if (mode->clock > 154000)
 935		return MODE_CLOCK_HIGH;
 936
 937	return MODE_OK;
 938}
 939
 940static void anx78xx_bridge_disable(struct drm_bridge *bridge)
 941{
 942	struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
 943
 944	/* Power off all modules except configuration registers access */
 945	anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
 946			 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
 947}
 948
 949static void anx78xx_bridge_mode_set(struct drm_bridge *bridge,
 950				const struct drm_display_mode *mode,
 951				const struct drm_display_mode *adjusted_mode)
 952{
 953	struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
 954	struct hdmi_avi_infoframe frame;
 955	int err;
 956
 957	if (WARN_ON(!anx78xx->powered))
 958		return;
 959
 960	mutex_lock(&anx78xx->lock);
 961
 962	err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
 963						       &anx78xx->connector,
 964						       adjusted_mode);
 965	if (err) {
 966		DRM_ERROR("Failed to setup AVI infoframe: %d\n", err);
 967		goto unlock;
 968	}
 969
 970	err = anx78xx_send_video_infoframe(anx78xx, &frame);
 971	if (err)
 972		DRM_ERROR("Failed to send AVI infoframe: %d\n", err);
 973
 974unlock:
 975	mutex_unlock(&anx78xx->lock);
 976}
 977
 978static void anx78xx_bridge_enable(struct drm_bridge *bridge)
 979{
 980	struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
 981	int err;
 982
 983	err = anx78xx_start(anx78xx);
 984	if (err) {
 985		DRM_ERROR("Failed to initialize: %d\n", err);
 986		return;
 987	}
 988
 989	err = anx78xx_set_hpd(anx78xx);
 990	if (err)
 991		DRM_ERROR("Failed to set HPD: %d\n", err);
 992}
 993
 994static const struct drm_bridge_funcs anx78xx_bridge_funcs = {
 995	.attach = anx78xx_bridge_attach,
 996	.detach = anx78xx_bridge_detach,
 997	.mode_valid = anx78xx_bridge_mode_valid,
 998	.disable = anx78xx_bridge_disable,
 999	.mode_set = anx78xx_bridge_mode_set,
1000	.enable = anx78xx_bridge_enable,
1001};
1002
1003static irqreturn_t anx78xx_hpd_threaded_handler(int irq, void *data)
1004{
1005	struct anx78xx *anx78xx = data;
1006	int err;
1007
1008	if (anx78xx->powered)
1009		return IRQ_HANDLED;
1010
1011	mutex_lock(&anx78xx->lock);
1012
1013	/* Cable is pulled, power on the chip */
1014	anx78xx_poweron(anx78xx);
1015
1016	err = anx78xx_enable_interrupts(anx78xx);
1017	if (err)
1018		DRM_ERROR("Failed to enable interrupts: %d\n", err);
1019
1020	mutex_unlock(&anx78xx->lock);
1021
1022	return IRQ_HANDLED;
1023}
1024
1025static int anx78xx_handle_dp_int_1(struct anx78xx *anx78xx, u8 irq)
1026{
1027	int err;
1028
1029	DRM_DEBUG_KMS("Handle DP interrupt 1: %02x\n", irq);
1030
1031	err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1032			   irq);
1033	if (err)
1034		return err;
1035
1036	if (irq & SP_TRAINING_FINISH) {
1037		DRM_DEBUG_KMS("IRQ: hardware link training finished\n");
1038		err = anx78xx_config_dp_output(anx78xx);
1039	}
1040
1041	return err;
1042}
1043
1044static bool anx78xx_handle_common_int_4(struct anx78xx *anx78xx, u8 irq)
1045{
1046	bool event = false;
1047	int err;
1048
1049	DRM_DEBUG_KMS("Handle common interrupt 4: %02x\n", irq);
1050
1051	err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
1052			   SP_COMMON_INT_STATUS4_REG, irq);
1053	if (err) {
1054		DRM_ERROR("Failed to write SP_COMMON_INT_STATUS4 %d\n", err);
1055		return event;
1056	}
1057
1058	if (irq & SP_HPD_LOST) {
1059		DRM_DEBUG_KMS("IRQ: Hot plug detect - cable is pulled out\n");
1060		event = true;
1061		anx78xx_poweroff(anx78xx);
1062		/* Free cached EDID */
1063		drm_edid_free(anx78xx->drm_edid);
1064		anx78xx->drm_edid = NULL;
1065	} else if (irq & SP_HPD_PLUG) {
1066		DRM_DEBUG_KMS("IRQ: Hot plug detect - cable plug\n");
1067		event = true;
1068	}
1069
1070	return event;
1071}
1072
1073static void anx78xx_handle_hdmi_int_1(struct anx78xx *anx78xx, u8 irq)
1074{
1075	unsigned int value;
1076	int err;
1077
1078	DRM_DEBUG_KMS("Handle HDMI interrupt 1: %02x\n", irq);
1079
1080	err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1081			   irq);
1082	if (err) {
1083		DRM_ERROR("Write HDMI int 1 failed: %d\n", err);
1084		return;
1085	}
1086
1087	if ((irq & SP_CKDT_CHG) || (irq & SP_SCDT_CHG)) {
1088		DRM_DEBUG_KMS("IRQ: HDMI input detected\n");
1089
1090		err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
1091				  SP_SYSTEM_STATUS_REG, &value);
1092		if (err) {
1093			DRM_ERROR("Read system status reg failed: %d\n", err);
1094			return;
1095		}
1096
1097		if (!(value & SP_TMDS_CLOCK_DET)) {
1098			DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI clock ***\n");
1099			return;
1100		}
1101
1102		if (!(value & SP_TMDS_DE_DET)) {
1103			DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI signal ***\n");
1104			return;
1105		}
1106
1107		err = anx78xx_dp_link_training(anx78xx);
1108		if (err)
1109			DRM_ERROR("Failed to start link training: %d\n", err);
1110	}
1111}
1112
1113static irqreturn_t anx78xx_intp_threaded_handler(int unused, void *data)
1114{
1115	struct anx78xx *anx78xx = data;
1116	bool event = false;
1117	unsigned int irq;
1118	int err;
1119
1120	mutex_lock(&anx78xx->lock);
1121
1122	err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1123			  &irq);
1124	if (err) {
1125		DRM_ERROR("Failed to read DP interrupt 1 status: %d\n", err);
1126		goto unlock;
1127	}
1128
1129	if (irq)
1130		anx78xx_handle_dp_int_1(anx78xx, irq);
1131
1132	err = regmap_read(anx78xx->map[I2C_IDX_TX_P2],
1133			  SP_COMMON_INT_STATUS4_REG, &irq);
1134	if (err) {
1135		DRM_ERROR("Failed to read common interrupt 4 status: %d\n",
1136			  err);
1137		goto unlock;
1138	}
1139
1140	if (irq)
1141		event = anx78xx_handle_common_int_4(anx78xx, irq);
1142
1143	/* Make sure we are still powered after handle HPD events */
1144	if (!anx78xx->powered)
1145		goto unlock;
1146
1147	err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1148			  &irq);
1149	if (err) {
1150		DRM_ERROR("Failed to read HDMI int 1 status: %d\n", err);
1151		goto unlock;
1152	}
1153
1154	if (irq)
1155		anx78xx_handle_hdmi_int_1(anx78xx, irq);
1156
1157unlock:
1158	mutex_unlock(&anx78xx->lock);
1159
1160	if (event)
1161		drm_helper_hpd_irq_event(anx78xx->connector.dev);
1162
1163	return IRQ_HANDLED;
1164}
1165
1166static void unregister_i2c_dummy_clients(struct anx78xx *anx78xx)
1167{
1168	unsigned int i;
1169
1170	for (i = 0; i < ARRAY_SIZE(anx78xx->i2c_dummy); i++)
1171		i2c_unregister_device(anx78xx->i2c_dummy[i]);
1172}
1173
1174static const struct regmap_config anx78xx_regmap_config = {
1175	.reg_bits = 8,
1176	.val_bits = 8,
1177};
1178
1179static const u16 anx78xx_chipid_list[] = {
1180	0x7808,
1181	0x7812,
1182	0x7814,
1183	0x7816,
1184	0x7818,
1185};
1186
1187static int anx78xx_i2c_probe(struct i2c_client *client)
1188{
1189	struct anx78xx *anx78xx;
1190	struct anx78xx_platform_data *pdata;
1191	unsigned int i, idl, idh, version;
1192	const u8 *i2c_addresses;
1193	bool found = false;
1194	int err;
1195
1196	anx78xx = devm_drm_bridge_alloc(&client->dev, struct anx78xx, bridge,
1197					&anx78xx_bridge_funcs);
1198	if (IS_ERR(anx78xx))
1199		return PTR_ERR(anx78xx);
1200
1201	pdata = &anx78xx->pdata;
1202
1203	mutex_init(&anx78xx->lock);
1204
1205	anx78xx->bridge.of_node = client->dev.of_node;
1206
1207	anx78xx->client = client;
1208	i2c_set_clientdata(client, anx78xx);
1209
1210	err = anx78xx_init_pdata(anx78xx);
1211	if (err) {
1212		if (err != -EPROBE_DEFER)
1213			DRM_ERROR("Failed to initialize pdata: %d\n", err);
1214
1215		return err;
1216	}
1217
1218	pdata->hpd_irq = gpiod_to_irq(pdata->gpiod_hpd);
1219	if (pdata->hpd_irq < 0) {
1220		DRM_ERROR("Failed to get HPD IRQ: %d\n", pdata->hpd_irq);
1221		return -ENODEV;
1222	}
1223
1224	pdata->intp_irq = client->irq;
1225	if (!pdata->intp_irq) {
1226		DRM_ERROR("Failed to get CABLE_DET and INTP IRQ\n");
1227		return -ENODEV;
1228	}
1229
1230	/* Map slave addresses of ANX7814 */
1231	i2c_addresses = device_get_match_data(&client->dev);
1232	for (i = 0; i < I2C_NUM_ADDRESSES; i++) {
1233		struct i2c_client *i2c_dummy;
1234
1235		i2c_dummy = i2c_new_dummy_device(client->adapter,
1236						 i2c_addresses[i] >> 1);
1237		if (IS_ERR(i2c_dummy)) {
1238			err = PTR_ERR(i2c_dummy);
1239			DRM_ERROR("Failed to reserve I2C bus %02x: %d\n",
1240				  i2c_addresses[i], err);
1241			goto err_unregister_i2c;
1242		}
1243
1244		anx78xx->i2c_dummy[i] = i2c_dummy;
1245		anx78xx->map[i] = devm_regmap_init_i2c(anx78xx->i2c_dummy[i],
1246						       &anx78xx_regmap_config);
1247		if (IS_ERR(anx78xx->map[i])) {
1248			err = PTR_ERR(anx78xx->map[i]);
1249			DRM_ERROR("Failed regmap initialization %02x\n",
1250				  i2c_addresses[i]);
1251			goto err_unregister_i2c;
1252		}
1253	}
1254
1255	/* Look for supported chip ID */
1256	anx78xx_poweron(anx78xx);
1257
1258	err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDL_REG,
1259			  &idl);
1260	if (err)
1261		goto err_poweroff;
1262
1263	err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDH_REG,
1264			  &idh);
1265	if (err)
1266		goto err_poweroff;
1267
1268	anx78xx->chipid = (u8)idl | ((u8)idh << 8);
1269
1270	err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_VERSION_REG,
1271			  &version);
1272	if (err)
1273		goto err_poweroff;
1274
1275	for (i = 0; i < ARRAY_SIZE(anx78xx_chipid_list); i++) {
1276		if (anx78xx->chipid == anx78xx_chipid_list[i]) {
1277			DRM_INFO("Found ANX%x (ver. %d) SlimPort Transmitter\n",
1278				 anx78xx->chipid, version);
1279			found = true;
1280			break;
1281		}
1282	}
1283
1284	if (!found) {
1285		DRM_ERROR("ANX%x (ver. %d) not supported by this driver\n",
1286			  anx78xx->chipid, version);
1287		err = -ENODEV;
1288		goto err_poweroff;
1289	}
1290
1291	err = devm_request_threaded_irq(&client->dev, pdata->hpd_irq, NULL,
1292					anx78xx_hpd_threaded_handler,
1293					IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1294					"anx78xx-hpd", anx78xx);
1295	if (err) {
1296		DRM_ERROR("Failed to request CABLE_DET threaded IRQ: %d\n",
1297			  err);
1298		goto err_poweroff;
1299	}
1300
1301	err = devm_request_threaded_irq(&client->dev, pdata->intp_irq, NULL,
1302					anx78xx_intp_threaded_handler,
1303					IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1304					"anx78xx-intp", anx78xx);
1305	if (err) {
1306		DRM_ERROR("Failed to request INTP threaded IRQ: %d\n", err);
1307		goto err_poweroff;
1308	}
1309
1310	drm_bridge_add(&anx78xx->bridge);
1311
1312	/* If cable is pulled out, just poweroff and wait for HPD event */
1313	if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
1314		anx78xx_poweroff(anx78xx);
1315
1316	return 0;
1317
1318err_poweroff:
1319	anx78xx_poweroff(anx78xx);
1320
1321err_unregister_i2c:
1322	unregister_i2c_dummy_clients(anx78xx);
1323	return err;
1324}
1325
1326static void anx78xx_i2c_remove(struct i2c_client *client)
1327{
1328	struct anx78xx *anx78xx = i2c_get_clientdata(client);
1329
1330	drm_bridge_remove(&anx78xx->bridge);
1331
1332	unregister_i2c_dummy_clients(anx78xx);
1333
1334	drm_edid_free(anx78xx->drm_edid);
1335}
1336
1337static const struct of_device_id anx78xx_match_table[] = {
1338	{ .compatible = "analogix,anx7808", .data = anx7808_i2c_addresses },
1339	{ .compatible = "analogix,anx7812", .data = anx781x_i2c_addresses },
1340	{ .compatible = "analogix,anx7814", .data = anx781x_i2c_addresses },
1341	{ .compatible = "analogix,anx7816", .data = anx781x_i2c_addresses },
1342	{ .compatible = "analogix,anx7818", .data = anx781x_i2c_addresses },
1343	{ /* sentinel */ },
1344};
1345MODULE_DEVICE_TABLE(of, anx78xx_match_table);
1346
1347static struct i2c_driver anx78xx_driver = {
1348	.driver = {
1349		   .name = "anx7814",
1350		   .of_match_table = anx78xx_match_table,
1351		  },
1352	.probe = anx78xx_i2c_probe,
1353	.remove = anx78xx_i2c_remove,
1354};
1355module_i2c_driver(anx78xx_driver);
1356
1357MODULE_DESCRIPTION("ANX78xx SlimPort Transmitter driver");
1358MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
1359MODULE_LICENSE("GPL v2");