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armada_crtc.c
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linux-6.19.14/drivers/gpu/drm/armada/armada_crtc.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2012 Russell King 4 * Rewritten from the dovefb driver, and Armada510 manuals. 5 */ 6 7#include <linux/clk.h> 8#include <linux/component.h> 9#include <linux/module.h> 10#include <linux/of.h> 11#include <linux/platform_device.h> 12#include <linux/property.h> 13 14#include <drm/drm_atomic.h> 15#include <drm/drm_atomic_helper.h> 16#include <drm/drm_print.h> 17#include <drm/drm_probe_helper.h> 18#include <drm/drm_vblank.h> 19 20#include "armada_crtc.h" 21#include "armada_drm.h" 22#include "armada_fb.h" 23#include "armada_gem.h" 24#include "armada_hw.h" 25#include "armada_plane.h" 26#include "armada_trace.h" 27 28/* 29 * A note about interlacing. Let's consider HDMI 1920x1080i. 30 * The timing parameters we have from X are: 31 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot 32 * 1920 2448 2492 2640 1080 1084 1094 1125 33 * Which get translated to: 34 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot 35 * 1920 2448 2492 2640 540 542 547 562 36 * 37 * This is how it is defined by CEA-861-D - line and pixel numbers are 38 * referenced to the rising edge of VSYNC and HSYNC. Total clocks per 39 * line: 2640. The odd frame, the first active line is at line 21, and 40 * the even frame, the first active line is 584. 41 * 42 * LN: 560 561 562 563 567 568 569 43 * DE: ~~~|____________________________//__________________________ 44 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____ 45 * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________ 46 * 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge). 47 * 48 * LN: 1123 1124 1125 1 5 6 7 49 * DE: ~~~|____________________________//__________________________ 50 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____ 51 * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________ 52 * 23 blanking lines 53 * 54 * The Armada LCD Controller line and pixel numbers are, like X timings, 55 * referenced to the top left of the active frame. 56 * 57 * So, translating these to our LCD controller: 58 * Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128. 59 * Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448. 60 * Note: Vsync front porch remains constant! 61 * 62 * if (odd_frame) { 63 * vtotal = mode->crtc_vtotal + 1; 64 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1; 65 * vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2 66 * } else { 67 * vtotal = mode->crtc_vtotal; 68 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay; 69 * vhorizpos = mode->crtc_hsync_start; 70 * } 71 * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end; 72 * 73 * So, we need to reprogram these registers on each vsync event: 74 * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL 75 * 76 * Note: we do not use the frame done interrupts because these appear 77 * to happen too early, and lead to jitter on the display (presumably 78 * they occur at the end of the last active line, before the vsync back 79 * porch, which we're reprogramming.) 80 */ 81 82void 83armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs) 84{ 85 while (regs->offset != ~0) { 86 void __iomem *reg = dcrtc->base + regs->offset; 87 uint32_t val; 88 89 val = regs->mask; 90 if (val != 0) 91 val &= readl_relaxed(reg); 92 writel_relaxed(val | regs->val, reg); 93 ++regs; 94 } 95} 96 97static void armada_drm_crtc_update(struct armada_crtc *dcrtc, bool enable) 98{ 99 uint32_t dumb_ctrl; 100 101 dumb_ctrl = dcrtc->cfg_dumb_ctrl; 102 103 if (enable) 104 dumb_ctrl |= CFG_DUMB_ENA; 105 106 /* 107 * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might 108 * be using SPI or GPIO. If we set this to DUMB_BLANK, we will 109 * force LCD_D[23:0] to output blank color, overriding the GPIO or 110 * SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode. 111 */ 112 if (!enable && (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) { 113 dumb_ctrl &= ~DUMB_MASK; 114 dumb_ctrl |= DUMB_BLANK; 115 } 116 117 armada_updatel(dumb_ctrl, 118 ~(CFG_INV_CSYNC | CFG_INV_HSYNC | CFG_INV_VSYNC), 119 dcrtc->base + LCD_SPU_DUMB_CTRL); 120} 121 122static void armada_drm_crtc_queue_state_event(struct drm_crtc *crtc) 123{ 124 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 125 struct drm_pending_vblank_event *event; 126 127 /* If we have an event, we need vblank events enabled */ 128 event = xchg(&crtc->state->event, NULL); 129 if (event) { 130 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 131 dcrtc->event = event; 132 } 133} 134 135static void armada_drm_update_gamma(struct drm_crtc *crtc) 136{ 137 struct drm_property_blob *blob = crtc->state->gamma_lut; 138 void __iomem *base = drm_to_armada_crtc(crtc)->base; 139 int i; 140 141 if (blob) { 142 struct drm_color_lut *lut = blob->data; 143 144 armada_updatel(CFG_CSB_256x8, CFG_CSB_256x8 | CFG_PDWN256x8, 145 base + LCD_SPU_SRAM_PARA1); 146 147 for (i = 0; i < 256; i++) { 148 writel_relaxed(drm_color_lut_extract(lut[i].red, 8), 149 base + LCD_SPU_SRAM_WRDAT); 150 writel_relaxed(i | SRAM_WRITE | SRAM_GAMMA_YR, 151 base + LCD_SPU_SRAM_CTRL); 152 readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN); 153 writel_relaxed(drm_color_lut_extract(lut[i].green, 8), 154 base + LCD_SPU_SRAM_WRDAT); 155 writel_relaxed(i | SRAM_WRITE | SRAM_GAMMA_UG, 156 base + LCD_SPU_SRAM_CTRL); 157 readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN); 158 writel_relaxed(drm_color_lut_extract(lut[i].blue, 8), 159 base + LCD_SPU_SRAM_WRDAT); 160 writel_relaxed(i | SRAM_WRITE | SRAM_GAMMA_VB, 161 base + LCD_SPU_SRAM_CTRL); 162 readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN); 163 } 164 armada_updatel(CFG_GAMMA_ENA, CFG_GAMMA_ENA, 165 base + LCD_SPU_DMA_CTRL0); 166 } else { 167 armada_updatel(0, CFG_GAMMA_ENA, base + LCD_SPU_DMA_CTRL0); 168 armada_updatel(CFG_PDWN256x8, CFG_CSB_256x8 | CFG_PDWN256x8, 169 base + LCD_SPU_SRAM_PARA1); 170 } 171} 172 173static enum drm_mode_status armada_drm_crtc_mode_valid(struct drm_crtc *crtc, 174 const struct drm_display_mode *mode) 175{ 176 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 177 178 if (mode->vscan > 1) 179 return MODE_NO_VSCAN; 180 181 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 182 return MODE_NO_DBLESCAN; 183 184 if (mode->flags & DRM_MODE_FLAG_HSKEW) 185 return MODE_H_ILLEGAL; 186 187 /* We can't do interlaced modes if we don't have the SPU_ADV_REG */ 188 if (!dcrtc->variant->has_spu_adv_reg && 189 mode->flags & DRM_MODE_FLAG_INTERLACE) 190 return MODE_NO_INTERLACE; 191 192 if (mode->flags & (DRM_MODE_FLAG_BCAST | DRM_MODE_FLAG_PIXMUX | 193 DRM_MODE_FLAG_CLKDIV2)) 194 return MODE_BAD; 195 196 return MODE_OK; 197} 198 199/* The mode_config.mutex will be held for this call */ 200static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc, 201 const struct drm_display_mode *mode, struct drm_display_mode *adj) 202{ 203 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 204 int ret; 205 206 /* 207 * Set CRTC modesetting parameters for the adjusted mode. This is 208 * applied after the connectors, bridges, and encoders have fixed up 209 * this mode, as described above drm_atomic_helper_check_modeset(). 210 */ 211 drm_mode_set_crtcinfo(adj, CRTC_INTERLACE_HALVE_V); 212 213 /* 214 * Validate the adjusted mode in case an encoder/bridge has set 215 * something we don't support. 216 */ 217 if (armada_drm_crtc_mode_valid(crtc, adj) != MODE_OK) 218 return false; 219 220 /* Check whether the display mode is possible */ 221 ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL); 222 if (ret) 223 return false; 224 225 return true; 226} 227 228/* These are locked by dev->vbl_lock */ 229static void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask) 230{ 231 if (dcrtc->irq_ena & mask) { 232 dcrtc->irq_ena &= ~mask; 233 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); 234 } 235} 236 237static void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask) 238{ 239 if ((dcrtc->irq_ena & mask) != mask) { 240 dcrtc->irq_ena |= mask; 241 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); 242 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask) 243 writel(0, dcrtc->base + LCD_SPU_IRQ_ISR); 244 } 245} 246 247static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat) 248{ 249 struct drm_pending_vblank_event *event; 250 void __iomem *base = dcrtc->base; 251 252 if (stat & DMA_FF_UNDERFLOW) 253 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num); 254 if (stat & GRA_FF_UNDERFLOW) 255 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num); 256 257 if (stat & VSYNC_IRQ) 258 drm_crtc_handle_vblank(&dcrtc->crtc); 259 260 spin_lock(&dcrtc->irq_lock); 261 if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) { 262 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1; 263 uint32_t val; 264 265 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH); 266 writel_relaxed(dcrtc->v[i].spu_v_h_total, 267 base + LCD_SPUT_V_H_TOTAL); 268 269 val = readl_relaxed(base + LCD_SPU_ADV_REG); 270 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN); 271 val |= dcrtc->v[i].spu_adv_reg; 272 writel_relaxed(val, base + LCD_SPU_ADV_REG); 273 } 274 275 if (stat & dcrtc->irq_ena & DUMB_FRAMEDONE) { 276 if (dcrtc->update_pending) { 277 armada_drm_crtc_update_regs(dcrtc, dcrtc->regs); 278 dcrtc->update_pending = false; 279 } 280 if (dcrtc->cursor_update) { 281 writel_relaxed(dcrtc->cursor_hw_pos, 282 base + LCD_SPU_HWC_OVSA_HPXL_VLN); 283 writel_relaxed(dcrtc->cursor_hw_sz, 284 base + LCD_SPU_HWC_HPXL_VLN); 285 armada_updatel(CFG_HWC_ENA, 286 CFG_HWC_ENA | CFG_HWC_1BITMOD | 287 CFG_HWC_1BITENA, 288 base + LCD_SPU_DMA_CTRL0); 289 dcrtc->cursor_update = false; 290 } 291 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); 292 } 293 spin_unlock(&dcrtc->irq_lock); 294 295 if (stat & VSYNC_IRQ && !dcrtc->update_pending) { 296 event = xchg(&dcrtc->event, NULL); 297 if (event) { 298 spin_lock(&dcrtc->crtc.dev->event_lock); 299 drm_crtc_send_vblank_event(&dcrtc->crtc, event); 300 spin_unlock(&dcrtc->crtc.dev->event_lock); 301 drm_crtc_vblank_put(&dcrtc->crtc); 302 } 303 } 304} 305 306static irqreturn_t armada_drm_irq(int irq, void *arg) 307{ 308 struct armada_crtc *dcrtc = arg; 309 u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR); 310 311 /* 312 * Reading the ISR appears to clear bits provided CLEAN_SPU_IRQ_ISR 313 * is set. Writing has some other effect to acknowledge the IRQ - 314 * without this, we only get a single IRQ. 315 */ 316 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); 317 318 trace_armada_drm_irq(&dcrtc->crtc, stat); 319 320 /* Mask out those interrupts we haven't enabled */ 321 v = stat & dcrtc->irq_ena; 322 323 if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) { 324 armada_drm_crtc_irq(dcrtc, stat); 325 return IRQ_HANDLED; 326 } 327 return IRQ_NONE; 328} 329 330/* The mode_config.mutex will be held for this call */ 331static void armada_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 332{ 333 struct drm_display_mode *adj = &crtc->state->adjusted_mode; 334 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 335 struct armada_regs regs[17]; 336 uint32_t lm, rm, tm, bm, val, sclk; 337 unsigned long flags; 338 unsigned i; 339 bool interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE); 340 341 i = 0; 342 rm = adj->crtc_hsync_start - adj->crtc_hdisplay; 343 lm = adj->crtc_htotal - adj->crtc_hsync_end; 344 bm = adj->crtc_vsync_start - adj->crtc_vdisplay; 345 tm = adj->crtc_vtotal - adj->crtc_vsync_end; 346 347 DRM_DEBUG_KMS("[CRTC:%d:%s] mode " DRM_MODE_FMT "\n", 348 crtc->base.id, crtc->name, DRM_MODE_ARG(adj)); 349 DRM_DEBUG_KMS("lm %d rm %d tm %d bm %d\n", lm, rm, tm, bm); 350 351 /* Now compute the divider for real */ 352 dcrtc->variant->compute_clock(dcrtc, adj, &sclk); 353 354 armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV); 355 356 spin_lock_irqsave(&dcrtc->irq_lock, flags); 357 358 dcrtc->interlaced = interlaced; 359 /* Even interlaced/progressive frame */ 360 dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 | 361 adj->crtc_htotal; 362 dcrtc->v[1].spu_v_porch = tm << 16 | bm; 363 val = adj->crtc_hsync_start; 364 dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN; 365 366 if (interlaced) { 367 /* Odd interlaced frame */ 368 val -= adj->crtc_htotal / 2; 369 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN; 370 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total + 371 (1 << 16); 372 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1; 373 } else { 374 dcrtc->v[0] = dcrtc->v[1]; 375 } 376 377 val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay; 378 379 armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE); 380 armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH); 381 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH); 382 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total, 383 LCD_SPUT_V_H_TOTAL); 384 385 if (dcrtc->variant->has_spu_adv_reg) 386 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg, 387 ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | 388 ADV_VSYNCOFFEN, LCD_SPU_ADV_REG); 389 390 val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0; 391 armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1); 392 393 /* 394 * The documentation doesn't indicate what the normal state of 395 * the sync signals are. Sebastian Hesselbart kindly probed 396 * these signals on his board to determine their state. 397 * 398 * The non-inverted state of the sync signals is active high. 399 * Setting these bits makes the appropriate signal active low. 400 */ 401 val = 0; 402 if (adj->flags & DRM_MODE_FLAG_NCSYNC) 403 val |= CFG_INV_CSYNC; 404 if (adj->flags & DRM_MODE_FLAG_NHSYNC) 405 val |= CFG_INV_HSYNC; 406 if (adj->flags & DRM_MODE_FLAG_NVSYNC) 407 val |= CFG_INV_VSYNC; 408 armada_reg_queue_mod(regs, i, val, CFG_INV_CSYNC | CFG_INV_HSYNC | 409 CFG_INV_VSYNC, LCD_SPU_DUMB_CTRL); 410 armada_reg_queue_end(regs, i); 411 412 armada_drm_crtc_update_regs(dcrtc, regs); 413 spin_unlock_irqrestore(&dcrtc->irq_lock, flags); 414} 415 416static int armada_drm_crtc_atomic_check(struct drm_crtc *crtc, 417 struct drm_atomic_state *state) 418{ 419 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 420 crtc); 421 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); 422 423 if (crtc_state->gamma_lut && drm_color_lut_size(crtc_state->gamma_lut) != 256) 424 return -EINVAL; 425 426 if (crtc_state->color_mgmt_changed) 427 crtc_state->planes_changed = true; 428 429 return 0; 430} 431 432static void armada_drm_crtc_atomic_begin(struct drm_crtc *crtc, 433 struct drm_atomic_state *state) 434{ 435 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 436 crtc); 437 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 438 439 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); 440 441 if (crtc_state->color_mgmt_changed) 442 armada_drm_update_gamma(crtc); 443 444 dcrtc->regs_idx = 0; 445 dcrtc->regs = dcrtc->atomic_regs; 446} 447 448static void armada_drm_crtc_atomic_flush(struct drm_crtc *crtc, 449 struct drm_atomic_state *state) 450{ 451 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 452 crtc); 453 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 454 455 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); 456 457 armada_reg_queue_end(dcrtc->regs, dcrtc->regs_idx); 458 459 /* 460 * If we aren't doing a full modeset, then we need to queue 461 * the event here. 462 */ 463 if (!drm_atomic_crtc_needs_modeset(crtc_state)) { 464 dcrtc->update_pending = true; 465 armada_drm_crtc_queue_state_event(crtc); 466 spin_lock_irq(&dcrtc->irq_lock); 467 armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA); 468 spin_unlock_irq(&dcrtc->irq_lock); 469 } else { 470 spin_lock_irq(&dcrtc->irq_lock); 471 armada_drm_crtc_update_regs(dcrtc, dcrtc->regs); 472 spin_unlock_irq(&dcrtc->irq_lock); 473 } 474} 475 476static void armada_drm_crtc_atomic_disable(struct drm_crtc *crtc, 477 struct drm_atomic_state *state) 478{ 479 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 480 crtc); 481 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 482 struct drm_pending_vblank_event *event; 483 484 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); 485 486 if (old_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 487 drm_crtc_vblank_put(crtc); 488 489 drm_crtc_vblank_off(crtc); 490 armada_drm_crtc_update(dcrtc, false); 491 492 if (!crtc->state->active) { 493 /* 494 * This modeset will be leaving the CRTC disabled, so 495 * call the backend to disable upstream clocks etc. 496 */ 497 if (dcrtc->variant->disable) 498 dcrtc->variant->disable(dcrtc); 499 500 /* 501 * We will not receive any further vblank events. 502 * Send the flip_done event manually. 503 */ 504 event = crtc->state->event; 505 crtc->state->event = NULL; 506 if (event) { 507 spin_lock_irq(&crtc->dev->event_lock); 508 drm_crtc_send_vblank_event(crtc, event); 509 spin_unlock_irq(&crtc->dev->event_lock); 510 } 511 } 512} 513 514static void armada_drm_crtc_atomic_enable(struct drm_crtc *crtc, 515 struct drm_atomic_state *state) 516{ 517 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 518 crtc); 519 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 520 521 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); 522 523 if (!old_state->active) { 524 /* 525 * This modeset is enabling the CRTC after it having 526 * been disabled. Reverse the call to ->disable in 527 * the atomic_disable(). 528 */ 529 if (dcrtc->variant->enable) 530 dcrtc->variant->enable(dcrtc, &crtc->state->adjusted_mode); 531 } 532 armada_drm_crtc_update(dcrtc, true); 533 drm_crtc_vblank_on(crtc); 534 535 if (crtc->state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 536 WARN_ON(drm_crtc_vblank_get(crtc)); 537 538 armada_drm_crtc_queue_state_event(crtc); 539} 540 541static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = { 542 .mode_valid = armada_drm_crtc_mode_valid, 543 .mode_fixup = armada_drm_crtc_mode_fixup, 544 .mode_set_nofb = armada_drm_crtc_mode_set_nofb, 545 .atomic_check = armada_drm_crtc_atomic_check, 546 .atomic_begin = armada_drm_crtc_atomic_begin, 547 .atomic_flush = armada_drm_crtc_atomic_flush, 548 .atomic_disable = armada_drm_crtc_atomic_disable, 549 .atomic_enable = armada_drm_crtc_atomic_enable, 550}; 551 552static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix, 553 unsigned stride, unsigned width, unsigned height) 554{ 555 uint32_t addr; 556 unsigned y; 557 558 addr = SRAM_HWC32_RAM1; 559 for (y = 0; y < height; y++) { 560 uint32_t *p = &pix[y * stride]; 561 unsigned x; 562 563 for (x = 0; x < width; x++, p++) { 564 uint32_t val = *p; 565 566 /* 567 * In "ARGB888" (HWC32) mode, writing to the SRAM 568 * requires these bits to contain: 569 * 31:24 = alpha 23:16 = blue 15:8 = green 7:0 = red 570 * So, it's actually ABGR8888. This is independent 571 * of the SWAPRB bits in DMA control register 0. 572 */ 573 val = (val & 0xff00ff00) | 574 (val & 0x000000ff) << 16 | 575 (val & 0x00ff0000) >> 16; 576 577 writel_relaxed(val, 578 base + LCD_SPU_SRAM_WRDAT); 579 writel_relaxed(addr | SRAM_WRITE, 580 base + LCD_SPU_SRAM_CTRL); 581 readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN); 582 addr += 1; 583 if ((addr & 0x00ff) == 0) 584 addr += 0xf00; 585 if ((addr & 0x30ff) == 0) 586 addr = SRAM_HWC32_RAM2; 587 } 588 } 589} 590 591static void armada_drm_crtc_cursor_tran(void __iomem *base) 592{ 593 unsigned addr; 594 595 for (addr = 0; addr < 256; addr++) { 596 /* write the default value */ 597 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT); 598 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN, 599 base + LCD_SPU_SRAM_CTRL); 600 } 601} 602 603static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload) 604{ 605 uint32_t xoff, xscr, w = dcrtc->cursor_w, s; 606 uint32_t yoff, yscr, h = dcrtc->cursor_h; 607 uint32_t para1; 608 609 /* 610 * Calculate the visible width and height of the cursor, 611 * screen position, and the position in the cursor bitmap. 612 */ 613 if (dcrtc->cursor_x < 0) { 614 xoff = -dcrtc->cursor_x; 615 xscr = 0; 616 w -= min(xoff, w); 617 } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) { 618 xoff = 0; 619 xscr = dcrtc->cursor_x; 620 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0); 621 } else { 622 xoff = 0; 623 xscr = dcrtc->cursor_x; 624 } 625 626 if (dcrtc->cursor_y < 0) { 627 yoff = -dcrtc->cursor_y; 628 yscr = 0; 629 h -= min(yoff, h); 630 } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) { 631 yoff = 0; 632 yscr = dcrtc->cursor_y; 633 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0); 634 } else { 635 yoff = 0; 636 yscr = dcrtc->cursor_y; 637 } 638 639 /* On interlaced modes, the vertical cursor size must be halved */ 640 s = dcrtc->cursor_w; 641 if (dcrtc->interlaced) { 642 s *= 2; 643 yscr /= 2; 644 h /= 2; 645 } 646 647 if (!dcrtc->cursor_obj || !h || !w) { 648 spin_lock_irq(&dcrtc->irq_lock); 649 dcrtc->cursor_update = false; 650 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); 651 spin_unlock_irq(&dcrtc->irq_lock); 652 return 0; 653 } 654 655 spin_lock_irq(&dcrtc->irq_lock); 656 para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1); 657 armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32, 658 dcrtc->base + LCD_SPU_SRAM_PARA1); 659 spin_unlock_irq(&dcrtc->irq_lock); 660 661 /* 662 * Initialize the transparency if the SRAM was powered down. 663 * We must also reload the cursor data as well. 664 */ 665 if (!(para1 & CFG_CSB_256x32)) { 666 armada_drm_crtc_cursor_tran(dcrtc->base); 667 reload = true; 668 } 669 670 if (dcrtc->cursor_hw_sz != (h << 16 | w)) { 671 spin_lock_irq(&dcrtc->irq_lock); 672 dcrtc->cursor_update = false; 673 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); 674 spin_unlock_irq(&dcrtc->irq_lock); 675 reload = true; 676 } 677 if (reload) { 678 struct armada_gem_object *obj = dcrtc->cursor_obj; 679 uint32_t *pix; 680 /* Set the top-left corner of the cursor image */ 681 pix = obj->addr; 682 pix += yoff * s + xoff; 683 armada_load_cursor_argb(dcrtc->base, pix, s, w, h); 684 } 685 686 /* Reload the cursor position, size and enable in the IRQ handler */ 687 spin_lock_irq(&dcrtc->irq_lock); 688 dcrtc->cursor_hw_pos = yscr << 16 | xscr; 689 dcrtc->cursor_hw_sz = h << 16 | w; 690 dcrtc->cursor_update = true; 691 armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA); 692 spin_unlock_irq(&dcrtc->irq_lock); 693 694 return 0; 695} 696 697static void cursor_update(void *data) 698{ 699 armada_drm_crtc_cursor_update(data, true); 700} 701 702static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc, 703 struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h) 704{ 705 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 706 struct armada_gem_object *obj = NULL; 707 int ret; 708 709 /* If no cursor support, replicate drm's return value */ 710 if (!dcrtc->variant->has_spu_adv_reg) 711 return -ENXIO; 712 713 if (handle && w > 0 && h > 0) { 714 /* maximum size is 64x32 or 32x64 */ 715 if (w > 64 || h > 64 || (w > 32 && h > 32)) 716 return -ENOMEM; 717 718 obj = armada_gem_object_lookup(file, handle); 719 if (!obj) 720 return -ENOENT; 721 722 /* Must be a kernel-mapped object */ 723 if (!obj->addr) { 724 drm_gem_object_put(&obj->obj); 725 return -EINVAL; 726 } 727 728 if (obj->obj.size < w * h * 4) { 729 DRM_ERROR("buffer is too small\n"); 730 drm_gem_object_put(&obj->obj); 731 return -ENOMEM; 732 } 733 } 734 735 if (dcrtc->cursor_obj) { 736 dcrtc->cursor_obj->update = NULL; 737 dcrtc->cursor_obj->update_data = NULL; 738 drm_gem_object_put(&dcrtc->cursor_obj->obj); 739 } 740 dcrtc->cursor_obj = obj; 741 dcrtc->cursor_w = w; 742 dcrtc->cursor_h = h; 743 ret = armada_drm_crtc_cursor_update(dcrtc, true); 744 if (obj) { 745 obj->update_data = dcrtc; 746 obj->update = cursor_update; 747 } 748 749 return ret; 750} 751 752static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 753{ 754 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 755 int ret; 756 757 /* If no cursor support, replicate drm's return value */ 758 if (!dcrtc->variant->has_spu_adv_reg) 759 return -EFAULT; 760 761 dcrtc->cursor_x = x; 762 dcrtc->cursor_y = y; 763 ret = armada_drm_crtc_cursor_update(dcrtc, false); 764 765 return ret; 766} 767 768static void armada_drm_crtc_destroy(struct drm_crtc *crtc) 769{ 770 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 771 struct armada_private *priv = drm_to_armada_dev(crtc->dev); 772 773 if (dcrtc->cursor_obj) 774 drm_gem_object_put(&dcrtc->cursor_obj->obj); 775 776 priv->dcrtc[dcrtc->num] = NULL; 777 drm_crtc_cleanup(&dcrtc->crtc); 778 779 if (dcrtc->variant->disable) 780 dcrtc->variant->disable(dcrtc); 781 782 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA); 783 784 of_node_put(dcrtc->crtc.port); 785 786 kfree(dcrtc); 787} 788 789static int armada_drm_crtc_late_register(struct drm_crtc *crtc) 790{ 791 if (IS_ENABLED(CONFIG_DEBUG_FS)) 792 armada_drm_crtc_debugfs_init(drm_to_armada_crtc(crtc)); 793 794 return 0; 795} 796 797/* These are called under the vbl_lock. */ 798static int armada_drm_crtc_enable_vblank(struct drm_crtc *crtc) 799{ 800 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 801 unsigned long flags; 802 803 spin_lock_irqsave(&dcrtc->irq_lock, flags); 804 armada_drm_crtc_enable_irq(dcrtc, VSYNC_IRQ_ENA); 805 spin_unlock_irqrestore(&dcrtc->irq_lock, flags); 806 return 0; 807} 808 809static void armada_drm_crtc_disable_vblank(struct drm_crtc *crtc) 810{ 811 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); 812 unsigned long flags; 813 814 spin_lock_irqsave(&dcrtc->irq_lock, flags); 815 armada_drm_crtc_disable_irq(dcrtc, VSYNC_IRQ_ENA); 816 spin_unlock_irqrestore(&dcrtc->irq_lock, flags); 817} 818 819static const struct drm_crtc_funcs armada_crtc_funcs = { 820 .reset = drm_atomic_helper_crtc_reset, 821 .cursor_set = armada_drm_crtc_cursor_set, 822 .cursor_move = armada_drm_crtc_cursor_move, 823 .destroy = armada_drm_crtc_destroy, 824 .set_config = drm_atomic_helper_set_config, 825 .page_flip = drm_atomic_helper_page_flip, 826 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 827 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 828 .late_register = armada_drm_crtc_late_register, 829 .enable_vblank = armada_drm_crtc_enable_vblank, 830 .disable_vblank = armada_drm_crtc_disable_vblank, 831}; 832 833int armada_crtc_select_clock(struct armada_crtc *dcrtc, 834 struct armada_clk_result *res, 835 const struct armada_clocking_params *params, 836 struct clk *clks[], size_t num_clks, 837 unsigned long desired_khz) 838{ 839 unsigned long desired_hz = desired_khz * 1000; 840 unsigned long desired_clk_hz; // requested clk input 841 unsigned long real_clk_hz; // actual clk input 842 unsigned long real_hz; // actual pixel clk 843 unsigned long permillage; 844 struct clk *clk; 845 u32 div; 846 int i; 847 848 DRM_DEBUG_KMS("[CRTC:%u:%s] desired clock=%luHz\n", 849 dcrtc->crtc.base.id, dcrtc->crtc.name, desired_hz); 850 851 for (i = 0; i < num_clks; i++) { 852 clk = clks[i]; 853 if (!clk) 854 continue; 855 856 if (params->settable & BIT(i)) { 857 real_clk_hz = clk_round_rate(clk, desired_hz); 858 desired_clk_hz = desired_hz; 859 } else { 860 real_clk_hz = clk_get_rate(clk); 861 desired_clk_hz = real_clk_hz; 862 } 863 864 /* If the clock can do exactly the desired rate, we're done */ 865 if (real_clk_hz == desired_hz) { 866 real_hz = real_clk_hz; 867 div = 1; 868 goto found; 869 } 870 871 /* Calculate the divider - if invalid, we can't do this rate */ 872 div = DIV_ROUND_CLOSEST(real_clk_hz, desired_hz); 873 if (div == 0 || div > params->div_max) 874 continue; 875 876 /* Calculate the actual rate - HDMI requires -0.6%..+0.5% */ 877 real_hz = DIV_ROUND_CLOSEST(real_clk_hz, div); 878 879 DRM_DEBUG_KMS("[CRTC:%u:%s] clk=%u %luHz div=%u real=%luHz\n", 880 dcrtc->crtc.base.id, dcrtc->crtc.name, 881 i, real_clk_hz, div, real_hz); 882 883 /* Avoid repeated division */ 884 if (real_hz < desired_hz) { 885 permillage = real_hz / desired_khz; 886 if (permillage < params->permillage_min) 887 continue; 888 } else { 889 permillage = DIV_ROUND_UP(real_hz, desired_khz); 890 if (permillage > params->permillage_max) 891 continue; 892 } 893 goto found; 894 } 895 896 return -ERANGE; 897 898found: 899 DRM_DEBUG_KMS("[CRTC:%u:%s] selected clk=%u %luHz div=%u real=%luHz\n", 900 dcrtc->crtc.base.id, dcrtc->crtc.name, 901 i, real_clk_hz, div, real_hz); 902 903 res->desired_clk_hz = desired_clk_hz; 904 res->clk = clk; 905 res->div = div; 906 907 return i; 908} 909 910static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev, 911 struct resource *res, int irq, const struct armada_variant *variant, 912 struct device_node *port) 913{ 914 struct armada_private *priv = drm_to_armada_dev(drm); 915 struct armada_crtc *dcrtc; 916 struct drm_plane *primary; 917 void __iomem *base; 918 int ret; 919 920 base = devm_ioremap_resource(dev, res); 921 if (IS_ERR(base)) 922 return PTR_ERR(base); 923 924 dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL); 925 if (!dcrtc) { 926 DRM_ERROR("failed to allocate Armada crtc\n"); 927 return -ENOMEM; 928 } 929 930 if (dev != drm->dev) 931 dev_set_drvdata(dev, dcrtc); 932 933 dcrtc->variant = variant; 934 dcrtc->base = base; 935 dcrtc->num = drm->mode_config.num_crtc; 936 dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0; 937 dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24; 938 spin_lock_init(&dcrtc->irq_lock); 939 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR; 940 941 /* Initialize some registers which we don't otherwise set */ 942 writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV); 943 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR); 944 writel_relaxed(dcrtc->spu_iopad_ctrl, 945 dcrtc->base + LCD_SPU_IOPAD_CONTROL); 946 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0); 947 writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | 948 CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 | 949 CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1); 950 writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1); 951 writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); 952 readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR); 953 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); 954 955 ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc", 956 dcrtc); 957 if (ret < 0) 958 goto err_crtc; 959 960 if (dcrtc->variant->init) { 961 ret = dcrtc->variant->init(dcrtc, dev); 962 if (ret) 963 goto err_crtc; 964 } 965 966 /* Ensure AXI pipeline is enabled */ 967 armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0); 968 969 priv->dcrtc[dcrtc->num] = dcrtc; 970 971 dcrtc->crtc.port = port; 972 973 primary = kzalloc(sizeof(*primary), GFP_KERNEL); 974 if (!primary) { 975 ret = -ENOMEM; 976 goto err_crtc; 977 } 978 979 ret = armada_drm_primary_plane_init(drm, primary); 980 if (ret) { 981 kfree(primary); 982 goto err_crtc; 983 } 984 985 ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, primary, NULL, 986 &armada_crtc_funcs, NULL); 987 if (ret) 988 goto err_crtc_init; 989 990 drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs); 991 992 ret = drm_mode_crtc_set_gamma_size(&dcrtc->crtc, 256); 993 if (ret) 994 return ret; 995 996 drm_crtc_enable_color_mgmt(&dcrtc->crtc, 0, false, 256); 997 998 return armada_overlay_plane_create(drm, 1 << dcrtc->num); 999 1000err_crtc_init: 1001 primary->funcs->destroy(primary); 1002err_crtc: 1003 kfree(dcrtc); 1004 1005 return ret; 1006} 1007 1008static int 1009armada_lcd_bind(struct device *dev, struct device *master, void *data) 1010{ 1011 struct platform_device *pdev = to_platform_device(dev); 1012 struct drm_device *drm = data; 1013 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1014 int irq = platform_get_irq(pdev, 0); 1015 const struct armada_variant *variant; 1016 struct device_node *port = NULL; 1017 struct device_node *np, *parent = dev->of_node; 1018 1019 if (irq < 0) 1020 return irq; 1021 1022 1023 variant = device_get_match_data(dev); 1024 if (!variant) 1025 return -ENXIO; 1026 1027 if (parent) { 1028 np = of_get_child_by_name(parent, "ports"); 1029 if (np) 1030 parent = np; 1031 port = of_get_child_by_name(parent, "port"); 1032 of_node_put(np); 1033 if (!port) { 1034 dev_err(dev, "no port node found in %pOF\n", parent); 1035 return -ENXIO; 1036 } 1037 } 1038 1039 return armada_drm_crtc_create(drm, dev, res, irq, variant, port); 1040} 1041 1042static void 1043armada_lcd_unbind(struct device *dev, struct device *master, void *data) 1044{ 1045 struct armada_crtc *dcrtc = dev_get_drvdata(dev); 1046 1047 armada_drm_crtc_destroy(&dcrtc->crtc); 1048} 1049 1050static const struct component_ops armada_lcd_ops = { 1051 .bind = armada_lcd_bind, 1052 .unbind = armada_lcd_unbind, 1053}; 1054 1055static int armada_lcd_probe(struct platform_device *pdev) 1056{ 1057 return component_add(&pdev->dev, &armada_lcd_ops); 1058} 1059 1060static void armada_lcd_remove(struct platform_device *pdev) 1061{ 1062 component_del(&pdev->dev, &armada_lcd_ops); 1063} 1064 1065static const struct of_device_id armada_lcd_of_match[] = { 1066 { 1067 .compatible = "marvell,dove-lcd", 1068 .data = &armada510_ops, 1069 }, 1070 {} 1071}; 1072MODULE_DEVICE_TABLE(of, armada_lcd_of_match); 1073 1074static const struct platform_device_id armada_lcd_platform_ids[] = { 1075 { 1076 .name = "armada-lcd", 1077 .driver_data = (unsigned long)&armada510_ops, 1078 }, { 1079 .name = "armada-510-lcd", 1080 .driver_data = (unsigned long)&armada510_ops, 1081 }, 1082 { }, 1083}; 1084MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids); 1085 1086struct platform_driver armada_lcd_platform_driver = { 1087 .probe = armada_lcd_probe, 1088 .remove = armada_lcd_remove, 1089 .driver = { 1090 .name = "armada-lcd", 1091 .owner = THIS_MODULE, 1092 .of_match_table = armada_lcd_of_match, 1093 }, 1094 .id_table = armada_lcd_platform_ids, 1095};
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