ras_umc_v12_0.h

  1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright 2025 Advanced Micro Devices, Inc.
  4 *
  5 * Permission is hereby granted, free of charge, to any person obtaining a
  6 * copy of this software and associated documentation files (the "Software"),
  7 * to deal in the Software without restriction, including without limitation
  8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9 * and/or sell copies of the Software, and to permit persons to whom the
 10 * Software is furnished to do so, subject to the following conditions:
 11 *
 12 * The above copyright notice and this permission notice shall be included in
 13 * all copies or substantial portions of the Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 21 * OTHER DEALINGS IN THE SOFTWARE.
 22 *
 23 */
 24#ifndef __RAS_UMC_V12_0_H__
 25#define __RAS_UMC_V12_0_H__
 26#include "ras.h"
 27
 28/* MCA_UMC_UMC0_MCUMC_ADDRT0 */
 29#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT                0x0
 30#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT                 0x38
 31#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK                  0x00FFFFFFFFFFFFFFL
 32#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved_MASK                   0xFF00000000000000L
 33
 34/* MCMP1_IPIDT0 */
 35#define MCMP1_IPIDT0__InstanceIdLo__SHIFT                          0x0
 36#define MCMP1_IPIDT0__HardwareID__SHIFT                            0x20
 37#define MCMP1_IPIDT0__InstanceIdHi__SHIFT                          0x2c
 38#define MCMP1_IPIDT0__McaType__SHIFT                               0x30
 39
 40#define MCMP1_IPIDT0__InstanceIdLo_MASK                            0x00000000FFFFFFFFL
 41#define MCMP1_IPIDT0__HardwareID_MASK                              0x00000FFF00000000L
 42#define MCMP1_IPIDT0__InstanceIdHi_MASK                            0x0000F00000000000L
 43#define MCMP1_IPIDT0__McaType_MASK                                 0xFFFF000000000000L
 44
 45/* number of umc channel instance with memory map register access */
 46#define UMC_V12_0_CHANNEL_INSTANCE_NUM		8
 47/* number of umc instance with memory map register access */
 48#define UMC_V12_0_UMC_INSTANCE_NUM		4
 49
 50/* one piece of normalized address is mapped to 8 pieces of physical address */
 51#define UMC_V12_0_NA_MAP_PA_NUM        8
 52
 53/* bank bits in MCA error address */
 54#define UMC_V12_0_MCA_B0_BIT 6
 55#define UMC_V12_0_MCA_B1_BIT 7
 56#define UMC_V12_0_MCA_B2_BIT 8
 57#define UMC_V12_0_MCA_B3_BIT 9
 58
 59/* row bits in MCA address */
 60#define UMC_V12_0_MCA_R0_BIT 10
 61
 62/* Stack ID bits in SOC physical address */
 63#define UMC_V12_0_PA_SID1_BIT 37
 64#define UMC_V12_0_PA_SID0_BIT 36
 65
 66/* bank bits in SOC physical address */
 67#define UMC_V12_0_PA_B3_BIT 18
 68#define UMC_V12_0_PA_B2_BIT 17
 69#define UMC_V12_0_PA_B1_BIT 20
 70#define UMC_V12_0_PA_B0_BIT 19
 71
 72/* row bits in SOC physical address */
 73#define UMC_V12_0_PA_R13_BIT 35
 74#define UMC_V12_0_PA_R12_BIT 34
 75#define UMC_V12_0_PA_R11_BIT 33
 76#define UMC_V12_0_PA_R10_BIT 32
 77#define UMC_V12_0_PA_R9_BIT 31
 78#define UMC_V12_0_PA_R8_BIT 30
 79#define UMC_V12_0_PA_R7_BIT 29
 80#define UMC_V12_0_PA_R6_BIT 28
 81#define UMC_V12_0_PA_R5_BIT 27
 82#define UMC_V12_0_PA_R4_BIT 26
 83#define UMC_V12_0_PA_R3_BIT 25
 84#define UMC_V12_0_PA_R2_BIT 24
 85#define UMC_V12_0_PA_R1_BIT 23
 86#define UMC_V12_0_PA_R0_BIT 22
 87
 88/* column bits in SOC physical address */
 89#define UMC_V12_0_PA_C4_BIT 21
 90#define UMC_V12_0_PA_C3_BIT 16
 91#define UMC_V12_0_PA_C2_BIT 15
 92#define UMC_V12_0_PA_C1_BIT 6
 93#define UMC_V12_0_PA_C0_BIT 5
 94
 95/* channel index bits in SOC physical address */
 96#define UMC_V12_0_PA_CH6_BIT 14
 97#define UMC_V12_0_PA_CH5_BIT 13
 98#define UMC_V12_0_PA_CH4_BIT 12
 99#define UMC_V12_0_PA_CH3_BIT 11
100#define UMC_V12_0_PA_CH2_BIT 10
101#define UMC_V12_0_PA_CH1_BIT 9
102#define UMC_V12_0_PA_CH0_BIT 8
103
104/* Pseudochannel index bits in SOC physical address */
105#define UMC_V12_0_PA_PC0_BIT 7
106
107#define UMC_V12_0_NA_C2_BIT 8
108
109#define UMC_V12_0_SOC_PA_TO_SID(pa) \
110	((((pa >> UMC_V12_0_PA_SID0_BIT) & 0x1ULL) << 0ULL) | \
111	 (((pa >> UMC_V12_0_PA_SID1_BIT) & 0x1ULL) << 1ULL))
112
113#define UMC_V12_0_SOC_PA_TO_BANK(pa) \
114	((((pa >> UMC_V12_0_PA_B0_BIT) & 0x1ULL) << 0ULL) | \
115	 (((pa >> UMC_V12_0_PA_B1_BIT) & 0x1ULL) << 1ULL) | \
116	 (((pa >> UMC_V12_0_PA_B2_BIT) & 0x1ULL) << 2ULL) | \
117	 (((pa >> UMC_V12_0_PA_B3_BIT) & 0x1ULL) << 3ULL))
118
119#define UMC_V12_0_SOC_PA_TO_ROW(pa) \
120	((((pa >> UMC_V12_0_PA_R0_BIT) & 0x1ULL) << 0ULL) | \
121	 (((pa >> UMC_V12_0_PA_R1_BIT) & 0x1ULL) << 1ULL) | \
122	 (((pa >> UMC_V12_0_PA_R2_BIT) & 0x1ULL) << 2ULL) | \
123	 (((pa >> UMC_V12_0_PA_R3_BIT) & 0x1ULL) << 3ULL) | \
124	 (((pa >> UMC_V12_0_PA_R4_BIT) & 0x1ULL) << 4ULL) | \
125	 (((pa >> UMC_V12_0_PA_R5_BIT) & 0x1ULL) << 5ULL) | \
126	 (((pa >> UMC_V12_0_PA_R6_BIT) & 0x1ULL) << 6ULL) | \
127	 (((pa >> UMC_V12_0_PA_R7_BIT) & 0x1ULL) << 7ULL) | \
128	 (((pa >> UMC_V12_0_PA_R8_BIT) & 0x1ULL) << 8ULL) | \
129	 (((pa >> UMC_V12_0_PA_R9_BIT) & 0x1ULL) << 9ULL) | \
130	 (((pa >> UMC_V12_0_PA_R10_BIT) & 0x1ULL) << 10ULL) | \
131	 (((pa >> UMC_V12_0_PA_R11_BIT) & 0x1ULL) << 11ULL) | \
132	 (((pa >> UMC_V12_0_PA_R12_BIT) & 0x1ULL) << 12ULL) | \
133	 (((pa >> UMC_V12_0_PA_R13_BIT) & 0x1ULL) << 13ULL))
134
135#define UMC_V12_0_SOC_PA_TO_COL(pa) \
136	((((pa >> UMC_V12_0_PA_C0_BIT) & 0x1ULL) << 0ULL) | \
137	 (((pa >> UMC_V12_0_PA_C1_BIT) & 0x1ULL) << 1ULL) | \
138	 (((pa >> UMC_V12_0_PA_C2_BIT) & 0x1ULL) << 2ULL) | \
139	 (((pa >> UMC_V12_0_PA_C3_BIT) & 0x1ULL) << 3ULL) | \
140	 (((pa >> UMC_V12_0_PA_C4_BIT) & 0x1ULL) << 4ULL))
141
142#define UMC_V12_0_SOC_PA_TO_CH(pa) \
143	((((pa >> UMC_V12_0_PA_CH0_BIT) & 0x1ULL) << 0ULL) | \
144	 (((pa >> UMC_V12_0_PA_CH1_BIT) & 0x1ULL) << 1ULL) | \
145	 (((pa >> UMC_V12_0_PA_CH2_BIT) & 0x1ULL) << 2ULL) | \
146	 (((pa >> UMC_V12_0_PA_CH3_BIT) & 0x1ULL) << 3ULL) | \
147	 (((pa >> UMC_V12_0_PA_CH4_BIT) & 0x1ULL) << 4ULL) | \
148	 (((pa >> UMC_V12_0_PA_CH5_BIT) & 0x1ULL) << 5ULL) | \
149	 (((pa >> UMC_V12_0_PA_CH6_BIT) & 0x1ULL) << 6ULL))
150
151#define UMC_V12_0_SOC_PA_TO_PC(pa) (((pa >> UMC_V12_0_PA_PC0_BIT) & 0x1ULL) << 0ULL)
152
153#define UMC_V12_0_SOC_SID_TO_PA(sid) \
154	((((sid >> 0ULL) & 0x1ULL) << UMC_V12_0_PA_SID0_BIT) | \
155	 (((sid >> 1ULL) & 0x1ULL) << UMC_V12_0_PA_SID1_BIT))
156
157#define UMC_V12_0_SOC_BANK_TO_PA(bank) \
158	((((bank >> 0ULL) & 0x1ULL) << UMC_V12_0_PA_B0_BIT) | \
159	 (((bank >> 1ULL) & 0x1ULL) << UMC_V12_0_PA_B1_BIT) | \
160	 (((bank >> 2ULL) & 0x1ULL) << UMC_V12_0_PA_B2_BIT) | \
161	 (((bank >> 3ULL) & 0x1ULL) << UMC_V12_0_PA_B3_BIT))
162
163#define UMC_V12_0_SOC_ROW_TO_PA(row) \
164	((((row >> 0ULL) & 0x1ULL) << UMC_V12_0_PA_R0_BIT) | \
165	 (((row >> 1ULL) & 0x1ULL) << UMC_V12_0_PA_R1_BIT) | \
166	 (((row >> 2ULL) & 0x1ULL) << UMC_V12_0_PA_R2_BIT) | \
167	 (((row >> 3ULL) & 0x1ULL) << UMC_V12_0_PA_R3_BIT) | \
168	 (((row >> 4ULL) & 0x1ULL) << UMC_V12_0_PA_R4_BIT) | \
169	 (((row >> 5ULL) & 0x1ULL) << UMC_V12_0_PA_R5_BIT) | \
170	 (((row >> 6ULL) & 0x1ULL) << UMC_V12_0_PA_R6_BIT) | \
171	 (((row >> 7ULL) & 0x1ULL) << UMC_V12_0_PA_R7_BIT) | \
172	 (((row >> 8ULL) & 0x1ULL) << UMC_V12_0_PA_R8_BIT) | \
173	 (((row >> 9ULL) & 0x1ULL) << UMC_V12_0_PA_R9_BIT) | \
174	 (((row >> 10ULL) & 0x1ULL) << UMC_V12_0_PA_R10_BIT) | \
175	 (((row >> 11ULL) & 0x1ULL) << UMC_V12_0_PA_R11_BIT) | \
176	 (((row >> 12ULL) & 0x1ULL) << UMC_V12_0_PA_R12_BIT) | \
177	 (((row >> 13ULL) & 0x1ULL) << UMC_V12_0_PA_R13_BIT))
178
179#define UMC_V12_0_SOC_COL_TO_PA(col) \
180	((((col >> 0ULL) & 0x1ULL) << UMC_V12_0_PA_C0_BIT) | \
181	 (((col >> 1ULL) & 0x1ULL) << UMC_V12_0_PA_C1_BIT) | \
182	 (((col >> 2ULL) & 0x1ULL) << UMC_V12_0_PA_C2_BIT) | \
183	 (((col >> 3ULL) & 0x1ULL) << UMC_V12_0_PA_C3_BIT) | \
184	 (((col >> 4ULL) & 0x1ULL) << UMC_V12_0_PA_C4_BIT))
185
186#define UMC_V12_0_SOC_CH_TO_PA(ch) \
187	((((ch >> 0ULL) & 0x1ULL) << UMC_V12_0_PA_CH0_BIT) | \
188	 (((ch >> 1ULL) & 0x1ULL) << UMC_V12_0_PA_CH1_BIT) | \
189	 (((ch >> 2ULL) & 0x1ULL) << UMC_V12_0_PA_CH2_BIT) | \
190	 (((ch >> 3ULL) & 0x1ULL) << UMC_V12_0_PA_CH3_BIT) | \
191	 (((ch >> 4ULL) & 0x1ULL) << UMC_V12_0_PA_CH4_BIT) | \
192	 (((ch >> 5ULL) & 0x1ULL) << UMC_V12_0_PA_CH5_BIT) | \
193	 (((ch >> 6ULL) & 0x1ULL) << UMC_V12_0_PA_CH6_BIT))
194
195#define UMC_V12_0_SOC_PC_TO_PA(pc) (((pc >> 0ULL) & 0x1ULL) << UMC_V12_0_PA_PC0_BIT)
196
197/* bank hash settings */
198#define UMC_V12_0_XOR_EN0 1
199#define UMC_V12_0_XOR_EN1 1
200#define UMC_V12_0_XOR_EN2 1
201#define UMC_V12_0_XOR_EN3 1
202#define UMC_V12_0_COL_XOR0 0x0
203#define UMC_V12_0_COL_XOR1 0x0
204#define UMC_V12_0_COL_XOR2 0x800
205#define UMC_V12_0_COL_XOR3 0x1000
206#define UMC_V12_0_ROW_XOR0 0x11111
207#define UMC_V12_0_ROW_XOR1 0x22222
208#define UMC_V12_0_ROW_XOR2 0x4444
209#define UMC_V12_0_ROW_XOR3 0x8888
210
211/* channel hash settings */
212#define UMC_V12_0_HASH_4K 0
213#define UMC_V12_0_HASH_64K 1
214#define UMC_V12_0_HASH_2M 1
215#define UMC_V12_0_HASH_1G 1
216#define UMC_V12_0_HASH_1T 1
217
218/* XOR some bits of PA into CH4~CH6 bits (bits 12~14 of PA),
219 * hash bit is only effective when related setting is enabled
220 */
221#define UMC_V12_0_CHANNEL_HASH_CH4(channel_idx, pa) ((((channel_idx) >> 5) & 0x1) ^ \
222				(((pa)  >> 20) & 0x1ULL & UMC_V12_0_HASH_64K) ^ \
223				(((pa)  >> 27) & 0x1ULL & UMC_V12_0_HASH_2M) ^ \
224				(((pa)  >> 34) & 0x1ULL & UMC_V12_0_HASH_1G) ^ \
225				(((pa)  >> 41) & 0x1ULL & UMC_V12_0_HASH_1T))
226#define UMC_V12_0_CHANNEL_HASH_CH5(channel_idx, pa) ((((channel_idx) >> 6) & 0x1) ^ \
227				(((pa)  >> 21) & 0x1ULL & UMC_V12_0_HASH_64K) ^ \
228				(((pa)  >> 28) & 0x1ULL & UMC_V12_0_HASH_2M) ^ \
229				(((pa)  >> 35) & 0x1ULL & UMC_V12_0_HASH_1G) ^ \
230				(((pa)  >> 42) & 0x1ULL & UMC_V12_0_HASH_1T))
231#define UMC_V12_0_CHANNEL_HASH_CH6(channel_idx, pa) ((((channel_idx) >> 4) & 0x1) ^ \
232				(((pa)  >> 19) & 0x1ULL & UMC_V12_0_HASH_64K) ^ \
233				(((pa)  >> 26) & 0x1ULL & UMC_V12_0_HASH_2M) ^ \
234				(((pa)  >> 33) & 0x1ULL & UMC_V12_0_HASH_1G) ^ \
235				(((pa)  >> 40) & 0x1ULL & UMC_V12_0_HASH_1T) ^ \
236				(((pa)  >> 47) & 0x1ULL & UMC_V12_0_HASH_1T))
237#define UMC_V12_0_SET_CHANNEL_HASH(channel_idx, pa) do { \
238		(pa) &= ~(0x7ULL << UMC_V12_0_PA_CH4_BIT); \
239		(pa) |= (UMC_V12_0_CHANNEL_HASH_CH4(channel_idx, pa) << UMC_V12_0_PA_CH4_BIT); \
240		(pa) |= (UMC_V12_0_CHANNEL_HASH_CH5(channel_idx, pa) << UMC_V12_0_PA_CH5_BIT); \
241		(pa) |= (UMC_V12_0_CHANNEL_HASH_CH6(channel_idx, pa) << UMC_V12_0_PA_CH6_BIT); \
242	} while (0)
243
244
245/*
246 * (addr / 256) * 4096, the higher 26 bits in ErrorAddr
247 * is the index of 4KB block
248 */
249#define ADDR_OF_4KB_BLOCK(addr)			(((addr) & ~0xffULL) << 4)
250/*
251 * (addr / 256) * 8192, the higher 26 bits in ErrorAddr
252 * is the index of 8KB block
253 */
254#define ADDR_OF_8KB_BLOCK(addr)			(((addr) & ~0xffULL) << 5)
255/*
256 * (addr / 256) * 32768, the higher 26 bits in ErrorAddr
257 * is the index of 8KB block
258 */
259#define ADDR_OF_32KB_BLOCK(addr)			(((addr) & ~0xffULL) << 7)
260/* channel index is the index of 256B block */
261#define ADDR_OF_256B_BLOCK(channel_index)	((channel_index) << 8)
262/* offset in 256B block */
263#define OFFSET_IN_256B_BLOCK(addr)		((addr) & 0xffULL)
264
265
266#define UMC_V12_ADDR_MASK_BAD_COLS(addr) \
267	((addr) & ~((0x3ULL << UMC_V12_0_PA_C2_BIT) | \
268			(0x1ULL << UMC_V12_0_PA_C4_BIT) | \
269			(0x1ULL << UMC_V12_0_PA_R13_BIT)))
270
271#define ACA_IPID_HI_2_UMC_AID(_ipid_hi) (((_ipid_hi) >> 2) & 0x3)
272#define ACA_IPID_LO_2_UMC_CH(_ipid_lo)  \
273	(((((_ipid_lo) >> 20) & 0x1) * 4) + (((_ipid_lo) >> 12) & 0xF))
274#define ACA_IPID_LO_2_UMC_INST(_ipid_lo) (((_ipid_lo) >> 21) & 0x7)
275
276#define ACA_IPID_2_DIE_ID(ipid)  ((REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi) >> 2) & 0x03)
277#define ACA_IPID_2_UMC_CH(ipid) \
278	(ACA_IPID_LO_2_UMC_CH(REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo)))
279
280#define ACA_IPID_2_UMC_INST(ipid) \
281	(ACA_IPID_LO_2_UMC_INST(REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo)))
282
283#define ACA_IPID_2_SOCKET_ID(ipid) \
284	(((REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo) & 0x1) << 2) | \
285	 (REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi) & 0x03))
286
287#define ACA_ADDR_2_ERR_ADDR(addr) \
288	REG_GET_FIELD(addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr)
289
290/* R13 bit shift should be considered, double the number */
291#define UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL (UMC_V12_0_NA_MAP_PA_NUM * 2)
292
293
294/* C2, C3, C4, R13, four MCA bits are looped in page retirement */
295#define UMC_V12_0_RETIRE_LOOP_BITS 4
296
297/* invalid node instance value */
298#define UMC_INV_AID_NODE 0xffff
299
300#define UMC_V12_0_AID_NUM_MAX     4
301#define UMC_V12_0_SOCKET_NUM_MAX  8
302
303#define UMC_V12_0_TOTAL_CHANNEL_NUM \
304	(UMC_V12_0_AID_NUM_MAX * UMC_V12_0_UMC_INSTANCE_NUM * UMC_V12_0_CHANNEL_INSTANCE_NUM)
305
306/* one device has 192GB HBM */
307#define SOCKET_LFB_SIZE   0x3000000000ULL
308
309extern const struct ras_umc_ip_func ras_umc_func_v12_0;
310
311int ras_umc_get_badpage_count(struct ras_core_context *ras_core);
312int ras_umc_get_badpage_record(struct ras_core_context *ras_core, uint32_t index, void *record);
313#endif
314