ras_nbio_v7_9.c

  1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright 2025 Advanced Micro Devices, Inc.
  4 *
  5 * Permission is hereby granted, free of charge, to any person obtaining a
  6 * copy of this software and associated documentation files (the "Software"),
  7 * to deal in the Software without restriction, including without limitation
  8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9 * and/or sell copies of the Software, and to permit persons to whom the
 10 * Software is furnished to do so, subject to the following conditions:
 11 *
 12 * The above copyright notice and this permission notice shall be included in
 13 * all copies or substantial portions of the Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 21 * OTHER DEALINGS IN THE SOFTWARE.
 22 *
 23 */
 24
 25#include "ras.h"
 26#include "ras_nbio_v7_9.h"
 27
 28#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT      0x12
 29#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK        0x00040000L
 30#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT     0x2
 31#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK       0x00000004L
 32#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT                0x11
 33#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK                  0x00020000L
 34#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT               0x1
 35#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK                 0x00000002L
 36
 37#define regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX      2
 38#define regBIF_BX0_BIF_DOORBELL_INT_CNTL               0x00fe
 39
 40#define regBIF_BX0_BIF_INTR_CNTL                                                       0x0101
 41#define regBIF_BX0_BIF_INTR_CNTL_BASE_IDX                                              2
 42
 43/* BIF_BX0_BIF_INTR_CNTL */
 44#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT                                 0x0
 45#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK                                   0x00000001L
 46
 47#define regBIF_BX_PF0_PARTITION_MEM_STATUS                                             0x0164
 48#define regBIF_BX_PF0_PARTITION_MEM_STATUS_BASE_IDX                                    2
 49/* BIF_BX_PF0_PARTITION_MEM_STATUS */
 50#define BIF_BX_PF0_PARTITION_MEM_STATUS__CHANGE_STATUE__SHIFT                          0x0
 51#define BIF_BX_PF0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT                               0x4
 52#define BIF_BX_PF0_PARTITION_MEM_STATUS__CHANGE_STATUE_MASK                            0x0000000FL
 53#define BIF_BX_PF0_PARTITION_MEM_STATUS__NPS_MODE_MASK                                 0x00000FF0L
 54
 55
 56static int nbio_v7_9_handle_ras_controller_intr_no_bifring(struct ras_core_context *ras_core)
 57{
 58	uint32_t bif_doorbell_intr_cntl = 0;
 59
 60	bif_doorbell_intr_cntl =
 61		RAS_DEV_RREG32_SOC15(ras_core->dev, NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);
 62
 63	if (REG_GET_FIELD(bif_doorbell_intr_cntl,
 64		BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
 65		/* driver has to clear the interrupt status when bif ring is disabled */
 66		bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
 67						BIF_BX0_BIF_DOORBELL_INT_CNTL,
 68						RAS_CNTLR_INTERRUPT_CLEAR, 1);
 69
 70		RAS_DEV_WREG32_SOC15(ras_core->dev,
 71			NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
 72
 73		/* TODO: handle ras controller interrupt */
 74	}
 75
 76	return 0;
 77}
 78
 79static int nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring(struct ras_core_context *ras_core)
 80{
 81	uint32_t bif_doorbell_intr_cntl = 0;
 82	int ret = 0;
 83
 84	bif_doorbell_intr_cntl =
 85		RAS_DEV_RREG32_SOC15(ras_core->dev, NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);
 86
 87	if (REG_GET_FIELD(bif_doorbell_intr_cntl,
 88		BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) {
 89		/* driver has to clear the interrupt status when bif ring is disabled */
 90		bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
 91						BIF_BX0_BIF_DOORBELL_INT_CNTL,
 92						RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1);
 93
 94		RAS_DEV_WREG32_SOC15(ras_core->dev,
 95			NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
 96
 97		ret = ras_core_handle_fatal_error(ras_core);
 98	}
 99
100	return ret;
101}
102
103static uint32_t nbio_v7_9_get_memory_partition_mode(struct ras_core_context *ras_core)
104{
105	uint32_t mem_status;
106	uint32_t mem_mode;
107
108	mem_status =
109		RAS_DEV_RREG32_SOC15(ras_core->dev, NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS);
110
111	/* Each bit represents a mode 1-8*/
112	mem_mode = REG_GET_FIELD(mem_status, BIF_BX_PF0_PARTITION_MEM_STATUS, NPS_MODE);
113
114	return ffs(mem_mode);
115}
116
117const struct ras_nbio_ip_func ras_nbio_v7_9 = {
118	.handle_ras_controller_intr_no_bifring =
119		nbio_v7_9_handle_ras_controller_intr_no_bifring,
120	.handle_ras_err_event_athub_intr_no_bifring =
121		nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring,
122	.get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode,
123};