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ras_mp1.h
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linux-6.19.14/drivers/gpu/drm/amd/ras/rascore/ras_mp1.h
1/* SPDX-License-Identifier: MIT */ 2/* 3 * Copyright 2025 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24#ifndef __RAS_MP1_H__ 25#define __RAS_MP1_H__ 26#include "ras.h" 27 28enum ras_err_type; 29struct ras_mp1_ip_func { 30 int (*get_valid_bank_count)(struct ras_core_context *ras_core, 31 enum ras_err_type type, u32 *count); 32 int (*dump_valid_bank)(struct ras_core_context *ras_core, 33 enum ras_err_type type, u32 idx, u32 reg_idx, u64 *val); 34}; 35 36struct ras_mp1 { 37 uint32_t mp1_ip_version; 38 const struct ras_mp1_ip_func *ip_func; 39 const struct ras_mp1_sys_func *sys_func; 40}; 41 42int ras_mp1_hw_init(struct ras_core_context *ras_core); 43int ras_mp1_hw_fini(struct ras_core_context *ras_core); 44 45int ras_mp1_get_bank_count(struct ras_core_context *ras_core, 46 enum ras_err_type type, u32 *count); 47 48int ras_mp1_dump_bank(struct ras_core_context *ras_core, 49 u32 ecc_type, u32 idx, u32 reg_idx, u64 *val); 50#endif
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