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ras_eeprom.c
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linux-6.19.14/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c
1// SPDX-License-Identifier: MIT 2/* 3 * Copyright 2025 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25#include "ras_eeprom.h" 26#include "ras.h" 27 28/* These are memory addresses as would be seen by one or more EEPROM 29 * chips strung on the I2C bus, usually by manipulating pins 1-3 of a 30 * set of EEPROM devices. They form a continuous memory space. 31 * 32 * The I2C device address includes the device type identifier, 1010b, 33 * which is a reserved value and indicates that this is an I2C EEPROM 34 * device. It also includes the top 3 bits of the 19 bit EEPROM memory 35 * address, namely bits 18, 17, and 16. This makes up the 7 bit 36 * address sent on the I2C bus with bit 0 being the direction bit, 37 * which is not represented here, and sent by the hardware directly. 38 * 39 * For instance, 40 * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. 41 * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. 42 * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. 43 * Depending on the size of the I2C EEPROM device(s), bits 18:16 may 44 * address memory in a device or a device on the I2C bus, depending on 45 * the status of pins 1-3. 46 * 47 * The RAS table lives either at address 0 or address 40000h of EEPROM. 48 */ 49#define EEPROM_I2C_MADDR_0 0x0 50#define EEPROM_I2C_MADDR_4 0x40000 51 52#define EEPROM_PAGE_BITS 8 53#define EEPROM_PAGE_SIZE (1U << EEPROM_PAGE_BITS) 54#define EEPROM_PAGE_MASK (EEPROM_PAGE_SIZE - 1) 55 56#define EEPROM_OFFSET_SIZE 2 57#define MAKE_I2C_ADDR(_aa) ((0xA << 3) | (((_aa) >> 16) & 0xF)) 58 59/* 60 * The 2 macros bellow represent the actual size in bytes that 61 * those entities occupy in the EEPROM memory. 62 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_umc_record) which 63 * uses uint64 to store 6b fields such as retired_page. 64 */ 65#define RAS_TABLE_HEADER_SIZE 20 66#define RAS_TABLE_RECORD_SIZE 24 67 68/* Table hdr is 'AMDR' */ 69#define RAS_TABLE_HDR_VAL 0x414d4452 70 71/* Bad GPU tag ‘BADG’ */ 72#define RAS_TABLE_HDR_BAD 0x42414447 73 74/* 75 * EEPROM Table structure v1 76 * --------------------------------- 77 * | | 78 * | EEPROM TABLE HEADER | 79 * | ( size 20 Bytes ) | 80 * | | 81 * --------------------------------- 82 * | | 83 * | BAD PAGE RECORD AREA | 84 * | | 85 * --------------------------------- 86 */ 87 88/* Assume 2-Mbit size EEPROM and take up the whole space. */ 89#define RAS_TBL_SIZE_BYTES (256 * 1024) 90#define RAS_TABLE_START 0 91#define RAS_HDR_START RAS_TABLE_START 92#define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE) 93#define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \ 94 / RAS_TABLE_RECORD_SIZE) 95 96/* 97 * EEPROM Table structrue v2.1 98 * --------------------------------- 99 * | | 100 * | EEPROM TABLE HEADER | 101 * | ( size 20 Bytes ) | 102 * | | 103 * --------------------------------- 104 * | | 105 * | EEPROM TABLE RAS INFO | 106 * | (available info size 4 Bytes) | 107 * | ( reserved size 252 Bytes ) | 108 * | | 109 * --------------------------------- 110 * | | 111 * | BAD PAGE RECORD AREA | 112 * | | 113 * --------------------------------- 114 */ 115 116/* EEPROM Table V2_1 */ 117#define RAS_TABLE_V2_1_INFO_SIZE 256 118#define RAS_TABLE_V2_1_INFO_START RAS_TABLE_HEADER_SIZE 119#define RAS_RECORD_START_V2_1 (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \ 120 RAS_TABLE_V2_1_INFO_SIZE) 121#define RAS_MAX_RECORD_COUNT_V2_1 ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \ 122 RAS_TABLE_V2_1_INFO_SIZE) \ 123 / RAS_TABLE_RECORD_SIZE) 124 125/* Given a zero-based index of an EEPROM RAS record, yields the EEPROM 126 * offset off of RAS_TABLE_START. That is, this is something you can 127 * add to control->i2c_address, and then tell I2C layer to read 128 * from/write to there. _N is the so called absolute index, 129 * because it starts right after the table header. 130 */ 131#define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \ 132 (_N) * RAS_TABLE_RECORD_SIZE) 133 134#define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \ 135 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE) 136 137/* Given a 0-based relative record index, 0, 1, 2, ..., etc., off 138 * of "fri", return the absolute record index off of the end of 139 * the table header. 140 */ 141#define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \ 142 (_C)->ras_max_record_count) 143 144#define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 145 RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE) 146 147#define RAS_NUM_RECS_V2_1(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 148 RAS_TABLE_HEADER_SIZE - \ 149 RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE) 150 151#define to_ras_core_context(x) (container_of(x, struct ras_core_context, ras_eeprom)) 152 153static bool __is_ras_eeprom_supported(struct ras_core_context *ras_core) 154{ 155 return ras_core->ras_eeprom_supported; 156} 157 158static bool __get_eeprom_i2c_addr(struct ras_core_context *ras_core, 159 struct ras_eeprom_control *control) 160{ 161 int ret = -EINVAL; 162 163 if (control->sys_func && 164 control->sys_func->update_eeprom_i2c_config) 165 ret = control->sys_func->update_eeprom_i2c_config(ras_core); 166 else 167 RAS_DEV_WARN(ras_core->dev, 168 "No eeprom i2c system config!\n"); 169 170 return !ret ? true : false; 171} 172 173static int __ras_eeprom_xfer(struct ras_core_context *ras_core, u32 eeprom_addr, 174 u8 *eeprom_buf, u32 buf_size, bool read) 175{ 176 struct ras_eeprom_control *control = &ras_core->ras_eeprom; 177 int ret; 178 179 if (control->sys_func && control->sys_func->eeprom_i2c_xfer) { 180 ret = control->sys_func->eeprom_i2c_xfer(ras_core, 181 eeprom_addr, eeprom_buf, buf_size, read); 182 183 if ((ret > 0) && !read) { 184 /* According to EEPROM specs the length of the 185 * self-writing cycle, tWR (tW), is 10 ms. 186 * 187 * TODO: Use polling on ACK, aka Acknowledge 188 * Polling, to minimize waiting for the 189 * internal write cycle to complete, as it is 190 * usually smaller than tWR (tW). 191 */ 192 msleep(10); 193 } 194 195 return ret; 196 } 197 198 RAS_DEV_ERR(ras_core->dev, "Error: No eeprom i2c system xfer function!\n"); 199 return -EINVAL; 200} 201 202static int __eeprom_xfer(struct ras_core_context *ras_core, u32 eeprom_addr, 203 u8 *eeprom_buf, u32 buf_size, bool read) 204{ 205 u16 limit; 206 u16 ps; /* Partial size */ 207 int res = 0, r; 208 209 if (read) 210 limit = ras_core->ras_eeprom.max_read_len; 211 else 212 limit = ras_core->ras_eeprom.max_write_len; 213 214 if (limit && (limit <= EEPROM_OFFSET_SIZE)) { 215 RAS_DEV_ERR(ras_core->dev, 216 "maddr:0x%04X size:0x%02X:quirk max_%s_len must be > %d", 217 eeprom_addr, buf_size, 218 read ? "read" : "write", EEPROM_OFFSET_SIZE); 219 return -EINVAL; 220 } 221 222 ras_core_down_gpu_reset_lock(ras_core); 223 224 if (limit == 0) { 225 res = __ras_eeprom_xfer(ras_core, eeprom_addr, 226 eeprom_buf, buf_size, read); 227 } else { 228 /* The "limit" includes all data bytes sent/received, 229 * which would include the EEPROM_OFFSET_SIZE bytes. 230 * Account for them here. 231 */ 232 limit -= EEPROM_OFFSET_SIZE; 233 for ( ; buf_size > 0; 234 buf_size -= ps, eeprom_addr += ps, eeprom_buf += ps) { 235 ps = (buf_size < limit) ? buf_size : limit; 236 237 r = __ras_eeprom_xfer(ras_core, eeprom_addr, 238 eeprom_buf, ps, read); 239 if (r < 0) 240 break; 241 242 res += r; 243 } 244 } 245 246 ras_core_up_gpu_reset_lock(ras_core); 247 248 return res; 249} 250 251static int __eeprom_read(struct ras_core_context *ras_core, 252 u32 eeprom_addr, u8 *eeprom_buf, u32 bytes) 253{ 254 return __eeprom_xfer(ras_core, eeprom_addr, 255 eeprom_buf, bytes, true); 256} 257 258static int __eeprom_write(struct ras_core_context *ras_core, 259 u32 eeprom_addr, u8 *eeprom_buf, u32 bytes) 260{ 261 return __eeprom_xfer(ras_core, eeprom_addr, 262 eeprom_buf, bytes, false); 263} 264 265static void 266__encode_table_header_to_buf(struct ras_eeprom_table_header *hdr, 267 unsigned char *buf) 268{ 269 u32 *pp = (uint32_t *)buf; 270 271 pp[0] = cpu_to_le32(hdr->header); 272 pp[1] = cpu_to_le32(hdr->version); 273 pp[2] = cpu_to_le32(hdr->first_rec_offset); 274 pp[3] = cpu_to_le32(hdr->tbl_size); 275 pp[4] = cpu_to_le32(hdr->checksum); 276} 277 278static void 279__decode_table_header_from_buf(struct ras_eeprom_table_header *hdr, 280 unsigned char *buf) 281{ 282 u32 *pp = (uint32_t *)buf; 283 284 hdr->header = le32_to_cpu(pp[0]); 285 hdr->version = le32_to_cpu(pp[1]); 286 hdr->first_rec_offset = le32_to_cpu(pp[2]); 287 hdr->tbl_size = le32_to_cpu(pp[3]); 288 hdr->checksum = le32_to_cpu(pp[4]); 289} 290 291static int __write_table_header(struct ras_eeprom_control *control) 292{ 293 u8 buf[RAS_TABLE_HEADER_SIZE]; 294 struct ras_core_context *ras_core = to_ras_core_context(control); 295 int res; 296 297 memset(buf, 0, sizeof(buf)); 298 __encode_table_header_to_buf(&control->tbl_hdr, buf); 299 300 /* i2c may be unstable in gpu reset */ 301 res = __eeprom_write(ras_core, 302 control->i2c_address + 303 control->ras_header_offset, 304 buf, RAS_TABLE_HEADER_SIZE); 305 306 if (res < 0) { 307 RAS_DEV_ERR(ras_core->dev, 308 "Failed to write EEPROM table header:%d\n", res); 309 } else if (res < RAS_TABLE_HEADER_SIZE) { 310 RAS_DEV_ERR(ras_core->dev, 311 "Short write:%d out of %d\n", res, RAS_TABLE_HEADER_SIZE); 312 res = -EIO; 313 } else { 314 res = 0; 315 } 316 317 return res; 318} 319 320static void 321__encode_table_ras_info_to_buf(struct ras_eeprom_table_ras_info *rai, 322 unsigned char *buf) 323{ 324 u32 *pp = (uint32_t *)buf; 325 u32 tmp; 326 327 tmp = ((uint32_t)(rai->rma_status) & 0xFF) | 328 (((uint32_t)(rai->health_percent) << 8) & 0xFF00) | 329 (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000); 330 pp[0] = cpu_to_le32(tmp); 331} 332 333static void 334__decode_table_ras_info_from_buf(struct ras_eeprom_table_ras_info *rai, 335 unsigned char *buf) 336{ 337 u32 *pp = (uint32_t *)buf; 338 u32 tmp; 339 340 tmp = le32_to_cpu(pp[0]); 341 rai->rma_status = tmp & 0xFF; 342 rai->health_percent = (tmp >> 8) & 0xFF; 343 rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF; 344} 345 346static int __write_table_ras_info(struct ras_eeprom_control *control) 347{ 348 struct ras_core_context *ras_core = to_ras_core_context(control); 349 u8 *buf; 350 int res; 351 352 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 353 if (!buf) { 354 RAS_DEV_ERR(ras_core->dev, 355 "Failed to alloc buf to write table ras info\n"); 356 return -ENOMEM; 357 } 358 359 __encode_table_ras_info_to_buf(&control->tbl_rai, buf); 360 361 /* i2c may be unstable in gpu reset */ 362 res = __eeprom_write(ras_core, 363 control->i2c_address + 364 control->ras_info_offset, 365 buf, RAS_TABLE_V2_1_INFO_SIZE); 366 367 if (res < 0) { 368 RAS_DEV_ERR(ras_core->dev, 369 "Failed to write EEPROM table ras info:%d\n", res); 370 } else if (res < RAS_TABLE_V2_1_INFO_SIZE) { 371 RAS_DEV_ERR(ras_core->dev, 372 "Short write:%d out of %d\n", res, RAS_TABLE_V2_1_INFO_SIZE); 373 res = -EIO; 374 } else { 375 res = 0; 376 } 377 378 kfree(buf); 379 380 return res; 381} 382 383static u8 __calc_hdr_byte_sum(const struct ras_eeprom_control *control) 384{ 385 int ii; 386 u8 *pp, csum; 387 u32 sz; 388 389 /* Header checksum, skip checksum field in the calculation */ 390 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); 391 pp = (u8 *) &control->tbl_hdr; 392 csum = 0; 393 for (ii = 0; ii < sz; ii++, pp++) 394 csum += *pp; 395 396 return csum; 397} 398 399static u8 __calc_ras_info_byte_sum(const struct ras_eeprom_control *control) 400{ 401 int ii; 402 u8 *pp, csum; 403 u32 sz; 404 405 sz = sizeof(control->tbl_rai); 406 pp = (u8 *) &control->tbl_rai; 407 csum = 0; 408 for (ii = 0; ii < sz; ii++, pp++) 409 csum += *pp; 410 411 return csum; 412} 413 414static int ras_eeprom_correct_header_tag( 415 struct ras_eeprom_control *control, 416 uint32_t header) 417{ 418 struct ras_eeprom_table_header *hdr = &control->tbl_hdr; 419 u8 *hh; 420 int res; 421 u8 csum; 422 423 csum = -hdr->checksum; 424 425 hh = (void *) &hdr->header; 426 csum -= (hh[0] + hh[1] + hh[2] + hh[3]); 427 hh = (void *) &header; 428 csum += hh[0] + hh[1] + hh[2] + hh[3]; 429 csum = -csum; 430 mutex_lock(&control->ras_tbl_mutex); 431 hdr->header = header; 432 hdr->checksum = csum; 433 res = __write_table_header(control); 434 mutex_unlock(&control->ras_tbl_mutex); 435 436 return res; 437} 438 439static void ras_set_eeprom_table_version(struct ras_eeprom_control *control) 440{ 441 struct ras_eeprom_table_header *hdr = &control->tbl_hdr; 442 443 hdr->version = RAS_TABLE_VER_V3; 444} 445 446int ras_eeprom_reset_table(struct ras_core_context *ras_core) 447{ 448 struct ras_eeprom_control *control = &ras_core->ras_eeprom; 449 struct ras_eeprom_table_header *hdr = &control->tbl_hdr; 450 struct ras_eeprom_table_ras_info *rai = &control->tbl_rai; 451 u8 csum; 452 int res; 453 454 mutex_lock(&control->ras_tbl_mutex); 455 456 hdr->header = RAS_TABLE_HDR_VAL; 457 ras_set_eeprom_table_version(control); 458 459 if (hdr->version >= RAS_TABLE_VER_V2_1) { 460 hdr->first_rec_offset = RAS_RECORD_START_V2_1; 461 hdr->tbl_size = RAS_TABLE_HEADER_SIZE + 462 RAS_TABLE_V2_1_INFO_SIZE; 463 rai->rma_status = RAS_GPU_HEALTH_USABLE; 464 /** 465 * GPU health represented as a percentage. 466 * 0 means worst health, 100 means fully health. 467 */ 468 rai->health_percent = 100; 469 /* ecc_page_threshold = 0 means disable bad page retirement */ 470 rai->ecc_page_threshold = control->record_threshold_count; 471 } else { 472 hdr->first_rec_offset = RAS_RECORD_START; 473 hdr->tbl_size = RAS_TABLE_HEADER_SIZE; 474 } 475 476 csum = __calc_hdr_byte_sum(control); 477 if (hdr->version >= RAS_TABLE_VER_V2_1) 478 csum += __calc_ras_info_byte_sum(control); 479 csum = -csum; 480 hdr->checksum = csum; 481 res = __write_table_header(control); 482 if (!res && hdr->version > RAS_TABLE_VER_V1) 483 res = __write_table_ras_info(control); 484 485 control->ras_num_recs = 0; 486 control->ras_fri = 0; 487 488 control->bad_channel_bitmap = 0; 489 ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM, 490 &control->ras_num_recs); 491 ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP, 492 &control->bad_channel_bitmap); 493 control->update_channel_flag = false; 494 495 mutex_unlock(&control->ras_tbl_mutex); 496 497 return res; 498} 499 500static void 501__encode_table_record_to_buf(struct ras_eeprom_control *control, 502 struct eeprom_umc_record *record, 503 unsigned char *buf) 504{ 505 __le64 tmp = 0; 506 int i = 0; 507 508 /* Next are all record fields according to EEPROM page spec in LE foramt */ 509 buf[i++] = record->err_type; 510 511 buf[i++] = record->bank; 512 513 tmp = cpu_to_le64(record->ts); 514 memcpy(buf + i, &tmp, 8); 515 i += 8; 516 517 tmp = cpu_to_le64((record->offset & 0xffffffffffff)); 518 memcpy(buf + i, &tmp, 6); 519 i += 6; 520 521 buf[i++] = record->mem_channel; 522 buf[i++] = record->mcumc_id; 523 524 tmp = cpu_to_le64((record->retired_row_pfn & 0xffffffffffff)); 525 memcpy(buf + i, &tmp, 6); 526} 527 528static void 529__decode_table_record_from_buf(struct ras_eeprom_control *control, 530 struct eeprom_umc_record *record, 531 unsigned char *buf) 532{ 533 __le64 tmp = 0; 534 int i = 0; 535 536 /* Next are all record fields according to EEPROM page spec in LE foramt */ 537 record->err_type = buf[i++]; 538 539 record->bank = buf[i++]; 540 541 memcpy(&tmp, buf + i, 8); 542 record->ts = le64_to_cpu(tmp); 543 i += 8; 544 545 memcpy(&tmp, buf + i, 6); 546 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff); 547 i += 6; 548 549 record->mem_channel = buf[i++]; 550 record->mcumc_id = buf[i++]; 551 552 memcpy(&tmp, buf + i, 6); 553 record->retired_row_pfn = (le64_to_cpu(tmp) & 0xffffffffffff); 554} 555 556bool ras_eeprom_check_safety_watermark(struct ras_core_context *ras_core) 557{ 558 struct ras_eeprom_control *control = &ras_core->ras_eeprom; 559 bool ret = false; 560 int bad_page_count; 561 562 if (!__is_ras_eeprom_supported(ras_core) || 563 !control->record_threshold_config) 564 return false; 565 566 bad_page_count = ras_umc_get_badpage_count(ras_core); 567 if (control->tbl_hdr.header == RAS_TABLE_HDR_BAD) { 568 if (bad_page_count > control->record_threshold_count) 569 RAS_DEV_WARN(ras_core->dev, "RAS records:%d exceed threshold:%d", 570 bad_page_count, control->record_threshold_count); 571 572 if ((control->record_threshold_config == WARN_NONSTOP_OVER_THRESHOLD) || 573 (control->record_threshold_config == NONSTOP_OVER_THRESHOLD)) { 574 RAS_DEV_WARN(ras_core->dev, 575 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures.\n"); 576 ret = false; 577 } else { 578 ras_core->is_rma = true; 579 RAS_DEV_WARN(ras_core->dev, 580 "Please consider adjusting the customized threshold.\n"); 581 ret = true; 582 } 583 } 584 585 return ret; 586} 587 588/** 589 * __ras_eeprom_write -- write indexed from buffer to EEPROM 590 * @control: pointer to control structure 591 * @buf: pointer to buffer containing data to write 592 * @fri: start writing at this index 593 * @num: number of records to write 594 * 595 * The caller must hold the table mutex in @control. 596 * Return 0 on success, -errno otherwise. 597 */ 598static int __ras_eeprom_write(struct ras_eeprom_control *control, 599 u8 *buf, const u32 fri, const u32 num) 600{ 601 struct ras_core_context *ras_core = to_ras_core_context(control); 602 u32 buf_size; 603 int res; 604 605 /* i2c may be unstable in gpu reset */ 606 buf_size = num * RAS_TABLE_RECORD_SIZE; 607 res = __eeprom_write(ras_core, 608 control->i2c_address + RAS_INDEX_TO_OFFSET(control, fri), 609 buf, buf_size); 610 if (res < 0) { 611 RAS_DEV_ERR(ras_core->dev, 612 "Writing %d EEPROM table records error:%d\n", num, res); 613 } else if (res < buf_size) { 614 /* Short write, return error.*/ 615 RAS_DEV_ERR(ras_core->dev, 616 "Wrote %d records out of %d\n", 617 (res/RAS_TABLE_RECORD_SIZE), num); 618 res = -EIO; 619 } else { 620 res = 0; 621 } 622 623 return res; 624} 625 626static int ras_eeprom_append_table(struct ras_eeprom_control *control, 627 struct eeprom_umc_record *record, 628 const u32 num) 629{ 630 u32 a, b, i; 631 u8 *buf, *pp; 632 int res; 633 634 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 635 if (!buf) 636 return -ENOMEM; 637 638 /* Encode all of them in one go. 639 */ 640 pp = buf; 641 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 642 __encode_table_record_to_buf(control, &record[i], pp); 643 644 /* update bad channel bitmap */ 645 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 646 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 647 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 648 control->update_channel_flag = true; 649 } 650 } 651 652 /* a, first record index to write into. 653 * b, last record index to write into. 654 * a = first index to read (fri) + number of records in the table, 655 * b = a + @num - 1. 656 * Let N = control->ras_max_num_record_count, then we have, 657 * case 0: 0 <= a <= b < N, 658 * just append @num records starting at a; 659 * case 1: 0 <= a < N <= b, 660 * append (N - a) records starting at a, and 661 * append the remainder, b % N + 1, starting at 0. 662 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases, 663 * case 2a: 0 <= a <= b < N 664 * append num records starting at a; and fix fri if b overwrote it, 665 * and since a <= b, if b overwrote it then a must've also, 666 * and if b didn't overwrite it, then a didn't also. 667 * case 2b: 0 <= b < a < N 668 * write num records starting at a, which wraps around 0=N 669 * and overwrite fri unconditionally. Now from case 2a, 670 * this means that b eclipsed fri to overwrite it and wrap 671 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally 672 * set fri = b + 1 (mod N). 673 * Now, since fri is updated in every case, except the trivial case 0, 674 * the number of records present in the table after writing, is, 675 * num_recs - 1 = b - fri (mod N), and we take the positive value, 676 * by adding an arbitrary multiple of N before taking the modulo N 677 * as shown below. 678 */ 679 a = control->ras_fri + control->ras_num_recs; 680 b = a + num - 1; 681 if (b < control->ras_max_record_count) { 682 res = __ras_eeprom_write(control, buf, a, num); 683 } else if (a < control->ras_max_record_count) { 684 u32 g0, g1; 685 686 g0 = control->ras_max_record_count - a; 687 g1 = b % control->ras_max_record_count + 1; 688 res = __ras_eeprom_write(control, buf, a, g0); 689 if (res) 690 goto Out; 691 res = __ras_eeprom_write(control, 692 buf + g0 * RAS_TABLE_RECORD_SIZE, 693 0, g1); 694 if (res) 695 goto Out; 696 if (g1 > control->ras_fri) 697 control->ras_fri = g1 % control->ras_max_record_count; 698 } else { 699 a %= control->ras_max_record_count; 700 b %= control->ras_max_record_count; 701 702 if (a <= b) { 703 /* Note that, b - a + 1 = num. */ 704 res = __ras_eeprom_write(control, buf, a, num); 705 if (res) 706 goto Out; 707 if (b >= control->ras_fri) 708 control->ras_fri = (b + 1) % control->ras_max_record_count; 709 } else { 710 u32 g0, g1; 711 712 /* b < a, which means, we write from 713 * a to the end of the table, and from 714 * the start of the table to b. 715 */ 716 g0 = control->ras_max_record_count - a; 717 g1 = b + 1; 718 res = __ras_eeprom_write(control, buf, a, g0); 719 if (res) 720 goto Out; 721 res = __ras_eeprom_write(control, 722 buf + g0 * RAS_TABLE_RECORD_SIZE, 0, g1); 723 if (res) 724 goto Out; 725 control->ras_fri = g1 % control->ras_max_record_count; 726 } 727 } 728 control->ras_num_recs = 1 + 729 (control->ras_max_record_count + b - control->ras_fri) 730 % control->ras_max_record_count; 731Out: 732 kfree(buf); 733 return res; 734} 735 736static int ras_eeprom_update_header(struct ras_eeprom_control *control) 737{ 738 struct ras_core_context *ras_core = to_ras_core_context(control); 739 int threshold_config = control->record_threshold_config; 740 u8 *buf, *pp, csum; 741 u32 buf_size; 742 int bad_page_count; 743 int res; 744 745 bad_page_count = ras_umc_get_badpage_count(ras_core); 746 /* Modify the header if it exceeds. 747 */ 748 if (threshold_config != 0 && 749 bad_page_count > control->record_threshold_count) { 750 RAS_DEV_WARN(ras_core->dev, 751 "Saved bad pages %d reaches threshold value %d\n", 752 bad_page_count, control->record_threshold_count); 753 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; 754 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) { 755 control->tbl_rai.rma_status = RAS_GPU_RETIRED__ECC_REACH_THRESHOLD; 756 control->tbl_rai.health_percent = 0; 757 } 758 759 if ((threshold_config != WARN_NONSTOP_OVER_THRESHOLD) && 760 (threshold_config != NONSTOP_OVER_THRESHOLD)) 761 ras_core->is_rma = true; 762 763 /* ignore the -ENOTSUPP return value */ 764 ras_core_event_notify(ras_core, RAS_EVENT_ID__DEVICE_RMA, NULL); 765 } 766 767 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 768 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 769 RAS_TABLE_V2_1_INFO_SIZE + 770 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 771 else 772 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + 773 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 774 control->tbl_hdr.checksum = 0; 775 776 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 777 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 778 if (!buf) { 779 RAS_DEV_ERR(ras_core->dev, 780 "allocating memory for table of size %d bytes failed\n", 781 control->tbl_hdr.tbl_size); 782 res = -ENOMEM; 783 goto Out; 784 } 785 786 res = __eeprom_read(ras_core, 787 control->i2c_address + 788 control->ras_record_offset, 789 buf, buf_size); 790 if (res < 0) { 791 RAS_DEV_ERR(ras_core->dev, 792 "EEPROM failed reading records:%d\n", res); 793 goto Out; 794 } else if (res < buf_size) { 795 RAS_DEV_ERR(ras_core->dev, 796 "EEPROM read %d out of %d bytes\n", res, buf_size); 797 res = -EIO; 798 goto Out; 799 } 800 801 /** 802 * bad page records have been stored in eeprom, 803 * now calculate gpu health percent 804 */ 805 if (threshold_config != 0 && 806 control->tbl_hdr.version >= RAS_TABLE_VER_V2_1 && 807 bad_page_count <= control->record_threshold_count) 808 control->tbl_rai.health_percent = ((control->record_threshold_count - 809 bad_page_count) * 100) / control->record_threshold_count; 810 811 /* Recalc the checksum. 812 */ 813 csum = 0; 814 for (pp = buf; pp < buf + buf_size; pp++) 815 csum += *pp; 816 817 csum += __calc_hdr_byte_sum(control); 818 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 819 csum += __calc_ras_info_byte_sum(control); 820 /* avoid sign extension when assigning to "checksum" */ 821 csum = -csum; 822 control->tbl_hdr.checksum = csum; 823 res = __write_table_header(control); 824 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1) 825 res = __write_table_ras_info(control); 826Out: 827 kfree(buf); 828 return res; 829} 830 831/** 832 * ras_core_eeprom_append -- append records to the EEPROM RAS table 833 * @control: pointer to control structure 834 * @record: array of records to append 835 * @num: number of records in @record array 836 * 837 * Append @num records to the table, calculate the checksum and write 838 * the table back to EEPROM. The maximum number of records that 839 * can be appended is between 1 and control->ras_max_record_count, 840 * regardless of how many records are already stored in the table. 841 * 842 * Return 0 on success or if EEPROM is not supported, -errno on error. 843 */ 844int ras_eeprom_append(struct ras_core_context *ras_core, 845 struct eeprom_umc_record *record, const u32 num) 846{ 847 struct ras_eeprom_control *control = &ras_core->ras_eeprom; 848 int res; 849 850 if (!__is_ras_eeprom_supported(ras_core)) 851 return 0; 852 853 if (num == 0) { 854 RAS_DEV_ERR(ras_core->dev, "will not append 0 records\n"); 855 return -EINVAL; 856 } else if ((num + control->ras_num_recs) > control->ras_max_record_count) { 857 RAS_DEV_ERR(ras_core->dev, 858 "cannot append %d records than the size of table %d\n", 859 num, control->ras_max_record_count); 860 return -EINVAL; 861 } 862 863 mutex_lock(&control->ras_tbl_mutex); 864 res = ras_eeprom_append_table(control, record, num); 865 if (!res) 866 res = ras_eeprom_update_header(control); 867 868 mutex_unlock(&control->ras_tbl_mutex); 869 870 return res; 871} 872 873/** 874 * __ras_eeprom_read -- read indexed from EEPROM into buffer 875 * @control: pointer to control structure 876 * @buf: pointer to buffer to read into 877 * @fri: first record index, start reading at this index, absolute index 878 * @num: number of records to read 879 * 880 * The caller must hold the table mutex in @control. 881 * Return 0 on success, -errno otherwise. 882 */ 883static int __ras_eeprom_read(struct ras_eeprom_control *control, 884 u8 *buf, const u32 fri, const u32 num) 885{ 886 struct ras_core_context *ras_core = to_ras_core_context(control); 887 u32 buf_size; 888 int res; 889 890 /* i2c may be unstable in gpu reset */ 891 buf_size = num * RAS_TABLE_RECORD_SIZE; 892 res = __eeprom_read(ras_core, 893 control->i2c_address + 894 RAS_INDEX_TO_OFFSET(control, fri), 895 buf, buf_size); 896 if (res < 0) { 897 RAS_DEV_ERR(ras_core->dev, 898 "Reading %d EEPROM table records error:%d\n", num, res); 899 } else if (res < buf_size) { 900 /* Short read, return error. 901 */ 902 RAS_DEV_ERR(ras_core->dev, 903 "Read %d records out of %d\n", 904 (res/RAS_TABLE_RECORD_SIZE), num); 905 res = -EIO; 906 } else { 907 res = 0; 908 } 909 910 return res; 911} 912 913int ras_eeprom_read(struct ras_core_context *ras_core, 914 struct eeprom_umc_record *record, const u32 num) 915{ 916 struct ras_eeprom_control *control = &ras_core->ras_eeprom; 917 int i, res; 918 u8 *buf, *pp; 919 u32 g0, g1; 920 921 if (!__is_ras_eeprom_supported(ras_core)) 922 return 0; 923 924 if (num == 0) { 925 RAS_DEV_ERR(ras_core->dev, "will not read 0 records\n"); 926 return -EINVAL; 927 } else if (num > control->ras_num_recs) { 928 RAS_DEV_ERR(ras_core->dev, 929 "too many records to read:%d available:%d\n", 930 num, control->ras_num_recs); 931 return -EINVAL; 932 } 933 934 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 935 if (!buf) 936 return -ENOMEM; 937 938 /* Determine how many records to read, from the first record 939 * index, fri, to the end of the table, and from the beginning 940 * of the table, such that the total number of records is 941 * @num, and we handle wrap around when fri > 0 and 942 * fri + num > RAS_MAX_RECORD_COUNT. 943 * 944 * First we compute the index of the last element 945 * which would be fetched from each region, 946 * g0 is in [fri, fri + num - 1], and 947 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1]. 948 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of 949 * the last element to fetch, we set g0 to _the number_ 950 * of elements to fetch, @num, since we know that the last 951 * indexed to be fetched does not exceed the table. 952 * 953 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then 954 * we set g0 to the number of elements to read 955 * until the end of the table, and g1 to the number of 956 * elements to read from the beginning of the table. 957 */ 958 g0 = control->ras_fri + num - 1; 959 g1 = g0 % control->ras_max_record_count; 960 if (g0 < control->ras_max_record_count) { 961 g0 = num; 962 g1 = 0; 963 } else { 964 g0 = control->ras_max_record_count - control->ras_fri; 965 g1 += 1; 966 } 967 968 mutex_lock(&control->ras_tbl_mutex); 969 res = __ras_eeprom_read(control, buf, control->ras_fri, g0); 970 if (res) 971 goto Out; 972 if (g1) { 973 res = __ras_eeprom_read(control, 974 buf + g0 * RAS_TABLE_RECORD_SIZE, 0, g1); 975 if (res) 976 goto Out; 977 } 978 979 res = 0; 980 981 /* Read up everything? Then transform. 982 */ 983 pp = buf; 984 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 985 __decode_table_record_from_buf(control, &record[i], pp); 986 987 /* update bad channel bitmap */ 988 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && 989 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 990 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 991 control->update_channel_flag = true; 992 } 993 } 994Out: 995 kfree(buf); 996 mutex_unlock(&control->ras_tbl_mutex); 997 998 return res; 999} 1000 1001uint32_t ras_eeprom_max_record_count(struct ras_core_context *ras_core) 1002{ 1003 struct ras_eeprom_control *control = &ras_core->ras_eeprom; 1004 1005 /* get available eeprom table version first before eeprom table init */ 1006 ras_set_eeprom_table_version(control); 1007 1008 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 1009 return RAS_MAX_RECORD_COUNT_V2_1; 1010 else 1011 return RAS_MAX_RECORD_COUNT; 1012} 1013 1014/** 1015 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum 1016 * @control: pointer to control structure 1017 * 1018 * Check the checksum of the stored in EEPROM RAS table. 1019 * 1020 * Return 0 if the checksum is correct, 1021 * positive if it is not correct, and 1022 * -errno on I/O error. 1023 */ 1024static int __verify_ras_table_checksum(struct ras_eeprom_control *control) 1025{ 1026 struct ras_core_context *ras_core = to_ras_core_context(control); 1027 int buf_size, res; 1028 u8 csum, *buf, *pp; 1029 1030 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) 1031 buf_size = RAS_TABLE_HEADER_SIZE + 1032 RAS_TABLE_V2_1_INFO_SIZE + 1033 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1034 else 1035 buf_size = RAS_TABLE_HEADER_SIZE + 1036 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1037 1038 buf = kzalloc(buf_size, GFP_KERNEL); 1039 if (!buf) { 1040 RAS_DEV_ERR(ras_core->dev, 1041 "Out of memory checking RAS table checksum.\n"); 1042 return -ENOMEM; 1043 } 1044 1045 res = __eeprom_read(ras_core, 1046 control->i2c_address + 1047 control->ras_header_offset, 1048 buf, buf_size); 1049 if (res < buf_size) { 1050 RAS_DEV_ERR(ras_core->dev, 1051 "Partial read for checksum, res:%d\n", res); 1052 /* On partial reads, return -EIO. 1053 */ 1054 if (res >= 0) 1055 res = -EIO; 1056 goto Out; 1057 } 1058 1059 csum = 0; 1060 for (pp = buf; pp < buf + buf_size; pp++) 1061 csum += *pp; 1062Out: 1063 kfree(buf); 1064 return res < 0 ? res : csum; 1065} 1066 1067static int __read_table_ras_info(struct ras_eeprom_control *control) 1068{ 1069 struct ras_eeprom_table_ras_info *rai = &control->tbl_rai; 1070 struct ras_core_context *ras_core = to_ras_core_context(control); 1071 unsigned char *buf; 1072 int res; 1073 1074 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); 1075 if (!buf) { 1076 RAS_DEV_ERR(ras_core->dev, 1077 "Failed to alloc buf to read EEPROM table ras info\n"); 1078 return -ENOMEM; 1079 } 1080 1081 /** 1082 * EEPROM table V2_1 supports ras info, 1083 * read EEPROM table ras info 1084 */ 1085 res = __eeprom_read(ras_core, 1086 control->i2c_address + control->ras_info_offset, 1087 buf, RAS_TABLE_V2_1_INFO_SIZE); 1088 if (res < RAS_TABLE_V2_1_INFO_SIZE) { 1089 RAS_DEV_ERR(ras_core->dev, 1090 "Failed to read EEPROM table ras info, res:%d\n", res); 1091 res = res >= 0 ? -EIO : res; 1092 goto Out; 1093 } 1094 1095 __decode_table_ras_info_from_buf(rai, buf); 1096 1097Out: 1098 kfree(buf); 1099 return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res; 1100} 1101 1102static int __check_ras_table_status(struct ras_core_context *ras_core) 1103{ 1104 struct ras_eeprom_control *control = &ras_core->ras_eeprom; 1105 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 }; 1106 struct ras_eeprom_table_header *hdr; 1107 int res; 1108 1109 hdr = &control->tbl_hdr; 1110 1111 if (!__is_ras_eeprom_supported(ras_core)) 1112 return 0; 1113 1114 if (!__get_eeprom_i2c_addr(ras_core, control)) 1115 return -EINVAL; 1116 1117 control->ras_header_offset = RAS_HDR_START; 1118 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START; 1119 mutex_init(&control->ras_tbl_mutex); 1120 1121 /* Read the table header from EEPROM address */ 1122 res = __eeprom_read(ras_core, 1123 control->i2c_address + control->ras_header_offset, 1124 buf, RAS_TABLE_HEADER_SIZE); 1125 if (res < RAS_TABLE_HEADER_SIZE) { 1126 RAS_DEV_ERR(ras_core->dev, 1127 "Failed to read EEPROM table header, res:%d\n", res); 1128 return res >= 0 ? -EIO : res; 1129 } 1130 1131 __decode_table_header_from_buf(hdr, buf); 1132 1133 if (hdr->header != RAS_TABLE_HDR_VAL && 1134 hdr->header != RAS_TABLE_HDR_BAD) { 1135 RAS_DEV_INFO(ras_core->dev, "Creating a new EEPROM table"); 1136 return ras_eeprom_reset_table(ras_core); 1137 } 1138 1139 switch (hdr->version) { 1140 case RAS_TABLE_VER_V2_1: 1141 case RAS_TABLE_VER_V3: 1142 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr); 1143 control->ras_record_offset = RAS_RECORD_START_V2_1; 1144 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; 1145 break; 1146 case RAS_TABLE_VER_V1: 1147 control->ras_num_recs = RAS_NUM_RECS(hdr); 1148 control->ras_record_offset = RAS_RECORD_START; 1149 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 1150 break; 1151 default: 1152 RAS_DEV_ERR(ras_core->dev, 1153 "RAS header invalid, unsupported version: %u", 1154 hdr->version); 1155 return -EINVAL; 1156 } 1157 1158 if (control->ras_num_recs > control->ras_max_record_count) { 1159 RAS_DEV_ERR(ras_core->dev, 1160 "RAS header invalid, records in header: %u max allowed :%u", 1161 control->ras_num_recs, control->ras_max_record_count); 1162 return -EINVAL; 1163 } 1164 1165 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); 1166 1167 return 0; 1168} 1169 1170int ras_eeprom_check_storage_status(struct ras_core_context *ras_core) 1171{ 1172 struct ras_eeprom_control *control = &ras_core->ras_eeprom; 1173 struct ras_eeprom_table_header *hdr; 1174 int bad_page_count; 1175 int res = 0; 1176 1177 if (!__is_ras_eeprom_supported(ras_core)) 1178 return 0; 1179 1180 if (!__get_eeprom_i2c_addr(ras_core, control)) 1181 return -EINVAL; 1182 1183 hdr = &control->tbl_hdr; 1184 1185 bad_page_count = ras_umc_get_badpage_count(ras_core); 1186 if (hdr->header == RAS_TABLE_HDR_VAL) { 1187 RAS_DEV_INFO(ras_core->dev, 1188 "Found existing EEPROM table with %d records\n", 1189 bad_page_count); 1190 1191 if (hdr->version >= RAS_TABLE_VER_V2_1) { 1192 res = __read_table_ras_info(control); 1193 if (res) 1194 return res; 1195 } 1196 1197 res = __verify_ras_table_checksum(control); 1198 if (res) 1199 RAS_DEV_ERR(ras_core->dev, 1200 "RAS table incorrect checksum or error:%d\n", res); 1201 1202 /* Warn if we are at 90% of the threshold or above 1203 */ 1204 if (10 * bad_page_count >= 9 * control->record_threshold_count) 1205 RAS_DEV_WARN(ras_core->dev, 1206 "RAS records:%u exceeds 90%% of threshold:%d\n", 1207 bad_page_count, 1208 control->record_threshold_count); 1209 1210 } else if (hdr->header == RAS_TABLE_HDR_BAD && 1211 control->record_threshold_config != 0) { 1212 if (hdr->version >= RAS_TABLE_VER_V2_1) { 1213 res = __read_table_ras_info(control); 1214 if (res) 1215 return res; 1216 } 1217 1218 res = __verify_ras_table_checksum(control); 1219 if (res) 1220 RAS_DEV_ERR(ras_core->dev, 1221 "RAS Table incorrect checksum or error:%d\n", res); 1222 1223 if (control->record_threshold_count >= bad_page_count) { 1224 /* This means that, the threshold was increased since 1225 * the last time the system was booted, and now, 1226 * ras->record_threshold_count - control->num_recs > 0, 1227 * so that at least one more record can be saved, 1228 * before the page count threshold is reached. 1229 */ 1230 RAS_DEV_INFO(ras_core->dev, 1231 "records:%d threshold:%d, resetting RAS table header signature", 1232 bad_page_count, 1233 control->record_threshold_count); 1234 res = ras_eeprom_correct_header_tag(control, RAS_TABLE_HDR_VAL); 1235 } else { 1236 RAS_DEV_ERR(ras_core->dev, "RAS records:%d exceed threshold:%d", 1237 bad_page_count, control->record_threshold_count); 1238 if ((control->record_threshold_config == WARN_NONSTOP_OVER_THRESHOLD) || 1239 (control->record_threshold_config == NONSTOP_OVER_THRESHOLD)) { 1240 RAS_DEV_WARN(ras_core->dev, 1241 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n"); 1242 res = 0; 1243 } else { 1244 ras_core->is_rma = true; 1245 RAS_DEV_ERR(ras_core->dev, 1246 "User defined threshold is set, runtime service will be halt when threshold is reached\n"); 1247 } 1248 } 1249 } 1250 1251 return res < 0 ? res : 0; 1252} 1253 1254int ras_eeprom_hw_init(struct ras_core_context *ras_core) 1255{ 1256 struct ras_eeprom_control *control; 1257 struct ras_eeprom_config *eeprom_cfg; 1258 1259 if (!ras_core) 1260 return -EINVAL; 1261 1262 ras_core->is_rma = false; 1263 1264 control = &ras_core->ras_eeprom; 1265 1266 memset(control, 0, sizeof(*control)); 1267 1268 eeprom_cfg = &ras_core->config->eeprom_cfg; 1269 control->record_threshold_config = 1270 eeprom_cfg->eeprom_record_threshold_config; 1271 1272 control->record_threshold_count = ras_eeprom_max_record_count(ras_core); 1273 if (eeprom_cfg->eeprom_record_threshold_count < 1274 control->record_threshold_count) 1275 control->record_threshold_count = 1276 eeprom_cfg->eeprom_record_threshold_count; 1277 1278 control->sys_func = eeprom_cfg->eeprom_sys_fn; 1279 control->max_read_len = eeprom_cfg->max_i2c_read_len; 1280 control->max_write_len = eeprom_cfg->max_i2c_write_len; 1281 control->i2c_adapter = eeprom_cfg->eeprom_i2c_adapter; 1282 control->i2c_port = eeprom_cfg->eeprom_i2c_port; 1283 control->i2c_address = eeprom_cfg->eeprom_i2c_addr; 1284 1285 control->update_channel_flag = false; 1286 1287 return __check_ras_table_status(ras_core); 1288} 1289 1290int ras_eeprom_hw_fini(struct ras_core_context *ras_core) 1291{ 1292 struct ras_eeprom_control *control; 1293 1294 if (!ras_core) 1295 return -EINVAL; 1296 1297 control = &ras_core->ras_eeprom; 1298 mutex_destroy(&control->ras_tbl_mutex); 1299 1300 return 0; 1301} 1302 1303uint32_t ras_eeprom_get_record_count(struct ras_core_context *ras_core) 1304{ 1305 if (!ras_core) 1306 return 0; 1307 1308 return ras_core->ras_eeprom.ras_num_recs; 1309} 1310 1311void ras_eeprom_sync_info(struct ras_core_context *ras_core) 1312{ 1313 struct ras_eeprom_control *control; 1314 1315 if (!ras_core) 1316 return; 1317 1318 control = &ras_core->ras_eeprom; 1319 ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM, 1320 &control->ras_num_recs); 1321 ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP, 1322 &control->bad_channel_bitmap); 1323} 1324 1325enum ras_gpu_health_status 1326 ras_eeprom_check_gpu_status(struct ras_core_context *ras_core) 1327{ 1328 struct ras_eeprom_control *control = &ras_core->ras_eeprom; 1329 struct ras_eeprom_table_ras_info *rai = &control->tbl_rai; 1330 1331 if (!__is_ras_eeprom_supported(ras_core) || 1332 !control->record_threshold_config) 1333 return RAS_GPU_HEALTH_NONE; 1334 1335 if (control->tbl_hdr.header == RAS_TABLE_HDR_BAD) 1336 return RAS_GPU_IN_BAD_STATUS; 1337 1338 return rai->rma_status; 1339}
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