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ras_aca_v1_0.h
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linux-6.19.14/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.h
1/* SPDX-License-Identifier: MIT */ 2/* 3 * Copyright 2025 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25#ifndef __RAS_ACA_V1_0_H__ 26#define __RAS_ACA_V1_0_H__ 27#include "ras.h" 28 29#define ACA__REG__FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> l) 30#define ACA_REG_STATUS_VAL(x) ACA__REG__FIELD(x, 63, 63) 31#define ACA_REG_STATUS_OVERFLOW(x) ACA__REG__FIELD(x, 62, 62) 32#define ACA_REG_STATUS_UC(x) ACA__REG__FIELD(x, 61, 61) 33#define ACA_REG_STATUS_EN(x) ACA__REG__FIELD(x, 60, 60) 34#define ACA_REG_STATUS_MISCV(x) ACA__REG__FIELD(x, 59, 59) 35#define ACA_REG_STATUS_ADDRV(x) ACA__REG__FIELD(x, 58, 58) 36#define ACA_REG_STATUS_PCC(x) ACA__REG__FIELD(x, 57, 57) 37#define ACA_REG_STATUS_ERRCOREIDVAL(x) ACA__REG__FIELD(x, 56, 56) 38#define ACA_REG_STATUS_TCC(x) ACA__REG__FIELD(x, 55, 55) 39#define ACA_REG_STATUS_SYNDV(x) ACA__REG__FIELD(x, 53, 53) 40#define ACA_REG_STATUS_CECC(x) ACA__REG__FIELD(x, 46, 46) 41#define ACA_REG_STATUS_UECC(x) ACA__REG__FIELD(x, 45, 45) 42#define ACA_REG_STATUS_DEFERRED(x) ACA__REG__FIELD(x, 44, 44) 43#define ACA_REG_STATUS_POISON(x) ACA__REG__FIELD(x, 43, 43) 44#define ACA_REG_STATUS_SCRUB(x) ACA__REG__FIELD(x, 40, 40) 45#define ACA_REG_STATUS_ERRCOREID(x) ACA__REG__FIELD(x, 37, 32) 46#define ACA_REG_STATUS_ADDRLSB(x) ACA__REG__FIELD(x, 29, 24) 47#define ACA_REG_STATUS_ERRORCODEEXT(x) ACA__REG__FIELD(x, 21, 16) 48#define ACA_REG_STATUS_ERRORCODE(x) ACA__REG__FIELD(x, 15, 0) 49 50#define ACA_REG_IPID_MCATYPE(x) ACA__REG__FIELD(x, 63, 48) 51#define ACA_REG_IPID_INSTANCEIDHI(x) ACA__REG__FIELD(x, 47, 44) 52#define ACA_REG_IPID_HARDWAREID(x) ACA__REG__FIELD(x, 43, 32) 53#define ACA_REG_IPID_INSTANCEIDLO(x) ACA__REG__FIELD(x, 31, 0) 54 55#define ACA_REG_MISC0_VALID(x) ACA__REG__FIELD(x, 63, 63) 56#define ACA_REG_MISC0_OVRFLW(x) ACA__REG__FIELD(x, 48, 48) 57#define ACA_REG_MISC0_ERRCNT(x) ACA__REG__FIELD(x, 43, 32) 58 59#define ACA_REG_SYND_ERRORINFORMATION(x) ACA__REG__FIELD(x, 17, 0) 60 61/* NOTE: The following codes refers to the smu header file */ 62#define ACA_EXTERROR_CODE_CE 0x3a 63#define ACA_EXTERROR_CODE_FAULT 0x3b 64 65#define mmSMNAID_XCD0_MCA_SMU 0x36430400 /* SMN AID XCD0 */ 66#define mmSMNAID_XCD1_MCA_SMU 0x38430400 /* SMN AID XCD1 */ 67#define mmSMNXCD_XCD0_MCA_SMU 0x40430400 /* SMN XCD XCD0 */ 68#define mmSMNAID_AID0_MCA_SMU 0x03b30400 /* SMN AID AID0 */ 69 70extern const struct ras_aca_ip_func ras_aca_func_v1_0; 71#endif
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