smu_cmn.c

   1/*
   2 * Copyright 2020 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 */
  22
  23#define SWSMU_CODE_LAYER_L4
  24
  25#include "amdgpu.h"
  26#include "amdgpu_smu.h"
  27#include "smu_cmn.h"
  28#include "soc15_common.h"
  29
  30/*
  31 * DO NOT use these for err/warn/info/debug messages.
  32 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  33 * They are more MGPU friendly.
  34 */
  35#undef pr_err
  36#undef pr_warn
  37#undef pr_info
  38#undef pr_debug
  39
  40#define MP1_C2PMSG_90__CONTENT_MASK                                                                    0xFFFFFFFFL
  41
  42const int link_speed[] = {25, 50, 80, 160, 320, 640};
  43
  44#undef __SMU_DUMMY_MAP
  45#define __SMU_DUMMY_MAP(type)	#type
  46static const char * const __smu_message_names[] = {
  47	SMU_MESSAGE_TYPES
  48};
  49
  50#define smu_cmn_call_asic_func(intf, smu, args...)                             \
  51	((smu)->ppt_funcs ? ((smu)->ppt_funcs->intf ?                          \
  52				     (smu)->ppt_funcs->intf(smu, ##args) :     \
  53				     -ENOTSUPP) :                              \
  54			    -EINVAL)
  55
  56static const char *smu_get_message_name(struct smu_context *smu,
  57					enum smu_message_type type)
  58{
  59	if (type >= SMU_MSG_MAX_COUNT)
  60		return "unknown smu message";
  61
  62	return __smu_message_names[type];
  63}
  64
  65static void smu_cmn_read_arg(struct smu_context *smu,
  66			     uint32_t *arg)
  67{
  68	struct amdgpu_device *adev = smu->adev;
  69
  70	*arg = RREG32(smu->param_reg);
  71}
  72
  73/* Redefine the SMU error codes here.
  74 *
  75 * Note that these definitions are redundant and should be removed
  76 * when the SMU has exported a unified header file containing these
  77 * macros, which header file we can just include and use the SMU's
  78 * macros. At the moment, these error codes are defined by the SMU
  79 * per-ASIC unfortunately, yet we're a one driver for all ASICs.
  80 */
  81#define SMU_RESP_NONE           0
  82#define SMU_RESP_OK             1
  83#define SMU_RESP_CMD_FAIL       0xFF
  84#define SMU_RESP_CMD_UNKNOWN    0xFE
  85#define SMU_RESP_CMD_BAD_PREREQ 0xFD
  86#define SMU_RESP_BUSY_OTHER     0xFC
  87#define SMU_RESP_DEBUG_END      0xFB
  88
  89#define SMU_RESP_UNEXP (~0U)
  90/**
  91 * __smu_cmn_poll_stat -- poll for a status from the SMU
  92 * @smu: a pointer to SMU context
  93 *
  94 * Returns the status of the SMU, which could be,
  95 *    0, the SMU is busy with your command;
  96 *    1, execution status: success, execution result: success;
  97 * 0xFF, execution status: success, execution result: failure;
  98 * 0xFE, unknown command;
  99 * 0xFD, valid command, but bad (command) prerequisites;
 100 * 0xFC, the command was rejected as the SMU is busy;
 101 * 0xFB, "SMC_Result_DebugDataDumpEnd".
 102 *
 103 * The values here are not defined by macros, because I'd rather we
 104 * include a single header file which defines them, which is
 105 * maintained by the SMU FW team, so that we're impervious to firmware
 106 * changes. At the moment those values are defined in various header
 107 * files, one for each ASIC, yet here we're a single ASIC-agnostic
 108 * interface. Such a change can be followed-up by a subsequent patch.
 109 */
 110static u32 __smu_cmn_poll_stat(struct smu_context *smu)
 111{
 112	struct amdgpu_device *adev = smu->adev;
 113	int timeout = adev->usec_timeout * 20;
 114	u32 reg;
 115
 116	for ( ; timeout > 0; timeout--) {
 117		reg = RREG32(smu->resp_reg);
 118		if ((reg & MP1_C2PMSG_90__CONTENT_MASK) != 0)
 119			break;
 120
 121		udelay(1);
 122	}
 123
 124	return reg;
 125}
 126
 127static void __smu_cmn_reg_print_error(struct smu_context *smu,
 128				      u32 reg_c2pmsg_90,
 129				      int msg_index,
 130				      u32 param,
 131				      enum smu_message_type msg)
 132{
 133	struct amdgpu_device *adev = smu->adev;
 134	const char *message = smu_get_message_name(smu, msg);
 135	u32 msg_idx, prm;
 136
 137	switch (reg_c2pmsg_90) {
 138	case SMU_RESP_NONE: {
 139		msg_idx = RREG32(smu->msg_reg);
 140		prm     = RREG32(smu->param_reg);
 141		dev_err_ratelimited(adev->dev,
 142				    "SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x%08X SMN_C2PMSG_82:0x%08X",
 143				    msg_idx, prm);
 144		}
 145		break;
 146	case SMU_RESP_OK:
 147		/* The SMU executed the command. It completed with a
 148		 * successful result.
 149		 */
 150		break;
 151	case SMU_RESP_CMD_FAIL:
 152		/* The SMU executed the command. It completed with an
 153		 * unsuccessful result.
 154		 */
 155		break;
 156	case SMU_RESP_CMD_UNKNOWN:
 157		dev_err_ratelimited(adev->dev,
 158				    "SMU: unknown command: index:%d param:0x%08X message:%s",
 159				    msg_index, param, message);
 160		break;
 161	case SMU_RESP_CMD_BAD_PREREQ:
 162		dev_err_ratelimited(adev->dev,
 163				    "SMU: valid command, bad prerequisites: index:%d param:0x%08X message:%s",
 164				    msg_index, param, message);
 165		break;
 166	case SMU_RESP_BUSY_OTHER:
 167		/* It is normal for SMU_MSG_GetBadPageCount to return busy
 168		 * so don't print error at this case.
 169		 */
 170		if (msg != SMU_MSG_GetBadPageCount)
 171			dev_err_ratelimited(adev->dev,
 172						"SMU: I'm very busy for your command: index:%d param:0x%08X message:%s",
 173						msg_index, param, message);
 174		break;
 175	case SMU_RESP_DEBUG_END:
 176		dev_err_ratelimited(adev->dev,
 177				    "SMU: I'm debugging!");
 178		break;
 179	case SMU_RESP_UNEXP:
 180		if (amdgpu_device_bus_status_check(smu->adev)) {
 181			/* print error immediately if device is off the bus */
 182			dev_err(adev->dev,
 183				"SMU: response:0x%08X for index:%d param:0x%08X message:%s?",
 184				reg_c2pmsg_90, msg_index, param, message);
 185			break;
 186		}
 187		fallthrough;
 188	default:
 189		dev_err_ratelimited(adev->dev,
 190				    "SMU: response:0x%08X for index:%d param:0x%08X message:%s?",
 191				    reg_c2pmsg_90, msg_index, param, message);
 192		break;
 193	}
 194}
 195
 196static int __smu_cmn_reg2errno(struct smu_context *smu, u32 reg_c2pmsg_90)
 197{
 198	int res;
 199
 200	switch (reg_c2pmsg_90) {
 201	case SMU_RESP_NONE:
 202		/* The SMU is busy--still executing your command.
 203		 */
 204		res = -ETIME;
 205		break;
 206	case SMU_RESP_OK:
 207		res = 0;
 208		break;
 209	case SMU_RESP_CMD_FAIL:
 210		/* Command completed successfully, but the command
 211		 * status was failure.
 212		 */
 213		res = -EIO;
 214		break;
 215	case SMU_RESP_CMD_UNKNOWN:
 216		/* Unknown command--ignored by the SMU.
 217		 */
 218		res = -EOPNOTSUPP;
 219		break;
 220	case SMU_RESP_CMD_BAD_PREREQ:
 221		/* Valid command--bad prerequisites.
 222		 */
 223		res = -EINVAL;
 224		break;
 225	case SMU_RESP_BUSY_OTHER:
 226		/* The SMU is busy with other commands. The client
 227		 * should retry in 10 us.
 228		 */
 229		res = -EBUSY;
 230		break;
 231	default:
 232		/* Unknown or debug response from the SMU.
 233		 */
 234		res = -EREMOTEIO;
 235		break;
 236	}
 237
 238	return res;
 239}
 240
 241static void __smu_cmn_send_msg(struct smu_context *smu,
 242			       u16 msg,
 243			       u32 param)
 244{
 245	struct amdgpu_device *adev = smu->adev;
 246
 247	WREG32(smu->resp_reg, 0);
 248	WREG32(smu->param_reg, param);
 249	WREG32(smu->msg_reg, msg);
 250}
 251
 252static inline uint32_t __smu_cmn_get_msg_flags(struct smu_context *smu,
 253					       enum smu_message_type msg)
 254{
 255	return smu->message_map[msg].flags;
 256}
 257
 258static int __smu_cmn_ras_filter_msg(struct smu_context *smu,
 259				    enum smu_message_type msg, bool *poll)
 260{
 261	struct amdgpu_device *adev = smu->adev;
 262	uint32_t flags, resp;
 263	bool fed_status, pri;
 264
 265	flags = __smu_cmn_get_msg_flags(smu, msg);
 266	*poll = true;
 267
 268	pri = !!(flags & SMU_MSG_NO_PRECHECK);
 269	/* When there is RAS fatal error, FW won't process non-RAS priority
 270	 * messages. Don't allow any messages other than RAS priority messages.
 271	 */
 272	fed_status = amdgpu_ras_get_fed_status(adev);
 273	if (fed_status) {
 274		if (!(flags & SMU_MSG_RAS_PRI)) {
 275			dev_dbg(adev->dev,
 276				"RAS error detected, skip sending %s",
 277				smu_get_message_name(smu, msg));
 278			return -EACCES;
 279		}
 280	}
 281
 282	if (pri || fed_status) {
 283		/* FW will ignore non-priority messages when a RAS fatal error
 284		 * or reset condition is detected. Hence it is possible that a
 285		 * previous message wouldn't have got response. Allow to
 286		 * continue without polling for response status for priority
 287		 * messages.
 288		 */
 289		resp = RREG32(smu->resp_reg);
 290		dev_dbg(adev->dev,
 291			"Sending priority message %s response status: %x",
 292			smu_get_message_name(smu, msg), resp);
 293		if (resp == 0)
 294			*poll = false;
 295	}
 296
 297	return 0;
 298}
 299
 300static int __smu_cmn_send_debug_msg(struct smu_context *smu,
 301			       u32 msg,
 302			       u32 param)
 303{
 304	struct amdgpu_device *adev = smu->adev;
 305
 306	WREG32(smu->debug_param_reg, param);
 307	WREG32(smu->debug_msg_reg, msg);
 308	WREG32(smu->debug_resp_reg, 0);
 309
 310	return 0;
 311}
 312/**
 313 * smu_cmn_send_msg_without_waiting -- send the message; don't wait for status
 314 * @smu: pointer to an SMU context
 315 * @msg_index: message index
 316 * @param: message parameter to send to the SMU
 317 *
 318 * Send a message to the SMU with the parameter passed. Do not wait
 319 * for status/result of the message, thus the "without_waiting".
 320 *
 321 * Return 0 on success, -errno on error if we weren't able to _send_
 322 * the message for some reason. See __smu_cmn_reg2errno() for details
 323 * of the -errno.
 324 */
 325int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
 326				     uint16_t msg_index,
 327				     uint32_t param)
 328{
 329	struct amdgpu_device *adev = smu->adev;
 330	u32 reg;
 331	int res;
 332
 333	if (adev->no_hw_access)
 334		return 0;
 335
 336	if (smu->smc_fw_state == SMU_FW_HANG) {
 337		dev_err(adev->dev, "SMU is in hanged state, failed to send smu message!\n");
 338		res = -EREMOTEIO;
 339		goto Out;
 340	}
 341
 342	if (smu->smc_fw_state == SMU_FW_INIT) {
 343		smu->smc_fw_state = SMU_FW_RUNTIME;
 344	} else {
 345		reg = __smu_cmn_poll_stat(smu);
 346		res = __smu_cmn_reg2errno(smu, reg);
 347		if (reg == SMU_RESP_NONE || res == -EREMOTEIO)
 348			goto Out;
 349	}
 350
 351	__smu_cmn_send_msg(smu, msg_index, param);
 352	res = 0;
 353Out:
 354	if (unlikely(adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) &&
 355	    res && (res != -ETIME)) {
 356		amdgpu_device_halt(adev);
 357		WARN_ON(1);
 358	}
 359
 360	return res;
 361}
 362
 363/**
 364 * smu_cmn_wait_for_response -- wait for response from the SMU
 365 * @smu: pointer to an SMU context
 366 *
 367 * Wait for status from the SMU.
 368 *
 369 * Return 0 on success, -errno on error, indicating the execution
 370 * status and result of the message being waited for. See
 371 * __smu_cmn_reg2errno() for details of the -errno.
 372 */
 373int smu_cmn_wait_for_response(struct smu_context *smu)
 374{
 375	u32 reg;
 376	int res;
 377
 378	reg = __smu_cmn_poll_stat(smu);
 379	res = __smu_cmn_reg2errno(smu, reg);
 380
 381	if (res == -EREMOTEIO)
 382		smu->smc_fw_state = SMU_FW_HANG;
 383
 384	if (unlikely(smu->adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) &&
 385	    res && (res != -ETIME)) {
 386		amdgpu_device_halt(smu->adev);
 387		WARN_ON(1);
 388	}
 389
 390	return res;
 391}
 392
 393/**
 394 * smu_cmn_send_smc_msg_with_param -- send a message with parameter
 395 * @smu: pointer to an SMU context
 396 * @msg: message to send
 397 * @param: parameter to send to the SMU
 398 * @read_arg: pointer to u32 to return a value from the SMU back
 399 *            to the caller
 400 *
 401 * Send the message @msg with parameter @param to the SMU, wait for
 402 * completion of the command, and return back a value from the SMU in
 403 * @read_arg pointer.
 404 *
 405 * Return 0 on success, -errno when a problem is encountered sending
 406 * message or receiving reply. If there is a PCI bus recovery or
 407 * the destination is a virtual GPU which does not allow this message
 408 * type, the message is simply dropped and success is also returned.
 409 * See __smu_cmn_reg2errno() for details of the -errno.
 410 *
 411 * If we weren't able to send the message to the SMU, we also print
 412 * the error to the standard log.
 413 *
 414 * Command completion status is printed only if the -errno is
 415 * -EREMOTEIO, indicating that the SMU returned back an
 416 * undefined/unknown/unspecified result. All other cases are
 417 * well-defined, not printed, but instead given back to the client to
 418 * decide what further to do.
 419 *
 420 * The return value, @read_arg is read back regardless, to give back
 421 * more information to the client, which on error would most likely be
 422 * @param, but we can't assume that. This also eliminates more
 423 * conditionals.
 424 */
 425int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
 426				    enum smu_message_type msg,
 427				    uint32_t param,
 428				    uint32_t *read_arg)
 429{
 430	struct amdgpu_device *adev = smu->adev;
 431	int res, index;
 432	bool poll = true;
 433	u32 reg;
 434
 435	if (adev->no_hw_access)
 436		return 0;
 437
 438	index = smu_cmn_to_asic_specific_index(smu,
 439					       CMN2ASIC_MAPPING_MSG,
 440					       msg);
 441	if (index < 0)
 442		return index == -EACCES ? 0 : index;
 443
 444	mutex_lock(&smu->message_lock);
 445
 446	if (smu->smc_fw_caps & SMU_FW_CAP_RAS_PRI) {
 447		res = __smu_cmn_ras_filter_msg(smu, msg, &poll);
 448		if (res)
 449			goto Out;
 450	}
 451
 452	if (smu->smc_fw_state == SMU_FW_HANG) {
 453		dev_err(adev->dev, "SMU is in hanged state, failed to send smu message!\n");
 454		res = -EREMOTEIO;
 455		goto Out;
 456	} else if (smu->smc_fw_state == SMU_FW_INIT) {
 457		/* Ignore initial smu response register value */
 458		poll = false;
 459		smu->smc_fw_state = SMU_FW_RUNTIME;
 460	}
 461
 462	if (poll) {
 463		reg = __smu_cmn_poll_stat(smu);
 464		res = __smu_cmn_reg2errno(smu, reg);
 465		if (reg == SMU_RESP_NONE || res == -EREMOTEIO) {
 466			__smu_cmn_reg_print_error(smu, reg, index, param, msg);
 467			goto Out;
 468		}
 469	}
 470	__smu_cmn_send_msg(smu, (uint16_t) index, param);
 471	reg = __smu_cmn_poll_stat(smu);
 472	res = __smu_cmn_reg2errno(smu, reg);
 473	if (res != 0) {
 474		if (res == -EREMOTEIO)
 475			smu->smc_fw_state = SMU_FW_HANG;
 476		__smu_cmn_reg_print_error(smu, reg, index, param, msg);
 477	}
 478	if (read_arg) {
 479		smu_cmn_read_arg(smu, read_arg);
 480		dev_dbg(adev->dev, "smu send message: %s(%d) param: 0x%08x, resp: 0x%08x, readval: 0x%08x\n",
 481			smu_get_message_name(smu, msg), index, param, reg, *read_arg);
 482	} else {
 483		dev_dbg(adev->dev, "smu send message: %s(%d) param: 0x%08x, resp: 0x%08x\n",
 484			smu_get_message_name(smu, msg), index, param, reg);
 485	}
 486Out:
 487	if (unlikely(adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) && res) {
 488		amdgpu_device_halt(adev);
 489		WARN_ON(1);
 490	}
 491
 492	mutex_unlock(&smu->message_lock);
 493	return res;
 494}
 495
 496int smu_cmn_send_smc_msg(struct smu_context *smu,
 497			 enum smu_message_type msg,
 498			 uint32_t *read_arg)
 499{
 500	return smu_cmn_send_smc_msg_with_param(smu,
 501					       msg,
 502					       0,
 503					       read_arg);
 504}
 505
 506int smu_cmn_send_debug_smc_msg(struct smu_context *smu,
 507			 uint32_t msg)
 508{
 509	return __smu_cmn_send_debug_msg(smu, msg, 0);
 510}
 511
 512int smu_cmn_send_debug_smc_msg_with_param(struct smu_context *smu,
 513			 uint32_t msg, uint32_t param)
 514{
 515	return __smu_cmn_send_debug_msg(smu, msg, param);
 516}
 517
 518int smu_cmn_to_asic_specific_index(struct smu_context *smu,
 519				   enum smu_cmn2asic_mapping_type type,
 520				   uint32_t index)
 521{
 522	struct cmn2asic_msg_mapping msg_mapping;
 523	struct cmn2asic_mapping mapping;
 524
 525	switch (type) {
 526	case CMN2ASIC_MAPPING_MSG:
 527		if (index >= SMU_MSG_MAX_COUNT ||
 528		    !smu->message_map)
 529			return -EINVAL;
 530
 531		msg_mapping = smu->message_map[index];
 532		if (!msg_mapping.valid_mapping)
 533			return -EINVAL;
 534
 535		if (amdgpu_sriov_vf(smu->adev) &&
 536		    !(msg_mapping.flags & SMU_MSG_VF_FLAG))
 537			return -EACCES;
 538
 539		return msg_mapping.map_to;
 540
 541	case CMN2ASIC_MAPPING_CLK:
 542		if (index >= SMU_CLK_COUNT ||
 543		    !smu->clock_map)
 544			return -EINVAL;
 545
 546		mapping = smu->clock_map[index];
 547		if (!mapping.valid_mapping)
 548			return -EINVAL;
 549
 550		return mapping.map_to;
 551
 552	case CMN2ASIC_MAPPING_FEATURE:
 553		if (index >= SMU_FEATURE_COUNT ||
 554		    !smu->feature_map)
 555			return -EINVAL;
 556
 557		mapping = smu->feature_map[index];
 558		if (!mapping.valid_mapping)
 559			return -EINVAL;
 560
 561		return mapping.map_to;
 562
 563	case CMN2ASIC_MAPPING_TABLE:
 564		if (index >= SMU_TABLE_COUNT ||
 565		    !smu->table_map)
 566			return -EINVAL;
 567
 568		mapping = smu->table_map[index];
 569		if (!mapping.valid_mapping)
 570			return -EINVAL;
 571
 572		return mapping.map_to;
 573
 574	case CMN2ASIC_MAPPING_PWR:
 575		if (index >= SMU_POWER_SOURCE_COUNT ||
 576		    !smu->pwr_src_map)
 577			return -EINVAL;
 578
 579		mapping = smu->pwr_src_map[index];
 580		if (!mapping.valid_mapping)
 581			return -EINVAL;
 582
 583		return mapping.map_to;
 584
 585	case CMN2ASIC_MAPPING_WORKLOAD:
 586		if (index >= PP_SMC_POWER_PROFILE_COUNT ||
 587		    !smu->workload_map)
 588			return -EINVAL;
 589
 590		mapping = smu->workload_map[index];
 591		if (!mapping.valid_mapping)
 592			return -ENOTSUPP;
 593
 594		return mapping.map_to;
 595
 596	default:
 597		return -EINVAL;
 598	}
 599}
 600
 601int smu_cmn_feature_is_supported(struct smu_context *smu,
 602				 enum smu_feature_mask mask)
 603{
 604	struct smu_feature *feature = &smu->smu_feature;
 605	int feature_id;
 606
 607	feature_id = smu_cmn_to_asic_specific_index(smu,
 608						    CMN2ASIC_MAPPING_FEATURE,
 609						    mask);
 610	if (feature_id < 0)
 611		return 0;
 612
 613	WARN_ON(feature_id > feature->feature_num);
 614
 615	return test_bit(feature_id, feature->supported);
 616}
 617
 618static int __smu_get_enabled_features(struct smu_context *smu,
 619			       uint64_t *enabled_features)
 620{
 621	return smu_cmn_call_asic_func(get_enabled_mask, smu, enabled_features);
 622}
 623
 624int smu_cmn_feature_is_enabled(struct smu_context *smu,
 625			       enum smu_feature_mask mask)
 626{
 627	struct amdgpu_device *adev = smu->adev;
 628	uint64_t enabled_features;
 629	int feature_id;
 630
 631	if (__smu_get_enabled_features(smu, &enabled_features)) {
 632		dev_err(adev->dev, "Failed to retrieve enabled ppfeatures!\n");
 633		return 0;
 634	}
 635
 636	/*
 637	 * For Renoir and Cyan Skillfish, they are assumed to have all features
 638	 * enabled. Also considering they have no feature_map available, the
 639	 * check here can avoid unwanted feature_map check below.
 640	 */
 641	if (enabled_features == ULLONG_MAX)
 642		return 1;
 643
 644	feature_id = smu_cmn_to_asic_specific_index(smu,
 645						    CMN2ASIC_MAPPING_FEATURE,
 646						    mask);
 647	if (feature_id < 0)
 648		return 0;
 649
 650	return test_bit(feature_id, (unsigned long *)&enabled_features);
 651}
 652
 653bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
 654				enum smu_clk_type clk_type)
 655{
 656	enum smu_feature_mask feature_id = 0;
 657
 658	switch (clk_type) {
 659	case SMU_MCLK:
 660	case SMU_UCLK:
 661		feature_id = SMU_FEATURE_DPM_UCLK_BIT;
 662		break;
 663	case SMU_GFXCLK:
 664	case SMU_SCLK:
 665		feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
 666		break;
 667	case SMU_SOCCLK:
 668		feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
 669		break;
 670	case SMU_VCLK:
 671	case SMU_VCLK1:
 672		feature_id = SMU_FEATURE_DPM_VCLK_BIT;
 673		break;
 674	case SMU_DCLK:
 675	case SMU_DCLK1:
 676		feature_id = SMU_FEATURE_DPM_DCLK_BIT;
 677		break;
 678	case SMU_FCLK:
 679		feature_id = SMU_FEATURE_DPM_FCLK_BIT;
 680		break;
 681	default:
 682		return true;
 683	}
 684
 685	if (!smu_cmn_feature_is_enabled(smu, feature_id))
 686		return false;
 687
 688	return true;
 689}
 690
 691int smu_cmn_get_enabled_mask(struct smu_context *smu,
 692			     uint64_t *feature_mask)
 693{
 694	uint32_t *feature_mask_high;
 695	uint32_t *feature_mask_low;
 696	int ret = 0, index = 0;
 697
 698	if (!feature_mask)
 699		return -EINVAL;
 700
 701	feature_mask_low = &((uint32_t *)feature_mask)[0];
 702	feature_mask_high = &((uint32_t *)feature_mask)[1];
 703
 704	index = smu_cmn_to_asic_specific_index(smu,
 705						CMN2ASIC_MAPPING_MSG,
 706						SMU_MSG_GetEnabledSmuFeatures);
 707	if (index > 0) {
 708		ret = smu_cmn_send_smc_msg_with_param(smu,
 709						      SMU_MSG_GetEnabledSmuFeatures,
 710						      0,
 711						      feature_mask_low);
 712		if (ret)
 713			return ret;
 714
 715		ret = smu_cmn_send_smc_msg_with_param(smu,
 716						      SMU_MSG_GetEnabledSmuFeatures,
 717						      1,
 718						      feature_mask_high);
 719	} else {
 720		ret = smu_cmn_send_smc_msg(smu,
 721					   SMU_MSG_GetEnabledSmuFeaturesHigh,
 722					   feature_mask_high);
 723		if (ret)
 724			return ret;
 725
 726		ret = smu_cmn_send_smc_msg(smu,
 727					   SMU_MSG_GetEnabledSmuFeaturesLow,
 728					   feature_mask_low);
 729	}
 730
 731	return ret;
 732}
 733
 734uint64_t smu_cmn_get_indep_throttler_status(
 735					const unsigned long dep_status,
 736					const uint8_t *throttler_map)
 737{
 738	uint64_t indep_status = 0;
 739	uint8_t dep_bit = 0;
 740
 741	for_each_set_bit(dep_bit, &dep_status, 32)
 742		indep_status |= 1ULL << throttler_map[dep_bit];
 743
 744	return indep_status;
 745}
 746
 747int smu_cmn_feature_update_enable_state(struct smu_context *smu,
 748					uint64_t feature_mask,
 749					bool enabled)
 750{
 751	int ret = 0;
 752
 753	if (enabled) {
 754		ret = smu_cmn_send_smc_msg_with_param(smu,
 755						  SMU_MSG_EnableSmuFeaturesLow,
 756						  lower_32_bits(feature_mask),
 757						  NULL);
 758		if (ret)
 759			return ret;
 760		ret = smu_cmn_send_smc_msg_with_param(smu,
 761						  SMU_MSG_EnableSmuFeaturesHigh,
 762						  upper_32_bits(feature_mask),
 763						  NULL);
 764	} else {
 765		ret = smu_cmn_send_smc_msg_with_param(smu,
 766						  SMU_MSG_DisableSmuFeaturesLow,
 767						  lower_32_bits(feature_mask),
 768						  NULL);
 769		if (ret)
 770			return ret;
 771		ret = smu_cmn_send_smc_msg_with_param(smu,
 772						  SMU_MSG_DisableSmuFeaturesHigh,
 773						  upper_32_bits(feature_mask),
 774						  NULL);
 775	}
 776
 777	return ret;
 778}
 779
 780int smu_cmn_feature_set_enabled(struct smu_context *smu,
 781				enum smu_feature_mask mask,
 782				bool enable)
 783{
 784	int feature_id;
 785
 786	feature_id = smu_cmn_to_asic_specific_index(smu,
 787						    CMN2ASIC_MAPPING_FEATURE,
 788						    mask);
 789	if (feature_id < 0)
 790		return -EINVAL;
 791
 792	return smu_cmn_feature_update_enable_state(smu,
 793					       1ULL << feature_id,
 794					       enable);
 795}
 796
 797#undef __SMU_DUMMY_MAP
 798#define __SMU_DUMMY_MAP(fea)	#fea
 799static const char *__smu_feature_names[] = {
 800	SMU_FEATURE_MASKS
 801};
 802
 803static const char *smu_get_feature_name(struct smu_context *smu,
 804					enum smu_feature_mask feature)
 805{
 806	if (feature >= SMU_FEATURE_COUNT)
 807		return "unknown smu feature";
 808	return __smu_feature_names[feature];
 809}
 810
 811size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
 812				   char *buf)
 813{
 814	int8_t sort_feature[MAX(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)];
 815	uint64_t feature_mask;
 816	int i, feature_index;
 817	uint32_t count = 0;
 818	size_t size = 0;
 819
 820	if (__smu_get_enabled_features(smu, &feature_mask))
 821		return 0;
 822
 823	size =  sysfs_emit_at(buf, size, "features high: 0x%08x low: 0x%08x\n",
 824			upper_32_bits(feature_mask), lower_32_bits(feature_mask));
 825
 826	memset(sort_feature, -1, sizeof(sort_feature));
 827
 828	for (i = 0; i < SMU_FEATURE_COUNT; i++) {
 829		feature_index = smu_cmn_to_asic_specific_index(smu,
 830							       CMN2ASIC_MAPPING_FEATURE,
 831							       i);
 832		if (feature_index < 0)
 833			continue;
 834
 835		sort_feature[feature_index] = i;
 836	}
 837
 838	size += sysfs_emit_at(buf, size, "%-2s. %-20s  %-3s : %-s\n",
 839			"No", "Feature", "Bit", "State");
 840
 841	for (feature_index = 0; feature_index < SMU_FEATURE_MAX; feature_index++) {
 842		if (sort_feature[feature_index] < 0)
 843			continue;
 844
 845		size += sysfs_emit_at(buf, size, "%02d. %-20s (%2d) : %s\n",
 846				count++,
 847				smu_get_feature_name(smu, sort_feature[feature_index]),
 848				feature_index,
 849				!!test_bit(feature_index, (unsigned long *)&feature_mask) ?
 850				"enabled" : "disabled");
 851	}
 852
 853	return size;
 854}
 855
 856int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
 857				uint64_t new_mask)
 858{
 859	int ret = 0;
 860	uint64_t feature_mask;
 861	uint64_t feature_2_enabled = 0;
 862	uint64_t feature_2_disabled = 0;
 863
 864	ret = __smu_get_enabled_features(smu, &feature_mask);
 865	if (ret)
 866		return ret;
 867
 868	feature_2_enabled  = ~feature_mask & new_mask;
 869	feature_2_disabled = feature_mask & ~new_mask;
 870
 871	if (feature_2_enabled) {
 872		ret = smu_cmn_feature_update_enable_state(smu,
 873							  feature_2_enabled,
 874							  true);
 875		if (ret)
 876			return ret;
 877	}
 878	if (feature_2_disabled) {
 879		ret = smu_cmn_feature_update_enable_state(smu,
 880							  feature_2_disabled,
 881							  false);
 882		if (ret)
 883			return ret;
 884	}
 885
 886	return ret;
 887}
 888
 889/**
 890 * smu_cmn_disable_all_features_with_exception - disable all dpm features
 891 *                                               except this specified by
 892 *                                               @mask
 893 *
 894 * @smu:               smu_context pointer
 895 * @mask:              the dpm feature which should not be disabled
 896 *                     SMU_FEATURE_COUNT: no exception, all dpm features
 897 *                     to disable
 898 *
 899 * Returns:
 900 * 0 on success or a negative error code on failure.
 901 */
 902int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
 903						enum smu_feature_mask mask)
 904{
 905	uint64_t features_to_disable = U64_MAX;
 906	int skipped_feature_id;
 907
 908	if (mask != SMU_FEATURE_COUNT) {
 909		skipped_feature_id = smu_cmn_to_asic_specific_index(smu,
 910								    CMN2ASIC_MAPPING_FEATURE,
 911								    mask);
 912		if (skipped_feature_id < 0)
 913			return -EINVAL;
 914
 915		features_to_disable &= ~(1ULL << skipped_feature_id);
 916	}
 917
 918	return smu_cmn_feature_update_enable_state(smu,
 919						   features_to_disable,
 920						   0);
 921}
 922
 923int smu_cmn_get_smc_version(struct smu_context *smu,
 924			    uint32_t *if_version,
 925			    uint32_t *smu_version)
 926{
 927	int ret = 0;
 928
 929	if (!if_version && !smu_version)
 930		return -EINVAL;
 931
 932	if (smu->smc_fw_if_version && smu->smc_fw_version)
 933	{
 934		if (if_version)
 935			*if_version = smu->smc_fw_if_version;
 936
 937		if (smu_version)
 938			*smu_version = smu->smc_fw_version;
 939
 940		return 0;
 941	}
 942
 943	if (if_version) {
 944		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion, if_version);
 945		if (ret)
 946			return ret;
 947
 948		smu->smc_fw_if_version = *if_version;
 949	}
 950
 951	if (smu_version) {
 952		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSmuVersion, smu_version);
 953		if (ret)
 954			return ret;
 955
 956		smu->smc_fw_version = *smu_version;
 957	}
 958
 959	return ret;
 960}
 961
 962int smu_cmn_update_table(struct smu_context *smu,
 963			 enum smu_table_id table_index,
 964			 int argument,
 965			 void *table_data,
 966			 bool drv2smu)
 967{
 968	struct smu_table_context *smu_table = &smu->smu_table;
 969	struct amdgpu_device *adev = smu->adev;
 970	struct smu_table *table = &smu_table->driver_table;
 971	int table_id = smu_cmn_to_asic_specific_index(smu,
 972						      CMN2ASIC_MAPPING_TABLE,
 973						      table_index);
 974	uint32_t table_size;
 975	int ret = 0;
 976	if (!table_data || table_index >= SMU_TABLE_COUNT || table_id < 0)
 977		return -EINVAL;
 978
 979	table_size = smu_table->tables[table_index].size;
 980
 981	if (drv2smu) {
 982		memcpy(table->cpu_addr, table_data, table_size);
 983		/*
 984		 * Flush hdp cache: to guard the content seen by
 985		 * GPU is consitent with CPU.
 986		 */
 987		amdgpu_hdp_flush(adev, NULL);
 988	}
 989
 990	ret = smu_cmn_send_smc_msg_with_param(smu, drv2smu ?
 991					  SMU_MSG_TransferTableDram2Smu :
 992					  SMU_MSG_TransferTableSmu2Dram,
 993					  table_id | ((argument & 0xFFFF) << 16),
 994					  NULL);
 995	if (ret)
 996		return ret;
 997
 998	if (!drv2smu) {
 999		amdgpu_hdp_invalidate(adev, NULL);
1000		memcpy(table_data, table->cpu_addr, table_size);
1001	}
1002
1003	return 0;
1004}
1005
1006int smu_cmn_write_watermarks_table(struct smu_context *smu)
1007{
1008	void *watermarks_table = smu->smu_table.watermarks_table;
1009
1010	if (!watermarks_table)
1011		return -EINVAL;
1012
1013	return smu_cmn_update_table(smu,
1014				    SMU_TABLE_WATERMARKS,
1015				    0,
1016				    watermarks_table,
1017				    true);
1018}
1019
1020int smu_cmn_write_pptable(struct smu_context *smu)
1021{
1022	void *pptable = smu->smu_table.driver_pptable;
1023
1024	return smu_cmn_update_table(smu,
1025				    SMU_TABLE_PPTABLE,
1026				    0,
1027				    pptable,
1028				    true);
1029}
1030
1031int smu_cmn_get_metrics_table(struct smu_context *smu,
1032			      void *metrics_table,
1033			      bool bypass_cache)
1034{
1035	struct smu_table_context *smu_table = &smu->smu_table;
1036	uint32_t table_size =
1037		smu_table->tables[SMU_TABLE_SMU_METRICS].size;
1038	int ret = 0;
1039
1040	if (bypass_cache ||
1041	    !smu_table->metrics_time ||
1042	    time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) {
1043		ret = smu_cmn_update_table(smu,
1044				       SMU_TABLE_SMU_METRICS,
1045				       0,
1046				       smu_table->metrics_table,
1047				       false);
1048		if (ret) {
1049			dev_info(smu->adev->dev, "Failed to export SMU metrics table!\n");
1050			return ret;
1051		}
1052		smu_table->metrics_time = jiffies;
1053	}
1054
1055	if (metrics_table)
1056		memcpy(metrics_table, smu_table->metrics_table, table_size);
1057
1058	return 0;
1059}
1060
1061int smu_cmn_get_combo_pptable(struct smu_context *smu)
1062{
1063	void *pptable = smu->smu_table.combo_pptable;
1064
1065	return smu_cmn_update_table(smu,
1066				    SMU_TABLE_COMBO_PPTABLE,
1067				    0,
1068				    pptable,
1069				    false);
1070}
1071
1072int smu_cmn_set_mp1_state(struct smu_context *smu,
1073			  enum pp_mp1_state mp1_state)
1074{
1075	enum smu_message_type msg;
1076	int ret;
1077
1078	switch (mp1_state) {
1079	case PP_MP1_STATE_SHUTDOWN:
1080		msg = SMU_MSG_PrepareMp1ForShutdown;
1081		break;
1082	case PP_MP1_STATE_UNLOAD:
1083		msg = SMU_MSG_PrepareMp1ForUnload;
1084		break;
1085	case PP_MP1_STATE_RESET:
1086		msg = SMU_MSG_PrepareMp1ForReset;
1087		break;
1088	case PP_MP1_STATE_NONE:
1089	default:
1090		return 0;
1091	}
1092
1093	ret = smu_cmn_send_smc_msg(smu, msg, NULL);
1094	if (ret)
1095		dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
1096
1097	return ret;
1098}
1099
1100bool smu_cmn_is_audio_func_enabled(struct amdgpu_device *adev)
1101{
1102	struct pci_dev *p = NULL;
1103	bool snd_driver_loaded;
1104
1105	/*
1106	 * If the ASIC comes with no audio function, we always assume
1107	 * it is "enabled".
1108	 */
1109	p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
1110			adev->pdev->bus->number, 1);
1111	if (!p)
1112		return true;
1113
1114	snd_driver_loaded = pci_is_enabled(p) ? true : false;
1115
1116	pci_dev_put(p);
1117
1118	return snd_driver_loaded;
1119}
1120
1121static char *smu_soc_policy_get_desc(struct smu_dpm_policy *policy, int level)
1122{
1123	if (level < 0 || !(policy->level_mask & BIT(level)))
1124		return "Invalid";
1125
1126	switch (level) {
1127	case SOC_PSTATE_DEFAULT:
1128		return "soc_pstate_default";
1129	case SOC_PSTATE_0:
1130		return "soc_pstate_0";
1131	case SOC_PSTATE_1:
1132		return "soc_pstate_1";
1133	case SOC_PSTATE_2:
1134		return "soc_pstate_2";
1135	}
1136
1137	return "Invalid";
1138}
1139
1140static struct smu_dpm_policy_desc pstate_policy_desc = {
1141	.name = STR_SOC_PSTATE_POLICY,
1142	.get_desc = smu_soc_policy_get_desc,
1143};
1144
1145void smu_cmn_generic_soc_policy_desc(struct smu_dpm_policy *policy)
1146{
1147	policy->desc = &pstate_policy_desc;
1148}
1149
1150static char *smu_xgmi_plpd_policy_get_desc(struct smu_dpm_policy *policy,
1151					   int level)
1152{
1153	if (level < 0 || !(policy->level_mask & BIT(level)))
1154		return "Invalid";
1155
1156	switch (level) {
1157	case XGMI_PLPD_DISALLOW:
1158		return "plpd_disallow";
1159	case XGMI_PLPD_DEFAULT:
1160		return "plpd_default";
1161	case XGMI_PLPD_OPTIMIZED:
1162		return "plpd_optimized";
1163	}
1164
1165	return "Invalid";
1166}
1167
1168static struct smu_dpm_policy_desc xgmi_plpd_policy_desc = {
1169	.name = STR_XGMI_PLPD_POLICY,
1170	.get_desc = smu_xgmi_plpd_policy_get_desc,
1171};
1172
1173void smu_cmn_generic_plpd_policy_desc(struct smu_dpm_policy *policy)
1174{
1175	policy->desc = &xgmi_plpd_policy_desc;
1176}
1177
1178void smu_cmn_get_backend_workload_mask(struct smu_context *smu,
1179				       u32 workload_mask,
1180				       u32 *backend_workload_mask)
1181{
1182	int workload_type;
1183	u32 profile_mode;
1184
1185	*backend_workload_mask = 0;
1186
1187	for (profile_mode = 0; profile_mode < PP_SMC_POWER_PROFILE_COUNT; profile_mode++) {
1188		if (!(workload_mask & (1 << profile_mode)))
1189			continue;
1190
1191		/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1192		workload_type = smu_cmn_to_asic_specific_index(smu,
1193							       CMN2ASIC_MAPPING_WORKLOAD,
1194							       profile_mode);
1195
1196		if (workload_type < 0)
1197			continue;
1198
1199		*backend_workload_mask |= 1 << workload_type;
1200	}
1201}