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smu_v13_0_6_ppt.h
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linux-6.19.14/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
1/* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef __SMU_13_0_6_PPT_H__ 24#define __SMU_13_0_6_PPT_H__ 25 26#define SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL 0x2 27#define SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL 0x4 28#define SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL 0x2 29#define SMU_CAP(x) SMU_13_0_6_CAPS_##x 30 31typedef enum { 32/*0*/ METRICS_VERSION_V0 = 0, 33/*1*/ METRICS_VERSION_V1 = 1, 34/*2*/ METRICS_VERSION_V2 = 2, 35 36/*3*/ NUM_METRICS = 3 37} METRICS_LIST_e; 38 39struct PPTable_t { 40 uint32_t MaxSocketPowerLimit; 41 uint32_t MaxGfxclkFrequency; 42 uint32_t MinGfxclkFrequency; 43 uint32_t FclkFrequencyTable[4]; 44 uint32_t UclkFrequencyTable[4]; 45 uint32_t SocclkFrequencyTable[4]; 46 uint32_t VclkFrequencyTable[4]; 47 uint32_t DclkFrequencyTable[4]; 48 uint32_t LclkFrequencyTable[4]; 49 uint32_t MaxLclkDpmRange; 50 uint32_t MinLclkDpmRange; 51 uint64_t PublicSerialNumber_AID; 52 uint32_t MaxNodePowerLimit; 53 uint32_t PPT1Max; 54 uint32_t PPT1Min; 55 uint32_t PPT1Default; 56 bool Init; 57}; 58 59enum smu_v13_0_6_caps { 60 SMU_CAP(DPM), 61 SMU_CAP(DPM_POLICY), 62 SMU_CAP(OTHER_END_METRICS), 63 SMU_CAP(SET_UCLK_MAX), 64 SMU_CAP(PCIE_METRICS), 65 SMU_CAP(MCA_DEBUG_MODE), 66 SMU_CAP(PER_INST_METRICS), 67 SMU_CAP(CTF_LIMIT), 68 SMU_CAP(RMA_MSG), 69 SMU_CAP(ACA_SYND), 70 SMU_CAP(SDMA_RESET), 71 SMU_CAP(VCN_RESET), 72 SMU_CAP(STATIC_METRICS), 73 SMU_CAP(HST_LIMIT_METRICS), 74 SMU_CAP(BOARD_VOLTAGE), 75 SMU_CAP(PLDM_VERSION), 76 SMU_CAP(TEMP_METRICS), 77 SMU_CAP(NPM_METRICS), 78 SMU_CAP(RAS_EEPROM), 79 SMU_CAP(FAST_PPT), 80 SMU_CAP(ALL), 81}; 82 83#define SMU_13_0_6_NUM_XGMI_LINKS 8 84#define SMU_13_0_6_MAX_GFX_CLKS 8 85#define SMU_13_0_6_MAX_CLKS 4 86#define SMU_13_0_6_MAX_XCC 8 87#define SMU_13_0_6_MAX_VCN 4 88#define SMU_13_0_6_MAX_JPEG 40 89 90extern void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu); 91bool smu_v13_0_6_cap_supported(struct smu_context *smu, enum smu_v13_0_6_caps cap); 92int smu_v13_0_6_get_static_metrics_table(struct smu_context *smu); 93int smu_v13_0_6_get_metrics_table(struct smu_context *smu, void *metrics_table, 94 bool bypass_cache); 95 96bool smu_v13_0_12_is_dpm_running(struct smu_context *smu); 97int smu_v13_0_12_get_max_metrics_size(void); 98size_t smu_v13_0_12_get_system_metrics_size(void); 99int smu_v13_0_12_setup_driver_pptable(struct smu_context *smu); 100int smu_v13_0_12_get_smu_metrics_data(struct smu_context *smu, 101 MetricsMember_t member, uint32_t *value); 102ssize_t smu_v13_0_12_get_xcp_metrics(struct smu_context *smu, 103 struct amdgpu_xcp *xcp, void *table, 104 void *smu_metrics); 105int smu_v13_0_12_tables_init(struct smu_context *smu); 106void smu_v13_0_12_tables_fini(struct smu_context *smu); 107int smu_v13_0_12_get_npm_data(struct smu_context *smu, 108 enum amd_pp_sensors sensor, 109 uint32_t *value); 110extern const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[]; 111extern const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[]; 112extern const struct smu_temp_funcs smu_v13_0_12_temp_funcs; 113extern const struct ras_smu_drv smu_v13_0_12_ras_smu_drv; 114 115#if defined(SWSMU_CODE_LAYER_L2) 116#include "smu_cmn.h" 117 118/* SMUv 13.0.6 GPU metrics*/ 119#define SMU_13_0_6_METRICS_FIELDS(SMU_SCALAR, SMU_ARRAY) \ 120 SMU_SCALAR(SMU_MATTR(TEMPERATURE_HOTSPOT), SMU_MUNIT(TEMP_1), \ 121 SMU_MTYPE(U16), temperature_hotspot); \ 122 SMU_SCALAR(SMU_MATTR(TEMPERATURE_MEM), SMU_MUNIT(TEMP_1), \ 123 SMU_MTYPE(U16), temperature_mem); \ 124 SMU_SCALAR(SMU_MATTR(TEMPERATURE_VRSOC), SMU_MUNIT(TEMP_1), \ 125 SMU_MTYPE(U16), temperature_vrsoc); \ 126 SMU_SCALAR(SMU_MATTR(CURR_SOCKET_POWER), SMU_MUNIT(POWER_1), \ 127 SMU_MTYPE(U16), curr_socket_power); \ 128 SMU_SCALAR(SMU_MATTR(AVERAGE_GFX_ACTIVITY), SMU_MUNIT(PERCENT), \ 129 SMU_MTYPE(U16), average_gfx_activity); \ 130 SMU_SCALAR(SMU_MATTR(AVERAGE_UMC_ACTIVITY), SMU_MUNIT(PERCENT), \ 131 SMU_MTYPE(U16), average_umc_activity); \ 132 SMU_SCALAR(SMU_MATTR(MEM_MAX_BANDWIDTH), SMU_MUNIT(BW_1), \ 133 SMU_MTYPE(U64), mem_max_bandwidth); \ 134 SMU_SCALAR(SMU_MATTR(ENERGY_ACCUMULATOR), SMU_MUNIT(NONE), \ 135 SMU_MTYPE(U64), energy_accumulator); \ 136 SMU_SCALAR(SMU_MATTR(SYSTEM_CLOCK_COUNTER), SMU_MUNIT(TIME_1), \ 137 SMU_MTYPE(U64), system_clock_counter); \ 138 SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \ 139 SMU_MTYPE(U32), accumulation_counter); \ 140 SMU_SCALAR(SMU_MATTR(PROCHOT_RESIDENCY_ACC), SMU_MUNIT(NONE), \ 141 SMU_MTYPE(U32), prochot_residency_acc); \ 142 SMU_SCALAR(SMU_MATTR(PPT_RESIDENCY_ACC), SMU_MUNIT(NONE), \ 143 SMU_MTYPE(U32), ppt_residency_acc); \ 144 SMU_SCALAR(SMU_MATTR(SOCKET_THM_RESIDENCY_ACC), SMU_MUNIT(NONE), \ 145 SMU_MTYPE(U32), socket_thm_residency_acc); \ 146 SMU_SCALAR(SMU_MATTR(VR_THM_RESIDENCY_ACC), SMU_MUNIT(NONE), \ 147 SMU_MTYPE(U32), vr_thm_residency_acc); \ 148 SMU_SCALAR(SMU_MATTR(HBM_THM_RESIDENCY_ACC), SMU_MUNIT(NONE), \ 149 SMU_MTYPE(U32), hbm_thm_residency_acc); \ 150 SMU_SCALAR(SMU_MATTR(GFXCLK_LOCK_STATUS), SMU_MUNIT(NONE), \ 151 SMU_MTYPE(U32), gfxclk_lock_status); \ 152 SMU_SCALAR(SMU_MATTR(PCIE_LINK_WIDTH), SMU_MUNIT(NONE), \ 153 SMU_MTYPE(U16), pcie_link_width); \ 154 SMU_SCALAR(SMU_MATTR(PCIE_LINK_SPEED), SMU_MUNIT(SPEED_2), \ 155 SMU_MTYPE(U16), pcie_link_speed); \ 156 SMU_SCALAR(SMU_MATTR(XGMI_LINK_WIDTH), SMU_MUNIT(NONE), \ 157 SMU_MTYPE(U16), xgmi_link_width); \ 158 SMU_SCALAR(SMU_MATTR(XGMI_LINK_SPEED), SMU_MUNIT(SPEED_1), \ 159 SMU_MTYPE(U16), xgmi_link_speed); \ 160 SMU_SCALAR(SMU_MATTR(GFX_ACTIVITY_ACC), SMU_MUNIT(PERCENT), \ 161 SMU_MTYPE(U32), gfx_activity_acc); \ 162 SMU_SCALAR(SMU_MATTR(MEM_ACTIVITY_ACC), SMU_MUNIT(PERCENT), \ 163 SMU_MTYPE(U32), mem_activity_acc); \ 164 SMU_SCALAR(SMU_MATTR(PCIE_BANDWIDTH_ACC), SMU_MUNIT(PERCENT), \ 165 SMU_MTYPE(U64), pcie_bandwidth_acc); \ 166 SMU_SCALAR(SMU_MATTR(PCIE_BANDWIDTH_INST), SMU_MUNIT(BW_1), \ 167 SMU_MTYPE(U64), pcie_bandwidth_inst); \ 168 SMU_SCALAR(SMU_MATTR(PCIE_L0_TO_RECOV_COUNT_ACC), SMU_MUNIT(NONE), \ 169 SMU_MTYPE(U64), pcie_l0_to_recov_count_acc); \ 170 SMU_SCALAR(SMU_MATTR(PCIE_REPLAY_COUNT_ACC), SMU_MUNIT(NONE), \ 171 SMU_MTYPE(U64), pcie_replay_count_acc); \ 172 SMU_SCALAR(SMU_MATTR(PCIE_REPLAY_ROVER_COUNT_ACC), SMU_MUNIT(NONE), \ 173 SMU_MTYPE(U64), pcie_replay_rover_count_acc); \ 174 SMU_SCALAR(SMU_MATTR(PCIE_NAK_SENT_COUNT_ACC), SMU_MUNIT(NONE), \ 175 SMU_MTYPE(U32), pcie_nak_sent_count_acc); \ 176 SMU_SCALAR(SMU_MATTR(PCIE_NAK_RCVD_COUNT_ACC), SMU_MUNIT(NONE), \ 177 SMU_MTYPE(U32), pcie_nak_rcvd_count_acc); \ 178 SMU_ARRAY(SMU_MATTR(XGMI_READ_DATA_ACC), SMU_MUNIT(DATA_1), \ 179 SMU_MTYPE(U64), xgmi_read_data_acc, \ 180 SMU_13_0_6_NUM_XGMI_LINKS); \ 181 SMU_ARRAY(SMU_MATTR(XGMI_WRITE_DATA_ACC), SMU_MUNIT(DATA_1), \ 182 SMU_MTYPE(U64), xgmi_write_data_acc, \ 183 SMU_13_0_6_NUM_XGMI_LINKS); \ 184 SMU_ARRAY(SMU_MATTR(XGMI_LINK_STATUS), SMU_MUNIT(NONE), \ 185 SMU_MTYPE(U16), xgmi_link_status, \ 186 SMU_13_0_6_NUM_XGMI_LINKS); \ 187 SMU_SCALAR(SMU_MATTR(FIRMWARE_TIMESTAMP), SMU_MUNIT(TIME_2), \ 188 SMU_MTYPE(U64), firmware_timestamp); \ 189 SMU_ARRAY(SMU_MATTR(CURRENT_GFXCLK), SMU_MUNIT(CLOCK_1), \ 190 SMU_MTYPE(U16), current_gfxclk, SMU_13_0_6_MAX_GFX_CLKS); \ 191 SMU_ARRAY(SMU_MATTR(CURRENT_SOCCLK), SMU_MUNIT(CLOCK_1), \ 192 SMU_MTYPE(U16), current_socclk, SMU_13_0_6_MAX_CLKS); \ 193 SMU_ARRAY(SMU_MATTR(CURRENT_VCLK0), SMU_MUNIT(CLOCK_1), \ 194 SMU_MTYPE(U16), current_vclk0, SMU_13_0_6_MAX_CLKS); \ 195 SMU_ARRAY(SMU_MATTR(CURRENT_DCLK0), SMU_MUNIT(CLOCK_1), \ 196 SMU_MTYPE(U16), current_dclk0, SMU_13_0_6_MAX_CLKS); \ 197 SMU_SCALAR(SMU_MATTR(CURRENT_UCLK), SMU_MUNIT(CLOCK_1), \ 198 SMU_MTYPE(U16), current_uclk); \ 199 SMU_SCALAR(SMU_MATTR(PCIE_LC_PERF_OTHER_END_RECOVERY), \ 200 SMU_MUNIT(NONE), SMU_MTYPE(U32), \ 201 pcie_lc_perf_other_end_recovery); \ 202 SMU_ARRAY(SMU_MATTR(GFX_BUSY_INST), SMU_MUNIT(PERCENT), \ 203 SMU_MTYPE(U32), gfx_busy_inst, SMU_13_0_6_MAX_XCC); \ 204 SMU_ARRAY(SMU_MATTR(JPEG_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U16), \ 205 jpeg_busy, SMU_13_0_6_MAX_JPEG); \ 206 SMU_ARRAY(SMU_MATTR(VCN_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U16), \ 207 vcn_busy, SMU_13_0_6_MAX_VCN); \ 208 SMU_ARRAY(SMU_MATTR(GFX_BUSY_ACC), SMU_MUNIT(PERCENT), SMU_MTYPE(U64), \ 209 gfx_busy_acc, SMU_13_0_6_MAX_XCC); \ 210 SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_PPT_ACC), SMU_MUNIT(NONE), \ 211 SMU_MTYPE(U64), gfx_below_host_limit_ppt_acc, \ 212 SMU_13_0_6_MAX_XCC); \ 213 SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_THM_ACC), SMU_MUNIT(NONE), \ 214 SMU_MTYPE(U64), gfx_below_host_limit_thm_acc, \ 215 SMU_13_0_6_MAX_XCC); \ 216 SMU_ARRAY(SMU_MATTR(GFX_LOW_UTILIZATION_ACC), SMU_MUNIT(NONE), \ 217 SMU_MTYPE(U64), gfx_low_utilization_acc, \ 218 SMU_13_0_6_MAX_XCC); \ 219 SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_TOTAL_ACC), SMU_MUNIT(NONE), \ 220 SMU_MTYPE(U64), gfx_below_host_limit_total_acc, \ 221 SMU_13_0_6_MAX_XCC); 222 223DECLARE_SMU_METRICS_CLASS(smu_v13_0_6_gpu_metrics, SMU_13_0_6_METRICS_FIELDS); 224void smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, 225 void *smu_metrics, 226 struct smu_v13_0_6_gpu_metrics *gpu_metrics); 227 228#define SMU_13_0_6_PARTITION_METRICS_FIELDS(SMU_SCALAR, SMU_ARRAY) \ 229 SMU_ARRAY(SMU_MATTR(CURRENT_GFXCLK), SMU_MUNIT(CLOCK_1), \ 230 SMU_MTYPE(U16), current_gfxclk, SMU_13_0_6_MAX_XCC); \ 231 SMU_ARRAY(SMU_MATTR(CURRENT_SOCCLK), SMU_MUNIT(CLOCK_1), \ 232 SMU_MTYPE(U16), current_socclk, SMU_13_0_6_MAX_CLKS); \ 233 SMU_ARRAY(SMU_MATTR(CURRENT_VCLK0), SMU_MUNIT(CLOCK_1), \ 234 SMU_MTYPE(U16), current_vclk0, SMU_13_0_6_MAX_CLKS); \ 235 SMU_ARRAY(SMU_MATTR(CURRENT_DCLK0), SMU_MUNIT(CLOCK_1), \ 236 SMU_MTYPE(U16), current_dclk0, SMU_13_0_6_MAX_CLKS); \ 237 SMU_SCALAR(SMU_MATTR(CURRENT_UCLK), SMU_MUNIT(CLOCK_1), \ 238 SMU_MTYPE(U16), current_uclk); \ 239 SMU_ARRAY(SMU_MATTR(GFX_BUSY_INST), SMU_MUNIT(PERCENT), \ 240 SMU_MTYPE(U32), gfx_busy_inst, SMU_13_0_6_MAX_XCC); \ 241 SMU_ARRAY(SMU_MATTR(JPEG_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U16), \ 242 jpeg_busy, SMU_13_0_6_MAX_JPEG); \ 243 SMU_ARRAY(SMU_MATTR(VCN_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U16), \ 244 vcn_busy, SMU_13_0_6_MAX_VCN); \ 245 SMU_ARRAY(SMU_MATTR(GFX_BUSY_ACC), SMU_MUNIT(PERCENT), SMU_MTYPE(U64), \ 246 gfx_busy_acc, SMU_13_0_6_MAX_XCC); \ 247 SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_PPT_ACC), SMU_MUNIT(NONE), \ 248 SMU_MTYPE(U64), gfx_below_host_limit_ppt_acc, \ 249 SMU_13_0_6_MAX_XCC); \ 250 SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_THM_ACC), SMU_MUNIT(NONE), \ 251 SMU_MTYPE(U64), gfx_below_host_limit_thm_acc, \ 252 SMU_13_0_6_MAX_XCC); \ 253 SMU_ARRAY(SMU_MATTR(GFX_LOW_UTILIZATION_ACC), SMU_MUNIT(NONE), \ 254 SMU_MTYPE(U64), gfx_low_utilization_acc, \ 255 SMU_13_0_6_MAX_XCC); \ 256 SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_TOTAL_ACC), SMU_MUNIT(NONE), \ 257 SMU_MTYPE(U64), gfx_below_host_limit_total_acc, \ 258 SMU_13_0_6_MAX_XCC); 259 260DECLARE_SMU_METRICS_CLASS(smu_v13_0_6_partition_metrics, 261 SMU_13_0_6_PARTITION_METRICS_FIELDS); 262 263#endif /* SWSMU_CODE_LAYER_L2 */ 264 265#endif
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