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smu_v13_0_12_ppt.c
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linux-6.19.14/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
1/* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#define SWSMU_CODE_LAYER_L2 25 26#include <linux/firmware.h> 27#include "amdgpu.h" 28#include "amdgpu_smu.h" 29#include "smu_v13_0_12_pmfw.h" 30#include "smu_v13_0_6_ppt.h" 31#include "smu_v13_0_12_ppsmc.h" 32#include "smu_v13_0.h" 33#include "amdgpu_xgmi.h" 34#include "amdgpu_fru_eeprom.h" 35#include <linux/pci.h> 36#include "smu_cmn.h" 37#include "amdgpu_ras.h" 38 39#undef MP1_Public 40#undef smnMP1_FIRMWARE_FLAGS 41 42/* 43 * DO NOT use these for err/warn/info/debug messages. 44 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 45 * They are more MGPU friendly. 46 */ 47#undef pr_err 48#undef pr_warn 49#undef pr_info 50#undef pr_debug 51 52#define SMU_13_0_12_FEA_MAP(smu_feature, smu_13_0_12_feature) \ 53 [smu_feature] = { 1, (smu_13_0_12_feature) } 54 55#define FEATURE_MASK(feature) (1ULL << feature) 56#define SMC_DPM_FEATURE \ 57 (FEATURE_MASK(FEATURE_DATA_CALCULATION) | \ 58 FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_FCLK)) 59 60#define NUM_JPEG_RINGS_FW 10 61#define NUM_JPEG_RINGS_GPU_METRICS(gpu_metrics) \ 62 (ARRAY_SIZE(gpu_metrics->jpeg_busy) / 4) 63 64const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[SMU_FEATURE_COUNT] = { 65 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATION), 66 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK), 67 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK), 68 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK), 69 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK), 70 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK), 71 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK), 72 SMU_13_0_12_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT), 73 SMU_13_0_12_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC), 74 SMU_13_0_12_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL), 75 SMU_13_0_12_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_SMU_CG), 76 SMU_13_0_12_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF), 77 SMU_13_0_12_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL), 78 SMU_13_0_12_FEA_MAP(SMU_FEATURE_SOC_PCC_BIT, FEATURE_SOC_PCC), 79 SMU_13_0_12_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DOWN), 80 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_VCN_BIT, FEATURE_DS_VCN), 81 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_MP1CLK_BIT, FEATURE_DS_MP1CLK), 82 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_MPIOCLK_BIT, FEATURE_DS_MPIOCLK), 83 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_MP0CLK_BIT, FEATURE_DS_MP0CLK), 84 SMU_13_0_12_FEA_MAP(SMU_FEATURE_PIT_BIT, FEATURE_PIT), 85 SMU_13_0_12_FEA_MAP(SMU_FEATURE_HROM_EN_BIT, FEATURE_HROM_EN), 86}; 87 88const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[SMU_MSG_MAX_COUNT] = { 89 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 90 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 91 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 92 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 93 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 94 MSG_MAP(RequestI2cTransaction, PPSMC_MSG_RequestI2cTransaction, 0), 95 MSG_MAP(GetMetricsTable, PPSMC_MSG_GetMetricsTable, 1), 96 MSG_MAP(GetMetricsVersion, PPSMC_MSG_GetMetricsVersion, 1), 97 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1), 98 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1), 99 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 100 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 101 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 102 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 103 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0), 104 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 105 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 106 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 107 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 108 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 109 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), 110 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, SMU_MSG_RAS_PRI | SMU_MSG_NO_PRECHECK), 111 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 112 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 113 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 114 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 115 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0), 116 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0), 117 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0), 118 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0), 119 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0), 120 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0), 121 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0), 122 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0), 123 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0), 124 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0), 125 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxDpmFreq, 1), 126 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxDpmFreq, 1), 127 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxClk, 1), 128 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1), 129 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareForDriverUnload, 0), 130 MSG_MAP(GetCTFLimit, PPSMC_MSG_GetCTFLimit, 0), 131 MSG_MAP(GetThermalLimit, PPSMC_MSG_ReadThrottlerLimit, 0), 132 MSG_MAP(ClearMcaOnRead, PPSMC_MSG_ClearMcaOnRead, 0), 133 MSG_MAP(QueryValidMcaCount, PPSMC_MSG_QueryValidMcaCount, SMU_MSG_RAS_PRI), 134 MSG_MAP(QueryValidMcaCeCount, PPSMC_MSG_QueryValidMcaCeCount, SMU_MSG_RAS_PRI), 135 MSG_MAP(McaBankDumpDW, PPSMC_MSG_McaBankDumpDW, SMU_MSG_RAS_PRI), 136 MSG_MAP(McaBankCeDumpDW, PPSMC_MSG_McaBankCeDumpDW, SMU_MSG_RAS_PRI), 137 MSG_MAP(SelectPLPDMode, PPSMC_MSG_SelectPLPDMode, 0), 138 MSG_MAP(RmaDueToBadPageThreshold, PPSMC_MSG_RmaDueToBadPageThreshold, 0), 139 MSG_MAP(SetThrottlingPolicy, PPSMC_MSG_SetThrottlingPolicy, 0), 140 MSG_MAP(ResetSDMA, PPSMC_MSG_ResetSDMA, 0), 141 MSG_MAP(ResetVCN, PPSMC_MSG_ResetVCN, 0), 142 MSG_MAP(GetStaticMetricsTable, PPSMC_MSG_GetStaticMetricsTable, 1), 143 MSG_MAP(GetSystemMetricsTable, PPSMC_MSG_GetSystemMetricsTable, 1), 144 MSG_MAP(GetRASTableVersion, PPSMC_MSG_GetRasTableVersion, 0), 145 MSG_MAP(GetBadPageCount, PPSMC_MSG_GetBadPageCount, 0), 146 MSG_MAP(GetBadPageMcaAddr, PPSMC_MSG_GetBadPageMcaAddress, 0), 147 MSG_MAP(SetTimestamp, PPSMC_MSG_SetTimestamp, 0), 148 MSG_MAP(GetTimestamp, PPSMC_MSG_GetTimestamp, 0), 149 MSG_MAP(GetBadPageIpid, PPSMC_MSG_GetBadPageIpIdLoHi, 0), 150 MSG_MAP(EraseRasTable, PPSMC_MSG_EraseRasTable, 0), 151 MSG_MAP(SetFastPptLimit, PPSMC_MSG_SetFastPptLimit, 1), 152 MSG_MAP(GetFastPptLimit, PPSMC_MSG_GetFastPptLimit, 1), 153}; 154 155int smu_v13_0_12_tables_init(struct smu_context *smu) 156{ 157 struct amdgpu_baseboard_temp_metrics_v1_0 *baseboard_temp_metrics; 158 struct amdgpu_gpuboard_temp_metrics_v1_0 *gpuboard_temp_metrics; 159 struct smu_table_context *smu_table = &smu->smu_table; 160 struct smu_table *tables = smu_table->tables; 161 struct smu_table_cache *cache; 162 int ret; 163 164 ret = smu_table_cache_init(smu, SMU_TABLE_PMFW_SYSTEM_METRICS, 165 smu_v13_0_12_get_system_metrics_size(), 5); 166 167 if (ret) 168 return ret; 169 170 ret = smu_table_cache_init(smu, SMU_TABLE_BASEBOARD_TEMP_METRICS, 171 sizeof(*baseboard_temp_metrics), 50); 172 if (ret) 173 return ret; 174 /* Initialize base board temperature metrics */ 175 cache = &(tables[SMU_TABLE_BASEBOARD_TEMP_METRICS].cache); 176 baseboard_temp_metrics = 177 (struct amdgpu_baseboard_temp_metrics_v1_0 *) cache->buffer; 178 smu_cmn_init_baseboard_temp_metrics(baseboard_temp_metrics, 1, 0); 179 /* Initialize GPU board temperature metrics */ 180 ret = smu_table_cache_init(smu, SMU_TABLE_GPUBOARD_TEMP_METRICS, 181 sizeof(*gpuboard_temp_metrics), 50); 182 if (ret) { 183 smu_table_cache_fini(smu, SMU_TABLE_PMFW_SYSTEM_METRICS); 184 smu_table_cache_fini(smu, SMU_TABLE_BASEBOARD_TEMP_METRICS); 185 return ret; 186 } 187 cache = &(tables[SMU_TABLE_GPUBOARD_TEMP_METRICS].cache); 188 gpuboard_temp_metrics = (struct amdgpu_gpuboard_temp_metrics_v1_0 *)cache->buffer; 189 smu_cmn_init_gpuboard_temp_metrics(gpuboard_temp_metrics, 1, 0); 190 191 return 0; 192} 193 194void smu_v13_0_12_tables_fini(struct smu_context *smu) 195{ 196 smu_table_cache_fini(smu, SMU_TABLE_BASEBOARD_TEMP_METRICS); 197 smu_table_cache_fini(smu, SMU_TABLE_GPUBOARD_TEMP_METRICS); 198 smu_table_cache_fini(smu, SMU_TABLE_PMFW_SYSTEM_METRICS); 199} 200 201static int smu_v13_0_12_get_enabled_mask(struct smu_context *smu, 202 uint64_t *feature_mask) 203{ 204 int ret; 205 206 ret = smu_cmn_get_enabled_mask(smu, feature_mask); 207 208 if (ret == -EIO) { 209 *feature_mask = 0; 210 ret = 0; 211 } 212 213 return ret; 214} 215 216static int smu_v13_0_12_fru_get_product_info(struct smu_context *smu, 217 StaticMetricsTable_t *static_metrics) 218{ 219 struct amdgpu_fru_info *fru_info; 220 struct amdgpu_device *adev = smu->adev; 221 222 if (!adev->fru_info) { 223 adev->fru_info = kzalloc(sizeof(*adev->fru_info), GFP_KERNEL); 224 if (!adev->fru_info) 225 return -ENOMEM; 226 } 227 228 fru_info = adev->fru_info; 229 strscpy(fru_info->product_number, static_metrics->ProductInfo.ModelNumber, 230 sizeof(fru_info->product_number)); 231 strscpy(fru_info->product_name, static_metrics->ProductInfo.Name, 232 sizeof(fru_info->product_name)); 233 strscpy(fru_info->serial, static_metrics->ProductInfo.Serial, 234 sizeof(fru_info->serial)); 235 strscpy(fru_info->manufacturer_name, static_metrics->ProductInfo.ManufacturerName, 236 sizeof(fru_info->manufacturer_name)); 237 strscpy(fru_info->fru_id, static_metrics->ProductInfo.FruId, 238 sizeof(fru_info->fru_id)); 239 240 return 0; 241} 242 243int smu_v13_0_12_get_max_metrics_size(void) 244{ 245 return max(sizeof(StaticMetricsTable_t), sizeof(MetricsTable_t)); 246} 247 248size_t smu_v13_0_12_get_system_metrics_size(void) 249{ 250 return sizeof(SystemMetricsTable_t); 251} 252 253static void smu_v13_0_12_init_xgmi_data(struct smu_context *smu, 254 StaticMetricsTable_t *static_metrics) 255{ 256 struct smu_table_context *smu_table = &smu->smu_table; 257 uint16_t max_speed; 258 uint8_t max_width; 259 int ret; 260 261 if (smu_table->tables[SMU_TABLE_SMU_METRICS].version >= 0x13) { 262 max_width = (uint8_t)static_metrics->MaxXgmiWidth; 263 max_speed = (uint16_t)static_metrics->MaxXgmiBitrate; 264 ret = 0; 265 } else { 266 MetricsTable_t *metrics = (MetricsTable_t *)smu_table->metrics_table; 267 268 ret = smu_v13_0_6_get_metrics_table(smu, NULL, true); 269 if (!ret) { 270 max_width = (uint8_t)metrics->XgmiWidth; 271 max_speed = (uint16_t)metrics->XgmiBitrate; 272 } 273 } 274 if (!ret) 275 amgpu_xgmi_set_max_speed_width(smu->adev, max_speed, max_width); 276} 277 278int smu_v13_0_12_setup_driver_pptable(struct smu_context *smu) 279{ 280 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 281 struct smu_table_context *smu_table = &smu->smu_table; 282 StaticMetricsTable_t *static_metrics = (StaticMetricsTable_t *)smu_table->metrics_table; 283 struct PPTable_t *pptable = 284 (struct PPTable_t *)smu_table->driver_pptable; 285 uint32_t table_version; 286 int ret, i, n; 287 288 if (!pptable->Init) { 289 ret = smu_v13_0_6_get_static_metrics_table(smu); 290 if (ret) 291 return ret; 292 293 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsVersion, 294 &table_version); 295 if (ret) 296 return ret; 297 smu_table->tables[SMU_TABLE_SMU_METRICS].version = 298 table_version; 299 300 pptable->MaxSocketPowerLimit = 301 SMUQ10_ROUND(static_metrics->MaxSocketPowerLimit); 302 pptable->MaxGfxclkFrequency = 303 SMUQ10_ROUND(static_metrics->MaxGfxclkFrequency); 304 pptable->MinGfxclkFrequency = 305 SMUQ10_ROUND(static_metrics->MinGfxclkFrequency); 306 307 for (i = 0; i < 4; ++i) { 308 pptable->FclkFrequencyTable[i] = 309 SMUQ10_ROUND(static_metrics->FclkFrequencyTable[i]); 310 pptable->UclkFrequencyTable[i] = 311 SMUQ10_ROUND(static_metrics->UclkFrequencyTable[i]); 312 pptable->SocclkFrequencyTable[i] = 313 SMUQ10_ROUND(static_metrics->SocclkFrequencyTable[i]); 314 pptable->VclkFrequencyTable[i] = 315 SMUQ10_ROUND(static_metrics->VclkFrequencyTable[i]); 316 pptable->DclkFrequencyTable[i] = 317 SMUQ10_ROUND(static_metrics->DclkFrequencyTable[i]); 318 pptable->LclkFrequencyTable[i] = 319 SMUQ10_ROUND(static_metrics->LclkFrequencyTable[i]); 320 } 321 322 /* use AID0 serial number by default */ 323 pptable->PublicSerialNumber_AID = 324 static_metrics->PublicSerialNumber_AID[0]; 325 326 amdgpu_device_set_uid(smu->adev->uid_info, AMDGPU_UID_TYPE_SOC, 327 0, pptable->PublicSerialNumber_AID); 328 n = ARRAY_SIZE(static_metrics->PublicSerialNumber_AID); 329 for (i = 0; i < n; i++) { 330 amdgpu_device_set_uid( 331 smu->adev->uid_info, AMDGPU_UID_TYPE_AID, i, 332 static_metrics->PublicSerialNumber_AID[i]); 333 } 334 n = ARRAY_SIZE(static_metrics->PublicSerialNumber_XCD); 335 for (i = 0; i < n; i++) { 336 amdgpu_device_set_uid( 337 smu->adev->uid_info, AMDGPU_UID_TYPE_XCD, i, 338 static_metrics->PublicSerialNumber_XCD[i]); 339 } 340 341 ret = smu_v13_0_12_fru_get_product_info(smu, static_metrics); 342 if (ret) 343 return ret; 344 345 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(BOARD_VOLTAGE))) { 346 if (!static_metrics->InputTelemetryVoltageInmV) { 347 dev_warn(smu->adev->dev, "Invalid board voltage %d\n", 348 static_metrics->InputTelemetryVoltageInmV); 349 } 350 dpm_context->board_volt = static_metrics->InputTelemetryVoltageInmV; 351 } 352 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(PLDM_VERSION)) && 353 static_metrics->pldmVersion[0] != 0xFFFFFFFF) 354 smu->adev->firmware.pldm_version = 355 static_metrics->pldmVersion[0]; 356 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(NPM_METRICS))) 357 pptable->MaxNodePowerLimit = 358 SMUQ10_ROUND(static_metrics->MaxNodePowerLimit); 359 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT)) && 360 static_metrics->PPT1Max) { 361 pptable->PPT1Max = static_metrics->PPT1Max; 362 pptable->PPT1Min = static_metrics->PPT1Min; 363 pptable->PPT1Default = static_metrics->PPT1Default; 364 } 365 smu_v13_0_12_init_xgmi_data(smu, static_metrics); 366 pptable->Init = true; 367 } 368 369 return 0; 370} 371 372bool smu_v13_0_12_is_dpm_running(struct smu_context *smu) 373{ 374 int ret; 375 uint64_t feature_enabled; 376 377 ret = smu_v13_0_12_get_enabled_mask(smu, &feature_enabled); 378 379 if (ret) 380 return false; 381 382 return !!(feature_enabled & SMC_DPM_FEATURE); 383} 384 385int smu_v13_0_12_get_smu_metrics_data(struct smu_context *smu, 386 MetricsMember_t member, 387 uint32_t *value) 388{ 389 struct smu_table_context *smu_table = &smu->smu_table; 390 MetricsTable_t *metrics = (MetricsTable_t *)smu_table->metrics_table; 391 struct amdgpu_device *adev = smu->adev; 392 int xcc_id; 393 394 /* For clocks with multiple instances, only report the first one */ 395 switch (member) { 396 case METRICS_CURR_GFXCLK: 397 case METRICS_AVERAGE_GFXCLK: 398 xcc_id = GET_INST(GC, 0); 399 *value = SMUQ10_ROUND(metrics->GfxclkFrequency[xcc_id]); 400 break; 401 case METRICS_CURR_SOCCLK: 402 case METRICS_AVERAGE_SOCCLK: 403 *value = SMUQ10_ROUND(metrics->SocclkFrequency[0]); 404 break; 405 case METRICS_CURR_UCLK: 406 case METRICS_AVERAGE_UCLK: 407 *value = SMUQ10_ROUND(metrics->UclkFrequency); 408 break; 409 case METRICS_CURR_VCLK: 410 *value = SMUQ10_ROUND(metrics->VclkFrequency[0]); 411 break; 412 case METRICS_CURR_DCLK: 413 *value = SMUQ10_ROUND(metrics->DclkFrequency[0]); 414 break; 415 case METRICS_CURR_FCLK: 416 *value = SMUQ10_ROUND(metrics->FclkFrequency); 417 break; 418 case METRICS_AVERAGE_GFXACTIVITY: 419 *value = SMUQ10_ROUND(metrics->SocketGfxBusy); 420 break; 421 case METRICS_AVERAGE_MEMACTIVITY: 422 *value = SMUQ10_ROUND(metrics->DramBandwidthUtilization); 423 break; 424 case METRICS_CURR_SOCKETPOWER: 425 *value = SMUQ10_ROUND(metrics->SocketPower) << 8; 426 break; 427 case METRICS_TEMPERATURE_HOTSPOT: 428 *value = SMUQ10_ROUND(metrics->MaxSocketTemperature) * 429 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 430 break; 431 case METRICS_TEMPERATURE_MEM: 432 *value = SMUQ10_ROUND(metrics->MaxHbmTemperature) * 433 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 434 break; 435 /* This is the max of all VRs and not just SOC VR. 436 * No need to define another data type for the same. 437 */ 438 case METRICS_TEMPERATURE_VRSOC: 439 *value = SMUQ10_ROUND(metrics->MaxVrTemperature) * 440 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 441 break; 442 default: 443 *value = UINT_MAX; 444 break; 445 } 446 447 return 0; 448} 449 450static int smu_v13_0_12_get_system_metrics_table(struct smu_context *smu) 451{ 452 struct smu_table_context *smu_table = &smu->smu_table; 453 struct smu_table *table = &smu_table->driver_table; 454 struct smu_table *tables = smu_table->tables; 455 struct smu_table *sys_table; 456 int ret; 457 458 sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; 459 if (smu_table_cache_is_valid(sys_table)) 460 return 0; 461 462 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSystemMetricsTable, NULL); 463 if (ret) { 464 dev_info(smu->adev->dev, 465 "Failed to export system metrics table!\n"); 466 return ret; 467 } 468 469 amdgpu_hdp_invalidate(smu->adev, NULL); 470 smu_table_cache_update_time(sys_table, jiffies); 471 memcpy(sys_table->cache.buffer, table->cpu_addr, 472 smu_v13_0_12_get_system_metrics_size()); 473 474 return 0; 475} 476 477static enum amdgpu_node_temp smu_v13_0_12_get_node_sensor_type(NODE_TEMP_e type) 478{ 479 switch (type) { 480 case NODE_TEMP_RETIMER: 481 return AMDGPU_RETIMER_X_TEMP; 482 case NODE_TEMP_IBC_TEMP: 483 return AMDGPU_OAM_X_IBC_TEMP; 484 case NODE_TEMP_IBC_2_TEMP: 485 return AMDGPU_OAM_X_IBC_2_TEMP; 486 case NODE_TEMP_VDD18_VR_TEMP: 487 return AMDGPU_OAM_X_VDD18_VR_TEMP; 488 case NODE_TEMP_04_HBM_B_VR_TEMP: 489 return AMDGPU_OAM_X_04_HBM_B_VR_TEMP; 490 case NODE_TEMP_04_HBM_D_VR_TEMP: 491 return AMDGPU_OAM_X_04_HBM_D_VR_TEMP; 492 default: 493 return -EINVAL; 494 } 495} 496 497static enum amdgpu_vr_temp smu_v13_0_12_get_vr_sensor_type(SVI_TEMP_e type) 498{ 499 switch (type) { 500 case SVI_VDDCR_VDD0_TEMP: 501 return AMDGPU_VDDCR_VDD0_TEMP; 502 case SVI_VDDCR_VDD1_TEMP: 503 return AMDGPU_VDDCR_VDD1_TEMP; 504 case SVI_VDDCR_VDD2_TEMP: 505 return AMDGPU_VDDCR_VDD2_TEMP; 506 case SVI_VDDCR_VDD3_TEMP: 507 return AMDGPU_VDDCR_VDD3_TEMP; 508 case SVI_VDDCR_SOC_A_TEMP: 509 return AMDGPU_VDDCR_SOC_A_TEMP; 510 case SVI_VDDCR_SOC_C_TEMP: 511 return AMDGPU_VDDCR_SOC_C_TEMP; 512 case SVI_VDDCR_SOCIO_A_TEMP: 513 return AMDGPU_VDDCR_SOCIO_A_TEMP; 514 case SVI_VDDCR_SOCIO_C_TEMP: 515 return AMDGPU_VDDCR_SOCIO_C_TEMP; 516 case SVI_VDD_085_HBM_TEMP: 517 return AMDGPU_VDD_085_HBM_TEMP; 518 case SVI_VDDCR_11_HBM_B_TEMP: 519 return AMDGPU_VDDCR_11_HBM_B_TEMP; 520 case SVI_VDDCR_11_HBM_D_TEMP: 521 return AMDGPU_VDDCR_11_HBM_D_TEMP; 522 case SVI_VDD_USR_TEMP: 523 return AMDGPU_VDD_USR_TEMP; 524 case SVI_VDDIO_11_E32_TEMP: 525 return AMDGPU_VDDIO_11_E32_TEMP; 526 default: 527 return -EINVAL; 528 } 529} 530 531static enum amdgpu_system_temp smu_v13_0_12_get_system_sensor_type(SYSTEM_TEMP_e type) 532{ 533 switch (type) { 534 case SYSTEM_TEMP_UBB_FPGA: 535 return AMDGPU_UBB_FPGA_TEMP; 536 case SYSTEM_TEMP_UBB_FRONT: 537 return AMDGPU_UBB_FRONT_TEMP; 538 case SYSTEM_TEMP_UBB_BACK: 539 return AMDGPU_UBB_BACK_TEMP; 540 case SYSTEM_TEMP_UBB_OAM7: 541 return AMDGPU_UBB_OAM7_TEMP; 542 case SYSTEM_TEMP_UBB_IBC: 543 return AMDGPU_UBB_IBC_TEMP; 544 case SYSTEM_TEMP_UBB_UFPGA: 545 return AMDGPU_UBB_UFPGA_TEMP; 546 case SYSTEM_TEMP_UBB_OAM1: 547 return AMDGPU_UBB_OAM1_TEMP; 548 case SYSTEM_TEMP_OAM_0_1_HSC: 549 return AMDGPU_OAM_0_1_HSC_TEMP; 550 case SYSTEM_TEMP_OAM_2_3_HSC: 551 return AMDGPU_OAM_2_3_HSC_TEMP; 552 case SYSTEM_TEMP_OAM_4_5_HSC: 553 return AMDGPU_OAM_4_5_HSC_TEMP; 554 case SYSTEM_TEMP_OAM_6_7_HSC: 555 return AMDGPU_OAM_6_7_HSC_TEMP; 556 case SYSTEM_TEMP_UBB_FPGA_0V72_VR: 557 return AMDGPU_UBB_FPGA_0V72_VR_TEMP; 558 case SYSTEM_TEMP_UBB_FPGA_3V3_VR: 559 return AMDGPU_UBB_FPGA_3V3_VR_TEMP; 560 case SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR: 561 return AMDGPU_RETIMER_0_1_2_3_1V2_VR_TEMP; 562 case SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR: 563 return AMDGPU_RETIMER_4_5_6_7_1V2_VR_TEMP; 564 case SYSTEM_TEMP_RETIMER_0_1_0V9_VR: 565 return AMDGPU_RETIMER_0_1_0V9_VR_TEMP; 566 case SYSTEM_TEMP_RETIMER_4_5_0V9_VR: 567 return AMDGPU_RETIMER_4_5_0V9_VR_TEMP; 568 case SYSTEM_TEMP_RETIMER_2_3_0V9_VR: 569 return AMDGPU_RETIMER_2_3_0V9_VR_TEMP; 570 case SYSTEM_TEMP_RETIMER_6_7_0V9_VR: 571 return AMDGPU_RETIMER_6_7_0V9_VR_TEMP; 572 case SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR: 573 return AMDGPU_OAM_0_1_2_3_3V3_VR_TEMP; 574 case SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR: 575 return AMDGPU_OAM_4_5_6_7_3V3_VR_TEMP; 576 case SYSTEM_TEMP_IBC_HSC: 577 return AMDGPU_IBC_HSC_TEMP; 578 case SYSTEM_TEMP_IBC: 579 return AMDGPU_IBC_TEMP; 580 default: 581 return -EINVAL; 582 } 583} 584 585static bool smu_v13_0_12_is_temp_metrics_supported(struct smu_context *smu, 586 enum smu_temp_metric_type type) 587{ 588 switch (type) { 589 case SMU_TEMP_METRIC_BASEBOARD: 590 if (smu->adev->gmc.xgmi.physical_node_id == 0 && 591 smu->adev->gmc.xgmi.num_physical_nodes > 1 && 592 smu_v13_0_6_cap_supported(smu, SMU_CAP(TEMP_METRICS))) 593 return true; 594 break; 595 case SMU_TEMP_METRIC_GPUBOARD: 596 return smu_v13_0_6_cap_supported(smu, SMU_CAP(TEMP_METRICS)); 597 default: 598 break; 599 } 600 601 return false; 602} 603 604int smu_v13_0_12_get_npm_data(struct smu_context *smu, 605 enum amd_pp_sensors sensor, 606 uint32_t *value) 607{ 608 struct smu_table_context *smu_table = &smu->smu_table; 609 struct PPTable_t *pptable = 610 (struct PPTable_t *)smu_table->driver_pptable; 611 struct smu_table *tables = smu_table->tables; 612 SystemMetricsTable_t *metrics; 613 struct smu_table *sys_table; 614 int ret; 615 616 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(NPM_METRICS))) 617 return -EOPNOTSUPP; 618 619 if (sensor == AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT) { 620 *value = pptable->MaxNodePowerLimit; 621 return 0; 622 } 623 624 ret = smu_v13_0_12_get_system_metrics_table(smu); 625 if (ret) 626 return ret; 627 628 sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; 629 metrics = (SystemMetricsTable_t *)sys_table->cache.buffer; 630 631 switch (sensor) { 632 case AMDGPU_PP_SENSOR_NODEPOWERLIMIT: 633 *value = SMUQ10_ROUND(metrics->NodePowerLimit); 634 break; 635 case AMDGPU_PP_SENSOR_NODEPOWER: 636 *value = SMUQ10_ROUND(metrics->NodePower); 637 break; 638 case AMDGPU_PP_SENSOR_GPPTRESIDENCY: 639 *value = SMUQ10_ROUND(metrics->GlobalPPTResidencyAcc); 640 break; 641 default: 642 return -EINVAL; 643 } 644 645 return ret; 646} 647 648static ssize_t smu_v13_0_12_get_temp_metrics(struct smu_context *smu, 649 enum smu_temp_metric_type type, void *table) 650{ 651 struct amdgpu_baseboard_temp_metrics_v1_0 *baseboard_temp_metrics; 652 struct amdgpu_gpuboard_temp_metrics_v1_0 *gpuboard_temp_metrics; 653 struct smu_table_context *smu_table = &smu->smu_table; 654 struct smu_table *tables = smu_table->tables; 655 SystemMetricsTable_t *metrics; 656 struct smu_table *data_table; 657 struct smu_table *sys_table; 658 int ret, sensor_type; 659 u32 idx, sensors; 660 ssize_t size; 661 662 if (type == SMU_TEMP_METRIC_BASEBOARD) { 663 /* Initialize base board temperature metrics */ 664 data_table = 665 &smu->smu_table.tables[SMU_TABLE_BASEBOARD_TEMP_METRICS]; 666 baseboard_temp_metrics = 667 (struct amdgpu_baseboard_temp_metrics_v1_0 *) 668 data_table->cache.buffer; 669 size = sizeof(*baseboard_temp_metrics); 670 } else { 671 data_table = 672 &smu->smu_table.tables[SMU_TABLE_GPUBOARD_TEMP_METRICS]; 673 gpuboard_temp_metrics = 674 (struct amdgpu_gpuboard_temp_metrics_v1_0 *) 675 data_table->cache.buffer; 676 size = sizeof(*baseboard_temp_metrics); 677 } 678 679 ret = smu_v13_0_12_get_system_metrics_table(smu); 680 if (ret) 681 return ret; 682 683 sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; 684 metrics = (SystemMetricsTable_t *)sys_table->cache.buffer; 685 smu_table_cache_update_time(data_table, jiffies); 686 687 if (type == SMU_TEMP_METRIC_GPUBOARD) { 688 gpuboard_temp_metrics->accumulation_counter = metrics->AccumulationCounter; 689 gpuboard_temp_metrics->label_version = metrics->LabelVersion; 690 gpuboard_temp_metrics->node_id = metrics->NodeIdentifier; 691 692 idx = 0; 693 for (sensors = 0; sensors < NODE_TEMP_MAX_TEMP_ENTRIES; sensors++) { 694 if (metrics->NodeTemperatures[sensors] != -1) { 695 sensor_type = smu_v13_0_12_get_node_sensor_type(sensors); 696 gpuboard_temp_metrics->node_temp[idx] = 697 ((int)metrics->NodeTemperatures[sensors]) & 0xFFFFFF; 698 gpuboard_temp_metrics->node_temp[idx] |= (sensor_type << 24); 699 idx++; 700 } 701 } 702 703 idx = 0; 704 705 for (sensors = 0; sensors < SVI_MAX_TEMP_ENTRIES; sensors++) { 706 if (metrics->VrTemperatures[sensors] != -1) { 707 sensor_type = smu_v13_0_12_get_vr_sensor_type(sensors); 708 gpuboard_temp_metrics->vr_temp[idx] = 709 ((int)metrics->VrTemperatures[sensors]) & 0xFFFFFF; 710 gpuboard_temp_metrics->vr_temp[idx] |= (sensor_type << 24); 711 idx++; 712 } 713 } 714 } else if (type == SMU_TEMP_METRIC_BASEBOARD) { 715 baseboard_temp_metrics->accumulation_counter = metrics->AccumulationCounter; 716 baseboard_temp_metrics->label_version = metrics->LabelVersion; 717 baseboard_temp_metrics->node_id = metrics->NodeIdentifier; 718 719 idx = 0; 720 for (sensors = 0; sensors < SYSTEM_TEMP_MAX_ENTRIES; sensors++) { 721 if (metrics->SystemTemperatures[sensors] != -1) { 722 sensor_type = smu_v13_0_12_get_system_sensor_type(sensors); 723 baseboard_temp_metrics->system_temp[idx] = 724 ((int)metrics->SystemTemperatures[sensors]) & 0xFFFFFF; 725 baseboard_temp_metrics->system_temp[idx] |= (sensor_type << 24); 726 idx++; 727 } 728 } 729 } 730 731 memcpy(table, data_table->cache.buffer, size); 732 733 return size; 734} 735 736ssize_t smu_v13_0_12_get_xcp_metrics(struct smu_context *smu, struct amdgpu_xcp *xcp, void *table, void *smu_metrics) 737{ 738 const u8 num_jpeg_rings = NUM_JPEG_RINGS_FW; 739 struct smu_v13_0_6_partition_metrics *xcp_metrics; 740 struct amdgpu_device *adev = smu->adev; 741 MetricsTable_t *metrics; 742 int inst, j, k, idx; 743 u32 inst_mask; 744 745 metrics = (MetricsTable_t *)smu_metrics; 746 xcp_metrics = (struct smu_v13_0_6_partition_metrics *)table; 747 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 748 idx = 0; 749 for_each_inst(k, inst_mask) { 750 /* Both JPEG and VCN has same instance */ 751 inst = GET_INST(VCN, k); 752 for (j = 0; j < num_jpeg_rings; ++j) { 753 xcp_metrics->jpeg_busy[(idx * num_jpeg_rings) + j] = 754 SMUQ10_ROUND(metrics-> 755 JpegBusy[(inst * num_jpeg_rings) + j]); 756 } 757 xcp_metrics->vcn_busy[idx] = 758 SMUQ10_ROUND(metrics->VcnBusy[inst]); 759 xcp_metrics->current_vclk0[idx] = SMUQ10_ROUND( 760 metrics->VclkFrequency[inst]); 761 xcp_metrics->current_dclk0[idx] = SMUQ10_ROUND( 762 metrics->DclkFrequency[inst]); 763 xcp_metrics->current_socclk[idx] = SMUQ10_ROUND( 764 metrics->SocclkFrequency[inst]); 765 766 idx++; 767 } 768 769 xcp_metrics->current_uclk = 770 SMUQ10_ROUND(metrics->UclkFrequency); 771 772 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); 773 idx = 0; 774 for_each_inst(k, inst_mask) { 775 inst = GET_INST(GC, k); 776 xcp_metrics->current_gfxclk[idx] = SMUQ10_ROUND(metrics->GfxclkFrequency[inst]); 777 xcp_metrics->gfx_busy_inst[idx] = SMUQ10_ROUND(metrics->GfxBusy[inst]); 778 xcp_metrics->gfx_busy_acc[idx] = SMUQ10_ROUND(metrics->GfxBusyAcc[inst]); 779 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(HST_LIMIT_METRICS))) { 780 xcp_metrics->gfx_below_host_limit_ppt_acc[idx] = SMUQ10_ROUND(metrics->GfxclkBelowHostLimitPptAcc[inst]); 781 xcp_metrics->gfx_below_host_limit_thm_acc[idx] = SMUQ10_ROUND(metrics->GfxclkBelowHostLimitThmAcc[inst]); 782 xcp_metrics->gfx_low_utilization_acc[idx] = SMUQ10_ROUND(metrics->GfxclkLowUtilizationAcc[inst]); 783 xcp_metrics->gfx_below_host_limit_total_acc[idx] = SMUQ10_ROUND(metrics->GfxclkBelowHostLimitTotalAcc[inst]); 784 } 785 idx++; 786 } 787 788 return sizeof(*xcp_metrics); 789} 790 791void smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, 792 void *smu_metrics, 793 struct smu_v13_0_6_gpu_metrics *gpu_metrics) 794{ 795 struct amdgpu_device *adev = smu->adev; 796 int ret = 0, xcc_id, inst, i, j; 797 u8 num_jpeg_rings_gpu_metrics; 798 MetricsTable_t *metrics; 799 800 metrics = (MetricsTable_t *)smu_metrics; 801 802 gpu_metrics->temperature_hotspot = 803 SMUQ10_ROUND(metrics->MaxSocketTemperature); 804 /* Individual HBM stack temperature is not reported */ 805 gpu_metrics->temperature_mem = 806 SMUQ10_ROUND(metrics->MaxHbmTemperature); 807 /* Reports max temperature of all voltage rails */ 808 gpu_metrics->temperature_vrsoc = 809 SMUQ10_ROUND(metrics->MaxVrTemperature); 810 811 gpu_metrics->average_gfx_activity = 812 SMUQ10_ROUND(metrics->SocketGfxBusy); 813 gpu_metrics->average_umc_activity = 814 SMUQ10_ROUND(metrics->DramBandwidthUtilization); 815 816 gpu_metrics->mem_max_bandwidth = 817 SMUQ10_ROUND(metrics->MaxDramBandwidth); 818 819 gpu_metrics->curr_socket_power = 820 SMUQ10_ROUND(metrics->SocketPower); 821 /* Energy counter reported in 15.259uJ (2^-16) units */ 822 gpu_metrics->energy_accumulator = metrics->SocketEnergyAcc; 823 824 for (i = 0; i < MAX_GFX_CLKS; i++) { 825 xcc_id = GET_INST(GC, i); 826 if (xcc_id >= 0) 827 gpu_metrics->current_gfxclk[i] = 828 SMUQ10_ROUND(metrics->GfxclkFrequency[xcc_id]); 829 830 if (i < MAX_CLKS) { 831 gpu_metrics->current_socclk[i] = 832 SMUQ10_ROUND(metrics->SocclkFrequency[i]); 833 inst = GET_INST(VCN, i); 834 if (inst >= 0) { 835 gpu_metrics->current_vclk0[i] = 836 SMUQ10_ROUND(metrics->VclkFrequency[inst]); 837 gpu_metrics->current_dclk0[i] = 838 SMUQ10_ROUND(metrics->DclkFrequency[inst]); 839 } 840 } 841 } 842 843 gpu_metrics->current_uclk = SMUQ10_ROUND(metrics->UclkFrequency); 844 845 /* Total accumulated cycle counter */ 846 gpu_metrics->accumulation_counter = metrics->AccumulationCounter; 847 848 /* Accumulated throttler residencies */ 849 gpu_metrics->prochot_residency_acc = metrics->ProchotResidencyAcc; 850 gpu_metrics->ppt_residency_acc = metrics->PptResidencyAcc; 851 gpu_metrics->socket_thm_residency_acc = metrics->SocketThmResidencyAcc; 852 gpu_metrics->vr_thm_residency_acc = metrics->VrThmResidencyAcc; 853 gpu_metrics->hbm_thm_residency_acc = metrics->HbmThmResidencyAcc; 854 855 /* Clock Lock Status. Each bit corresponds to each GFXCLK instance */ 856 gpu_metrics->gfxclk_lock_status = metrics->GfxLockXCDMak >> GET_INST(GC, 0); 857 858 gpu_metrics->pcie_link_width = metrics->PCIeLinkWidth; 859 gpu_metrics->pcie_link_speed = 860 pcie_gen_to_speed(metrics->PCIeLinkSpeed); 861 gpu_metrics->pcie_bandwidth_acc = 862 SMUQ10_ROUND(metrics->PcieBandwidthAcc[0]); 863 gpu_metrics->pcie_bandwidth_inst = 864 SMUQ10_ROUND(metrics->PcieBandwidth[0]); 865 gpu_metrics->pcie_l0_to_recov_count_acc = metrics->PCIeL0ToRecoveryCountAcc; 866 gpu_metrics->pcie_replay_count_acc = metrics->PCIenReplayAAcc; 867 gpu_metrics->pcie_replay_rover_count_acc = 868 metrics->PCIenReplayARolloverCountAcc; 869 gpu_metrics->pcie_nak_sent_count_acc = metrics->PCIeNAKSentCountAcc; 870 gpu_metrics->pcie_nak_rcvd_count_acc = metrics->PCIeNAKReceivedCountAcc; 871 gpu_metrics->pcie_lc_perf_other_end_recovery = metrics->PCIeOtherEndRecoveryAcc; 872 873 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 874 875 gpu_metrics->gfx_activity_acc = SMUQ10_ROUND(metrics->SocketGfxBusyAcc); 876 gpu_metrics->mem_activity_acc = SMUQ10_ROUND(metrics->DramBandwidthUtilizationAcc); 877 878 for (i = 0; i < NUM_XGMI_LINKS; i++) { 879 j = amdgpu_xgmi_get_ext_link(adev, i); 880 if (j < 0 || j >= NUM_XGMI_LINKS) 881 continue; 882 gpu_metrics->xgmi_read_data_acc[j] = 883 SMUQ10_ROUND(metrics->XgmiReadDataSizeAcc[i]); 884 gpu_metrics->xgmi_write_data_acc[j] = 885 SMUQ10_ROUND(metrics->XgmiWriteDataSizeAcc[i]); 886 ret = amdgpu_get_xgmi_link_status(adev, i); 887 if (ret >= 0) 888 gpu_metrics->xgmi_link_status[j] = ret; 889 } 890 891 num_jpeg_rings_gpu_metrics = NUM_JPEG_RINGS_GPU_METRICS(gpu_metrics); 892 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 893 inst = GET_INST(VCN, i); 894 895 for (j = 0; j < num_jpeg_rings_gpu_metrics; ++j) { 896 gpu_metrics->jpeg_busy[(i * num_jpeg_rings_gpu_metrics) + 897 j] = 898 SMUQ10_ROUND( 899 metrics->JpegBusy[(inst * 900 NUM_JPEG_RINGS_FW) + 901 j]); 902 } 903 gpu_metrics->vcn_busy[i] = SMUQ10_ROUND(metrics->VcnBusy[inst]); 904 } 905 906 for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); ++i) { 907 inst = GET_INST(GC, i); 908 gpu_metrics->gfx_busy_inst[i] = 909 SMUQ10_ROUND(metrics->GfxBusy[inst]); 910 gpu_metrics->gfx_busy_acc[i] = 911 SMUQ10_ROUND(metrics->GfxBusyAcc[inst]); 912 if (smu_v13_0_6_cap_supported(smu, 913 SMU_CAP(HST_LIMIT_METRICS))) { 914 gpu_metrics 915 ->gfx_below_host_limit_ppt_acc[i] = SMUQ10_ROUND( 916 metrics->GfxclkBelowHostLimitPptAcc[inst]); 917 gpu_metrics 918 ->gfx_below_host_limit_thm_acc[i] = SMUQ10_ROUND( 919 metrics->GfxclkBelowHostLimitThmAcc[inst]); 920 gpu_metrics->gfx_low_utilization_acc[i] = SMUQ10_ROUND( 921 metrics->GfxclkLowUtilizationAcc[inst]); 922 gpu_metrics->gfx_below_host_limit_total_acc 923 [i] = SMUQ10_ROUND( 924 metrics->GfxclkBelowHostLimitTotalAcc[inst]); 925 } 926 } 927 928 gpu_metrics->xgmi_link_width = metrics->XgmiWidth; 929 gpu_metrics->xgmi_link_speed = metrics->XgmiBitrate; 930 931 gpu_metrics->firmware_timestamp = metrics->Timestamp; 932} 933 934const struct smu_temp_funcs smu_v13_0_12_temp_funcs = { 935 .temp_metrics_is_supported = smu_v13_0_12_is_temp_metrics_supported, 936 .get_temp_metrics = smu_v13_0_12_get_temp_metrics, 937}; 938 939static int smu_v13_0_12_get_ras_table_version(struct amdgpu_device *adev, 940 uint32_t *table_version) 941{ 942 struct smu_context *smu = adev->powerplay.pp_handle; 943 944 return smu_cmn_send_smc_msg_with_param(smu, 945 SMU_MSG_GetRASTableVersion, 0, table_version); 946} 947 948static int smu_v13_0_12_get_badpage_count(struct amdgpu_device *adev, uint32_t *count, 949 uint32_t timeout) 950{ 951 struct smu_context *smu = adev->powerplay.pp_handle; 952 uint64_t end, now; 953 int ret = 0; 954 955 now = (uint64_t)ktime_to_ms(ktime_get()); 956 end = now + timeout; 957 do { 958 ret = smu_cmn_send_smc_msg_with_param(smu, 959 SMU_MSG_GetBadPageCount, 0, count); 960 /* eeprom is not ready */ 961 if (ret != -EBUSY) 962 return ret; 963 mdelay(10); 964 now = (uint64_t)ktime_to_ms(ktime_get()); 965 } while (now < end); 966 967 dev_err(adev->dev, 968 "smu get bad page count timeout!\n"); 969 return ret; 970} 971 972static int smu_v13_0_12_set_timestamp(struct amdgpu_device *adev, uint64_t timestamp) 973{ 974 struct smu_context *smu = adev->powerplay.pp_handle; 975 976 return smu_cmn_send_smc_msg_with_param(smu, 977 SMU_MSG_SetTimestamp, (uint32_t)timestamp, 0); 978} 979 980static int smu_v13_0_12_get_timestamp(struct amdgpu_device *adev, 981 uint16_t index, uint64_t *timestamp) 982{ 983 struct smu_context *smu = adev->powerplay.pp_handle; 984 uint32_t temp; 985 int ret; 986 987 ret = smu_cmn_send_smc_msg_with_param(smu, 988 SMU_MSG_GetTimestamp, index, &temp); 989 if (!ret) 990 *timestamp = temp; 991 992 return ret; 993} 994 995static int smu_v13_0_12_get_badpage_ipid(struct amdgpu_device *adev, 996 uint16_t index, uint64_t *ipid) 997{ 998 struct smu_context *smu = adev->powerplay.pp_handle; 999 uint32_t temp_arg, temp_ipid_lo, temp_ipid_high; 1000 int ret; 1001 1002 temp_arg = index | (1 << 16); 1003 ret = smu_cmn_send_smc_msg_with_param(smu, 1004 SMU_MSG_GetBadPageIpid, temp_arg, &temp_ipid_lo); 1005 if (ret) 1006 return ret; 1007 1008 temp_arg = index | (2 << 16); 1009 ret = smu_cmn_send_smc_msg_with_param(smu, 1010 SMU_MSG_GetBadPageIpid, temp_arg, &temp_ipid_high); 1011 if (!ret) 1012 *ipid = (uint64_t)temp_ipid_high << 32 | temp_ipid_lo; 1013 return ret; 1014} 1015 1016static int smu_v13_0_12_erase_ras_table(struct amdgpu_device *adev, 1017 uint32_t *result) 1018{ 1019 struct smu_context *smu = adev->powerplay.pp_handle; 1020 1021 return smu_cmn_send_smc_msg_with_param(smu, 1022 SMU_MSG_EraseRasTable, 0, result); 1023} 1024 1025static int smu_v13_0_12_get_badpage_mca_addr(struct amdgpu_device *adev, 1026 uint16_t index, uint64_t *mca_addr) 1027{ 1028 struct smu_context *smu = adev->powerplay.pp_handle; 1029 uint32_t temp_arg, temp_addr_lo, temp_addr_high; 1030 int ret; 1031 1032 temp_arg = index | (1 << 16); 1033 ret = smu_cmn_send_smc_msg_with_param(smu, 1034 SMU_MSG_GetBadPageMcaAddr, temp_arg, &temp_addr_lo); 1035 if (ret) 1036 return ret; 1037 1038 temp_arg = index | (2 << 16); 1039 ret = smu_cmn_send_smc_msg_with_param(smu, 1040 SMU_MSG_GetBadPageMcaAddr, temp_arg, &temp_addr_high); 1041 if (!ret) 1042 *mca_addr = (uint64_t)temp_addr_high << 32 | temp_addr_lo; 1043 return ret; 1044} 1045 1046static const struct ras_eeprom_smu_funcs smu_v13_0_12_eeprom_smu_funcs = { 1047 .get_ras_table_version = smu_v13_0_12_get_ras_table_version, 1048 .get_badpage_count = smu_v13_0_12_get_badpage_count, 1049 .get_badpage_mca_addr = smu_v13_0_12_get_badpage_mca_addr, 1050 .set_timestamp = smu_v13_0_12_set_timestamp, 1051 .get_timestamp = smu_v13_0_12_get_timestamp, 1052 .get_badpage_ipid = smu_v13_0_12_get_badpage_ipid, 1053 .erase_ras_table = smu_v13_0_12_erase_ras_table, 1054}; 1055 1056static void smu_v13_0_12_ras_smu_feature_flags(struct amdgpu_device *adev, uint64_t *flags) 1057{ 1058 struct smu_context *smu = adev->powerplay.pp_handle; 1059 1060 if (!flags) 1061 return; 1062 1063 *flags = 0ULL; 1064 1065 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(RAS_EEPROM))) 1066 *flags |= RAS_SMU_FEATURE_BIT__RAS_EEPROM; 1067 1068} 1069 1070const struct ras_smu_drv smu_v13_0_12_ras_smu_drv = { 1071 .smu_eeprom_funcs = &smu_v13_0_12_eeprom_smu_funcs, 1072 .ras_smu_feature_flags = smu_v13_0_12_ras_smu_feature_flags, 1073};
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