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smu_v13_0_0_ppt.c
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linux-6.19.14/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
1/* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#define SWSMU_CODE_LAYER_L2 25 26#include <linux/firmware.h> 27#include <linux/pci.h> 28#include <linux/i2c.h> 29#include "amdgpu.h" 30#include "amdgpu_smu.h" 31#include "atomfirmware.h" 32#include "amdgpu_atomfirmware.h" 33#include "amdgpu_atombios.h" 34#include "smu_v13_0.h" 35#include "smu13_driver_if_v13_0_0.h" 36#include "soc15_common.h" 37#include "atom.h" 38#include "smu_v13_0_0_ppt.h" 39#include "smu_v13_0_0_pptable.h" 40#include "smu_v13_0_0_ppsmc.h" 41#include "nbio/nbio_4_3_0_offset.h" 42#include "nbio/nbio_4_3_0_sh_mask.h" 43#include "mp/mp_13_0_0_offset.h" 44#include "mp/mp_13_0_0_sh_mask.h" 45 46#include "asic_reg/mp/mp_13_0_0_sh_mask.h" 47#include "smu_cmn.h" 48#include "amdgpu_ras.h" 49 50/* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55#undef pr_err 56#undef pr_warn 57#undef pr_info 58#undef pr_debug 59 60#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 62static void smu_v13_0_0_get_od_setting_limits(struct smu_context *smu, 63 int od_feature_bit, 64 int32_t *min, int32_t *max); 65 66#define FEATURE_MASK(feature) (1ULL << feature) 67#define SMC_DPM_FEATURE ( \ 68 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 72 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 73 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) 74 75#define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000 76 77#define mmMP1_SMN_C2PMSG_66 0x0282 78#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 79 80#define mmMP1_SMN_C2PMSG_82 0x0292 81#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 82 83#define mmMP1_SMN_C2PMSG_90 0x029a 84#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 85 86#define mmMP1_SMN_C2PMSG_75 0x028b 87#define mmMP1_SMN_C2PMSG_75_BASE_IDX 0 88 89#define mmMP1_SMN_C2PMSG_53 0x0275 90#define mmMP1_SMN_C2PMSG_53_BASE_IDX 0 91 92#define mmMP1_SMN_C2PMSG_54 0x0276 93#define mmMP1_SMN_C2PMSG_54_BASE_IDX 0 94 95#define DEBUGSMC_MSG_Mode1Reset 2 96 97/* 98 * SMU_v13_0_10 supports ECCTABLE since version 80.34.0, 99 * use this to check ECCTABLE feature whether support 100 */ 101#define SUPPORT_ECCTABLE_SMU_13_0_10_VERSION 0x00502200 102 103#define PP_OD_FEATURE_GFXCLK_FMIN 0 104#define PP_OD_FEATURE_GFXCLK_FMAX 1 105#define PP_OD_FEATURE_UCLK_FMIN 2 106#define PP_OD_FEATURE_UCLK_FMAX 3 107#define PP_OD_FEATURE_GFX_VF_CURVE 4 108#define PP_OD_FEATURE_FAN_CURVE_TEMP 5 109#define PP_OD_FEATURE_FAN_CURVE_PWM 6 110#define PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT 7 111#define PP_OD_FEATURE_FAN_ACOUSTIC_TARGET 8 112#define PP_OD_FEATURE_FAN_TARGET_TEMPERATURE 9 113#define PP_OD_FEATURE_FAN_MINIMUM_PWM 10 114#define PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE 11 115#define PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP 12 116 117#define LINK_SPEED_MAX 3 118 119static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = { 120 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 121 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 122 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 123 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 124 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 125 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 126 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 127 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 128 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 129 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), 130 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), 131 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1), 132 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1), 133 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 0), 134 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 135 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 136 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 137 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 138 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 139 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 140 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 141 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 142 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 143 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 144 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 145 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 146 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 147 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 148 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 149 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 150 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 151 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 152 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 153 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 154 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 155 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 156 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 0), 157 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 158 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 159 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 160 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 161 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 162 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 163 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 164 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 165 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 166 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0), 167 MSG_MAP(Mode2Reset, PPSMC_MSG_Mode2Reset, 0), 168 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 169 MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0), 170 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 171 MSG_MAP(SetNumBadMemoryPagesRetired, PPSMC_MSG_SetNumBadMemoryPagesRetired, 0), 172 MSG_MAP(SetBadMemoryPagesRetiredFlagsPerChannel, 173 PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel, 0), 174 MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow, 0), 175 MSG_MAP(AllowIHHostInterrupt, PPSMC_MSG_AllowIHHostInterrupt, 0), 176 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 177 MSG_MAP(DALNotPresent, PPSMC_MSG_DALNotPresent, 0), 178 MSG_MAP(EnableUCLKShadow, PPSMC_MSG_EnableUCLKShadow, 0), 179}; 180 181static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = { 182 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 183 CLK_MAP(SCLK, PPCLK_GFXCLK), 184 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 185 CLK_MAP(FCLK, PPCLK_FCLK), 186 CLK_MAP(UCLK, PPCLK_UCLK), 187 CLK_MAP(MCLK, PPCLK_UCLK), 188 CLK_MAP(VCLK, PPCLK_VCLK_0), 189 CLK_MAP(VCLK1, PPCLK_VCLK_1), 190 CLK_MAP(DCLK, PPCLK_DCLK_0), 191 CLK_MAP(DCLK1, PPCLK_DCLK_1), 192 CLK_MAP(DCEFCLK, PPCLK_DCFCLK), 193}; 194 195static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] = { 196 FEA_MAP(FW_DATA_READ), 197 FEA_MAP(DPM_GFXCLK), 198 FEA_MAP(DPM_GFX_POWER_OPTIMIZER), 199 FEA_MAP(DPM_UCLK), 200 FEA_MAP(DPM_FCLK), 201 FEA_MAP(DPM_SOCCLK), 202 FEA_MAP(DPM_MP0CLK), 203 FEA_MAP(DPM_LINK), 204 FEA_MAP(DPM_DCN), 205 FEA_MAP(VMEMP_SCALING), 206 FEA_MAP(VDDIO_MEM_SCALING), 207 FEA_MAP(DS_GFXCLK), 208 FEA_MAP(DS_SOCCLK), 209 FEA_MAP(DS_FCLK), 210 FEA_MAP(DS_LCLK), 211 FEA_MAP(DS_DCFCLK), 212 FEA_MAP(DS_UCLK), 213 FEA_MAP(GFX_ULV), 214 FEA_MAP(FW_DSTATE), 215 FEA_MAP(GFXOFF), 216 FEA_MAP(BACO), 217 FEA_MAP(MM_DPM), 218 FEA_MAP(SOC_MPCLK_DS), 219 FEA_MAP(BACO_MPCLK_DS), 220 FEA_MAP(THROTTLERS), 221 FEA_MAP(SMARTSHIFT), 222 FEA_MAP(GTHR), 223 FEA_MAP(ACDC), 224 FEA_MAP(VR0HOT), 225 FEA_MAP(FW_CTF), 226 FEA_MAP(FAN_CONTROL), 227 FEA_MAP(GFX_DCS), 228 FEA_MAP(GFX_READ_MARGIN), 229 FEA_MAP(LED_DISPLAY), 230 FEA_MAP(GFXCLK_SPREAD_SPECTRUM), 231 FEA_MAP(OUT_OF_BAND_MONITOR), 232 FEA_MAP(OPTIMIZED_VMIN), 233 FEA_MAP(GFX_IMU), 234 FEA_MAP(BOOT_TIME_CAL), 235 FEA_MAP(GFX_PCC_DFLL), 236 FEA_MAP(SOC_CG), 237 FEA_MAP(DF_CSTATE), 238 FEA_MAP(GFX_EDC), 239 FEA_MAP(BOOT_POWER_OPT), 240 FEA_MAP(CLOCK_POWER_DOWN_BYPASS), 241 FEA_MAP(DS_VCN), 242 FEA_MAP(BACO_CG), 243 FEA_MAP(MEM_TEMP_READ), 244 FEA_MAP(ATHUB_MMHUB_PG), 245 FEA_MAP(SOC_PCC), 246 [SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT}, 247 [SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT}, 248 [SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT}, 249}; 250 251static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = { 252 TAB_MAP(PPTABLE), 253 TAB_MAP(WATERMARKS), 254 TAB_MAP(AVFS_PSM_DEBUG), 255 TAB_MAP(PMSTATUSLOG), 256 TAB_MAP(SMU_METRICS), 257 TAB_MAP(DRIVER_SMU_CONFIG), 258 TAB_MAP(ACTIVITY_MONITOR_COEFF), 259 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE}, 260 TAB_MAP(I2C_COMMANDS), 261 TAB_MAP(ECCINFO), 262 TAB_MAP(OVERDRIVE), 263 TAB_MAP(WIFIBAND), 264}; 265 266static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 267 PWR_MAP(AC), 268 PWR_MAP(DC), 269}; 270 271static struct cmn2asic_mapping smu_v13_0_0_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 272 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 273 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 274 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 275 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 276 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 277 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 278 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 279 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D, WORKLOAD_PPLIB_WINDOW_3D_BIT), 280}; 281 282static const uint8_t smu_v13_0_0_throttler_map[] = { 283 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 284 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 285 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 286 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 287 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 288 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 289 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 290 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 291 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 292 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 293 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 294 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 295 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 296 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 297 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 298 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT), 299 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 300}; 301 302static int 303smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu, 304 uint32_t *feature_mask, uint32_t num) 305{ 306 struct amdgpu_device *adev = smu->adev; 307 308 if (num > 2) 309 return -EINVAL; 310 311 memset(feature_mask, 0xff, sizeof(uint32_t) * num); 312 313 if (!(adev->pm.pp_feature & PP_SCLK_DPM_MASK)) { 314 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 315 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT); 316 } 317 318 if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) || 319 !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) 320 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); 321 322 if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)) 323 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 324 325 /* PMFW 78.58 contains a critical fix for gfxoff feature */ 326 if ((smu->smc_fw_version < 0x004e3a00) || 327 !(adev->pm.pp_feature & PP_GFXOFF_MASK)) 328 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT); 329 330 if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) { 331 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); 332 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); 333 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); 334 } 335 336 if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)) 337 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 338 339 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { 340 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT); 341 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT); 342 } 343 344 if (!(adev->pm.pp_feature & PP_ULV_MASK)) 345 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT); 346 347 return 0; 348} 349 350static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu) 351{ 352 struct smu_table_context *table_context = &smu->smu_table; 353 struct smu_13_0_0_powerplay_table *powerplay_table = 354 table_context->power_play_table; 355 struct smu_baco_context *smu_baco = &smu->smu_baco; 356 PPTable_t *pptable = smu->smu_table.driver_pptable; 357 const OverDriveLimits_t * const overdrive_upperlimits = 358 &pptable->SkuTable.OverDriveLimitsBasicMax; 359 const OverDriveLimits_t * const overdrive_lowerlimits = 360 &pptable->SkuTable.OverDriveLimitsMin; 361 362 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC) 363 smu->dc_controlled_by_gpio = true; 364 365 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO) { 366 smu_baco->platform_support = true; 367 368 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO) 369 smu_baco->maco_support = true; 370 } 371 372 if (!overdrive_lowerlimits->FeatureCtrlMask || 373 !overdrive_upperlimits->FeatureCtrlMask) 374 smu->od_enabled = false; 375 376 table_context->thermal_controller_type = 377 powerplay_table->thermal_controller_type; 378 379 /* 380 * Instead of having its own buffer space and get overdrive_table copied, 381 * smu->od_settings just points to the actual overdrive_table 382 */ 383 smu->od_settings = &powerplay_table->overdrive_table; 384 385 smu->adev->pm.no_fan = 386 !(pptable->SkuTable.FeaturesToRun[0] & (1 << FEATURE_FAN_CONTROL_BIT)); 387 388 return 0; 389} 390 391static int smu_v13_0_0_store_powerplay_table(struct smu_context *smu) 392{ 393 struct smu_table_context *table_context = &smu->smu_table; 394 struct smu_13_0_0_powerplay_table *powerplay_table = 395 table_context->power_play_table; 396 397 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 398 sizeof(PPTable_t)); 399 400 return 0; 401} 402 403#ifndef atom_smc_dpm_info_table_13_0_0 404struct atom_smc_dpm_info_table_13_0_0 { 405 struct atom_common_table_header table_header; 406 BoardTable_t BoardTable; 407}; 408#endif 409 410static int smu_v13_0_0_append_powerplay_table(struct smu_context *smu) 411{ 412 struct smu_table_context *table_context = &smu->smu_table; 413 PPTable_t *smc_pptable = table_context->driver_pptable; 414 struct atom_smc_dpm_info_table_13_0_0 *smc_dpm_table; 415 BoardTable_t *BoardTable = &smc_pptable->BoardTable; 416 int index, ret; 417 418 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 419 smc_dpm_info); 420 421 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 422 (uint8_t **)&smc_dpm_table); 423 if (ret) 424 return ret; 425 426 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t)); 427 428 return 0; 429} 430 431static int smu_v13_0_0_get_pptable_from_pmfw(struct smu_context *smu, 432 void **table, 433 uint32_t *size) 434{ 435 struct smu_table_context *smu_table = &smu->smu_table; 436 void *combo_pptable = smu_table->combo_pptable; 437 int ret = 0; 438 439 ret = smu_cmn_get_combo_pptable(smu); 440 if (ret) 441 return ret; 442 443 *table = combo_pptable; 444 *size = sizeof(struct smu_13_0_0_powerplay_table); 445 446 return 0; 447} 448 449static int smu_v13_0_0_setup_pptable(struct smu_context *smu) 450{ 451 struct smu_table_context *smu_table = &smu->smu_table; 452 struct amdgpu_device *adev = smu->adev; 453 int ret = 0; 454 455 if (amdgpu_sriov_vf(smu->adev)) 456 return 0; 457 458 ret = smu_v13_0_0_get_pptable_from_pmfw(smu, 459 &smu_table->power_play_table, 460 &smu_table->power_play_table_size); 461 if (ret) 462 return ret; 463 464 ret = smu_v13_0_0_store_powerplay_table(smu); 465 if (ret) 466 return ret; 467 468 /* 469 * With SCPM enabled, the operation below will be handled 470 * by PSP. Driver involvment is unnecessary and useless. 471 */ 472 if (!adev->scpm_enabled) { 473 ret = smu_v13_0_0_append_powerplay_table(smu); 474 if (ret) 475 return ret; 476 } 477 478 ret = smu_v13_0_0_check_powerplay_table(smu); 479 if (ret) 480 return ret; 481 482 return ret; 483} 484 485static int smu_v13_0_0_tables_init(struct smu_context *smu) 486{ 487 struct smu_table_context *smu_table = &smu->smu_table; 488 struct smu_table *tables = smu_table->tables; 489 490 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 491 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 492 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 493 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 494 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t), 495 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 496 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 497 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 498 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTableExternal_t), 499 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 500 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, 501 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 502 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 503 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE, 504 AMDGPU_GEM_DOMAIN_VRAM); 505 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE, 506 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 507 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t), 508 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 509 SMU_TABLE_INIT(tables, SMU_TABLE_WIFIBAND, 510 sizeof(WifiBandEntryTable_t), PAGE_SIZE, 511 AMDGPU_GEM_DOMAIN_VRAM); 512 513 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL); 514 if (!smu_table->metrics_table) 515 goto err0_out; 516 smu_table->metrics_time = 0; 517 518 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 519 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 520 if (!smu_table->gpu_metrics_table) 521 goto err1_out; 522 523 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 524 if (!smu_table->watermarks_table) 525 goto err2_out; 526 527 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL); 528 if (!smu_table->ecc_table) 529 goto err3_out; 530 531 return 0; 532 533err3_out: 534 kfree(smu_table->watermarks_table); 535err2_out: 536 kfree(smu_table->gpu_metrics_table); 537err1_out: 538 kfree(smu_table->metrics_table); 539err0_out: 540 return -ENOMEM; 541} 542 543static int smu_v13_0_0_allocate_dpm_context(struct smu_context *smu) 544{ 545 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 546 547 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 548 GFP_KERNEL); 549 if (!smu_dpm->dpm_context) 550 return -ENOMEM; 551 552 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); 553 554 return 0; 555} 556 557static int smu_v13_0_0_init_smc_tables(struct smu_context *smu) 558{ 559 int ret = 0; 560 561 ret = smu_v13_0_0_tables_init(smu); 562 if (ret) 563 return ret; 564 565 ret = smu_v13_0_0_allocate_dpm_context(smu); 566 if (ret) 567 return ret; 568 569 return smu_v13_0_init_smc_tables(smu); 570} 571 572static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu) 573{ 574 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 575 struct smu_table_context *table_context = &smu->smu_table; 576 PPTable_t *pptable = table_context->driver_pptable; 577 SkuTable_t *skutable = &pptable->SkuTable; 578 struct smu_13_0_dpm_table *dpm_table; 579 int ret = 0; 580 581 /* socclk dpm table setup */ 582 dpm_table = &dpm_context->dpm_tables.soc_table; 583 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 584 ret = smu_v13_0_set_single_dpm_table(smu, 585 SMU_SOCCLK, 586 dpm_table); 587 if (ret) 588 return ret; 589 } else { 590 dpm_table->count = 1; 591 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 592 dpm_table->dpm_levels[0].enabled = true; 593 dpm_table->min = dpm_table->dpm_levels[0].value; 594 dpm_table->max = dpm_table->dpm_levels[0].value; 595 } 596 597 /* gfxclk dpm table setup */ 598 dpm_table = &dpm_context->dpm_tables.gfx_table; 599 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 600 ret = smu_v13_0_set_single_dpm_table(smu, 601 SMU_GFXCLK, 602 dpm_table); 603 if (ret) 604 return ret; 605 606 /* 607 * Update the reported maximum shader clock to the value 608 * which can be guarded to be achieved on all cards. This 609 * is aligned with Window setting. And considering that value 610 * might be not the peak frequency the card can achieve, it 611 * is normal some real-time clock frequency can overtake this 612 * labelled maximum clock frequency(for example in pp_dpm_sclk 613 * sysfs output). 614 */ 615 if (skutable->DriverReportedClocks.GameClockAc && 616 (dpm_table->dpm_levels[dpm_table->count - 1].value > 617 skutable->DriverReportedClocks.GameClockAc)) { 618 dpm_table->dpm_levels[dpm_table->count - 1].value = 619 skutable->DriverReportedClocks.GameClockAc; 620 dpm_table->max = skutable->DriverReportedClocks.GameClockAc; 621 } 622 } else { 623 dpm_table->count = 1; 624 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 625 dpm_table->dpm_levels[0].enabled = true; 626 dpm_table->min = dpm_table->dpm_levels[0].value; 627 dpm_table->max = dpm_table->dpm_levels[0].value; 628 } 629 630 /* uclk dpm table setup */ 631 dpm_table = &dpm_context->dpm_tables.uclk_table; 632 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 633 ret = smu_v13_0_set_single_dpm_table(smu, 634 SMU_UCLK, 635 dpm_table); 636 if (ret) 637 return ret; 638 } else { 639 dpm_table->count = 1; 640 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 641 dpm_table->dpm_levels[0].enabled = true; 642 dpm_table->min = dpm_table->dpm_levels[0].value; 643 dpm_table->max = dpm_table->dpm_levels[0].value; 644 } 645 646 /* fclk dpm table setup */ 647 dpm_table = &dpm_context->dpm_tables.fclk_table; 648 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 649 ret = smu_v13_0_set_single_dpm_table(smu, 650 SMU_FCLK, 651 dpm_table); 652 if (ret) 653 return ret; 654 } else { 655 dpm_table->count = 1; 656 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 657 dpm_table->dpm_levels[0].enabled = true; 658 dpm_table->min = dpm_table->dpm_levels[0].value; 659 dpm_table->max = dpm_table->dpm_levels[0].value; 660 } 661 662 /* vclk dpm table setup */ 663 dpm_table = &dpm_context->dpm_tables.vclk_table; 664 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) { 665 ret = smu_v13_0_set_single_dpm_table(smu, 666 SMU_VCLK, 667 dpm_table); 668 if (ret) 669 return ret; 670 } else { 671 dpm_table->count = 1; 672 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 673 dpm_table->dpm_levels[0].enabled = true; 674 dpm_table->min = dpm_table->dpm_levels[0].value; 675 dpm_table->max = dpm_table->dpm_levels[0].value; 676 } 677 678 /* dclk dpm table setup */ 679 dpm_table = &dpm_context->dpm_tables.dclk_table; 680 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) { 681 ret = smu_v13_0_set_single_dpm_table(smu, 682 SMU_DCLK, 683 dpm_table); 684 if (ret) 685 return ret; 686 } else { 687 dpm_table->count = 1; 688 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 689 dpm_table->dpm_levels[0].enabled = true; 690 dpm_table->min = dpm_table->dpm_levels[0].value; 691 dpm_table->max = dpm_table->dpm_levels[0].value; 692 } 693 694 /* dcefclk dpm table setup */ 695 dpm_table = &dpm_context->dpm_tables.dcef_table; 696 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) { 697 ret = smu_v13_0_set_single_dpm_table(smu, 698 SMU_DCEFCLK, 699 dpm_table); 700 if (ret) 701 return ret; 702 } else { 703 dpm_table->count = 1; 704 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 705 dpm_table->dpm_levels[0].enabled = true; 706 dpm_table->min = dpm_table->dpm_levels[0].value; 707 dpm_table->max = dpm_table->dpm_levels[0].value; 708 } 709 710 return 0; 711} 712 713static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu) 714{ 715 int ret = 0; 716 uint64_t feature_enabled; 717 718 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 719 if (ret) 720 return false; 721 722 return !!(feature_enabled & SMC_DPM_FEATURE); 723} 724 725static int smu_v13_0_0_system_features_control(struct smu_context *smu, 726 bool en) 727{ 728 return smu_v13_0_system_features_control(smu, en); 729} 730 731static uint32_t smu_v13_0_get_throttler_status(SmuMetrics_t *metrics) 732{ 733 uint32_t throttler_status = 0; 734 int i; 735 736 for (i = 0; i < THROTTLER_COUNT; i++) 737 throttler_status |= 738 (metrics->ThrottlingPercentage[i] ? 1U << i : 0); 739 740 return throttler_status; 741} 742 743#define SMU_13_0_0_BUSY_THRESHOLD 15 744static int smu_v13_0_0_get_smu_metrics_data(struct smu_context *smu, 745 MetricsMember_t member, 746 uint32_t *value) 747{ 748 struct smu_table_context *smu_table = &smu->smu_table; 749 SmuMetrics_t *metrics = 750 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 751 int ret = 0; 752 753 ret = smu_cmn_get_metrics_table(smu, 754 NULL, 755 false); 756 if (ret) 757 return ret; 758 759 switch (member) { 760 case METRICS_CURR_GFXCLK: 761 *value = metrics->CurrClock[PPCLK_GFXCLK]; 762 break; 763 case METRICS_CURR_SOCCLK: 764 *value = metrics->CurrClock[PPCLK_SOCCLK]; 765 break; 766 case METRICS_CURR_UCLK: 767 *value = metrics->CurrClock[PPCLK_UCLK]; 768 break; 769 case METRICS_CURR_VCLK: 770 *value = metrics->CurrClock[PPCLK_VCLK_0]; 771 break; 772 case METRICS_CURR_VCLK1: 773 *value = metrics->CurrClock[PPCLK_VCLK_1]; 774 break; 775 case METRICS_CURR_DCLK: 776 *value = metrics->CurrClock[PPCLK_DCLK_0]; 777 break; 778 case METRICS_CURR_DCLK1: 779 *value = metrics->CurrClock[PPCLK_DCLK_1]; 780 break; 781 case METRICS_CURR_FCLK: 782 *value = metrics->CurrClock[PPCLK_FCLK]; 783 break; 784 case METRICS_CURR_DCEFCLK: 785 *value = metrics->CurrClock[PPCLK_DCFCLK]; 786 break; 787 case METRICS_AVERAGE_GFXCLK: 788 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD) 789 *value = metrics->AverageGfxclkFrequencyPostDs; 790 else 791 *value = metrics->AverageGfxclkFrequencyPreDs; 792 break; 793 case METRICS_AVERAGE_FCLK: 794 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD) 795 *value = metrics->AverageFclkFrequencyPostDs; 796 else 797 *value = metrics->AverageFclkFrequencyPreDs; 798 break; 799 case METRICS_AVERAGE_UCLK: 800 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD) 801 *value = metrics->AverageMemclkFrequencyPostDs; 802 else 803 *value = metrics->AverageMemclkFrequencyPreDs; 804 break; 805 case METRICS_AVERAGE_VCLK: 806 *value = metrics->AverageVclk0Frequency; 807 break; 808 case METRICS_AVERAGE_DCLK: 809 *value = metrics->AverageDclk0Frequency; 810 break; 811 case METRICS_AVERAGE_VCLK1: 812 *value = metrics->AverageVclk1Frequency; 813 break; 814 case METRICS_AVERAGE_DCLK1: 815 *value = metrics->AverageDclk1Frequency; 816 break; 817 case METRICS_AVERAGE_GFXACTIVITY: 818 *value = metrics->AverageGfxActivity; 819 break; 820 case METRICS_AVERAGE_MEMACTIVITY: 821 *value = metrics->AverageUclkActivity; 822 break; 823 case METRICS_AVERAGE_VCNACTIVITY: 824 *value = max(metrics->Vcn0ActivityPercentage, 825 metrics->Vcn1ActivityPercentage); 826 break; 827 case METRICS_AVERAGE_SOCKETPOWER: 828 *value = metrics->AverageSocketPower << 8; 829 break; 830 case METRICS_TEMPERATURE_EDGE: 831 *value = metrics->AvgTemperature[TEMP_EDGE] * 832 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 833 break; 834 case METRICS_TEMPERATURE_HOTSPOT: 835 *value = metrics->AvgTemperature[TEMP_HOTSPOT] * 836 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 837 break; 838 case METRICS_TEMPERATURE_MEM: 839 *value = metrics->AvgTemperature[TEMP_MEM] * 840 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 841 break; 842 case METRICS_TEMPERATURE_VRGFX: 843 *value = metrics->AvgTemperature[TEMP_VR_GFX] * 844 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 845 break; 846 case METRICS_TEMPERATURE_VRSOC: 847 *value = metrics->AvgTemperature[TEMP_VR_SOC] * 848 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 849 break; 850 case METRICS_THROTTLER_STATUS: 851 *value = smu_v13_0_get_throttler_status(metrics); 852 break; 853 case METRICS_CURR_FANSPEED: 854 *value = metrics->AvgFanRpm; 855 break; 856 case METRICS_CURR_FANPWM: 857 *value = metrics->AvgFanPwm; 858 break; 859 case METRICS_VOLTAGE_VDDGFX: 860 *value = metrics->AvgVoltage[SVI_PLANE_GFX]; 861 break; 862 case METRICS_PCIE_RATE: 863 *value = metrics->PcieRate; 864 break; 865 case METRICS_PCIE_WIDTH: 866 *value = metrics->PcieWidth; 867 break; 868 default: 869 *value = UINT_MAX; 870 break; 871 } 872 873 return ret; 874} 875 876static int smu_v13_0_0_get_dpm_ultimate_freq(struct smu_context *smu, 877 enum smu_clk_type clk_type, 878 uint32_t *min, 879 uint32_t *max) 880{ 881 struct smu_13_0_dpm_context *dpm_context = 882 smu->smu_dpm.dpm_context; 883 struct smu_13_0_dpm_table *dpm_table; 884 885 switch (clk_type) { 886 case SMU_MCLK: 887 case SMU_UCLK: 888 /* uclk dpm table */ 889 dpm_table = &dpm_context->dpm_tables.uclk_table; 890 break; 891 case SMU_GFXCLK: 892 case SMU_SCLK: 893 /* gfxclk dpm table */ 894 dpm_table = &dpm_context->dpm_tables.gfx_table; 895 break; 896 case SMU_SOCCLK: 897 /* socclk dpm table */ 898 dpm_table = &dpm_context->dpm_tables.soc_table; 899 break; 900 case SMU_FCLK: 901 /* fclk dpm table */ 902 dpm_table = &dpm_context->dpm_tables.fclk_table; 903 break; 904 case SMU_VCLK: 905 case SMU_VCLK1: 906 /* vclk dpm table */ 907 dpm_table = &dpm_context->dpm_tables.vclk_table; 908 break; 909 case SMU_DCLK: 910 case SMU_DCLK1: 911 /* dclk dpm table */ 912 dpm_table = &dpm_context->dpm_tables.dclk_table; 913 break; 914 default: 915 dev_err(smu->adev->dev, "Unsupported clock type!\n"); 916 return -EINVAL; 917 } 918 919 if (min) 920 *min = dpm_table->min; 921 if (max) 922 *max = dpm_table->max; 923 924 return 0; 925} 926 927static int smu_v13_0_0_read_sensor(struct smu_context *smu, 928 enum amd_pp_sensors sensor, 929 void *data, 930 uint32_t *size) 931{ 932 struct smu_table_context *table_context = &smu->smu_table; 933 PPTable_t *smc_pptable = table_context->driver_pptable; 934 int ret = 0; 935 936 switch (sensor) { 937 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 938 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm; 939 *size = 4; 940 break; 941 case AMDGPU_PP_SENSOR_MEM_LOAD: 942 ret = smu_v13_0_0_get_smu_metrics_data(smu, 943 METRICS_AVERAGE_MEMACTIVITY, 944 (uint32_t *)data); 945 *size = 4; 946 break; 947 case AMDGPU_PP_SENSOR_GPU_LOAD: 948 ret = smu_v13_0_0_get_smu_metrics_data(smu, 949 METRICS_AVERAGE_GFXACTIVITY, 950 (uint32_t *)data); 951 *size = 4; 952 break; 953 case AMDGPU_PP_SENSOR_VCN_LOAD: 954 ret = smu_v13_0_0_get_smu_metrics_data(smu, 955 METRICS_AVERAGE_VCNACTIVITY, 956 (uint32_t *)data); 957 *size = 4; 958 break; 959 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 960 ret = smu_v13_0_0_get_smu_metrics_data(smu, 961 METRICS_AVERAGE_SOCKETPOWER, 962 (uint32_t *)data); 963 *size = 4; 964 break; 965 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 966 ret = smu_v13_0_0_get_smu_metrics_data(smu, 967 METRICS_TEMPERATURE_HOTSPOT, 968 (uint32_t *)data); 969 *size = 4; 970 break; 971 case AMDGPU_PP_SENSOR_EDGE_TEMP: 972 ret = smu_v13_0_0_get_smu_metrics_data(smu, 973 METRICS_TEMPERATURE_EDGE, 974 (uint32_t *)data); 975 *size = 4; 976 break; 977 case AMDGPU_PP_SENSOR_MEM_TEMP: 978 ret = smu_v13_0_0_get_smu_metrics_data(smu, 979 METRICS_TEMPERATURE_MEM, 980 (uint32_t *)data); 981 *size = 4; 982 break; 983 case AMDGPU_PP_SENSOR_GFX_MCLK: 984 ret = smu_v13_0_0_get_smu_metrics_data(smu, 985 METRICS_CURR_UCLK, 986 (uint32_t *)data); 987 *(uint32_t *)data *= 100; 988 *size = 4; 989 break; 990 case AMDGPU_PP_SENSOR_GFX_SCLK: 991 ret = smu_v13_0_0_get_smu_metrics_data(smu, 992 METRICS_AVERAGE_GFXCLK, 993 (uint32_t *)data); 994 *(uint32_t *)data *= 100; 995 *size = 4; 996 break; 997 case AMDGPU_PP_SENSOR_VDDGFX: 998 ret = smu_v13_0_0_get_smu_metrics_data(smu, 999 METRICS_VOLTAGE_VDDGFX, 1000 (uint32_t *)data); 1001 *size = 4; 1002 break; 1003 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 1004 default: 1005 ret = -EOPNOTSUPP; 1006 break; 1007 } 1008 1009 return ret; 1010} 1011 1012static int smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context *smu, 1013 enum smu_clk_type clk_type, 1014 uint32_t *value) 1015{ 1016 MetricsMember_t member_type; 1017 int clk_id = 0; 1018 1019 clk_id = smu_cmn_to_asic_specific_index(smu, 1020 CMN2ASIC_MAPPING_CLK, 1021 clk_type); 1022 if (clk_id < 0) 1023 return -EINVAL; 1024 1025 switch (clk_id) { 1026 case PPCLK_GFXCLK: 1027 member_type = METRICS_AVERAGE_GFXCLK; 1028 break; 1029 case PPCLK_UCLK: 1030 member_type = METRICS_CURR_UCLK; 1031 break; 1032 case PPCLK_FCLK: 1033 member_type = METRICS_CURR_FCLK; 1034 break; 1035 case PPCLK_SOCCLK: 1036 member_type = METRICS_CURR_SOCCLK; 1037 break; 1038 case PPCLK_VCLK_0: 1039 member_type = METRICS_AVERAGE_VCLK; 1040 break; 1041 case PPCLK_DCLK_0: 1042 member_type = METRICS_AVERAGE_DCLK; 1043 break; 1044 case PPCLK_VCLK_1: 1045 member_type = METRICS_AVERAGE_VCLK1; 1046 break; 1047 case PPCLK_DCLK_1: 1048 member_type = METRICS_AVERAGE_DCLK1; 1049 break; 1050 case PPCLK_DCFCLK: 1051 member_type = METRICS_CURR_DCEFCLK; 1052 break; 1053 default: 1054 return -EINVAL; 1055 } 1056 1057 return smu_v13_0_0_get_smu_metrics_data(smu, 1058 member_type, 1059 value); 1060} 1061 1062static bool smu_v13_0_0_is_od_feature_supported(struct smu_context *smu, 1063 int od_feature_bit) 1064{ 1065 PPTable_t *pptable = smu->smu_table.driver_pptable; 1066 const OverDriveLimits_t * const overdrive_upperlimits = 1067 &pptable->SkuTable.OverDriveLimitsBasicMax; 1068 int32_t min_value, max_value; 1069 bool feature_enabled; 1070 1071 switch (od_feature_bit) { 1072 case PP_OD_FEATURE_FAN_CURVE_BIT: 1073 feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); 1074 if (feature_enabled) { 1075 smu_v13_0_0_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_TEMP, 1076 &min_value, &max_value); 1077 if (!min_value && !max_value) { 1078 feature_enabled = false; 1079 goto out; 1080 } 1081 1082 smu_v13_0_0_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_PWM, 1083 &min_value, &max_value); 1084 if (!min_value && !max_value) { 1085 feature_enabled = false; 1086 goto out; 1087 } 1088 } 1089 break; 1090 default: 1091 feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); 1092 break; 1093 } 1094 1095out: 1096 return feature_enabled; 1097} 1098 1099static void smu_v13_0_0_get_od_setting_limits(struct smu_context *smu, 1100 int od_feature_bit, 1101 int32_t *min, 1102 int32_t *max) 1103{ 1104 PPTable_t *pptable = smu->smu_table.driver_pptable; 1105 const OverDriveLimits_t * const overdrive_upperlimits = 1106 &pptable->SkuTable.OverDriveLimitsBasicMax; 1107 const OverDriveLimits_t * const overdrive_lowerlimits = 1108 &pptable->SkuTable.OverDriveLimitsMin; 1109 int32_t od_min_setting, od_max_setting; 1110 1111 switch (od_feature_bit) { 1112 case PP_OD_FEATURE_GFXCLK_FMIN: 1113 od_min_setting = overdrive_lowerlimits->GfxclkFmin; 1114 od_max_setting = overdrive_upperlimits->GfxclkFmin; 1115 break; 1116 case PP_OD_FEATURE_GFXCLK_FMAX: 1117 od_min_setting = overdrive_lowerlimits->GfxclkFmax; 1118 od_max_setting = overdrive_upperlimits->GfxclkFmax; 1119 break; 1120 case PP_OD_FEATURE_UCLK_FMIN: 1121 od_min_setting = overdrive_lowerlimits->UclkFmin; 1122 od_max_setting = overdrive_upperlimits->UclkFmin; 1123 break; 1124 case PP_OD_FEATURE_UCLK_FMAX: 1125 od_min_setting = overdrive_lowerlimits->UclkFmax; 1126 od_max_setting = overdrive_upperlimits->UclkFmax; 1127 break; 1128 case PP_OD_FEATURE_GFX_VF_CURVE: 1129 od_min_setting = overdrive_lowerlimits->VoltageOffsetPerZoneBoundary; 1130 od_max_setting = overdrive_upperlimits->VoltageOffsetPerZoneBoundary; 1131 break; 1132 case PP_OD_FEATURE_FAN_CURVE_TEMP: 1133 od_min_setting = overdrive_lowerlimits->FanLinearTempPoints; 1134 od_max_setting = overdrive_upperlimits->FanLinearTempPoints; 1135 break; 1136 case PP_OD_FEATURE_FAN_CURVE_PWM: 1137 od_min_setting = overdrive_lowerlimits->FanLinearPwmPoints; 1138 od_max_setting = overdrive_upperlimits->FanLinearPwmPoints; 1139 break; 1140 case PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT: 1141 od_min_setting = overdrive_lowerlimits->AcousticLimitRpmThreshold; 1142 od_max_setting = overdrive_upperlimits->AcousticLimitRpmThreshold; 1143 break; 1144 case PP_OD_FEATURE_FAN_ACOUSTIC_TARGET: 1145 od_min_setting = overdrive_lowerlimits->AcousticTargetRpmThreshold; 1146 od_max_setting = overdrive_upperlimits->AcousticTargetRpmThreshold; 1147 break; 1148 case PP_OD_FEATURE_FAN_TARGET_TEMPERATURE: 1149 od_min_setting = overdrive_lowerlimits->FanTargetTemperature; 1150 od_max_setting = overdrive_upperlimits->FanTargetTemperature; 1151 break; 1152 case PP_OD_FEATURE_FAN_MINIMUM_PWM: 1153 od_min_setting = overdrive_lowerlimits->FanMinimumPwm; 1154 od_max_setting = overdrive_upperlimits->FanMinimumPwm; 1155 break; 1156 case PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE: 1157 od_min_setting = overdrive_lowerlimits->FanZeroRpmEnable; 1158 od_max_setting = overdrive_upperlimits->FanZeroRpmEnable; 1159 break; 1160 case PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP: 1161 od_min_setting = overdrive_lowerlimits->FanZeroRpmStopTemp; 1162 od_max_setting = overdrive_upperlimits->FanZeroRpmStopTemp; 1163 break; 1164 default: 1165 od_min_setting = od_max_setting = INT_MAX; 1166 break; 1167 } 1168 1169 if (min) 1170 *min = od_min_setting; 1171 if (max) 1172 *max = od_max_setting; 1173} 1174 1175static void smu_v13_0_0_dump_od_table(struct smu_context *smu, 1176 OverDriveTableExternal_t *od_table) 1177{ 1178 struct amdgpu_device *adev = smu->adev; 1179 1180 dev_dbg(adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->OverDriveTable.GfxclkFmin, 1181 od_table->OverDriveTable.GfxclkFmax); 1182 dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin, 1183 od_table->OverDriveTable.UclkFmax); 1184} 1185 1186static int smu_v13_0_0_get_overdrive_table(struct smu_context *smu, 1187 OverDriveTableExternal_t *od_table) 1188{ 1189 int ret = 0; 1190 1191 ret = smu_cmn_update_table(smu, 1192 SMU_TABLE_OVERDRIVE, 1193 0, 1194 (void *)od_table, 1195 false); 1196 if (ret) 1197 dev_err(smu->adev->dev, "Failed to get overdrive table!\n"); 1198 1199 return ret; 1200} 1201 1202static int smu_v13_0_0_upload_overdrive_table(struct smu_context *smu, 1203 OverDriveTableExternal_t *od_table) 1204{ 1205 int ret = 0; 1206 1207 ret = smu_cmn_update_table(smu, 1208 SMU_TABLE_OVERDRIVE, 1209 0, 1210 (void *)od_table, 1211 true); 1212 if (ret) 1213 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n"); 1214 1215 return ret; 1216} 1217 1218static int smu_v13_0_0_print_clk_levels(struct smu_context *smu, 1219 enum smu_clk_type clk_type, 1220 char *buf) 1221{ 1222 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1223 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1224 OverDriveTableExternal_t *od_table = 1225 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table; 1226 struct smu_13_0_dpm_table *single_dpm_table; 1227 struct smu_13_0_pcie_table *pcie_table; 1228 uint32_t gen_speed, lane_width; 1229 int i, curr_freq, size = 0, start_offset = 0; 1230 int32_t min_value, max_value; 1231 int ret = 0; 1232 1233 smu_cmn_get_sysfs_buf(&buf, &size); 1234 start_offset = size; 1235 1236 if (amdgpu_ras_intr_triggered()) { 1237 size += sysfs_emit_at(buf, size, "unavailable\n"); 1238 return size - start_offset; 1239 } 1240 1241 switch (clk_type) { 1242 case SMU_SCLK: 1243 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 1244 break; 1245 case SMU_MCLK: 1246 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 1247 break; 1248 case SMU_SOCCLK: 1249 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 1250 break; 1251 case SMU_FCLK: 1252 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 1253 break; 1254 case SMU_VCLK: 1255 case SMU_VCLK1: 1256 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 1257 break; 1258 case SMU_DCLK: 1259 case SMU_DCLK1: 1260 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 1261 break; 1262 case SMU_DCEFCLK: 1263 single_dpm_table = &(dpm_context->dpm_tables.dcef_table); 1264 break; 1265 default: 1266 break; 1267 } 1268 1269 switch (clk_type) { 1270 case SMU_SCLK: 1271 case SMU_MCLK: 1272 case SMU_SOCCLK: 1273 case SMU_FCLK: 1274 case SMU_VCLK: 1275 case SMU_VCLK1: 1276 case SMU_DCLK: 1277 case SMU_DCLK1: 1278 case SMU_DCEFCLK: 1279 ret = smu_v13_0_0_get_current_clk_freq_by_table(smu, clk_type, &curr_freq); 1280 if (ret) { 1281 dev_err(smu->adev->dev, "Failed to get current clock freq!"); 1282 return ret; 1283 } 1284 1285 if (single_dpm_table->is_fine_grained) { 1286 /* 1287 * For fine grained dpms, there are only two dpm levels: 1288 * - level 0 -> min clock freq 1289 * - level 1 -> max clock freq 1290 * And the current clock frequency can be any value between them. 1291 * So, if the current clock frequency is not at level 0 or level 1, 1292 * we will fake it as three dpm levels: 1293 * - level 0 -> min clock freq 1294 * - level 1 -> current actual clock freq 1295 * - level 2 -> max clock freq 1296 */ 1297 if ((single_dpm_table->dpm_levels[0].value != curr_freq) && 1298 (single_dpm_table->dpm_levels[1].value != curr_freq)) { 1299 size += sysfs_emit_at(buf, size, "0: %uMhz\n", 1300 single_dpm_table->dpm_levels[0].value); 1301 size += sysfs_emit_at(buf, size, "1: %uMhz *\n", 1302 curr_freq); 1303 size += sysfs_emit_at(buf, size, "2: %uMhz\n", 1304 single_dpm_table->dpm_levels[1].value); 1305 } else { 1306 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", 1307 single_dpm_table->dpm_levels[0].value, 1308 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : ""); 1309 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 1310 single_dpm_table->dpm_levels[1].value, 1311 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : ""); 1312 } 1313 } else { 1314 for (i = 0; i < single_dpm_table->count; i++) 1315 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 1316 i, single_dpm_table->dpm_levels[i].value, 1317 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : ""); 1318 } 1319 break; 1320 case SMU_PCIE: 1321 ret = smu_v13_0_0_get_smu_metrics_data(smu, 1322 METRICS_PCIE_RATE, 1323 &gen_speed); 1324 if (ret) 1325 return ret; 1326 1327 ret = smu_v13_0_0_get_smu_metrics_data(smu, 1328 METRICS_PCIE_WIDTH, 1329 &lane_width); 1330 if (ret) 1331 return ret; 1332 1333 pcie_table = &(dpm_context->dpm_tables.pcie_table); 1334 for (i = 0; i < pcie_table->num_of_link_levels; i++) 1335 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1336 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," : 1337 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," : 1338 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," : 1339 (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "", 1340 (pcie_table->pcie_lane[i] == 1) ? "x1" : 1341 (pcie_table->pcie_lane[i] == 2) ? "x2" : 1342 (pcie_table->pcie_lane[i] == 3) ? "x4" : 1343 (pcie_table->pcie_lane[i] == 4) ? "x8" : 1344 (pcie_table->pcie_lane[i] == 5) ? "x12" : 1345 (pcie_table->pcie_lane[i] == 6) ? "x16" : "", 1346 pcie_table->clk_freq[i], 1347 (gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) && 1348 (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ? 1349 "*" : ""); 1350 break; 1351 1352 case SMU_OD_SCLK: 1353 if (!smu_v13_0_0_is_od_feature_supported(smu, 1354 PP_OD_FEATURE_GFXCLK_BIT)) 1355 break; 1356 1357 size += sysfs_emit_at(buf, size, "OD_SCLK:\n"); 1358 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", 1359 od_table->OverDriveTable.GfxclkFmin, 1360 od_table->OverDriveTable.GfxclkFmax); 1361 break; 1362 1363 case SMU_OD_MCLK: 1364 if (!smu_v13_0_0_is_od_feature_supported(smu, 1365 PP_OD_FEATURE_UCLK_BIT)) 1366 break; 1367 1368 size += sysfs_emit_at(buf, size, "OD_MCLK:\n"); 1369 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", 1370 od_table->OverDriveTable.UclkFmin, 1371 od_table->OverDriveTable.UclkFmax); 1372 break; 1373 1374 case SMU_OD_VDDGFX_OFFSET: 1375 if (!smu_v13_0_0_is_od_feature_supported(smu, 1376 PP_OD_FEATURE_GFX_VF_CURVE_BIT)) 1377 break; 1378 1379 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n"); 1380 size += sysfs_emit_at(buf, size, "%dmV\n", 1381 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[0]); 1382 break; 1383 1384 case SMU_OD_FAN_CURVE: 1385 if (!smu_v13_0_0_is_od_feature_supported(smu, 1386 PP_OD_FEATURE_FAN_CURVE_BIT)) 1387 break; 1388 1389 size += sysfs_emit_at(buf, size, "OD_FAN_CURVE:\n"); 1390 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++) 1391 size += sysfs_emit_at(buf, size, "%d: %dC %d%%\n", 1392 i, 1393 (int)od_table->OverDriveTable.FanLinearTempPoints[i], 1394 (int)od_table->OverDriveTable.FanLinearPwmPoints[i]); 1395 1396 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1397 smu_v13_0_0_get_od_setting_limits(smu, 1398 PP_OD_FEATURE_FAN_CURVE_TEMP, 1399 &min_value, 1400 &max_value); 1401 size += sysfs_emit_at(buf, size, "FAN_CURVE(hotspot temp): %uC %uC\n", 1402 min_value, max_value); 1403 1404 smu_v13_0_0_get_od_setting_limits(smu, 1405 PP_OD_FEATURE_FAN_CURVE_PWM, 1406 &min_value, 1407 &max_value); 1408 size += sysfs_emit_at(buf, size, "FAN_CURVE(fan speed): %u%% %u%%\n", 1409 min_value, max_value); 1410 1411 break; 1412 1413 case SMU_OD_ACOUSTIC_LIMIT: 1414 if (!smu_v13_0_0_is_od_feature_supported(smu, 1415 PP_OD_FEATURE_FAN_CURVE_BIT)) 1416 break; 1417 1418 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_LIMIT:\n"); 1419 size += sysfs_emit_at(buf, size, "%d\n", 1420 (int)od_table->OverDriveTable.AcousticLimitRpmThreshold); 1421 1422 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1423 smu_v13_0_0_get_od_setting_limits(smu, 1424 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT, 1425 &min_value, 1426 &max_value); 1427 size += sysfs_emit_at(buf, size, "ACOUSTIC_LIMIT: %u %u\n", 1428 min_value, max_value); 1429 break; 1430 1431 case SMU_OD_ACOUSTIC_TARGET: 1432 if (!smu_v13_0_0_is_od_feature_supported(smu, 1433 PP_OD_FEATURE_FAN_CURVE_BIT)) 1434 break; 1435 1436 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_TARGET:\n"); 1437 size += sysfs_emit_at(buf, size, "%d\n", 1438 (int)od_table->OverDriveTable.AcousticTargetRpmThreshold); 1439 1440 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1441 smu_v13_0_0_get_od_setting_limits(smu, 1442 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET, 1443 &min_value, 1444 &max_value); 1445 size += sysfs_emit_at(buf, size, "ACOUSTIC_TARGET: %u %u\n", 1446 min_value, max_value); 1447 break; 1448 1449 case SMU_OD_FAN_TARGET_TEMPERATURE: 1450 if (!smu_v13_0_0_is_od_feature_supported(smu, 1451 PP_OD_FEATURE_FAN_CURVE_BIT)) 1452 break; 1453 1454 size += sysfs_emit_at(buf, size, "FAN_TARGET_TEMPERATURE:\n"); 1455 size += sysfs_emit_at(buf, size, "%d\n", 1456 (int)od_table->OverDriveTable.FanTargetTemperature); 1457 1458 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1459 smu_v13_0_0_get_od_setting_limits(smu, 1460 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE, 1461 &min_value, 1462 &max_value); 1463 size += sysfs_emit_at(buf, size, "TARGET_TEMPERATURE: %u %u\n", 1464 min_value, max_value); 1465 break; 1466 1467 case SMU_OD_FAN_MINIMUM_PWM: 1468 if (!smu_v13_0_0_is_od_feature_supported(smu, 1469 PP_OD_FEATURE_FAN_CURVE_BIT)) 1470 break; 1471 1472 size += sysfs_emit_at(buf, size, "FAN_MINIMUM_PWM:\n"); 1473 size += sysfs_emit_at(buf, size, "%d\n", 1474 (int)od_table->OverDriveTable.FanMinimumPwm); 1475 1476 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1477 smu_v13_0_0_get_od_setting_limits(smu, 1478 PP_OD_FEATURE_FAN_MINIMUM_PWM, 1479 &min_value, 1480 &max_value); 1481 size += sysfs_emit_at(buf, size, "MINIMUM_PWM: %u %u\n", 1482 min_value, max_value); 1483 break; 1484 1485 case SMU_OD_FAN_ZERO_RPM_ENABLE: 1486 if (!smu_v13_0_0_is_od_feature_supported(smu, 1487 PP_OD_FEATURE_ZERO_FAN_BIT)) 1488 break; 1489 1490 size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_ENABLE:\n"); 1491 size += sysfs_emit_at(buf, size, "%d\n", 1492 (int)od_table->OverDriveTable.FanZeroRpmEnable); 1493 1494 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1495 smu_v13_0_0_get_od_setting_limits(smu, 1496 PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE, 1497 &min_value, 1498 &max_value); 1499 size += sysfs_emit_at(buf, size, "ZERO_RPM_ENABLE: %u %u\n", 1500 min_value, max_value); 1501 break; 1502 1503 case SMU_OD_FAN_ZERO_RPM_STOP_TEMP: 1504 if (!smu_v13_0_0_is_od_feature_supported(smu, 1505 PP_OD_FEATURE_ZERO_FAN_BIT)) 1506 break; 1507 1508 size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_STOP_TEMPERATURE:\n"); 1509 size += sysfs_emit_at(buf, size, "%d\n", 1510 (int)od_table->OverDriveTable.FanZeroRpmStopTemp); 1511 1512 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1513 smu_v13_0_0_get_od_setting_limits(smu, 1514 PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP, 1515 &min_value, 1516 &max_value); 1517 size += sysfs_emit_at(buf, size, "ZERO_RPM_STOP_TEMPERATURE: %u %u\n", 1518 min_value, max_value); 1519 break; 1520 1521 case SMU_OD_RANGE: 1522 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) && 1523 !smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) && 1524 !smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) 1525 break; 1526 1527 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1528 1529 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) { 1530 smu_v13_0_0_get_od_setting_limits(smu, 1531 PP_OD_FEATURE_GFXCLK_FMIN, 1532 &min_value, 1533 NULL); 1534 smu_v13_0_0_get_od_setting_limits(smu, 1535 PP_OD_FEATURE_GFXCLK_FMAX, 1536 NULL, 1537 &max_value); 1538 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 1539 min_value, max_value); 1540 } 1541 1542 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) { 1543 smu_v13_0_0_get_od_setting_limits(smu, 1544 PP_OD_FEATURE_UCLK_FMIN, 1545 &min_value, 1546 NULL); 1547 smu_v13_0_0_get_od_setting_limits(smu, 1548 PP_OD_FEATURE_UCLK_FMAX, 1549 NULL, 1550 &max_value); 1551 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n", 1552 min_value, max_value); 1553 } 1554 1555 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) { 1556 smu_v13_0_0_get_od_setting_limits(smu, 1557 PP_OD_FEATURE_GFX_VF_CURVE, 1558 &min_value, 1559 &max_value); 1560 size += sysfs_emit_at(buf, size, "VDDGFX_OFFSET: %7dmv %10dmv\n", 1561 min_value, max_value); 1562 } 1563 break; 1564 1565 default: 1566 break; 1567 } 1568 1569 return size - start_offset; 1570} 1571 1572 1573static int smu_v13_0_0_od_restore_table_single(struct smu_context *smu, long input) 1574{ 1575 struct smu_table_context *table_context = &smu->smu_table; 1576 OverDriveTableExternal_t *boot_overdrive_table = 1577 (OverDriveTableExternal_t *)table_context->boot_overdrive_table; 1578 OverDriveTableExternal_t *od_table = 1579 (OverDriveTableExternal_t *)table_context->overdrive_table; 1580 struct amdgpu_device *adev = smu->adev; 1581 int i; 1582 1583 switch (input) { 1584 case PP_OD_EDIT_FAN_CURVE: 1585 for (i = 0; i < NUM_OD_FAN_MAX_POINTS; i++) { 1586 od_table->OverDriveTable.FanLinearTempPoints[i] = 1587 boot_overdrive_table->OverDriveTable.FanLinearTempPoints[i]; 1588 od_table->OverDriveTable.FanLinearPwmPoints[i] = 1589 boot_overdrive_table->OverDriveTable.FanLinearPwmPoints[i]; 1590 } 1591 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO; 1592 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT); 1593 break; 1594 case PP_OD_EDIT_ACOUSTIC_LIMIT: 1595 od_table->OverDriveTable.AcousticLimitRpmThreshold = 1596 boot_overdrive_table->OverDriveTable.AcousticLimitRpmThreshold; 1597 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO; 1598 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT); 1599 break; 1600 case PP_OD_EDIT_ACOUSTIC_TARGET: 1601 od_table->OverDriveTable.AcousticTargetRpmThreshold = 1602 boot_overdrive_table->OverDriveTable.AcousticTargetRpmThreshold; 1603 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO; 1604 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT); 1605 break; 1606 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE: 1607 od_table->OverDriveTable.FanTargetTemperature = 1608 boot_overdrive_table->OverDriveTable.FanTargetTemperature; 1609 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO; 1610 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT); 1611 break; 1612 case PP_OD_EDIT_FAN_MINIMUM_PWM: 1613 od_table->OverDriveTable.FanMinimumPwm = 1614 boot_overdrive_table->OverDriveTable.FanMinimumPwm; 1615 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO; 1616 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT); 1617 break; 1618 case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE: 1619 od_table->OverDriveTable.FanZeroRpmEnable = 1620 boot_overdrive_table->OverDriveTable.FanZeroRpmEnable; 1621 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT); 1622 break; 1623 case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP: 1624 od_table->OverDriveTable.FanZeroRpmStopTemp = 1625 boot_overdrive_table->OverDriveTable.FanZeroRpmStopTemp; 1626 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT); 1627 break; 1628 default: 1629 dev_info(adev->dev, "Invalid table index: %ld\n", input); 1630 return -EINVAL; 1631 } 1632 1633 return 0; 1634} 1635 1636static int smu_v13_0_0_od_edit_dpm_table(struct smu_context *smu, 1637 enum PP_OD_DPM_TABLE_COMMAND type, 1638 long input[], 1639 uint32_t size) 1640{ 1641 struct smu_table_context *table_context = &smu->smu_table; 1642 OverDriveTableExternal_t *od_table = 1643 (OverDriveTableExternal_t *)table_context->overdrive_table; 1644 struct amdgpu_device *adev = smu->adev; 1645 uint32_t offset_of_voltageoffset; 1646 int32_t minimum, maximum; 1647 uint32_t feature_ctrlmask; 1648 int i, ret = 0; 1649 1650 switch (type) { 1651 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1652 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) { 1653 dev_warn(adev->dev, "GFXCLK_LIMITS setting not supported!\n"); 1654 return -ENOTSUPP; 1655 } 1656 1657 for (i = 0; i < size; i += 2) { 1658 if (i + 2 > size) { 1659 dev_info(adev->dev, "invalid number of input parameters %d\n", size); 1660 return -EINVAL; 1661 } 1662 1663 switch (input[i]) { 1664 case 0: 1665 smu_v13_0_0_get_od_setting_limits(smu, 1666 PP_OD_FEATURE_GFXCLK_FMIN, 1667 &minimum, 1668 &maximum); 1669 if (input[i + 1] < minimum || 1670 input[i + 1] > maximum) { 1671 dev_info(adev->dev, "GfxclkFmin (%ld) must be within [%u, %u]!\n", 1672 input[i + 1], minimum, maximum); 1673 return -EINVAL; 1674 } 1675 1676 od_table->OverDriveTable.GfxclkFmin = input[i + 1]; 1677 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT; 1678 break; 1679 1680 case 1: 1681 smu_v13_0_0_get_od_setting_limits(smu, 1682 PP_OD_FEATURE_GFXCLK_FMAX, 1683 &minimum, 1684 &maximum); 1685 if (input[i + 1] < minimum || 1686 input[i + 1] > maximum) { 1687 dev_info(adev->dev, "GfxclkFmax (%ld) must be within [%u, %u]!\n", 1688 input[i + 1], minimum, maximum); 1689 return -EINVAL; 1690 } 1691 1692 od_table->OverDriveTable.GfxclkFmax = input[i + 1]; 1693 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT; 1694 break; 1695 1696 default: 1697 dev_info(adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]); 1698 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n"); 1699 return -EINVAL; 1700 } 1701 } 1702 1703 if (od_table->OverDriveTable.GfxclkFmin > od_table->OverDriveTable.GfxclkFmax) { 1704 dev_err(adev->dev, 1705 "Invalid setting: GfxclkFmin(%u) is bigger than GfxclkFmax(%u)\n", 1706 (uint32_t)od_table->OverDriveTable.GfxclkFmin, 1707 (uint32_t)od_table->OverDriveTable.GfxclkFmax); 1708 return -EINVAL; 1709 } 1710 break; 1711 1712 case PP_OD_EDIT_MCLK_VDDC_TABLE: 1713 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) { 1714 dev_warn(adev->dev, "UCLK_LIMITS setting not supported!\n"); 1715 return -ENOTSUPP; 1716 } 1717 1718 for (i = 0; i < size; i += 2) { 1719 if (i + 2 > size) { 1720 dev_info(adev->dev, "invalid number of input parameters %d\n", size); 1721 return -EINVAL; 1722 } 1723 1724 switch (input[i]) { 1725 case 0: 1726 smu_v13_0_0_get_od_setting_limits(smu, 1727 PP_OD_FEATURE_UCLK_FMIN, 1728 &minimum, 1729 &maximum); 1730 if (input[i + 1] < minimum || 1731 input[i + 1] > maximum) { 1732 dev_info(adev->dev, "UclkFmin (%ld) must be within [%u, %u]!\n", 1733 input[i + 1], minimum, maximum); 1734 return -EINVAL; 1735 } 1736 1737 od_table->OverDriveTable.UclkFmin = input[i + 1]; 1738 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT; 1739 break; 1740 1741 case 1: 1742 smu_v13_0_0_get_od_setting_limits(smu, 1743 PP_OD_FEATURE_UCLK_FMAX, 1744 &minimum, 1745 &maximum); 1746 if (input[i + 1] < minimum || 1747 input[i + 1] > maximum) { 1748 dev_info(adev->dev, "UclkFmax (%ld) must be within [%u, %u]!\n", 1749 input[i + 1], minimum, maximum); 1750 return -EINVAL; 1751 } 1752 1753 od_table->OverDriveTable.UclkFmax = input[i + 1]; 1754 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT; 1755 break; 1756 1757 default: 1758 dev_info(adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]); 1759 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n"); 1760 return -EINVAL; 1761 } 1762 } 1763 1764 if (od_table->OverDriveTable.UclkFmin > od_table->OverDriveTable.UclkFmax) { 1765 dev_err(adev->dev, 1766 "Invalid setting: UclkFmin(%u) is bigger than UclkFmax(%u)\n", 1767 (uint32_t)od_table->OverDriveTable.UclkFmin, 1768 (uint32_t)od_table->OverDriveTable.UclkFmax); 1769 return -EINVAL; 1770 } 1771 break; 1772 1773 case PP_OD_EDIT_VDDGFX_OFFSET: 1774 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) { 1775 dev_warn(adev->dev, "Gfx offset setting not supported!\n"); 1776 return -ENOTSUPP; 1777 } 1778 1779 smu_v13_0_0_get_od_setting_limits(smu, 1780 PP_OD_FEATURE_GFX_VF_CURVE, 1781 &minimum, 1782 &maximum); 1783 if (input[0] < minimum || 1784 input[0] > maximum) { 1785 dev_info(adev->dev, "Voltage offset (%ld) must be within [%d, %d]!\n", 1786 input[0], minimum, maximum); 1787 return -EINVAL; 1788 } 1789 1790 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++) 1791 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] = input[0]; 1792 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT); 1793 break; 1794 1795 case PP_OD_EDIT_FAN_CURVE: 1796 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) { 1797 dev_warn(adev->dev, "Fan curve setting not supported!\n"); 1798 return -ENOTSUPP; 1799 } 1800 1801 if (input[0] >= NUM_OD_FAN_MAX_POINTS - 1 || 1802 input[0] < 0) 1803 return -EINVAL; 1804 1805 smu_v13_0_0_get_od_setting_limits(smu, 1806 PP_OD_FEATURE_FAN_CURVE_TEMP, 1807 &minimum, 1808 &maximum); 1809 if (input[1] < minimum || 1810 input[1] > maximum) { 1811 dev_info(adev->dev, "Fan curve temp setting(%ld) must be within [%d, %d]!\n", 1812 input[1], minimum, maximum); 1813 return -EINVAL; 1814 } 1815 1816 smu_v13_0_0_get_od_setting_limits(smu, 1817 PP_OD_FEATURE_FAN_CURVE_PWM, 1818 &minimum, 1819 &maximum); 1820 if (input[2] < minimum || 1821 input[2] > maximum) { 1822 dev_info(adev->dev, "Fan curve pwm setting(%ld) must be within [%d, %d]!\n", 1823 input[2], minimum, maximum); 1824 return -EINVAL; 1825 } 1826 1827 od_table->OverDriveTable.FanLinearTempPoints[input[0]] = input[1]; 1828 od_table->OverDriveTable.FanLinearPwmPoints[input[0]] = input[2]; 1829 od_table->OverDriveTable.FanMode = FAN_MODE_MANUAL_LINEAR; 1830 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT); 1831 break; 1832 1833 case PP_OD_EDIT_ACOUSTIC_LIMIT: 1834 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) { 1835 dev_warn(adev->dev, "Fan curve setting not supported!\n"); 1836 return -ENOTSUPP; 1837 } 1838 1839 smu_v13_0_0_get_od_setting_limits(smu, 1840 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT, 1841 &minimum, 1842 &maximum); 1843 if (input[0] < minimum || 1844 input[0] > maximum) { 1845 dev_info(adev->dev, "acoustic limit threshold setting(%ld) must be within [%d, %d]!\n", 1846 input[0], minimum, maximum); 1847 return -EINVAL; 1848 } 1849 1850 od_table->OverDriveTable.AcousticLimitRpmThreshold = input[0]; 1851 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO; 1852 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT); 1853 break; 1854 1855 case PP_OD_EDIT_ACOUSTIC_TARGET: 1856 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) { 1857 dev_warn(adev->dev, "Fan curve setting not supported!\n"); 1858 return -ENOTSUPP; 1859 } 1860 1861 smu_v13_0_0_get_od_setting_limits(smu, 1862 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET, 1863 &minimum, 1864 &maximum); 1865 if (input[0] < minimum || 1866 input[0] > maximum) { 1867 dev_info(adev->dev, "acoustic target threshold setting(%ld) must be within [%d, %d]!\n", 1868 input[0], minimum, maximum); 1869 return -EINVAL; 1870 } 1871 1872 od_table->OverDriveTable.AcousticTargetRpmThreshold = input[0]; 1873 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO; 1874 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT); 1875 break; 1876 1877 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE: 1878 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) { 1879 dev_warn(adev->dev, "Fan curve setting not supported!\n"); 1880 return -ENOTSUPP; 1881 } 1882 1883 smu_v13_0_0_get_od_setting_limits(smu, 1884 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE, 1885 &minimum, 1886 &maximum); 1887 if (input[0] < minimum || 1888 input[0] > maximum) { 1889 dev_info(adev->dev, "fan target temperature setting(%ld) must be within [%d, %d]!\n", 1890 input[0], minimum, maximum); 1891 return -EINVAL; 1892 } 1893 1894 od_table->OverDriveTable.FanTargetTemperature = input[0]; 1895 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO; 1896 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT); 1897 break; 1898 1899 case PP_OD_EDIT_FAN_MINIMUM_PWM: 1900 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) { 1901 dev_warn(adev->dev, "Fan curve setting not supported!\n"); 1902 return -ENOTSUPP; 1903 } 1904 1905 smu_v13_0_0_get_od_setting_limits(smu, 1906 PP_OD_FEATURE_FAN_MINIMUM_PWM, 1907 &minimum, 1908 &maximum); 1909 if (input[0] < minimum || 1910 input[0] > maximum) { 1911 dev_info(adev->dev, "fan minimum pwm setting(%ld) must be within [%d, %d]!\n", 1912 input[0], minimum, maximum); 1913 return -EINVAL; 1914 } 1915 1916 od_table->OverDriveTable.FanMinimumPwm = input[0]; 1917 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO; 1918 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT); 1919 break; 1920 1921 case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE: 1922 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) { 1923 dev_warn(adev->dev, "Zero RPM setting not supported!\n"); 1924 return -ENOTSUPP; 1925 } 1926 1927 smu_v13_0_0_get_od_setting_limits(smu, 1928 PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE, 1929 &minimum, 1930 &maximum); 1931 if (input[0] < minimum || 1932 input[0] > maximum) { 1933 dev_info(adev->dev, "zero RPM enable setting(%ld) must be within [%d, %d]!\n", 1934 input[0], minimum, maximum); 1935 return -EINVAL; 1936 } 1937 1938 od_table->OverDriveTable.FanZeroRpmEnable = input[0]; 1939 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT); 1940 break; 1941 1942 case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP: 1943 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) { 1944 dev_warn(adev->dev, "Zero RPM setting not supported!\n"); 1945 return -ENOTSUPP; 1946 } 1947 1948 smu_v13_0_0_get_od_setting_limits(smu, 1949 PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP, 1950 &minimum, 1951 &maximum); 1952 if (input[0] < minimum || 1953 input[0] > maximum) { 1954 dev_info(adev->dev, "zero RPM stop temperature setting(%ld) must be within [%d, %d]!\n", 1955 input[0], minimum, maximum); 1956 return -EINVAL; 1957 } 1958 1959 od_table->OverDriveTable.FanZeroRpmStopTemp = input[0]; 1960 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT); 1961 break; 1962 1963 case PP_OD_RESTORE_DEFAULT_TABLE: 1964 if (size == 1) { 1965 ret = smu_v13_0_0_od_restore_table_single(smu, input[0]); 1966 if (ret) 1967 return ret; 1968 } else { 1969 feature_ctrlmask = od_table->OverDriveTable.FeatureCtrlMask; 1970 memcpy(od_table, 1971 table_context->boot_overdrive_table, 1972 sizeof(OverDriveTableExternal_t)); 1973 od_table->OverDriveTable.FeatureCtrlMask = feature_ctrlmask; 1974 } 1975 fallthrough; 1976 case PP_OD_COMMIT_DPM_TABLE: 1977 /* 1978 * The member below instructs PMFW the settings focused in 1979 * this single operation. 1980 * `uint32_t FeatureCtrlMask;` 1981 * It does not contain actual informations about user's custom 1982 * settings. Thus we do not cache it. 1983 */ 1984 offset_of_voltageoffset = offsetof(OverDriveTable_t, VoltageOffsetPerZoneBoundary); 1985 if (memcmp((u8 *)od_table + offset_of_voltageoffset, 1986 table_context->user_overdrive_table + offset_of_voltageoffset, 1987 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset)) { 1988 smu_v13_0_0_dump_od_table(smu, od_table); 1989 1990 ret = smu_v13_0_0_upload_overdrive_table(smu, od_table); 1991 if (ret) { 1992 dev_err(adev->dev, "Failed to upload overdrive table!\n"); 1993 return ret; 1994 } 1995 1996 od_table->OverDriveTable.FeatureCtrlMask = 0; 1997 memcpy(table_context->user_overdrive_table + offset_of_voltageoffset, 1998 (u8 *)od_table + offset_of_voltageoffset, 1999 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset); 2000 2001 if (!memcmp(table_context->user_overdrive_table, 2002 table_context->boot_overdrive_table, 2003 sizeof(OverDriveTableExternal_t))) 2004 smu->user_dpm_profile.user_od = false; 2005 else 2006 smu->user_dpm_profile.user_od = true; 2007 } 2008 break; 2009 2010 default: 2011 return -ENOSYS; 2012 } 2013 2014 return ret; 2015} 2016 2017static int smu_v13_0_0_force_clk_levels(struct smu_context *smu, 2018 enum smu_clk_type clk_type, 2019 uint32_t mask) 2020{ 2021 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2022 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 2023 struct smu_13_0_dpm_table *single_dpm_table; 2024 uint32_t soft_min_level, soft_max_level; 2025 uint32_t min_freq, max_freq; 2026 int ret = 0; 2027 2028 soft_min_level = mask ? (ffs(mask) - 1) : 0; 2029 soft_max_level = mask ? (fls(mask) - 1) : 0; 2030 2031 switch (clk_type) { 2032 case SMU_GFXCLK: 2033 case SMU_SCLK: 2034 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 2035 break; 2036 case SMU_MCLK: 2037 case SMU_UCLK: 2038 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 2039 break; 2040 case SMU_SOCCLK: 2041 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 2042 break; 2043 case SMU_FCLK: 2044 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 2045 break; 2046 case SMU_VCLK: 2047 case SMU_VCLK1: 2048 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 2049 break; 2050 case SMU_DCLK: 2051 case SMU_DCLK1: 2052 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 2053 break; 2054 default: 2055 break; 2056 } 2057 2058 switch (clk_type) { 2059 case SMU_GFXCLK: 2060 case SMU_SCLK: 2061 case SMU_MCLK: 2062 case SMU_UCLK: 2063 case SMU_SOCCLK: 2064 case SMU_FCLK: 2065 case SMU_VCLK: 2066 case SMU_VCLK1: 2067 case SMU_DCLK: 2068 case SMU_DCLK1: 2069 if (single_dpm_table->is_fine_grained) { 2070 /* There is only 2 levels for fine grained DPM */ 2071 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 2072 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 2073 } else { 2074 if ((soft_max_level >= single_dpm_table->count) || 2075 (soft_min_level >= single_dpm_table->count)) 2076 return -EINVAL; 2077 } 2078 2079 min_freq = single_dpm_table->dpm_levels[soft_min_level].value; 2080 max_freq = single_dpm_table->dpm_levels[soft_max_level].value; 2081 2082 ret = smu_v13_0_set_soft_freq_limited_range(smu, 2083 clk_type, 2084 min_freq, 2085 max_freq, 2086 false); 2087 break; 2088 case SMU_DCEFCLK: 2089 case SMU_PCIE: 2090 default: 2091 break; 2092 } 2093 2094 return ret; 2095} 2096 2097static const struct smu_temperature_range smu13_thermal_policy[] = { 2098 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 2099 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 2100}; 2101 2102static int smu_v13_0_0_get_thermal_temperature_range(struct smu_context *smu, 2103 struct smu_temperature_range *range) 2104{ 2105 struct smu_table_context *table_context = &smu->smu_table; 2106 struct smu_13_0_0_powerplay_table *powerplay_table = 2107 table_context->power_play_table; 2108 PPTable_t *pptable = smu->smu_table.driver_pptable; 2109 2110 if (amdgpu_sriov_vf(smu->adev)) 2111 return 0; 2112 2113 if (!range) 2114 return -EINVAL; 2115 2116 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); 2117 2118 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] * 2119 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2120 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) * 2121 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2122 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] * 2123 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2124 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) * 2125 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2126 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] * 2127 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2128 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)* 2129 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2130 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 2131 range->software_shutdown_temp_offset = pptable->SkuTable.FanAbnormalTempLimitOffset; 2132 2133 return 0; 2134} 2135 2136static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu, 2137 void **table) 2138{ 2139 struct smu_table_context *smu_table = &smu->smu_table; 2140 struct gpu_metrics_v1_3 *gpu_metrics = 2141 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 2142 SmuMetricsExternal_t metrics_ext; 2143 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics; 2144 uint32_t mp1_ver = amdgpu_ip_version(smu->adev, MP1_HWIP, 0); 2145 int ret = 0; 2146 2147 ret = smu_cmn_get_metrics_table(smu, 2148 &metrics_ext, 2149 true); 2150 if (ret) 2151 return ret; 2152 2153 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 2154 2155 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE]; 2156 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT]; 2157 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM]; 2158 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX]; 2159 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC]; 2160 gpu_metrics->temperature_vrmem = max(metrics->AvgTemperature[TEMP_VR_MEM0], 2161 metrics->AvgTemperature[TEMP_VR_MEM1]); 2162 2163 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity; 2164 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity; 2165 gpu_metrics->average_mm_activity = max(metrics->Vcn0ActivityPercentage, 2166 metrics->Vcn1ActivityPercentage); 2167 2168 gpu_metrics->average_socket_power = metrics->AverageSocketPower; 2169 2170 if ((mp1_ver == IP_VERSION(13, 0, 0) && smu->smc_fw_version <= 0x004e1e00) || 2171 (mp1_ver == IP_VERSION(13, 0, 10) && smu->smc_fw_version <= 0x00500800)) 2172 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; 2173 else 2174 gpu_metrics->energy_accumulator = UINT_MAX; 2175 2176 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD) 2177 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs; 2178 else 2179 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs; 2180 2181 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD) 2182 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs; 2183 else 2184 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs; 2185 2186 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency; 2187 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency; 2188 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency; 2189 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency; 2190 2191 gpu_metrics->current_gfxclk = gpu_metrics->average_gfxclk_frequency; 2192 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK]; 2193 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK]; 2194 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0]; 2195 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0]; 2196 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1]; 2197 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1]; 2198 2199 gpu_metrics->throttle_status = 2200 smu_v13_0_get_throttler_status(metrics); 2201 gpu_metrics->indep_throttle_status = 2202 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status, 2203 smu_v13_0_0_throttler_map); 2204 2205 gpu_metrics->current_fan_speed = metrics->AvgFanRpm; 2206 2207 gpu_metrics->pcie_link_width = metrics->PcieWidth; 2208 if ((metrics->PcieRate - 1) > LINK_SPEED_MAX) 2209 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(1); 2210 else 2211 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(metrics->PcieRate); 2212 2213 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2214 2215 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX]; 2216 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC]; 2217 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP]; 2218 2219 *table = (void *)gpu_metrics; 2220 2221 return sizeof(struct gpu_metrics_v1_3); 2222} 2223 2224static void smu_v13_0_0_set_supported_od_feature_mask(struct smu_context *smu) 2225{ 2226 struct amdgpu_device *adev = smu->adev; 2227 2228 if (smu_v13_0_0_is_od_feature_supported(smu, 2229 PP_OD_FEATURE_FAN_CURVE_BIT)) 2230 adev->pm.od_feature_mask |= OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE | 2231 OD_OPS_SUPPORT_FAN_CURVE_SET | 2232 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE | 2233 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET | 2234 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE | 2235 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET | 2236 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE | 2237 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET | 2238 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE | 2239 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET | 2240 OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE | 2241 OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET | 2242 OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_RETRIEVE | 2243 OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_SET; 2244} 2245 2246static int smu_v13_0_0_set_default_od_settings(struct smu_context *smu) 2247{ 2248 OverDriveTableExternal_t *od_table = 2249 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table; 2250 OverDriveTableExternal_t *boot_od_table = 2251 (OverDriveTableExternal_t *)smu->smu_table.boot_overdrive_table; 2252 OverDriveTableExternal_t *user_od_table = 2253 (OverDriveTableExternal_t *)smu->smu_table.user_overdrive_table; 2254 OverDriveTableExternal_t user_od_table_bak; 2255 int ret = 0; 2256 int i; 2257 2258 ret = smu_v13_0_0_get_overdrive_table(smu, boot_od_table); 2259 if (ret) 2260 return ret; 2261 2262 smu_v13_0_0_dump_od_table(smu, boot_od_table); 2263 2264 memcpy(od_table, 2265 boot_od_table, 2266 sizeof(OverDriveTableExternal_t)); 2267 2268 /* 2269 * For S3/S4/Runpm resume, we need to setup those overdrive tables again, 2270 * but we have to preserve user defined values in "user_od_table". 2271 */ 2272 if (!smu->adev->in_suspend) { 2273 memcpy(user_od_table, 2274 boot_od_table, 2275 sizeof(OverDriveTableExternal_t)); 2276 smu->user_dpm_profile.user_od = false; 2277 } else if (smu->user_dpm_profile.user_od) { 2278 memcpy(&user_od_table_bak, 2279 user_od_table, 2280 sizeof(OverDriveTableExternal_t)); 2281 memcpy(user_od_table, 2282 boot_od_table, 2283 sizeof(OverDriveTableExternal_t)); 2284 user_od_table->OverDriveTable.GfxclkFmin = 2285 user_od_table_bak.OverDriveTable.GfxclkFmin; 2286 user_od_table->OverDriveTable.GfxclkFmax = 2287 user_od_table_bak.OverDriveTable.GfxclkFmax; 2288 user_od_table->OverDriveTable.UclkFmin = 2289 user_od_table_bak.OverDriveTable.UclkFmin; 2290 user_od_table->OverDriveTable.UclkFmax = 2291 user_od_table_bak.OverDriveTable.UclkFmax; 2292 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++) 2293 user_od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] = 2294 user_od_table_bak.OverDriveTable.VoltageOffsetPerZoneBoundary[i]; 2295 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++) { 2296 user_od_table->OverDriveTable.FanLinearTempPoints[i] = 2297 user_od_table_bak.OverDriveTable.FanLinearTempPoints[i]; 2298 user_od_table->OverDriveTable.FanLinearPwmPoints[i] = 2299 user_od_table_bak.OverDriveTable.FanLinearPwmPoints[i]; 2300 } 2301 user_od_table->OverDriveTable.AcousticLimitRpmThreshold = 2302 user_od_table_bak.OverDriveTable.AcousticLimitRpmThreshold; 2303 user_od_table->OverDriveTable.AcousticTargetRpmThreshold = 2304 user_od_table_bak.OverDriveTable.AcousticTargetRpmThreshold; 2305 user_od_table->OverDriveTable.FanTargetTemperature = 2306 user_od_table_bak.OverDriveTable.FanTargetTemperature; 2307 user_od_table->OverDriveTable.FanMinimumPwm = 2308 user_od_table_bak.OverDriveTable.FanMinimumPwm; 2309 user_od_table->OverDriveTable.FanZeroRpmEnable = 2310 user_od_table_bak.OverDriveTable.FanZeroRpmEnable; 2311 user_od_table->OverDriveTable.FanZeroRpmStopTemp = 2312 user_od_table_bak.OverDriveTable.FanZeroRpmStopTemp; 2313 } 2314 2315 smu_v13_0_0_set_supported_od_feature_mask(smu); 2316 2317 return 0; 2318} 2319 2320static int smu_v13_0_0_restore_user_od_settings(struct smu_context *smu) 2321{ 2322 struct smu_table_context *table_context = &smu->smu_table; 2323 OverDriveTableExternal_t *od_table = table_context->overdrive_table; 2324 OverDriveTableExternal_t *user_od_table = table_context->user_overdrive_table; 2325 int res; 2326 2327 user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) | 2328 BIT(PP_OD_FEATURE_UCLK_BIT) | 2329 BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) | 2330 BIT(PP_OD_FEATURE_FAN_CURVE_BIT) | 2331 BIT(PP_OD_FEATURE_ZERO_FAN_BIT); 2332 res = smu_v13_0_0_upload_overdrive_table(smu, user_od_table); 2333 user_od_table->OverDriveTable.FeatureCtrlMask = 0; 2334 if (res == 0) 2335 memcpy(od_table, user_od_table, sizeof(OverDriveTableExternal_t)); 2336 2337 return res; 2338} 2339 2340static int smu_v13_0_0_populate_umd_state_clk(struct smu_context *smu) 2341{ 2342 struct smu_13_0_dpm_context *dpm_context = 2343 smu->smu_dpm.dpm_context; 2344 struct smu_13_0_dpm_table *gfx_table = 2345 &dpm_context->dpm_tables.gfx_table; 2346 struct smu_13_0_dpm_table *mem_table = 2347 &dpm_context->dpm_tables.uclk_table; 2348 struct smu_13_0_dpm_table *soc_table = 2349 &dpm_context->dpm_tables.soc_table; 2350 struct smu_13_0_dpm_table *vclk_table = 2351 &dpm_context->dpm_tables.vclk_table; 2352 struct smu_13_0_dpm_table *dclk_table = 2353 &dpm_context->dpm_tables.dclk_table; 2354 struct smu_13_0_dpm_table *fclk_table = 2355 &dpm_context->dpm_tables.fclk_table; 2356 struct smu_umd_pstate_table *pstate_table = 2357 &smu->pstate_table; 2358 struct smu_table_context *table_context = &smu->smu_table; 2359 PPTable_t *pptable = table_context->driver_pptable; 2360 DriverReportedClocks_t driver_clocks = 2361 pptable->SkuTable.DriverReportedClocks; 2362 2363 pstate_table->gfxclk_pstate.min = gfx_table->min; 2364 if (driver_clocks.GameClockAc && 2365 (driver_clocks.GameClockAc < gfx_table->max)) 2366 pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc; 2367 else 2368 pstate_table->gfxclk_pstate.peak = gfx_table->max; 2369 2370 pstate_table->uclk_pstate.min = mem_table->min; 2371 pstate_table->uclk_pstate.peak = mem_table->max; 2372 2373 pstate_table->socclk_pstate.min = soc_table->min; 2374 pstate_table->socclk_pstate.peak = soc_table->max; 2375 2376 pstate_table->vclk_pstate.min = vclk_table->min; 2377 pstate_table->vclk_pstate.peak = vclk_table->max; 2378 2379 pstate_table->dclk_pstate.min = dclk_table->min; 2380 pstate_table->dclk_pstate.peak = dclk_table->max; 2381 2382 pstate_table->fclk_pstate.min = fclk_table->min; 2383 pstate_table->fclk_pstate.peak = fclk_table->max; 2384 2385 if (driver_clocks.BaseClockAc && 2386 driver_clocks.BaseClockAc < gfx_table->max) 2387 pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc; 2388 else 2389 pstate_table->gfxclk_pstate.standard = gfx_table->max; 2390 pstate_table->uclk_pstate.standard = mem_table->max; 2391 pstate_table->socclk_pstate.standard = soc_table->min; 2392 pstate_table->vclk_pstate.standard = vclk_table->min; 2393 pstate_table->dclk_pstate.standard = dclk_table->min; 2394 pstate_table->fclk_pstate.standard = fclk_table->min; 2395 2396 return 0; 2397} 2398 2399static void smu_v13_0_0_get_unique_id(struct smu_context *smu) 2400{ 2401 struct smu_table_context *smu_table = &smu->smu_table; 2402 SmuMetrics_t *metrics = 2403 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 2404 struct amdgpu_device *adev = smu->adev; 2405 uint32_t upper32 = 0, lower32 = 0; 2406 int ret; 2407 2408 ret = smu_cmn_get_metrics_table(smu, NULL, false); 2409 if (ret) 2410 goto out; 2411 2412 upper32 = metrics->PublicSerialNumberUpper; 2413 lower32 = metrics->PublicSerialNumberLower; 2414 2415out: 2416 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 2417} 2418 2419static int smu_v13_0_0_get_fan_speed_pwm(struct smu_context *smu, 2420 uint32_t *speed) 2421{ 2422 int ret; 2423 2424 if (!speed) 2425 return -EINVAL; 2426 2427 ret = smu_v13_0_0_get_smu_metrics_data(smu, 2428 METRICS_CURR_FANPWM, 2429 speed); 2430 if (ret) { 2431 dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!"); 2432 return ret; 2433 } 2434 2435 /* Convert the PMFW output which is in percent to pwm(255) based */ 2436 *speed = min(*speed * 255 / 100, (uint32_t)255); 2437 2438 return 0; 2439} 2440 2441static int smu_v13_0_0_get_fan_speed_rpm(struct smu_context *smu, 2442 uint32_t *speed) 2443{ 2444 if (!speed) 2445 return -EINVAL; 2446 2447 return smu_v13_0_0_get_smu_metrics_data(smu, 2448 METRICS_CURR_FANSPEED, 2449 speed); 2450} 2451 2452static int smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context *smu) 2453{ 2454 struct smu_table_context *table_context = &smu->smu_table; 2455 PPTable_t *pptable = table_context->driver_pptable; 2456 SkuTable_t *skutable = &pptable->SkuTable; 2457 2458 /* 2459 * Skip the MGpuFanBoost setting for those ASICs 2460 * which do not support it 2461 */ 2462 if (skutable->MGpuAcousticLimitRpmThreshold == 0) 2463 return 0; 2464 2465 return smu_cmn_send_smc_msg_with_param(smu, 2466 SMU_MSG_SetMGpuFanBoostLimitRpm, 2467 0, 2468 NULL); 2469} 2470 2471static int smu_v13_0_0_get_power_limit(struct smu_context *smu, 2472 uint32_t *current_power_limit, 2473 uint32_t *default_power_limit, 2474 uint32_t *max_power_limit, 2475 uint32_t *min_power_limit) 2476{ 2477 struct smu_table_context *table_context = &smu->smu_table; 2478 struct smu_13_0_0_powerplay_table *powerplay_table = 2479 (struct smu_13_0_0_powerplay_table *)table_context->power_play_table; 2480 PPTable_t *pptable = table_context->driver_pptable; 2481 SkuTable_t *skutable = &pptable->SkuTable; 2482 uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0; 2483 uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC]; 2484 2485 if (smu_v13_0_get_current_power_limit(smu, &power_limit)) 2486 power_limit = smu->adev->pm.ac_power ? 2487 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] : 2488 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0]; 2489 2490 if (current_power_limit) 2491 *current_power_limit = power_limit; 2492 if (default_power_limit) 2493 *default_power_limit = power_limit; 2494 2495 if (powerplay_table) { 2496 if (smu->od_enabled && 2497 smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) { 2498 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]); 2499 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]); 2500 } else if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) { 2501 od_percent_upper = 0; 2502 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]); 2503 } 2504 } 2505 2506 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n", 2507 od_percent_upper, od_percent_lower, power_limit); 2508 2509 if (max_power_limit) { 2510 *max_power_limit = msg_limit * (100 + od_percent_upper); 2511 *max_power_limit /= 100; 2512 } 2513 2514 if (min_power_limit) { 2515 *min_power_limit = power_limit * (100 - od_percent_lower); 2516 *min_power_limit /= 100; 2517 } 2518 2519 return 0; 2520} 2521 2522static int smu_v13_0_0_get_power_profile_mode(struct smu_context *smu, 2523 char *buf) 2524{ 2525 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 2526 DpmActivityMonitorCoeffInt_t *activity_monitor = 2527 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 2528 static const char *title[] = { 2529 "PROFILE_INDEX(NAME)", 2530 "CLOCK_TYPE(NAME)", 2531 "FPS", 2532 "MinActiveFreqType", 2533 "MinActiveFreq", 2534 "BoosterFreqType", 2535 "BoosterFreq", 2536 "PD_Data_limit_c", 2537 "PD_Data_error_coeff", 2538 "PD_Data_error_rate_coeff"}; 2539 int16_t workload_type = 0; 2540 uint32_t i, size = 0; 2541 int result = 0; 2542 2543 if (!buf) 2544 return -EINVAL; 2545 2546 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s\n", 2547 title[0], title[1], title[2], title[3], title[4], title[5], 2548 title[6], title[7], title[8], title[9]); 2549 2550 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 2551 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 2552 workload_type = smu_cmn_to_asic_specific_index(smu, 2553 CMN2ASIC_MAPPING_WORKLOAD, 2554 i); 2555 if (workload_type == -ENOTSUPP) 2556 continue; 2557 else if (workload_type < 0) 2558 return -EINVAL; 2559 2560 result = smu_cmn_update_table(smu, 2561 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 2562 workload_type, 2563 (void *)(&activity_monitor_external), 2564 false); 2565 if (result) { 2566 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 2567 return result; 2568 } 2569 2570 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n", 2571 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 2572 2573 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n", 2574 " ", 2575 0, 2576 "GFXCLK", 2577 activity_monitor->Gfx_FPS, 2578 activity_monitor->Gfx_MinActiveFreqType, 2579 activity_monitor->Gfx_MinActiveFreq, 2580 activity_monitor->Gfx_BoosterFreqType, 2581 activity_monitor->Gfx_BoosterFreq, 2582 activity_monitor->Gfx_PD_Data_limit_c, 2583 activity_monitor->Gfx_PD_Data_error_coeff, 2584 activity_monitor->Gfx_PD_Data_error_rate_coeff); 2585 2586 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n", 2587 " ", 2588 1, 2589 "FCLK", 2590 activity_monitor->Fclk_FPS, 2591 activity_monitor->Fclk_MinActiveFreqType, 2592 activity_monitor->Fclk_MinActiveFreq, 2593 activity_monitor->Fclk_BoosterFreqType, 2594 activity_monitor->Fclk_BoosterFreq, 2595 activity_monitor->Fclk_PD_Data_limit_c, 2596 activity_monitor->Fclk_PD_Data_error_coeff, 2597 activity_monitor->Fclk_PD_Data_error_rate_coeff); 2598 } 2599 2600 return size; 2601} 2602 2603#define SMU_13_0_0_CUSTOM_PARAMS_COUNT 9 2604#define SMU_13_0_0_CUSTOM_PARAMS_CLOCK_COUNT 2 2605#define SMU_13_0_0_CUSTOM_PARAMS_SIZE (SMU_13_0_0_CUSTOM_PARAMS_CLOCK_COUNT * SMU_13_0_0_CUSTOM_PARAMS_COUNT * sizeof(long)) 2606 2607static int smu_v13_0_0_set_power_profile_mode_coeff(struct smu_context *smu, 2608 long *input) 2609{ 2610 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 2611 DpmActivityMonitorCoeffInt_t *activity_monitor = 2612 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 2613 int ret, idx; 2614 2615 ret = smu_cmn_update_table(smu, 2616 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 2617 WORKLOAD_PPLIB_CUSTOM_BIT, 2618 (void *)(&activity_monitor_external), 2619 false); 2620 if (ret) { 2621 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 2622 return ret; 2623 } 2624 2625 idx = 0 * SMU_13_0_0_CUSTOM_PARAMS_COUNT; 2626 if (input[idx]) { 2627 /* Gfxclk */ 2628 activity_monitor->Gfx_FPS = input[idx + 1]; 2629 activity_monitor->Gfx_MinActiveFreqType = input[idx + 2]; 2630 activity_monitor->Gfx_MinActiveFreq = input[idx + 3]; 2631 activity_monitor->Gfx_BoosterFreqType = input[idx + 4]; 2632 activity_monitor->Gfx_BoosterFreq = input[idx + 5]; 2633 activity_monitor->Gfx_PD_Data_limit_c = input[idx + 6]; 2634 activity_monitor->Gfx_PD_Data_error_coeff = input[idx + 7]; 2635 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[idx + 8]; 2636 } 2637 idx = 1 * SMU_13_0_0_CUSTOM_PARAMS_COUNT; 2638 if (input[idx]) { 2639 /* Fclk */ 2640 activity_monitor->Fclk_FPS = input[idx + 1]; 2641 activity_monitor->Fclk_MinActiveFreqType = input[idx + 2]; 2642 activity_monitor->Fclk_MinActiveFreq = input[idx + 3]; 2643 activity_monitor->Fclk_BoosterFreqType = input[idx + 4]; 2644 activity_monitor->Fclk_BoosterFreq = input[idx + 5]; 2645 activity_monitor->Fclk_PD_Data_limit_c = input[idx + 6]; 2646 activity_monitor->Fclk_PD_Data_error_coeff = input[idx + 7]; 2647 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[idx + 8]; 2648 } 2649 2650 ret = smu_cmn_update_table(smu, 2651 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 2652 WORKLOAD_PPLIB_CUSTOM_BIT, 2653 (void *)(&activity_monitor_external), 2654 true); 2655 if (ret) { 2656 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 2657 return ret; 2658 } 2659 2660 return ret; 2661} 2662 2663static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, 2664 u32 workload_mask, 2665 long *custom_params, 2666 u32 custom_params_max_idx) 2667{ 2668 u32 backend_workload_mask = 0; 2669 int workload_type, ret, idx = -1, i; 2670 2671 smu_cmn_get_backend_workload_mask(smu, workload_mask, 2672 &backend_workload_mask); 2673 2674 /* Add optimizations for SMU13.0.0/10. Reuse the power saving profile */ 2675 if ((workload_mask & (1 << PP_SMC_POWER_PROFILE_COMPUTE)) && 2676 ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0) && 2677 ((smu->adev->pm.fw_version == 0x004e6601) || 2678 (smu->adev->pm.fw_version >= 0x004e7300))) || 2679 (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) && 2680 smu->adev->pm.fw_version >= 0x00504500))) { 2681 workload_type = smu_cmn_to_asic_specific_index(smu, 2682 CMN2ASIC_MAPPING_WORKLOAD, 2683 PP_SMC_POWER_PROFILE_POWERSAVING); 2684 if (workload_type >= 0) 2685 backend_workload_mask |= 1 << workload_type; 2686 } 2687 2688 if (workload_mask & (1 << PP_SMC_POWER_PROFILE_CUSTOM)) { 2689 if (!smu->custom_profile_params) { 2690 smu->custom_profile_params = 2691 kzalloc(SMU_13_0_0_CUSTOM_PARAMS_SIZE, GFP_KERNEL); 2692 if (!smu->custom_profile_params) 2693 return -ENOMEM; 2694 } 2695 if (custom_params && custom_params_max_idx) { 2696 if (custom_params_max_idx != SMU_13_0_0_CUSTOM_PARAMS_COUNT) 2697 return -EINVAL; 2698 if (custom_params[0] >= SMU_13_0_0_CUSTOM_PARAMS_CLOCK_COUNT) 2699 return -EINVAL; 2700 idx = custom_params[0] * SMU_13_0_0_CUSTOM_PARAMS_COUNT; 2701 smu->custom_profile_params[idx] = 1; 2702 for (i = 1; i < custom_params_max_idx; i++) 2703 smu->custom_profile_params[idx + i] = custom_params[i]; 2704 } 2705 ret = smu_v13_0_0_set_power_profile_mode_coeff(smu, 2706 smu->custom_profile_params); 2707 if (ret) { 2708 if (idx != -1) 2709 smu->custom_profile_params[idx] = 0; 2710 return ret; 2711 } 2712 } else if (smu->custom_profile_params) { 2713 memset(smu->custom_profile_params, 0, SMU_13_0_0_CUSTOM_PARAMS_SIZE); 2714 } 2715 2716 ret = smu_cmn_send_smc_msg_with_param(smu, 2717 SMU_MSG_SetWorkloadMask, 2718 backend_workload_mask, 2719 NULL); 2720 if (ret) { 2721 dev_err(smu->adev->dev, "Failed to set workload mask 0x%08x\n", 2722 workload_mask); 2723 if (idx != -1) 2724 smu->custom_profile_params[idx] = 0; 2725 return ret; 2726 } 2727 2728 return ret; 2729} 2730 2731static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu) 2732{ 2733 struct amdgpu_device *adev = smu->adev; 2734 u32 smu_version; 2735 int ret; 2736 2737 /* SRIOV does not support SMU mode1 reset */ 2738 if (amdgpu_sriov_vf(adev)) 2739 return false; 2740 2741 /* PMFW support is available since 78.41 */ 2742 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 2743 if (ret) 2744 return false; 2745 2746 if (smu_version < 0x004e2900) 2747 return false; 2748 2749 return true; 2750} 2751 2752static int smu_v13_0_0_i2c_xfer(struct i2c_adapter *i2c_adap, 2753 struct i2c_msg *msg, int num_msgs) 2754{ 2755 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 2756 struct amdgpu_device *adev = smu_i2c->adev; 2757 struct smu_context *smu = adev->powerplay.pp_handle; 2758 struct smu_table_context *smu_table = &smu->smu_table; 2759 struct smu_table *table = &smu_table->driver_table; 2760 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 2761 int i, j, r, c; 2762 u16 dir; 2763 2764 if (!adev->pm.dpm_enabled) 2765 return -EBUSY; 2766 2767 req = kzalloc(sizeof(*req), GFP_KERNEL); 2768 if (!req) 2769 return -ENOMEM; 2770 2771 req->I2CcontrollerPort = smu_i2c->port; 2772 req->I2CSpeed = I2C_SPEED_FAST_400K; 2773 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 2774 dir = msg[0].flags & I2C_M_RD; 2775 2776 for (c = i = 0; i < num_msgs; i++) { 2777 for (j = 0; j < msg[i].len; j++, c++) { 2778 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 2779 2780 if (!(msg[i].flags & I2C_M_RD)) { 2781 /* write */ 2782 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK; 2783 cmd->ReadWriteData = msg[i].buf[j]; 2784 } 2785 2786 if ((dir ^ msg[i].flags) & I2C_M_RD) { 2787 /* The direction changes. 2788 */ 2789 dir = msg[i].flags & I2C_M_RD; 2790 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 2791 } 2792 2793 req->NumCmds++; 2794 2795 /* 2796 * Insert STOP if we are at the last byte of either last 2797 * message for the transaction or the client explicitly 2798 * requires a STOP at this particular message. 2799 */ 2800 if ((j == msg[i].len - 1) && 2801 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 2802 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 2803 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 2804 } 2805 } 2806 } 2807 mutex_lock(&adev->pm.mutex); 2808 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 2809 if (r) 2810 goto fail; 2811 2812 for (c = i = 0; i < num_msgs; i++) { 2813 if (!(msg[i].flags & I2C_M_RD)) { 2814 c += msg[i].len; 2815 continue; 2816 } 2817 for (j = 0; j < msg[i].len; j++, c++) { 2818 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 2819 2820 msg[i].buf[j] = cmd->ReadWriteData; 2821 } 2822 } 2823 r = num_msgs; 2824fail: 2825 mutex_unlock(&adev->pm.mutex); 2826 kfree(req); 2827 return r; 2828} 2829 2830static u32 smu_v13_0_0_i2c_func(struct i2c_adapter *adap) 2831{ 2832 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 2833} 2834 2835static const struct i2c_algorithm smu_v13_0_0_i2c_algo = { 2836 .master_xfer = smu_v13_0_0_i2c_xfer, 2837 .functionality = smu_v13_0_0_i2c_func, 2838}; 2839 2840static const struct i2c_adapter_quirks smu_v13_0_0_i2c_control_quirks = { 2841 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 2842 .max_read_len = MAX_SW_I2C_COMMANDS, 2843 .max_write_len = MAX_SW_I2C_COMMANDS, 2844 .max_comb_1st_msg_len = 2, 2845 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 2846}; 2847 2848static int smu_v13_0_0_i2c_control_init(struct smu_context *smu) 2849{ 2850 struct amdgpu_device *adev = smu->adev; 2851 int res, i; 2852 2853 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 2854 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 2855 struct i2c_adapter *control = &smu_i2c->adapter; 2856 2857 smu_i2c->adev = adev; 2858 smu_i2c->port = i; 2859 mutex_init(&smu_i2c->mutex); 2860 control->owner = THIS_MODULE; 2861 control->dev.parent = &adev->pdev->dev; 2862 control->algo = &smu_v13_0_0_i2c_algo; 2863 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); 2864 control->quirks = &smu_v13_0_0_i2c_control_quirks; 2865 i2c_set_adapdata(control, smu_i2c); 2866 2867 res = devm_i2c_add_adapter(adev->dev, control); 2868 if (res) { 2869 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 2870 return res; 2871 } 2872 } 2873 2874 /* assign the buses used for the FRU EEPROM and RAS EEPROM */ 2875 /* XXX ideally this would be something in a vbios data table */ 2876 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; 2877 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 2878 2879 return 0; 2880} 2881 2882static void smu_v13_0_0_i2c_control_fini(struct smu_context *smu) 2883{ 2884 struct amdgpu_device *adev = smu->adev; 2885 2886 adev->pm.ras_eeprom_i2c_bus = NULL; 2887 adev->pm.fru_eeprom_i2c_bus = NULL; 2888} 2889 2890static int smu_v13_0_0_set_mp1_state(struct smu_context *smu, 2891 enum pp_mp1_state mp1_state) 2892{ 2893 int ret; 2894 2895 switch (mp1_state) { 2896 case PP_MP1_STATE_UNLOAD: 2897 ret = smu_cmn_send_smc_msg_with_param(smu, 2898 SMU_MSG_PrepareMp1ForUnload, 2899 0x55, NULL); 2900 2901 if (!ret && smu->smu_baco.state == SMU_BACO_STATE_EXIT) 2902 ret = smu_v13_0_disable_pmfw_state(smu); 2903 2904 break; 2905 default: 2906 /* Ignore others */ 2907 ret = 0; 2908 } 2909 2910 return ret; 2911} 2912 2913static int smu_v13_0_0_set_df_cstate(struct smu_context *smu, 2914 enum pp_df_cstate state) 2915{ 2916 return smu_cmn_send_smc_msg_with_param(smu, 2917 SMU_MSG_DFCstateControl, 2918 state, 2919 NULL); 2920} 2921 2922static void smu_v13_0_0_set_mode1_reset_param(struct smu_context *smu, 2923 uint32_t supported_version, 2924 uint32_t *param) 2925{ 2926 struct amdgpu_device *adev = smu->adev; 2927 2928 if ((smu->smc_fw_version >= supported_version) && 2929 amdgpu_ras_get_fed_status(adev)) 2930 /* Set RAS fatal error reset flag */ 2931 *param = 1 << 16; 2932 else 2933 *param = 0; 2934} 2935 2936static int smu_v13_0_0_mode1_reset(struct smu_context *smu) 2937{ 2938 int ret; 2939 uint32_t param; 2940 struct amdgpu_device *adev = smu->adev; 2941 2942 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2943 case IP_VERSION(13, 0, 0): 2944 /* SMU 13_0_0 PMFW supports RAS fatal error reset from 78.77 */ 2945 smu_v13_0_0_set_mode1_reset_param(smu, 0x004e4d00, ¶m); 2946 2947 ret = smu_cmn_send_smc_msg_with_param(smu, 2948 SMU_MSG_Mode1Reset, param, NULL); 2949 break; 2950 2951 case IP_VERSION(13, 0, 10): 2952 /* SMU 13_0_10 PMFW supports RAS fatal error reset from 80.28 */ 2953 smu_v13_0_0_set_mode1_reset_param(smu, 0x00501c00, ¶m); 2954 2955 ret = smu_cmn_send_debug_smc_msg_with_param(smu, 2956 DEBUGSMC_MSG_Mode1Reset, param); 2957 break; 2958 2959 default: 2960 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); 2961 break; 2962 } 2963 2964 if (!ret) { 2965 /* disable mmio access while doing mode 1 reset*/ 2966 smu->adev->no_hw_access = true; 2967 /* ensure no_hw_access is globally visible before any MMIO */ 2968 smp_mb(); 2969 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); 2970 } 2971 2972 return ret; 2973} 2974 2975static int smu_v13_0_0_mode2_reset(struct smu_context *smu) 2976{ 2977 int ret; 2978 struct amdgpu_device *adev = smu->adev; 2979 2980 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10)) 2981 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode2Reset, NULL); 2982 else 2983 return -EOPNOTSUPP; 2984 2985 return ret; 2986} 2987 2988static int smu_v13_0_0_enable_gfx_features(struct smu_context *smu) 2989{ 2990 struct amdgpu_device *adev = smu->adev; 2991 2992 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10)) 2993 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableAllSmuFeatures, 2994 FEATURE_PWR_GFX, NULL); 2995 else 2996 return -EOPNOTSUPP; 2997} 2998 2999static void smu_v13_0_0_set_smu_mailbox_registers(struct smu_context *smu) 3000{ 3001 struct amdgpu_device *adev = smu->adev; 3002 3003 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 3004 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 3005 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 3006 3007 smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53); 3008 smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75); 3009 smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54); 3010} 3011 3012static int smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context *smu, 3013 uint32_t size) 3014{ 3015 int ret = 0; 3016 3017 /* message SMU to update the bad page number on SMUBUS */ 3018 ret = smu_cmn_send_smc_msg_with_param(smu, 3019 SMU_MSG_SetNumBadMemoryPagesRetired, 3020 size, NULL); 3021 if (ret) 3022 dev_err(smu->adev->dev, 3023 "[%s] failed to message SMU to update bad memory pages number\n", 3024 __func__); 3025 3026 return ret; 3027} 3028 3029static int smu_v13_0_0_send_bad_mem_channel_flag(struct smu_context *smu, 3030 uint32_t size) 3031{ 3032 int ret = 0; 3033 3034 /* message SMU to update the bad channel info on SMUBUS */ 3035 ret = smu_cmn_send_smc_msg_with_param(smu, 3036 SMU_MSG_SetBadMemoryPagesRetiredFlagsPerChannel, 3037 size, NULL); 3038 if (ret) 3039 dev_err(smu->adev->dev, 3040 "[%s] failed to message SMU to update bad memory pages channel info\n", 3041 __func__); 3042 3043 return ret; 3044} 3045 3046static int smu_v13_0_0_check_ecc_table_support(struct smu_context *smu) 3047{ 3048 struct amdgpu_device *adev = smu->adev; 3049 int ret = 0; 3050 3051 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10)) && 3052 (smu->smc_fw_version >= SUPPORT_ECCTABLE_SMU_13_0_10_VERSION)) 3053 return ret; 3054 else 3055 return -EOPNOTSUPP; 3056} 3057 3058static ssize_t smu_v13_0_0_get_ecc_info(struct smu_context *smu, 3059 void *table) 3060{ 3061 struct smu_table_context *smu_table = &smu->smu_table; 3062 struct amdgpu_device *adev = smu->adev; 3063 EccInfoTable_t *ecc_table = NULL; 3064 struct ecc_info_per_ch *ecc_info_per_channel = NULL; 3065 int i, ret = 0; 3066 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table; 3067 3068 ret = smu_v13_0_0_check_ecc_table_support(smu); 3069 if (ret) 3070 return ret; 3071 3072 ret = smu_cmn_update_table(smu, 3073 SMU_TABLE_ECCINFO, 3074 0, 3075 smu_table->ecc_table, 3076 false); 3077 if (ret) { 3078 dev_info(adev->dev, "Failed to export SMU ecc table!\n"); 3079 return ret; 3080 } 3081 3082 ecc_table = (EccInfoTable_t *)smu_table->ecc_table; 3083 3084 for (i = 0; i < ARRAY_SIZE(ecc_table->EccInfo); i++) { 3085 ecc_info_per_channel = &(eccinfo->ecc[i]); 3086 ecc_info_per_channel->ce_count_lo_chip = 3087 ecc_table->EccInfo[i].ce_count_lo_chip; 3088 ecc_info_per_channel->ce_count_hi_chip = 3089 ecc_table->EccInfo[i].ce_count_hi_chip; 3090 ecc_info_per_channel->mca_umc_status = 3091 ecc_table->EccInfo[i].mca_umc_status; 3092 ecc_info_per_channel->mca_umc_addr = 3093 ecc_table->EccInfo[i].mca_umc_addr; 3094 } 3095 3096 return ret; 3097} 3098 3099static bool smu_v13_0_0_wbrf_support_check(struct smu_context *smu) 3100{ 3101 struct amdgpu_device *adev = smu->adev; 3102 3103 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 3104 case IP_VERSION(13, 0, 0): 3105 return smu->smc_fw_version >= 0x004e6300; 3106 case IP_VERSION(13, 0, 10): 3107 return smu->smc_fw_version >= 0x00503300; 3108 default: 3109 return false; 3110 } 3111} 3112 3113static int smu_v13_0_0_set_power_limit(struct smu_context *smu, 3114 enum smu_ppt_limit_type limit_type, 3115 uint32_t limit) 3116{ 3117 PPTable_t *pptable = smu->smu_table.driver_pptable; 3118 SkuTable_t *skutable = &pptable->SkuTable; 3119 uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC]; 3120 struct smu_table_context *table_context = &smu->smu_table; 3121 OverDriveTableExternal_t *od_table = 3122 (OverDriveTableExternal_t *)table_context->overdrive_table; 3123 int ret = 0; 3124 3125 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 3126 return -EINVAL; 3127 3128 if (limit <= msg_limit) { 3129 if (smu->current_power_limit > msg_limit) { 3130 od_table->OverDriveTable.Ppt = 0; 3131 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT; 3132 3133 ret = smu_v13_0_0_upload_overdrive_table(smu, od_table); 3134 if (ret) { 3135 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n"); 3136 return ret; 3137 } 3138 } 3139 return smu_v13_0_set_power_limit(smu, limit_type, limit); 3140 } else if (smu->od_enabled) { 3141 ret = smu_v13_0_set_power_limit(smu, limit_type, msg_limit); 3142 if (ret) 3143 return ret; 3144 3145 od_table->OverDriveTable.Ppt = (limit * 100) / msg_limit - 100; 3146 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT; 3147 3148 ret = smu_v13_0_0_upload_overdrive_table(smu, od_table); 3149 if (ret) { 3150 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n"); 3151 return ret; 3152 } 3153 3154 smu->current_power_limit = limit; 3155 } else { 3156 return -EINVAL; 3157 } 3158 3159 return 0; 3160} 3161 3162static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu, 3163 uint8_t pcie_gen_cap, 3164 uint8_t pcie_width_cap) 3165{ 3166 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 3167 struct smu_13_0_pcie_table *pcie_table = 3168 &dpm_context->dpm_tables.pcie_table; 3169 int num_of_levels; 3170 uint32_t smu_pcie_arg; 3171 uint32_t link_level; 3172 struct smu_table_context *table_context = &smu->smu_table; 3173 PPTable_t *pptable = table_context->driver_pptable; 3174 SkuTable_t *skutable = &pptable->SkuTable; 3175 int ret = 0; 3176 int i; 3177 3178 pcie_table->num_of_link_levels = 0; 3179 3180 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) { 3181 if (!skutable->PcieGenSpeed[link_level] && 3182 !skutable->PcieLaneCount[link_level] && 3183 !skutable->LclkFreq[link_level]) 3184 continue; 3185 3186 pcie_table->pcie_gen[pcie_table->num_of_link_levels] = 3187 skutable->PcieGenSpeed[link_level]; 3188 pcie_table->pcie_lane[pcie_table->num_of_link_levels] = 3189 skutable->PcieLaneCount[link_level]; 3190 pcie_table->clk_freq[pcie_table->num_of_link_levels] = 3191 skutable->LclkFreq[link_level]; 3192 pcie_table->num_of_link_levels++; 3193 } 3194 3195 num_of_levels = pcie_table->num_of_link_levels; 3196 if (!num_of_levels) 3197 return 0; 3198 3199 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { 3200 if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap) 3201 pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1]; 3202 3203 if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap) 3204 pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1]; 3205 3206 /* Force all levels to use the same settings */ 3207 for (i = 0; i < num_of_levels; i++) { 3208 pcie_table->pcie_gen[i] = pcie_gen_cap; 3209 pcie_table->pcie_lane[i] = pcie_width_cap; 3210 smu_pcie_arg = i << 16; 3211 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8; 3212 smu_pcie_arg |= pcie_table->pcie_lane[i]; 3213 3214 ret = smu_cmn_send_smc_msg_with_param(smu, 3215 SMU_MSG_OverridePcieParameters, 3216 smu_pcie_arg, 3217 NULL); 3218 if (ret) 3219 break; 3220 } 3221 } else { 3222 for (i = 0; i < num_of_levels; i++) { 3223 if (pcie_table->pcie_gen[i] > pcie_gen_cap || 3224 pcie_table->pcie_lane[i] > pcie_width_cap) { 3225 pcie_table->pcie_gen[i] = pcie_table->pcie_gen[i] > pcie_gen_cap ? 3226 pcie_gen_cap : pcie_table->pcie_gen[i]; 3227 pcie_table->pcie_lane[i] = pcie_table->pcie_lane[i] > pcie_width_cap ? 3228 pcie_width_cap : pcie_table->pcie_lane[i]; 3229 smu_pcie_arg = i << 16; 3230 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8; 3231 smu_pcie_arg |= pcie_table->pcie_lane[i]; 3232 3233 ret = smu_cmn_send_smc_msg_with_param(smu, 3234 SMU_MSG_OverridePcieParameters, 3235 smu_pcie_arg, 3236 NULL); 3237 if (ret) 3238 break; 3239 } 3240 } 3241 } 3242 3243 return ret; 3244} 3245 3246static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { 3247 .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask, 3248 .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table, 3249 .i2c_init = smu_v13_0_0_i2c_control_init, 3250 .i2c_fini = smu_v13_0_0_i2c_control_fini, 3251 .is_dpm_running = smu_v13_0_0_is_dpm_running, 3252 .init_microcode = smu_v13_0_init_microcode, 3253 .load_microcode = smu_v13_0_load_microcode, 3254 .fini_microcode = smu_v13_0_fini_microcode, 3255 .init_smc_tables = smu_v13_0_0_init_smc_tables, 3256 .fini_smc_tables = smu_v13_0_fini_smc_tables, 3257 .init_power = smu_v13_0_init_power, 3258 .fini_power = smu_v13_0_fini_power, 3259 .check_fw_status = smu_v13_0_check_fw_status, 3260 .setup_pptable = smu_v13_0_0_setup_pptable, 3261 .check_fw_version = smu_v13_0_check_fw_version, 3262 .write_pptable = smu_cmn_write_pptable, 3263 .set_driver_table_location = smu_v13_0_set_driver_table_location, 3264 .system_features_control = smu_v13_0_0_system_features_control, 3265 .set_allowed_mask = smu_v13_0_set_allowed_mask, 3266 .get_enabled_mask = smu_cmn_get_enabled_mask, 3267 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable, 3268 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable, 3269 .get_dpm_ultimate_freq = smu_v13_0_0_get_dpm_ultimate_freq, 3270 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 3271 .read_sensor = smu_v13_0_0_read_sensor, 3272 .feature_is_enabled = smu_cmn_feature_is_enabled, 3273 .print_clk_levels = smu_v13_0_0_print_clk_levels, 3274 .force_clk_levels = smu_v13_0_0_force_clk_levels, 3275 .update_pcie_parameters = smu_v13_0_0_update_pcie_parameters, 3276 .get_thermal_temperature_range = smu_v13_0_0_get_thermal_temperature_range, 3277 .register_irq_handler = smu_v13_0_register_irq_handler, 3278 .enable_thermal_alert = smu_v13_0_enable_thermal_alert, 3279 .disable_thermal_alert = smu_v13_0_disable_thermal_alert, 3280 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 3281 .get_gpu_metrics = smu_v13_0_0_get_gpu_metrics, 3282 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range, 3283 .set_default_od_settings = smu_v13_0_0_set_default_od_settings, 3284 .restore_user_od_settings = smu_v13_0_0_restore_user_od_settings, 3285 .od_edit_dpm_table = smu_v13_0_0_od_edit_dpm_table, 3286 .init_pptable_microcode = smu_v13_0_init_pptable_microcode, 3287 .populate_umd_state_clk = smu_v13_0_0_populate_umd_state_clk, 3288 .set_performance_level = smu_v13_0_set_performance_level, 3289 .gfx_off_control = smu_v13_0_gfx_off_control, 3290 .get_unique_id = smu_v13_0_0_get_unique_id, 3291 .get_fan_speed_pwm = smu_v13_0_0_get_fan_speed_pwm, 3292 .get_fan_speed_rpm = smu_v13_0_0_get_fan_speed_rpm, 3293 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm, 3294 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm, 3295 .get_fan_control_mode = smu_v13_0_get_fan_control_mode, 3296 .set_fan_control_mode = smu_v13_0_set_fan_control_mode, 3297 .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost, 3298 .get_power_limit = smu_v13_0_0_get_power_limit, 3299 .set_power_limit = smu_v13_0_0_set_power_limit, 3300 .set_power_source = smu_v13_0_set_power_source, 3301 .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode, 3302 .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode, 3303 .run_btc = smu_v13_0_run_btc, 3304 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 3305 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 3306 .set_tool_table_location = smu_v13_0_set_tool_table_location, 3307 .deep_sleep_control = smu_v13_0_deep_sleep_control, 3308 .gfx_ulv_control = smu_v13_0_gfx_ulv_control, 3309 .get_bamaco_support = smu_v13_0_get_bamaco_support, 3310 .baco_enter = smu_v13_0_baco_enter, 3311 .baco_exit = smu_v13_0_baco_exit, 3312 .mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported, 3313 .mode1_reset = smu_v13_0_0_mode1_reset, 3314 .mode2_reset = smu_v13_0_0_mode2_reset, 3315 .enable_gfx_features = smu_v13_0_0_enable_gfx_features, 3316 .set_mp1_state = smu_v13_0_0_set_mp1_state, 3317 .set_df_cstate = smu_v13_0_0_set_df_cstate, 3318 .send_hbm_bad_pages_num = smu_v13_0_0_smu_send_bad_mem_page_num, 3319 .send_hbm_bad_channel_flag = smu_v13_0_0_send_bad_mem_channel_flag, 3320 .gpo_control = smu_v13_0_gpo_control, 3321 .get_ecc_info = smu_v13_0_0_get_ecc_info, 3322 .notify_display_change = smu_v13_0_notify_display_change, 3323 .is_asic_wbrf_supported = smu_v13_0_0_wbrf_support_check, 3324 .enable_uclk_shadow = smu_v13_0_enable_uclk_shadow, 3325 .set_wbrf_exclusion_ranges = smu_v13_0_set_wbrf_exclusion_ranges, 3326 .interrupt_work = smu_v13_0_interrupt_work, 3327}; 3328 3329void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu) 3330{ 3331 smu->ppt_funcs = &smu_v13_0_0_ppt_funcs; 3332 smu->message_map = smu_v13_0_0_message_map; 3333 smu->clock_map = smu_v13_0_0_clk_map; 3334 smu->feature_map = smu_v13_0_0_feature_mask_map; 3335 smu->table_map = smu_v13_0_0_table_map; 3336 smu->pwr_src_map = smu_v13_0_0_pwr_src_map; 3337 smu->workload_map = smu_v13_0_0_workload_map; 3338 smu->smc_driver_if_version = SMU13_0_0_DRIVER_IF_VERSION; 3339 smu_v13_0_0_set_smu_mailbox_registers(smu); 3340 3341 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == 3342 IP_VERSION(13, 0, 10) && 3343 !amdgpu_device_has_display_hardware(smu->adev)) 3344 smu->adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3345}
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