smu_v11_0.c

   1/*
   2 * Copyright 2019 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 */
  22
  23#include <linux/firmware.h>
  24#include <linux/module.h>
  25#include <linux/pci.h>
  26#include <linux/reboot.h>
  27
  28#define SMU_11_0_PARTIAL_PPTABLE
  29#define SWSMU_CODE_LAYER_L3
  30
  31#include "amdgpu.h"
  32#include "amdgpu_smu.h"
  33#include "atomfirmware.h"
  34#include "amdgpu_atomfirmware.h"
  35#include "amdgpu_atombios.h"
  36#include "smu_v11_0.h"
  37#include "soc15_common.h"
  38#include "atom.h"
  39#include "amdgpu_ras.h"
  40#include "smu_cmn.h"
  41
  42#include "asic_reg/thm/thm_11_0_2_offset.h"
  43#include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  44#include "asic_reg/mp/mp_11_0_offset.h"
  45#include "asic_reg/mp/mp_11_0_sh_mask.h"
  46#include "asic_reg/smuio/smuio_11_0_0_offset.h"
  47#include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  48
  49/*
  50 * DO NOT use these for err/warn/info/debug messages.
  51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  52 * They are more MGPU friendly.
  53 */
  54#undef pr_err
  55#undef pr_warn
  56#undef pr_info
  57#undef pr_debug
  58
  59MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
  60MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  61MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
  62MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
  63MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
  64MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
  65MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
  66MODULE_FIRMWARE("amdgpu/beige_goby_smc.bin");
  67
  68#define SMU11_VOLTAGE_SCALE 4
  69
  70#define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms
  71
  72#define smnPCIE_LC_LINK_WIDTH_CNTL		0x11140288
  73#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
  74#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
  75#define smnPCIE_LC_SPEED_CNTL			0x11140290
  76#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
  77#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
  78
  79#define mmTHM_BACO_CNTL_ARCT			0xA7
  80#define mmTHM_BACO_CNTL_ARCT_BASE_IDX		0
  81
  82static void smu_v11_0_poll_baco_exit(struct smu_context *smu)
  83{
  84	struct amdgpu_device *adev = smu->adev;
  85	uint32_t data, loop = 0;
  86
  87	do {
  88		usleep_range(1000, 1100);
  89		data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
  90	} while ((data & 0x100) && (++loop < 100));
  91}
  92
  93int smu_v11_0_init_microcode(struct smu_context *smu)
  94{
  95	struct amdgpu_device *adev = smu->adev;
  96	char ucode_prefix[25];
  97	int err = 0;
  98	const struct smc_firmware_header_v1_0 *hdr;
  99	const struct common_firmware_header *header;
 100	struct amdgpu_firmware_info *ucode = NULL;
 101
 102	if (amdgpu_sriov_vf(adev) &&
 103	    ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 9)) ||
 104	     (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7))))
 105		return 0;
 106
 107	amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
 108	err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
 109				   "amdgpu/%s.bin", ucode_prefix);
 110	if (err)
 111		goto out;
 112
 113	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 114	amdgpu_ucode_print_smc_hdr(&hdr->header);
 115	adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 116
 117	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 118		ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 119		ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 120		ucode->fw = adev->pm.fw;
 121		header = (const struct common_firmware_header *)ucode->fw->data;
 122		adev->firmware.fw_size +=
 123			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 124	}
 125
 126out:
 127	if (err)
 128		amdgpu_ucode_release(&adev->pm.fw);
 129	return err;
 130}
 131
 132void smu_v11_0_fini_microcode(struct smu_context *smu)
 133{
 134	struct amdgpu_device *adev = smu->adev;
 135
 136	amdgpu_ucode_release(&adev->pm.fw);
 137	adev->pm.fw_version = 0;
 138}
 139
 140int smu_v11_0_load_microcode(struct smu_context *smu)
 141{
 142	struct amdgpu_device *adev = smu->adev;
 143	const uint32_t *src;
 144	const struct smc_firmware_header_v1_0 *hdr;
 145	uint32_t addr_start = MP1_SRAM;
 146	uint32_t i;
 147	uint32_t smc_fw_size;
 148	uint32_t mp1_fw_flags;
 149
 150	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 151	src = (const uint32_t *)(adev->pm.fw->data +
 152		le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 153	smc_fw_size = hdr->header.ucode_size_bytes;
 154
 155	for (i = 1; i < smc_fw_size/4 - 1; i++) {
 156		WREG32_PCIE(addr_start, src[i]);
 157		addr_start += 4;
 158	}
 159
 160	WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 161		1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 162	WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 163		1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 164
 165	for (i = 0; i < adev->usec_timeout; i++) {
 166		mp1_fw_flags = RREG32_PCIE(MP1_Public |
 167			(smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 168		if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 169			MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 170			break;
 171		udelay(1);
 172	}
 173
 174	if (i == adev->usec_timeout)
 175		return -ETIME;
 176
 177	return 0;
 178}
 179
 180int smu_v11_0_check_fw_status(struct smu_context *smu)
 181{
 182	struct amdgpu_device *adev = smu->adev;
 183	uint32_t mp1_fw_flags;
 184
 185	mp1_fw_flags = RREG32_PCIE(MP1_Public |
 186				   (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 187
 188	if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 189	    MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 190		return 0;
 191
 192	return -EIO;
 193}
 194
 195int smu_v11_0_check_fw_version(struct smu_context *smu)
 196{
 197	struct amdgpu_device *adev = smu->adev;
 198	uint32_t if_version = 0xff, smu_version = 0xff;
 199	uint8_t smu_program, smu_major, smu_minor, smu_debug;
 200	int ret = 0;
 201
 202	ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
 203	if (ret)
 204		return ret;
 205
 206	smu_program = (smu_version >> 24) & 0xff;
 207	smu_major = (smu_version >> 16) & 0xff;
 208	smu_minor = (smu_version >> 8) & 0xff;
 209	smu_debug = (smu_version >> 0) & 0xff;
 210	if (smu->is_apu)
 211		adev->pm.fw_version = smu_version;
 212
 213	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
 214	case IP_VERSION(11, 0, 0):
 215		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
 216		break;
 217	case IP_VERSION(11, 0, 9):
 218		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
 219		break;
 220	case IP_VERSION(11, 0, 5):
 221		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
 222		break;
 223	case IP_VERSION(11, 0, 7):
 224		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
 225		break;
 226	case IP_VERSION(11, 0, 11):
 227		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
 228		break;
 229	case IP_VERSION(11, 5, 0):
 230	case IP_VERSION(11, 5, 2):
 231		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
 232		break;
 233	case IP_VERSION(11, 0, 12):
 234		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
 235		break;
 236	case IP_VERSION(11, 0, 13):
 237		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby;
 238		break;
 239	case IP_VERSION(11, 0, 8):
 240		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Cyan_Skillfish;
 241		break;
 242	case IP_VERSION(11, 0, 2):
 243		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
 244		break;
 245	default:
 246		dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
 247			amdgpu_ip_version(adev, MP1_HWIP, 0));
 248		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
 249		break;
 250	}
 251
 252	/*
 253	 * 1. if_version mismatch is not critical as our fw is designed
 254	 * to be backward compatible.
 255	 * 2. New fw usually brings some optimizations. But that's visible
 256	 * only on the paired driver.
 257	 * Considering above, we just leave user a verbal message instead
 258	 * of halt driver loading.
 259	 */
 260	if (if_version != smu->smc_driver_if_version) {
 261		dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 262			"smu fw program = %d, version = 0x%08x (%d.%d.%d)\n",
 263			smu->smc_driver_if_version, if_version,
 264			smu_program, smu_version, smu_major, smu_minor, smu_debug);
 265	}
 266
 267	return ret;
 268}
 269
 270static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 271{
 272	struct amdgpu_device *adev = smu->adev;
 273	uint32_t ppt_offset_bytes;
 274	const struct smc_firmware_header_v2_0 *v2;
 275
 276	v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 277
 278	ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 279	*size = le32_to_cpu(v2->ppt_size_bytes);
 280	*table = (uint8_t *)v2 + ppt_offset_bytes;
 281
 282	return 0;
 283}
 284
 285static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 286				      uint32_t *size, uint32_t pptable_id)
 287{
 288	struct amdgpu_device *adev = smu->adev;
 289	const struct smc_firmware_header_v2_1 *v2_1;
 290	struct smc_soft_pptable_entry *entries;
 291	uint32_t pptable_count = 0;
 292	int i = 0;
 293
 294	v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 295	entries = (struct smc_soft_pptable_entry *)
 296		((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 297	pptable_count = le32_to_cpu(v2_1->pptable_count);
 298	for (i = 0; i < pptable_count; i++) {
 299		if (le32_to_cpu(entries[i].id) == pptable_id) {
 300			*table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 301			*size = le32_to_cpu(entries[i].ppt_size_bytes);
 302			break;
 303		}
 304	}
 305
 306	if (i == pptable_count)
 307		return -EINVAL;
 308
 309	return 0;
 310}
 311
 312int smu_v11_0_setup_pptable(struct smu_context *smu)
 313{
 314	struct amdgpu_device *adev = smu->adev;
 315	const struct smc_firmware_header_v1_0 *hdr;
 316	int ret, index;
 317	uint32_t size = 0;
 318	uint16_t atom_table_size;
 319	uint8_t frev, crev;
 320	void *table;
 321	uint16_t version_major, version_minor;
 322
 323	if (!amdgpu_sriov_vf(adev)) {
 324		hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 325		version_major = le16_to_cpu(hdr->header.header_version_major);
 326		version_minor = le16_to_cpu(hdr->header.header_version_minor);
 327		if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 328			dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
 329			switch (version_minor) {
 330			case 0:
 331				ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 332				break;
 333			case 1:
 334				ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 335								smu->smu_table.boot_values.pp_table_id);
 336				break;
 337			default:
 338				ret = -EINVAL;
 339				break;
 340			}
 341			if (ret)
 342				return ret;
 343			goto out;
 344		}
 345	}
 346
 347	dev_info(adev->dev, "use vbios provided pptable\n");
 348	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 349						powerplayinfo);
 350
 351	ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
 352						(uint8_t **)&table);
 353	if (ret)
 354		return ret;
 355	size = atom_table_size;
 356
 357out:
 358	if (!smu->smu_table.power_play_table)
 359		smu->smu_table.power_play_table = table;
 360	if (!smu->smu_table.power_play_table_size)
 361		smu->smu_table.power_play_table_size = size;
 362
 363	return 0;
 364}
 365
 366int smu_v11_0_init_smc_tables(struct smu_context *smu)
 367{
 368	struct smu_table_context *smu_table = &smu->smu_table;
 369	struct smu_table *tables = smu_table->tables;
 370	int ret = 0;
 371
 372	smu_table->driver_pptable =
 373		kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
 374	if (!smu_table->driver_pptable) {
 375		ret = -ENOMEM;
 376		goto err0_out;
 377	}
 378
 379	smu_table->max_sustainable_clocks =
 380		kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL);
 381	if (!smu_table->max_sustainable_clocks) {
 382		ret = -ENOMEM;
 383		goto err1_out;
 384	}
 385
 386	/* Arcturus does not support OVERDRIVE */
 387	if (tables[SMU_TABLE_OVERDRIVE].size) {
 388		smu_table->overdrive_table =
 389			kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 390		if (!smu_table->overdrive_table) {
 391			ret = -ENOMEM;
 392			goto err2_out;
 393		}
 394
 395		smu_table->boot_overdrive_table =
 396			kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 397		if (!smu_table->boot_overdrive_table) {
 398			ret = -ENOMEM;
 399			goto err3_out;
 400		}
 401
 402		smu_table->user_overdrive_table =
 403			kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 404		if (!smu_table->user_overdrive_table) {
 405			ret = -ENOMEM;
 406			goto err4_out;
 407		}
 408
 409	}
 410
 411	return 0;
 412
 413err4_out:
 414	kfree(smu_table->boot_overdrive_table);
 415err3_out:
 416	kfree(smu_table->overdrive_table);
 417err2_out:
 418	kfree(smu_table->max_sustainable_clocks);
 419err1_out:
 420	kfree(smu_table->driver_pptable);
 421err0_out:
 422	return ret;
 423}
 424
 425int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 426{
 427	struct smu_table_context *smu_table = &smu->smu_table;
 428	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 429
 430	kfree(smu_table->gpu_metrics_table);
 431	kfree(smu_table->user_overdrive_table);
 432	kfree(smu_table->boot_overdrive_table);
 433	kfree(smu_table->overdrive_table);
 434	kfree(smu_table->max_sustainable_clocks);
 435	kfree(smu_table->driver_pptable);
 436	kfree(smu_table->clocks_table);
 437	smu_table->gpu_metrics_table = NULL;
 438	smu_table->user_overdrive_table = NULL;
 439	smu_table->boot_overdrive_table = NULL;
 440	smu_table->overdrive_table = NULL;
 441	smu_table->max_sustainable_clocks = NULL;
 442	smu_table->driver_pptable = NULL;
 443	smu_table->clocks_table = NULL;
 444	kfree(smu_table->hardcode_pptable);
 445	smu_table->hardcode_pptable = NULL;
 446
 447	kfree(smu_table->driver_smu_config_table);
 448	kfree(smu_table->ecc_table);
 449	kfree(smu_table->metrics_table);
 450	kfree(smu_table->watermarks_table);
 451	smu_table->driver_smu_config_table = NULL;
 452	smu_table->ecc_table = NULL;
 453	smu_table->metrics_table = NULL;
 454	smu_table->watermarks_table = NULL;
 455	smu_table->metrics_time = 0;
 456
 457	kfree(smu_dpm->dpm_context);
 458	kfree(smu_dpm->golden_dpm_context);
 459	kfree(smu_dpm->dpm_current_power_state);
 460	kfree(smu_dpm->dpm_request_power_state);
 461	smu_dpm->dpm_context = NULL;
 462	smu_dpm->golden_dpm_context = NULL;
 463	smu_dpm->dpm_context_size = 0;
 464	smu_dpm->dpm_current_power_state = NULL;
 465	smu_dpm->dpm_request_power_state = NULL;
 466
 467	return 0;
 468}
 469
 470int smu_v11_0_init_power(struct smu_context *smu)
 471{
 472	struct amdgpu_device *adev = smu->adev;
 473	struct smu_power_context *smu_power = &smu->smu_power;
 474	u32 ip_version = amdgpu_ip_version(adev, MP1_HWIP, 0);
 475	size_t size = ((ip_version == IP_VERSION(11, 5, 0)) ||
 476			(ip_version == IP_VERSION(11, 5, 2))) ?
 477				sizeof(struct smu_11_5_power_context) :
 478				sizeof(struct smu_11_0_power_context);
 479
 480	smu_power->power_context = kzalloc(size, GFP_KERNEL);
 481	if (!smu_power->power_context)
 482		return -ENOMEM;
 483	smu_power->power_context_size = size;
 484
 485	return 0;
 486}
 487
 488int smu_v11_0_fini_power(struct smu_context *smu)
 489{
 490	struct smu_power_context *smu_power = &smu->smu_power;
 491
 492	kfree(smu_power->power_context);
 493	smu_power->power_context = NULL;
 494	smu_power->power_context_size = 0;
 495
 496	return 0;
 497}
 498
 499static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
 500					    uint8_t clk_id,
 501					    uint8_t syspll_id,
 502					    uint32_t *clk_freq)
 503{
 504	struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 505	struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 506	int ret, index;
 507
 508	input.clk_id = clk_id;
 509	input.syspll_id = syspll_id;
 510	input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 511	index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 512					    getsmuclockinfo);
 513
 514	ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 515					(uint32_t *)&input, sizeof(input));
 516	if (ret)
 517		return -EINVAL;
 518
 519	output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 520	*clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 521
 522	return 0;
 523}
 524
 525int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 526{
 527	int ret, index;
 528	uint16_t size;
 529	uint8_t frev, crev;
 530	struct atom_common_table_header *header;
 531	struct atom_firmware_info_v3_3 *v_3_3;
 532	struct atom_firmware_info_v3_1 *v_3_1;
 533
 534	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 535					    firmwareinfo);
 536
 537	ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 538				      (uint8_t **)&header);
 539	if (ret)
 540		return ret;
 541
 542	if (header->format_revision != 3) {
 543		dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n");
 544		return -EINVAL;
 545	}
 546
 547	switch (header->content_revision) {
 548	case 0:
 549	case 1:
 550	case 2:
 551		v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 552		smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 553		smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 554		smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 555		smu->smu_table.boot_values.socclk = 0;
 556		smu->smu_table.boot_values.dcefclk = 0;
 557		smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 558		smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 559		smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 560		smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 561		smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 562		smu->smu_table.boot_values.pp_table_id = 0;
 563		smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability;
 564		break;
 565	case 3:
 566	case 4:
 567	default:
 568		v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 569		smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 570		smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 571		smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 572		smu->smu_table.boot_values.socclk = 0;
 573		smu->smu_table.boot_values.dcefclk = 0;
 574		smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 575		smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 576		smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 577		smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 578		smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 579		smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 580		smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability;
 581	}
 582
 583	smu->smu_table.boot_values.format_revision = header->format_revision;
 584	smu->smu_table.boot_values.content_revision = header->content_revision;
 585
 586	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 587					 (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
 588					 (uint8_t)0,
 589					 &smu->smu_table.boot_values.socclk);
 590
 591	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 592					 (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
 593					 (uint8_t)0,
 594					 &smu->smu_table.boot_values.dcefclk);
 595
 596	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 597					 (uint8_t)SMU11_SYSPLL0_ECLK_ID,
 598					 (uint8_t)0,
 599					 &smu->smu_table.boot_values.eclk);
 600
 601	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 602					 (uint8_t)SMU11_SYSPLL0_VCLK_ID,
 603					 (uint8_t)0,
 604					 &smu->smu_table.boot_values.vclk);
 605
 606	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 607					 (uint8_t)SMU11_SYSPLL0_DCLK_ID,
 608					 (uint8_t)0,
 609					 &smu->smu_table.boot_values.dclk);
 610
 611	if ((smu->smu_table.boot_values.format_revision == 3) &&
 612	    (smu->smu_table.boot_values.content_revision >= 2))
 613		smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 614						 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
 615						 (uint8_t)SMU11_SYSPLL1_2_ID,
 616						 &smu->smu_table.boot_values.fclk);
 617
 618	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 619					 (uint8_t)SMU11_SYSPLL3_1_LCLK_ID,
 620					 (uint8_t)SMU11_SYSPLL3_1_ID,
 621					 &smu->smu_table.boot_values.lclk);
 622
 623	return 0;
 624}
 625
 626int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 627{
 628	struct smu_table_context *smu_table = &smu->smu_table;
 629	struct smu_table *memory_pool = &smu_table->memory_pool;
 630	int ret = 0;
 631	uint64_t address;
 632	uint32_t address_low, address_high;
 633
 634	if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 635		return ret;
 636
 637	address = (uintptr_t)memory_pool->cpu_addr;
 638	address_high = (uint32_t)upper_32_bits(address);
 639	address_low  = (uint32_t)lower_32_bits(address);
 640
 641	ret = smu_cmn_send_smc_msg_with_param(smu,
 642					  SMU_MSG_SetSystemVirtualDramAddrHigh,
 643					  address_high,
 644					  NULL);
 645	if (ret)
 646		return ret;
 647	ret = smu_cmn_send_smc_msg_with_param(smu,
 648					  SMU_MSG_SetSystemVirtualDramAddrLow,
 649					  address_low,
 650					  NULL);
 651	if (ret)
 652		return ret;
 653
 654	address = memory_pool->mc_address;
 655	address_high = (uint32_t)upper_32_bits(address);
 656	address_low  = (uint32_t)lower_32_bits(address);
 657
 658	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 659					  address_high, NULL);
 660	if (ret)
 661		return ret;
 662	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 663					  address_low, NULL);
 664	if (ret)
 665		return ret;
 666	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 667					  (uint32_t)memory_pool->size, NULL);
 668	if (ret)
 669		return ret;
 670
 671	return ret;
 672}
 673
 674int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 675{
 676	int ret;
 677
 678	ret = smu_cmn_send_smc_msg_with_param(smu,
 679					  SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
 680	if (ret)
 681		dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!");
 682
 683	return ret;
 684}
 685
 686int smu_v11_0_set_driver_table_location(struct smu_context *smu)
 687{
 688	struct smu_table *driver_table = &smu->smu_table.driver_table;
 689	int ret = 0;
 690
 691	if (driver_table->mc_address) {
 692		ret = smu_cmn_send_smc_msg_with_param(smu,
 693				SMU_MSG_SetDriverDramAddrHigh,
 694				upper_32_bits(driver_table->mc_address),
 695				NULL);
 696		if (!ret)
 697			ret = smu_cmn_send_smc_msg_with_param(smu,
 698				SMU_MSG_SetDriverDramAddrLow,
 699				lower_32_bits(driver_table->mc_address),
 700				NULL);
 701	}
 702
 703	return ret;
 704}
 705
 706int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 707{
 708	int ret = 0;
 709	struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 710
 711	if (tool_table->mc_address) {
 712		ret = smu_cmn_send_smc_msg_with_param(smu,
 713				SMU_MSG_SetToolsDramAddrHigh,
 714				upper_32_bits(tool_table->mc_address),
 715				NULL);
 716		if (!ret)
 717			ret = smu_cmn_send_smc_msg_with_param(smu,
 718				SMU_MSG_SetToolsDramAddrLow,
 719				lower_32_bits(tool_table->mc_address),
 720				NULL);
 721	}
 722
 723	return ret;
 724}
 725
 726int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 727{
 728	struct amdgpu_device *adev = smu->adev;
 729
 730	/* Navy_Flounder/Dimgrey_Cavefish do not support to change
 731	 * display num currently
 732	 */
 733	if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 11) ||
 734	    amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) ||
 735	    amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2) ||
 736	    amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 12) ||
 737	    amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
 738		return 0;
 739
 740	return smu_cmn_send_smc_msg_with_param(smu,
 741					       SMU_MSG_NumOfDisplays,
 742					       count,
 743					       NULL);
 744}
 745
 746
 747int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 748{
 749	struct smu_feature *feature = &smu->smu_feature;
 750	int ret = 0;
 751	uint32_t feature_mask[2];
 752
 753	if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) {
 754		ret = -EINVAL;
 755		goto failed;
 756	}
 757
 758	bitmap_to_arr32(feature_mask, feature->allowed, 64);
 759
 760	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 761					  feature_mask[1], NULL);
 762	if (ret)
 763		goto failed;
 764
 765	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 766					  feature_mask[0], NULL);
 767	if (ret)
 768		goto failed;
 769
 770failed:
 771	return ret;
 772}
 773
 774int smu_v11_0_system_features_control(struct smu_context *smu,
 775					     bool en)
 776{
 777	return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 778					  SMU_MSG_DisableAllSmuFeatures), NULL);
 779}
 780
 781int smu_v11_0_notify_display_change(struct smu_context *smu)
 782{
 783	int ret = 0;
 784
 785	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 786	    smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 787		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
 788
 789	return ret;
 790}
 791
 792static int
 793smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 794				    enum smu_clk_type clock_select)
 795{
 796	int ret = 0;
 797	int clk_id;
 798
 799	if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 800	    (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
 801		return 0;
 802
 803	clk_id = smu_cmn_to_asic_specific_index(smu,
 804						CMN2ASIC_MAPPING_CLK,
 805						clock_select);
 806	if (clk_id < 0)
 807		return -EINVAL;
 808
 809	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 810					  clk_id << 16, clock);
 811	if (ret) {
 812		dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 813		return ret;
 814	}
 815
 816	if (*clock != 0)
 817		return 0;
 818
 819	/* if DC limit is zero, return AC limit */
 820	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 821					  clk_id << 16, clock);
 822	if (ret) {
 823		dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 824		return ret;
 825	}
 826
 827	return 0;
 828}
 829
 830int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 831{
 832	struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
 833			smu->smu_table.max_sustainable_clocks;
 834	int ret = 0;
 835
 836	max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 837	max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 838	max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 839	max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 840	max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 841	max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 842
 843	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 844		ret = smu_v11_0_get_max_sustainable_clock(smu,
 845							  &(max_sustainable_clocks->uclock),
 846							  SMU_UCLK);
 847		if (ret) {
 848			dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
 849			       __func__);
 850			return ret;
 851		}
 852	}
 853
 854	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 855		ret = smu_v11_0_get_max_sustainable_clock(smu,
 856							  &(max_sustainable_clocks->soc_clock),
 857							  SMU_SOCCLK);
 858		if (ret) {
 859			dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
 860			       __func__);
 861			return ret;
 862		}
 863	}
 864
 865	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 866		ret = smu_v11_0_get_max_sustainable_clock(smu,
 867							  &(max_sustainable_clocks->dcef_clock),
 868							  SMU_DCEFCLK);
 869		if (ret) {
 870			dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
 871			       __func__);
 872			return ret;
 873		}
 874
 875		ret = smu_v11_0_get_max_sustainable_clock(smu,
 876							  &(max_sustainable_clocks->display_clock),
 877							  SMU_DISPCLK);
 878		if (ret) {
 879			dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
 880			       __func__);
 881			return ret;
 882		}
 883		ret = smu_v11_0_get_max_sustainable_clock(smu,
 884							  &(max_sustainable_clocks->phy_clock),
 885							  SMU_PHYCLK);
 886		if (ret) {
 887			dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
 888			       __func__);
 889			return ret;
 890		}
 891		ret = smu_v11_0_get_max_sustainable_clock(smu,
 892							  &(max_sustainable_clocks->pixel_clock),
 893							  SMU_PIXCLK);
 894		if (ret) {
 895			dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
 896			       __func__);
 897			return ret;
 898		}
 899	}
 900
 901	if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
 902		max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
 903
 904	return 0;
 905}
 906
 907int smu_v11_0_get_current_power_limit(struct smu_context *smu,
 908				      uint32_t *power_limit)
 909{
 910	int power_src;
 911	int ret = 0;
 912
 913	if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
 914		return -EINVAL;
 915
 916	power_src = smu_cmn_to_asic_specific_index(smu,
 917					CMN2ASIC_MAPPING_PWR,
 918					smu->adev->pm.ac_power ?
 919					SMU_POWER_SOURCE_AC :
 920					SMU_POWER_SOURCE_DC);
 921	if (power_src < 0)
 922		return -EINVAL;
 923
 924	/*
 925	 * BIT 24-31: ControllerId (only PPT0 is supported for now)
 926	 * BIT 16-23: PowerSource
 927	 */
 928	ret = smu_cmn_send_smc_msg_with_param(smu,
 929					  SMU_MSG_GetPptLimit,
 930					  (0 << 24) | (power_src << 16),
 931					  power_limit);
 932	if (ret)
 933		dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
 934
 935	return ret;
 936}
 937
 938int smu_v11_0_set_power_limit(struct smu_context *smu,
 939			      enum smu_ppt_limit_type limit_type,
 940			      uint32_t limit)
 941{
 942	int power_src;
 943	int ret = 0;
 944	uint32_t limit_param;
 945
 946	if (limit_type != SMU_DEFAULT_PPT_LIMIT)
 947		return -EINVAL;
 948
 949	if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
 950		dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
 951		return -EOPNOTSUPP;
 952	}
 953
 954	power_src = smu_cmn_to_asic_specific_index(smu,
 955					CMN2ASIC_MAPPING_PWR,
 956					smu->adev->pm.ac_power ?
 957					SMU_POWER_SOURCE_AC :
 958					SMU_POWER_SOURCE_DC);
 959	if (power_src < 0)
 960		return -EINVAL;
 961
 962	/*
 963	 * BIT 24-31: ControllerId (only PPT0 is supported for now)
 964	 * BIT 16-23: PowerSource
 965	 * BIT 0-15: PowerLimit
 966	 */
 967	limit_param  = (limit & 0xFFFF);
 968	limit_param |= 0 << 24;
 969	limit_param |= (power_src) << 16;
 970	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit_param, NULL);
 971	if (ret) {
 972		dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
 973		return ret;
 974	}
 975
 976	smu->current_power_limit = limit;
 977
 978	return 0;
 979}
 980
 981static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
 982{
 983	return smu_cmn_send_smc_msg(smu,
 984				SMU_MSG_ReenableAcDcInterrupt,
 985				NULL);
 986}
 987
 988static int smu_v11_0_process_pending_interrupt(struct smu_context *smu)
 989{
 990	int ret = 0;
 991
 992	if (smu->dc_controlled_by_gpio &&
 993	    smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
 994		ret = smu_v11_0_ack_ac_dc_interrupt(smu);
 995
 996	return ret;
 997}
 998
 999void smu_v11_0_interrupt_work(struct smu_context *smu)
1000{
1001	if (smu_v11_0_ack_ac_dc_interrupt(smu))
1002		dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n");
1003}
1004
1005int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1006{
1007	int ret = 0;
1008
1009	if (smu->smu_table.thermal_controller_type) {
1010		ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1011		if (ret)
1012			return ret;
1013	}
1014
1015	/*
1016	 * After init there might have been missed interrupts triggered
1017	 * before driver registers for interrupt (Ex. AC/DC).
1018	 */
1019	return smu_v11_0_process_pending_interrupt(smu);
1020}
1021
1022int smu_v11_0_disable_thermal_alert(struct smu_context *smu)
1023{
1024	int ret = 0;
1025
1026	if (smu->smu_table.thermal_controller_type)
1027		ret = amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1028
1029	return ret;
1030}
1031
1032static uint16_t convert_to_vddc(uint8_t vid)
1033{
1034	return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1035}
1036
1037int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1038{
1039	struct amdgpu_device *adev = smu->adev;
1040	uint32_t vdd = 0, val_vid = 0;
1041
1042	if (!value)
1043		return -EINVAL;
1044	val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1045		SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1046		SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1047
1048	vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1049
1050	*value = vdd;
1051
1052	return 0;
1053
1054}
1055
1056int
1057smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1058					struct pp_display_clock_request
1059					*clock_req)
1060{
1061	enum amd_pp_clock_type clk_type = clock_req->clock_type;
1062	int ret = 0;
1063	enum smu_clk_type clk_select = 0;
1064	uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1065
1066	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1067		smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1068		switch (clk_type) {
1069		case amd_pp_dcef_clock:
1070			clk_select = SMU_DCEFCLK;
1071			break;
1072		case amd_pp_disp_clock:
1073			clk_select = SMU_DISPCLK;
1074			break;
1075		case amd_pp_pixel_clock:
1076			clk_select = SMU_PIXCLK;
1077			break;
1078		case amd_pp_phy_clock:
1079			clk_select = SMU_PHYCLK;
1080			break;
1081		case amd_pp_mem_clock:
1082			clk_select = SMU_UCLK;
1083			break;
1084		default:
1085			dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1086			ret = -EINVAL;
1087			break;
1088		}
1089
1090		if (ret)
1091			goto failed;
1092
1093		if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1094			return 0;
1095
1096		ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1097
1098		if(clk_select == SMU_UCLK)
1099			smu->hard_min_uclk_req_from_dal = clk_freq;
1100	}
1101
1102failed:
1103	return ret;
1104}
1105
1106int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1107{
1108	int ret = 0;
1109	struct amdgpu_device *adev = smu->adev;
1110
1111	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1112	case IP_VERSION(11, 0, 0):
1113	case IP_VERSION(11, 0, 5):
1114	case IP_VERSION(11, 0, 9):
1115	case IP_VERSION(11, 0, 7):
1116	case IP_VERSION(11, 0, 11):
1117	case IP_VERSION(11, 0, 12):
1118	case IP_VERSION(11, 0, 13):
1119	case IP_VERSION(11, 5, 0):
1120	case IP_VERSION(11, 5, 2):
1121		if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1122			return 0;
1123		if (enable)
1124			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
1125		else
1126			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
1127		break;
1128	default:
1129		break;
1130	}
1131
1132	return ret;
1133}
1134
1135uint32_t
1136smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1137{
1138	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1139		return AMD_FAN_CTRL_AUTO;
1140	else
1141		return smu->user_dpm_profile.fan_mode;
1142}
1143
1144static int
1145smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1146{
1147	int ret = 0;
1148
1149	if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1150		return 0;
1151
1152	ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1153	if (ret)
1154		dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1155		       __func__, (auto_fan_control ? "Start" : "Stop"));
1156
1157	return ret;
1158}
1159
1160static int
1161smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1162{
1163	struct amdgpu_device *adev = smu->adev;
1164
1165	WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1166		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1167				   CG_FDO_CTRL2, TMIN, 0));
1168	WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1169		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1170				   CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1171
1172	return 0;
1173}
1174
1175int
1176smu_v11_0_set_fan_speed_pwm(struct smu_context *smu, uint32_t speed)
1177{
1178	struct amdgpu_device *adev = smu->adev;
1179	uint32_t duty100, duty;
1180	uint64_t tmp64;
1181
1182	speed = min_t(uint32_t, speed, 255);
1183
1184	duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1185				CG_FDO_CTRL1, FMAX_DUTY100);
1186	if (!duty100)
1187		return -EINVAL;
1188
1189	tmp64 = (uint64_t)speed * duty100;
1190	do_div(tmp64, 255);
1191	duty = (uint32_t)tmp64;
1192
1193	WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1194		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1195				   CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1196
1197	return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1198}
1199
1200int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1201				uint32_t speed)
1202{
1203	struct amdgpu_device *adev = smu->adev;
1204	/*
1205	 * crystal_clock_freq used for fan speed rpm calculation is
1206	 * always 25Mhz. So, hardcode it as 2500(in 10K unit).
1207	 */
1208	uint32_t crystal_clock_freq = 2500;
1209	uint32_t tach_period;
1210
1211	if (!speed || speed > UINT_MAX/8)
1212		return -EINVAL;
1213	/*
1214	 * To prevent from possible overheat, some ASICs may have requirement
1215	 * for minimum fan speed:
1216	 * - For some NV10 SKU, the fan speed cannot be set lower than
1217	 *   700 RPM.
1218	 * - For some Sienna Cichlid SKU, the fan speed cannot be set
1219	 *   lower than 500 RPM.
1220	 */
1221	tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1222	WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1223		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1224				   CG_TACH_CTRL, TARGET_PERIOD,
1225				   tach_period));
1226
1227	return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1228}
1229
1230int smu_v11_0_get_fan_speed_pwm(struct smu_context *smu,
1231				uint32_t *speed)
1232{
1233	struct amdgpu_device *adev = smu->adev;
1234	uint32_t duty100, duty;
1235	uint64_t tmp64;
1236
1237	/*
1238	 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1239	 * detected via register retrieving. To workaround this, we will
1240	 * report the fan speed as 0 PWM if user just requested such.
1241	 */
1242	if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM)
1243	     && !smu->user_dpm_profile.fan_speed_pwm) {
1244		*speed = 0;
1245		return 0;
1246	}
1247
1248	duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1249				CG_FDO_CTRL1, FMAX_DUTY100);
1250	duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
1251				CG_THERMAL_STATUS, FDO_PWM_DUTY);
1252	if (!duty100)
1253		return -EINVAL;
1254
1255	tmp64 = (uint64_t)duty * 255;
1256	do_div(tmp64, duty100);
1257	*speed = min_t(uint32_t, tmp64, 255);
1258
1259	return 0;
1260}
1261
1262int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
1263				uint32_t *speed)
1264{
1265	struct amdgpu_device *adev = smu->adev;
1266	uint32_t crystal_clock_freq = 2500;
1267	uint32_t tach_status;
1268	uint64_t tmp64;
1269
1270	/*
1271	 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1272	 * detected via register retrieving. To workaround this, we will
1273	 * report the fan speed as 0 RPM if user just requested such.
1274	 */
1275	if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM)
1276	     && !smu->user_dpm_profile.fan_speed_rpm) {
1277		*speed = 0;
1278		return 0;
1279	}
1280
1281	tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1282
1283	tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS);
1284	if (tach_status) {
1285		do_div(tmp64, tach_status);
1286		*speed = (uint32_t)tmp64;
1287	} else {
1288		dev_warn_once(adev->dev, "Got zero output on CG_TACH_STATUS reading!\n");
1289		*speed = 0;
1290	}
1291
1292	return 0;
1293}
1294
1295int
1296smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1297			       uint32_t mode)
1298{
1299	int ret = 0;
1300
1301	switch (mode) {
1302	case AMD_FAN_CTRL_NONE:
1303		ret = smu_v11_0_auto_fan_control(smu, 0);
1304		if (!ret)
1305			ret = smu_v11_0_set_fan_speed_pwm(smu, 255);
1306		break;
1307	case AMD_FAN_CTRL_MANUAL:
1308		ret = smu_v11_0_auto_fan_control(smu, 0);
1309		break;
1310	case AMD_FAN_CTRL_AUTO:
1311		ret = smu_v11_0_auto_fan_control(smu, 1);
1312		break;
1313	default:
1314		break;
1315	}
1316
1317	if (ret) {
1318		dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1319		return -EINVAL;
1320	}
1321
1322	return ret;
1323}
1324
1325int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1326				     uint32_t pstate)
1327{
1328	return smu_cmn_send_smc_msg_with_param(smu,
1329					       SMU_MSG_SetXgmiMode,
1330					       pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1331					  NULL);
1332}
1333
1334static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
1335				   struct amdgpu_irq_src *source,
1336				   unsigned tyep,
1337				   enum amdgpu_interrupt_state state)
1338{
1339	struct smu_context *smu = adev->powerplay.pp_handle;
1340	uint32_t low, high;
1341	uint32_t val = 0;
1342
1343	switch (state) {
1344	case AMDGPU_IRQ_STATE_DISABLE:
1345		/* For THM irqs */
1346		val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1347		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1348		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1349		WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1350
1351		WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1352
1353		/* For MP1 SW irqs */
1354		val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1355		val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1356		WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1357
1358		break;
1359	case AMDGPU_IRQ_STATE_ENABLE:
1360		/* For THM irqs */
1361		low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1362				smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1363		high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1364				smu->thermal_range.software_shutdown_temp);
1365
1366		val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1367		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1368		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1369		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1370		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1371		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1372		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1373		val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1374		WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1375
1376		val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1377		val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1378		val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1379		WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1380
1381		/* For MP1 SW irqs */
1382		val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);
1383		val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1384		val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1385		WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val);
1386
1387		val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1388		val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1389		WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1390
1391		break;
1392	default:
1393		break;
1394	}
1395
1396	return 0;
1397}
1398
1399#define THM_11_0__SRCID__THM_DIG_THERM_L2H		0		/* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1400#define THM_11_0__SRCID__THM_DIG_THERM_H2L		1		/* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1401
1402#define SMUIO_11_0__SRCID__SMUIO_GPIO19			83
1403
1404static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1405				 struct amdgpu_irq_src *source,
1406				 struct amdgpu_iv_entry *entry)
1407{
1408	struct smu_context *smu = adev->powerplay.pp_handle;
1409	uint32_t client_id = entry->client_id;
1410	uint32_t src_id = entry->src_id;
1411	/*
1412	 * ctxid is used to distinguish different
1413	 * events for SMCToHost interrupt.
1414	 */
1415	uint32_t ctxid = entry->src_data[0];
1416	uint32_t data;
1417
1418	if (client_id == SOC15_IH_CLIENTID_THM) {
1419		switch (src_id) {
1420		case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1421			schedule_delayed_work(&smu->swctf_delayed_work,
1422					      msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY));
1423		break;
1424		case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1425			dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1426		break;
1427		default:
1428			dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1429				src_id);
1430		break;
1431		}
1432	} else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1433		dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1434		/*
1435		 * HW CTF just occurred. Shutdown to prevent further damage.
1436		 */
1437		dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1438		orderly_poweroff(true);
1439	} else if (client_id == SOC15_IH_CLIENTID_MP1) {
1440		if (src_id == SMU_IH_INTERRUPT_ID_TO_DRIVER) {
1441			/* ACK SMUToHost interrupt */
1442			data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1443			data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1444			WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data);
1445
1446			switch (ctxid) {
1447			case SMU_IH_INTERRUPT_CONTEXT_ID_AC:
1448				dev_dbg(adev->dev, "Switched to AC mode!\n");
1449				schedule_work(&smu->interrupt_work);
1450				adev->pm.ac_power = true;
1451				break;
1452			case SMU_IH_INTERRUPT_CONTEXT_ID_DC:
1453				dev_dbg(adev->dev, "Switched to DC mode!\n");
1454				schedule_work(&smu->interrupt_work);
1455				adev->pm.ac_power = false;
1456				break;
1457			case SMU_IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING:
1458				/*
1459				 * Increment the throttle interrupt counter
1460				 */
1461				atomic64_inc(&smu->throttle_int_counter);
1462
1463				if (!atomic_read(&adev->throttling_logging_enabled))
1464					return 0;
1465
1466				if (__ratelimit(&adev->throttling_logging_rs))
1467					schedule_work(&smu->throttling_logging_work);
1468
1469				break;
1470			default:
1471				dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n",
1472									ctxid, client_id);
1473				break;
1474			}
1475		}
1476	}
1477
1478	return 0;
1479}
1480
1481static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1482{
1483	.set = smu_v11_0_set_irq_state,
1484	.process = smu_v11_0_irq_process,
1485};
1486
1487int smu_v11_0_register_irq_handler(struct smu_context *smu)
1488{
1489	struct amdgpu_device *adev = smu->adev;
1490	struct amdgpu_irq_src *irq_src = &smu->irq_source;
1491	int ret = 0;
1492
1493	irq_src->num_types = 1;
1494	irq_src->funcs = &smu_v11_0_irq_funcs;
1495
1496	ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1497				THM_11_0__SRCID__THM_DIG_THERM_L2H,
1498				irq_src);
1499	if (ret)
1500		return ret;
1501
1502	ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1503				THM_11_0__SRCID__THM_DIG_THERM_H2L,
1504				irq_src);
1505	if (ret)
1506		return ret;
1507
1508	/* Register CTF(GPIO_19) interrupt */
1509	ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1510				SMUIO_11_0__SRCID__SMUIO_GPIO19,
1511				irq_src);
1512	if (ret)
1513		return ret;
1514
1515	ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1516				SMU_IH_INTERRUPT_ID_TO_DRIVER,
1517				irq_src);
1518	if (ret)
1519		return ret;
1520
1521	return ret;
1522}
1523
1524int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1525		struct pp_smu_nv_clock_table *max_clocks)
1526{
1527	struct smu_table_context *table_context = &smu->smu_table;
1528	struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1529
1530	if (!max_clocks || !table_context->max_sustainable_clocks)
1531		return -EINVAL;
1532
1533	sustainable_clocks = table_context->max_sustainable_clocks;
1534
1535	max_clocks->dcfClockInKhz =
1536			(unsigned int) sustainable_clocks->dcef_clock * 1000;
1537	max_clocks->displayClockInKhz =
1538			(unsigned int) sustainable_clocks->display_clock * 1000;
1539	max_clocks->phyClockInKhz =
1540			(unsigned int) sustainable_clocks->phy_clock * 1000;
1541	max_clocks->pixelClockInKhz =
1542			(unsigned int) sustainable_clocks->pixel_clock * 1000;
1543	max_clocks->uClockInKhz =
1544			(unsigned int) sustainable_clocks->uclock * 1000;
1545	max_clocks->socClockInKhz =
1546			(unsigned int) sustainable_clocks->soc_clock * 1000;
1547	max_clocks->dscClockInKhz = 0;
1548	max_clocks->dppClockInKhz = 0;
1549	max_clocks->fabricClockInKhz = 0;
1550
1551	return 0;
1552}
1553
1554int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1555{
1556	return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1557}
1558
1559int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu,
1560				      enum smu_baco_seq baco_seq)
1561{
1562	return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
1563}
1564
1565int smu_v11_0_get_bamaco_support(struct smu_context *smu)
1566{
1567	struct smu_baco_context *smu_baco = &smu->smu_baco;
1568	int bamaco_support = 0;
1569
1570	if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support)
1571		return 0;
1572
1573	if (smu_baco->maco_support)
1574		bamaco_support |= MACO_SUPPORT;
1575
1576	/* return true if ASIC is in BACO state already */
1577	if (smu_v11_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
1578		return bamaco_support |= BACO_SUPPORT;
1579
1580	/* Arcturus does not support this bit mask */
1581	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1582	   !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1583		return 0;
1584
1585	return (bamaco_support |= BACO_SUPPORT);
1586}
1587
1588enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1589{
1590	struct smu_baco_context *smu_baco = &smu->smu_baco;
1591
1592	return smu_baco->state;
1593}
1594
1595#define D3HOT_BACO_SEQUENCE 0
1596#define D3HOT_BAMACO_SEQUENCE 2
1597
1598int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1599{
1600	struct smu_baco_context *smu_baco = &smu->smu_baco;
1601	struct amdgpu_device *adev = smu->adev;
1602	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1603	uint32_t data;
1604	int ret = 0;
1605
1606	if (smu_v11_0_baco_get_state(smu) == state)
1607		return 0;
1608
1609	if (state == SMU_BACO_STATE_ENTER) {
1610		switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1611		case IP_VERSION(11, 0, 7):
1612		case IP_VERSION(11, 0, 11):
1613		case IP_VERSION(11, 0, 12):
1614		case IP_VERSION(11, 0, 13):
1615			if (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)
1616				ret = smu_cmn_send_smc_msg_with_param(smu,
1617								      SMU_MSG_EnterBaco,
1618								      D3HOT_BAMACO_SEQUENCE,
1619								      NULL);
1620			else
1621				ret = smu_cmn_send_smc_msg_with_param(smu,
1622								      SMU_MSG_EnterBaco,
1623								      D3HOT_BACO_SEQUENCE,
1624								      NULL);
1625			break;
1626		default:
1627			if (!ras || !adev->ras_enabled ||
1628			    (adev->init_lvl->level ==
1629			     AMDGPU_INIT_LEVEL_MINIMAL_XGMI)) {
1630				if (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
1631				    IP_VERSION(11, 0, 2)) {
1632					data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
1633					data |= 0x80000000;
1634					WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data);
1635				} else {
1636					data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1637					data |= 0x80000000;
1638					WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1639				}
1640
1641				ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
1642			} else {
1643				ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);
1644			}
1645			break;
1646		}
1647
1648	} else {
1649		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
1650		if (ret)
1651			return ret;
1652
1653		/* clear vbios scratch 6 and 7 for coming asic reinit */
1654		WREG32(adev->bios_scratch_reg_offset + 6, 0);
1655		WREG32(adev->bios_scratch_reg_offset + 7, 0);
1656	}
1657
1658	if (!ret)
1659		smu_baco->state = state;
1660
1661	return ret;
1662}
1663
1664int smu_v11_0_baco_enter(struct smu_context *smu)
1665{
1666	int ret = 0;
1667
1668	ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1669	if (ret)
1670		return ret;
1671
1672	msleep(10);
1673
1674	return ret;
1675}
1676
1677int smu_v11_0_baco_exit(struct smu_context *smu)
1678{
1679	int ret;
1680
1681	ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1682	if (!ret) {
1683		/*
1684		 * Poll BACO exit status to ensure FW has completed
1685		 * BACO exit process to avoid timing issues.
1686		 */
1687		smu_v11_0_poll_baco_exit(smu);
1688	}
1689
1690	return ret;
1691}
1692
1693int smu_v11_0_mode1_reset(struct smu_context *smu)
1694{
1695	int ret = 0;
1696
1697	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1698	if (!ret)
1699		msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS);
1700
1701	return ret;
1702}
1703
1704int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable)
1705{
1706	int ret = 0;
1707
1708	ret =  smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LightSBR, enable ? 1 : 0, NULL);
1709
1710	return ret;
1711}
1712
1713
1714int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1715						 uint32_t *min, uint32_t *max)
1716{
1717	int ret = 0, clk_id = 0;
1718	uint32_t param = 0;
1719	uint32_t clock_limit;
1720
1721	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1722		switch (clk_type) {
1723		case SMU_MCLK:
1724		case SMU_UCLK:
1725			clock_limit = smu->smu_table.boot_values.uclk;
1726			break;
1727		case SMU_GFXCLK:
1728		case SMU_SCLK:
1729			clock_limit = smu->smu_table.boot_values.gfxclk;
1730			break;
1731		case SMU_SOCCLK:
1732			clock_limit = smu->smu_table.boot_values.socclk;
1733			break;
1734		default:
1735			clock_limit = 0;
1736			break;
1737		}
1738
1739		/* clock in Mhz unit */
1740		if (min)
1741			*min = clock_limit / 100;
1742		if (max)
1743			*max = clock_limit / 100;
1744
1745		return 0;
1746	}
1747
1748	clk_id = smu_cmn_to_asic_specific_index(smu,
1749						CMN2ASIC_MAPPING_CLK,
1750						clk_type);
1751	if (clk_id < 0) {
1752		ret = -EINVAL;
1753		goto failed;
1754	}
1755	param = (clk_id & 0xffff) << 16;
1756
1757	if (max) {
1758		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1759		if (ret)
1760			goto failed;
1761	}
1762
1763	if (min) {
1764		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1765		if (ret)
1766			goto failed;
1767	}
1768
1769failed:
1770	return ret;
1771}
1772
1773int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
1774					  enum smu_clk_type clk_type,
1775					  uint32_t min,
1776					  uint32_t max,
1777					  bool automatic)
1778{
1779	int ret = 0, clk_id = 0;
1780	uint32_t param;
1781
1782	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1783		return 0;
1784
1785	clk_id = smu_cmn_to_asic_specific_index(smu,
1786						CMN2ASIC_MAPPING_CLK,
1787						clk_type);
1788	if (clk_id < 0)
1789		return clk_id;
1790
1791	if (max > 0) {
1792		if (automatic)
1793			param = (uint32_t)((clk_id << 16) | 0xffff);
1794		else
1795			param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1796		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1797						  param, NULL);
1798		if (ret)
1799			goto out;
1800	}
1801
1802	if (min > 0) {
1803		if (automatic)
1804			param = (uint32_t)((clk_id << 16) | 0);
1805		else
1806			param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1807		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1808						  param, NULL);
1809		if (ret)
1810			goto out;
1811	}
1812
1813out:
1814	return ret;
1815}
1816
1817int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
1818					  enum smu_clk_type clk_type,
1819					  uint32_t min,
1820					  uint32_t max)
1821{
1822	int ret = 0, clk_id = 0;
1823	uint32_t param;
1824
1825	if (min <= 0 && max <= 0)
1826		return -EINVAL;
1827
1828	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1829		return 0;
1830
1831	clk_id = smu_cmn_to_asic_specific_index(smu,
1832						CMN2ASIC_MAPPING_CLK,
1833						clk_type);
1834	if (clk_id < 0)
1835		return clk_id;
1836
1837	if (max > 0) {
1838		param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1839		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1840						  param, NULL);
1841		if (ret)
1842			return ret;
1843	}
1844
1845	if (min > 0) {
1846		param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1847		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1848						  param, NULL);
1849		if (ret)
1850			return ret;
1851	}
1852
1853	return ret;
1854}
1855
1856int smu_v11_0_set_performance_level(struct smu_context *smu,
1857				    enum amd_dpm_forced_level level)
1858{
1859	struct smu_11_0_dpm_context *dpm_context =
1860				smu->smu_dpm.dpm_context;
1861	struct smu_11_0_dpm_table *gfx_table =
1862				&dpm_context->dpm_tables.gfx_table;
1863	struct smu_11_0_dpm_table *mem_table =
1864				&dpm_context->dpm_tables.uclk_table;
1865	struct smu_11_0_dpm_table *soc_table =
1866				&dpm_context->dpm_tables.soc_table;
1867	struct smu_umd_pstate_table *pstate_table =
1868				&smu->pstate_table;
1869	struct amdgpu_device *adev = smu->adev;
1870	uint32_t sclk_min = 0, sclk_max = 0;
1871	uint32_t mclk_min = 0, mclk_max = 0;
1872	uint32_t socclk_min = 0, socclk_max = 0;
1873	int ret = 0;
1874	bool auto_level = false;
1875
1876	switch (level) {
1877	case AMD_DPM_FORCED_LEVEL_HIGH:
1878		sclk_min = sclk_max = gfx_table->max;
1879		mclk_min = mclk_max = mem_table->max;
1880		socclk_min = socclk_max = soc_table->max;
1881		break;
1882	case AMD_DPM_FORCED_LEVEL_LOW:
1883		sclk_min = sclk_max = gfx_table->min;
1884		mclk_min = mclk_max = mem_table->min;
1885		socclk_min = socclk_max = soc_table->min;
1886		break;
1887	case AMD_DPM_FORCED_LEVEL_AUTO:
1888		sclk_min = gfx_table->min;
1889		sclk_max = gfx_table->max;
1890		mclk_min = mem_table->min;
1891		mclk_max = mem_table->max;
1892		socclk_min = soc_table->min;
1893		socclk_max = soc_table->max;
1894		auto_level = true;
1895		break;
1896	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1897		sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1898		mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1899		socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1900		break;
1901	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1902		sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1903		break;
1904	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1905		mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1906		break;
1907	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1908		sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1909		mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1910		socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1911		break;
1912	case AMD_DPM_FORCED_LEVEL_MANUAL:
1913	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1914		return 0;
1915	default:
1916		dev_err(adev->dev, "Invalid performance level %d\n", level);
1917		return -EINVAL;
1918	}
1919
1920	/*
1921	 * Separate MCLK and SOCCLK soft min/max settings are not allowed
1922	 * on Arcturus.
1923	 */
1924	if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) {
1925		mclk_min = mclk_max = 0;
1926		socclk_min = socclk_max = 0;
1927		auto_level = false;
1928	}
1929
1930	if (sclk_min && sclk_max) {
1931		ret = smu_v11_0_set_soft_freq_limited_range(smu,
1932							    SMU_GFXCLK,
1933							    sclk_min,
1934							    sclk_max,
1935							    auto_level);
1936		if (ret)
1937			return ret;
1938	}
1939
1940	if (mclk_min && mclk_max) {
1941		ret = smu_v11_0_set_soft_freq_limited_range(smu,
1942							    SMU_MCLK,
1943							    mclk_min,
1944							    mclk_max,
1945							    auto_level);
1946		if (ret)
1947			return ret;
1948	}
1949
1950	if (socclk_min && socclk_max) {
1951		ret = smu_v11_0_set_soft_freq_limited_range(smu,
1952							    SMU_SOCCLK,
1953							    socclk_min,
1954							    socclk_max,
1955							    auto_level);
1956		if (ret)
1957			return ret;
1958	}
1959
1960	return ret;
1961}
1962
1963int smu_v11_0_set_power_source(struct smu_context *smu,
1964			       enum smu_power_src_type power_src)
1965{
1966	int pwr_source;
1967
1968	pwr_source = smu_cmn_to_asic_specific_index(smu,
1969						    CMN2ASIC_MAPPING_PWR,
1970						    (uint32_t)power_src);
1971	if (pwr_source < 0)
1972		return -EINVAL;
1973
1974	return smu_cmn_send_smc_msg_with_param(smu,
1975					SMU_MSG_NotifyPowerSource,
1976					pwr_source,
1977					NULL);
1978}
1979
1980int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
1981				    enum smu_clk_type clk_type,
1982				    uint16_t level,
1983				    uint32_t *value)
1984{
1985	int ret = 0, clk_id = 0;
1986	uint32_t param;
1987
1988	if (!value)
1989		return -EINVAL;
1990
1991	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1992		return 0;
1993
1994	clk_id = smu_cmn_to_asic_specific_index(smu,
1995						CMN2ASIC_MAPPING_CLK,
1996						clk_type);
1997	if (clk_id < 0)
1998		return clk_id;
1999
2000	param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
2001
2002	ret = smu_cmn_send_smc_msg_with_param(smu,
2003					  SMU_MSG_GetDpmFreqByIndex,
2004					  param,
2005					  value);
2006	if (ret)
2007		return ret;
2008
2009	/*
2010	 * BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
2011	 * now, we un-support it
2012	 */
2013	*value = *value & 0x7fffffff;
2014
2015	return ret;
2016}
2017
2018int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
2019				  enum smu_clk_type clk_type,
2020				  uint32_t *value)
2021{
2022	return smu_v11_0_get_dpm_freq_by_index(smu,
2023					       clk_type,
2024					       0xff,
2025					       value);
2026}
2027
2028int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
2029				   enum smu_clk_type clk_type,
2030				   struct smu_11_0_dpm_table *single_dpm_table)
2031{
2032	int ret = 0;
2033	uint32_t clk;
2034	int i;
2035
2036	ret = smu_v11_0_get_dpm_level_count(smu,
2037					    clk_type,
2038					    &single_dpm_table->count);
2039	if (ret) {
2040		dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
2041		return ret;
2042	}
2043
2044	for (i = 0; i < single_dpm_table->count; i++) {
2045		ret = smu_v11_0_get_dpm_freq_by_index(smu,
2046						      clk_type,
2047						      i,
2048						      &clk);
2049		if (ret) {
2050			dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2051			return ret;
2052		}
2053
2054		single_dpm_table->dpm_levels[i].value = clk;
2055		single_dpm_table->dpm_levels[i].enabled = true;
2056
2057		if (i == 0)
2058			single_dpm_table->min = clk;
2059		else if (i == single_dpm_table->count - 1)
2060			single_dpm_table->max = clk;
2061	}
2062
2063	return 0;
2064}
2065
2066int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu)
2067{
2068	struct amdgpu_device *adev = smu->adev;
2069
2070	return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2071		PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2072		>> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2073}
2074
2075uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu)
2076{
2077	uint32_t width_level;
2078
2079	width_level = smu_v11_0_get_current_pcie_link_width_level(smu);
2080	if (width_level > LINK_WIDTH_MAX)
2081		width_level = 0;
2082
2083	return link_width[width_level];
2084}
2085
2086int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2087{
2088	struct amdgpu_device *adev = smu->adev;
2089
2090	return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2091		PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2092		>> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2093}
2094
2095uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
2096{
2097	uint32_t speed_level;
2098
2099	speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu);
2100	if (speed_level > LINK_SPEED_MAX)
2101		speed_level = 0;
2102
2103	return link_speed[speed_level];
2104}
2105
2106int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
2107			      bool enablement)
2108{
2109	int ret = 0;
2110
2111	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2112		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2113
2114	return ret;
2115}
2116
2117int smu_v11_0_deep_sleep_control(struct smu_context *smu,
2118				 bool enablement)
2119{
2120	struct amdgpu_device *adev = smu->adev;
2121	int ret = 0;
2122
2123	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2124		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2125		if (ret) {
2126			dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2127			return ret;
2128		}
2129	}
2130
2131	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2132		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2133		if (ret) {
2134			dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2135			return ret;
2136		}
2137	}
2138
2139	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2140		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2141		if (ret) {
2142			dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2143			return ret;
2144		}
2145	}
2146
2147	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2148		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2149		if (ret) {
2150			dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2151			return ret;
2152		}
2153	}
2154
2155	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2156		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2157		if (ret) {
2158			dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2159			return ret;
2160		}
2161	}
2162
2163	return ret;
2164}
2165
2166int smu_v11_0_restore_user_od_settings(struct smu_context *smu)
2167{
2168	struct smu_table_context *table_context = &smu->smu_table;
2169	void *user_od_table = table_context->user_overdrive_table;
2170	int ret = 0;
2171
2172	ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)user_od_table, true);
2173	if (ret)
2174		dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2175
2176	return ret;
2177}
2178
2179void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu)
2180{
2181	struct amdgpu_device *adev = smu->adev;
2182
2183	smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2184	smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2185	smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2186}