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sienna_cichlid_ppt.c
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linux-6.19.14/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1/* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#define SWSMU_CODE_LAYER_L2 25 26#include <linux/firmware.h> 27#include <linux/pci.h> 28#include <linux/i2c.h> 29#include "amdgpu.h" 30#include "amdgpu_dpm.h" 31#include "amdgpu_smu.h" 32#include "atomfirmware.h" 33#include "amdgpu_atomfirmware.h" 34#include "amdgpu_atombios.h" 35#include "smu_v11_0.h" 36#include "smu11_driver_if_sienna_cichlid.h" 37#include "soc15_common.h" 38#include "atom.h" 39#include "sienna_cichlid_ppt.h" 40#include "smu_v11_0_7_pptable.h" 41#include "smu_v11_0_7_ppsmc.h" 42#include "nbio/nbio_2_3_offset.h" 43#include "nbio/nbio_2_3_sh_mask.h" 44#include "thm/thm_11_0_2_offset.h" 45#include "thm/thm_11_0_2_sh_mask.h" 46#include "mp/mp_11_0_offset.h" 47#include "mp/mp_11_0_sh_mask.h" 48 49#include "asic_reg/mp/mp_11_0_sh_mask.h" 50#include "amdgpu_ras.h" 51#include "smu_cmn.h" 52 53/* 54 * DO NOT use these for err/warn/info/debug messages. 55 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 56 * They are more MGPU friendly. 57 */ 58#undef pr_err 59#undef pr_warn 60#undef pr_info 61#undef pr_debug 62 63#define FEATURE_MASK(feature) (1ULL << feature) 64#define SMC_DPM_FEATURE ( \ 65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \ 72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) 73 74#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15 75 76#define GET_PPTABLE_MEMBER(field, member) \ 77 do { \ 78 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == \ 79 IP_VERSION(11, 0, 13)) \ 80 (*member) = (smu->smu_table.driver_pptable + \ 81 offsetof(PPTable_beige_goby_t, field)); \ 82 else \ 83 (*member) = (smu->smu_table.driver_pptable + \ 84 offsetof(PPTable_t, field)); \ 85 } while (0) 86 87/* STB FIFO depth is in 64bit units */ 88#define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8 89 90/* 91 * SMU support ECCTABLE since version 58.70.0, 92 * use this to check whether ECCTABLE feature is supported. 93 */ 94#define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600 95 96static int get_table_size(struct smu_context *smu) 97{ 98 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13)) 99 return sizeof(PPTable_beige_goby_t); 100 else 101 return sizeof(PPTable_t); 102} 103 104static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = { 105 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 106 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 107 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 108 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 109 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 110 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 111 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 112 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 113 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 114 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), 115 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), 116 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1), 117 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1), 118 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 119 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 120 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 121 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 122 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 123 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 124 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 125 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 126 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 127 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 128 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 129 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 130 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 131 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), 132 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 133 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 134 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 135 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 136 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0), 137 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0), 138 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0), 139 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 140 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 141 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 142 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0), 143 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0), 144 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 145 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 146 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 147 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 148 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 149 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 150 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 151 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 152 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 153 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 154 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0), 155 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 156 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0), 157 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 158 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0), 159 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0), 160 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0), 161 MSG_MAP(DriverMode2Reset, PPSMC_MSG_DriverMode2Reset, 0), 162}; 163 164static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = { 165 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 166 CLK_MAP(SCLK, PPCLK_GFXCLK), 167 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 168 CLK_MAP(FCLK, PPCLK_FCLK), 169 CLK_MAP(UCLK, PPCLK_UCLK), 170 CLK_MAP(MCLK, PPCLK_UCLK), 171 CLK_MAP(DCLK, PPCLK_DCLK_0), 172 CLK_MAP(DCLK1, PPCLK_DCLK_1), 173 CLK_MAP(VCLK, PPCLK_VCLK_0), 174 CLK_MAP(VCLK1, PPCLK_VCLK_1), 175 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK), 176 CLK_MAP(DISPCLK, PPCLK_DISPCLK), 177 CLK_MAP(PIXCLK, PPCLK_PIXCLK), 178 CLK_MAP(PHYCLK, PPCLK_PHYCLK), 179}; 180 181static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = { 182 FEA_MAP(DPM_PREFETCHER), 183 FEA_MAP(DPM_GFXCLK), 184 FEA_MAP(DPM_GFX_GPO), 185 FEA_MAP(DPM_UCLK), 186 FEA_MAP(DPM_FCLK), 187 FEA_MAP(DPM_SOCCLK), 188 FEA_MAP(DPM_MP0CLK), 189 FEA_MAP(DPM_LINK), 190 FEA_MAP(DPM_DCEFCLK), 191 FEA_MAP(DPM_XGMI), 192 FEA_MAP(MEM_VDDCI_SCALING), 193 FEA_MAP(MEM_MVDD_SCALING), 194 FEA_MAP(DS_GFXCLK), 195 FEA_MAP(DS_SOCCLK), 196 FEA_MAP(DS_FCLK), 197 FEA_MAP(DS_LCLK), 198 FEA_MAP(DS_DCEFCLK), 199 FEA_MAP(DS_UCLK), 200 FEA_MAP(GFX_ULV), 201 FEA_MAP(FW_DSTATE), 202 FEA_MAP(GFXOFF), 203 FEA_MAP(BACO), 204 FEA_MAP(MM_DPM_PG), 205 FEA_MAP(RSMU_SMN_CG), 206 FEA_MAP(PPT), 207 FEA_MAP(TDC), 208 FEA_MAP(APCC_PLUS), 209 FEA_MAP(GTHR), 210 FEA_MAP(ACDC), 211 FEA_MAP(VR0HOT), 212 FEA_MAP(VR1HOT), 213 FEA_MAP(FW_CTF), 214 FEA_MAP(FAN_CONTROL), 215 FEA_MAP(THERMAL), 216 FEA_MAP(GFX_DCS), 217 FEA_MAP(RM), 218 FEA_MAP(LED_DISPLAY), 219 FEA_MAP(GFX_SS), 220 FEA_MAP(OUT_OF_BAND_MONITOR), 221 FEA_MAP(TEMP_DEPENDENT_VMIN), 222 FEA_MAP(MMHUB_PG), 223 FEA_MAP(ATHUB_PG), 224 FEA_MAP(APCC_DFLL), 225}; 226 227static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = { 228 TAB_MAP(PPTABLE), 229 TAB_MAP(WATERMARKS), 230 TAB_MAP(AVFS_PSM_DEBUG), 231 TAB_MAP(AVFS_FUSE_OVERRIDE), 232 TAB_MAP(PMSTATUSLOG), 233 TAB_MAP(SMU_METRICS), 234 TAB_MAP(DRIVER_SMU_CONFIG), 235 TAB_MAP(ACTIVITY_MONITOR_COEFF), 236 TAB_MAP(OVERDRIVE), 237 TAB_MAP(I2C_COMMANDS), 238 TAB_MAP(PACE), 239 TAB_MAP(ECCINFO), 240}; 241 242static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 243 PWR_MAP(AC), 244 PWR_MAP(DC), 245}; 246 247static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 248 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 249 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 250 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 251 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 252 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 253 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 254 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 255}; 256 257static const uint8_t sienna_cichlid_throttler_map[] = { 258 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 259 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 260 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 261 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 262 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 263 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 264 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 265 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 266 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 267 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 268 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 269 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 270 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 271 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 272 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 273 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 274 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT), 275 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 276}; 277 278static int 279sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, 280 uint32_t *feature_mask, uint32_t num) 281{ 282 struct amdgpu_device *adev = smu->adev; 283 284 if (num > 2) 285 return -EINVAL; 286 287 memset(feature_mask, 0, sizeof(uint32_t) * num); 288 289 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) 290 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) 291 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) 292 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) 293 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) 294 | FEATURE_MASK(FEATURE_DS_FCLK_BIT) 295 | FEATURE_MASK(FEATURE_DS_UCLK_BIT) 296 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) 297 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT) 298 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) 299 | FEATURE_MASK(FEATURE_GFX_SS_BIT) 300 | FEATURE_MASK(FEATURE_VR0HOT_BIT) 301 | FEATURE_MASK(FEATURE_PPT_BIT) 302 | FEATURE_MASK(FEATURE_TDC_BIT) 303 | FEATURE_MASK(FEATURE_BACO_BIT) 304 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) 305 | FEATURE_MASK(FEATURE_FW_CTF_BIT) 306 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) 307 | FEATURE_MASK(FEATURE_THERMAL_BIT) 308 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); 309 310 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { 311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 312 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT); 313 } 314 315 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && 316 (amdgpu_ip_version(adev, MP1_HWIP, 0) > IP_VERSION(11, 0, 7)) && 317 !(adev->flags & AMD_IS_APU)) 318 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT); 319 320 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) 321 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) 322 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) 323 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); 324 325 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 327 328 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); 330 331 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) 332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 333 334 if (adev->pm.pp_feature & PP_ULV_MASK) 335 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 336 337 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 338 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 339 340 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 341 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 342 343 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) 344 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); 345 346 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) 347 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); 348 349 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN || 350 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) 351 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT); 352 353 if (smu->dc_controlled_by_gpio) 354 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); 355 356 if (amdgpu_device_should_use_aspm(adev)) 357 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); 358 359 return 0; 360} 361 362static void sienna_cichlid_check_bxco_support(struct smu_context *smu) 363{ 364 struct smu_table_context *table_context = &smu->smu_table; 365 struct smu_11_0_7_powerplay_table *powerplay_table = 366 table_context->power_play_table; 367 struct smu_baco_context *smu_baco = &smu->smu_baco; 368 struct amdgpu_device *adev = smu->adev; 369 uint32_t val; 370 371 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) { 372 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); 373 smu_baco->platform_support = 374 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : 375 false; 376 377 /* 378 * Disable BACO entry/exit completely on below SKUs to 379 * avoid hardware intermittent failures. 380 */ 381 if (((adev->pdev->device == 0x73A1) && 382 (adev->pdev->revision == 0x00)) || 383 ((adev->pdev->device == 0x73BF) && 384 (adev->pdev->revision == 0xCF)) || 385 ((adev->pdev->device == 0x7422) && 386 (adev->pdev->revision == 0x00)) || 387 ((adev->pdev->device == 0x73A3) && 388 (adev->pdev->revision == 0x00)) || 389 ((adev->pdev->device == 0x73E3) && 390 (adev->pdev->revision == 0x00))) 391 smu_baco->platform_support = false; 392 393 } 394} 395 396static void sienna_cichlid_check_fan_support(struct smu_context *smu) 397{ 398 struct smu_table_context *table_context = &smu->smu_table; 399 PPTable_t *pptable = table_context->driver_pptable; 400 uint64_t features = *(uint64_t *) pptable->FeaturesToRun; 401 402 /* Fan control is not possible if PPTable has it disabled */ 403 smu->adev->pm.no_fan = 404 !(features & (1ULL << FEATURE_FAN_CONTROL_BIT)); 405 if (smu->adev->pm.no_fan) 406 dev_info_once(smu->adev->dev, 407 "PMFW based fan control disabled"); 408} 409 410static int sienna_cichlid_check_powerplay_table(struct smu_context *smu) 411{ 412 struct smu_table_context *table_context = &smu->smu_table; 413 struct smu_11_0_7_powerplay_table *powerplay_table = 414 table_context->power_play_table; 415 416 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC) 417 smu->dc_controlled_by_gpio = true; 418 419 sienna_cichlid_check_bxco_support(smu); 420 sienna_cichlid_check_fan_support(smu); 421 422 table_context->thermal_controller_type = 423 powerplay_table->thermal_controller_type; 424 425 /* 426 * Instead of having its own buffer space and get overdrive_table copied, 427 * smu->od_settings just points to the actual overdrive_table 428 */ 429 smu->od_settings = &powerplay_table->overdrive_table; 430 431 return 0; 432} 433 434static int sienna_cichlid_append_powerplay_table(struct smu_context *smu) 435{ 436 struct atom_smc_dpm_info_v4_9 *smc_dpm_table; 437 int index, ret; 438 PPTable_beige_goby_t *ppt_beige_goby; 439 PPTable_t *ppt; 440 441 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13)) 442 ppt_beige_goby = smu->smu_table.driver_pptable; 443 else 444 ppt = smu->smu_table.driver_pptable; 445 446 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 447 smc_dpm_info); 448 449 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 450 (uint8_t **)&smc_dpm_table); 451 if (ret) 452 return ret; 453 454 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13)) 455 smu_memcpy_trailing(ppt_beige_goby, I2cControllers, BoardReserved, 456 smc_dpm_table, I2cControllers); 457 else 458 smu_memcpy_trailing(ppt, I2cControllers, BoardReserved, 459 smc_dpm_table, I2cControllers); 460 461 return 0; 462} 463 464static int sienna_cichlid_store_powerplay_table(struct smu_context *smu) 465{ 466 struct smu_table_context *table_context = &smu->smu_table; 467 struct smu_11_0_7_powerplay_table *powerplay_table = 468 table_context->power_play_table; 469 int table_size; 470 471 table_size = get_table_size(smu); 472 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 473 table_size); 474 475 return 0; 476} 477 478static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu) 479{ 480 struct amdgpu_device *adev = smu->adev; 481 uint32_t *board_reserved; 482 uint16_t *freq_table_gfx; 483 uint32_t i; 484 485 /* Fix some OEM SKU specific stability issues */ 486 GET_PPTABLE_MEMBER(BoardReserved, &board_reserved); 487 if ((adev->pdev->device == 0x73DF) && 488 (adev->pdev->revision == 0XC3) && 489 (adev->pdev->subsystem_device == 0x16C2) && 490 (adev->pdev->subsystem_vendor == 0x1043)) 491 board_reserved[0] = 1387; 492 493 GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx); 494 if ((adev->pdev->device == 0x73DF) && 495 (adev->pdev->revision == 0XC3) && 496 ((adev->pdev->subsystem_device == 0x16C2) || 497 (adev->pdev->subsystem_device == 0x133C)) && 498 (adev->pdev->subsystem_vendor == 0x1043)) { 499 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) { 500 if (freq_table_gfx[i] > 2500) 501 freq_table_gfx[i] = 2500; 502 } 503 } 504 505 return 0; 506} 507 508static int sienna_cichlid_setup_pptable(struct smu_context *smu) 509{ 510 int ret = 0; 511 512 ret = smu_v11_0_setup_pptable(smu); 513 if (ret) 514 return ret; 515 516 ret = sienna_cichlid_store_powerplay_table(smu); 517 if (ret) 518 return ret; 519 520 ret = sienna_cichlid_append_powerplay_table(smu); 521 if (ret) 522 return ret; 523 524 ret = sienna_cichlid_check_powerplay_table(smu); 525 if (ret) 526 return ret; 527 528 return sienna_cichlid_patch_pptable_quirk(smu); 529} 530 531static int sienna_cichlid_tables_init(struct smu_context *smu) 532{ 533 struct smu_table_context *smu_table = &smu->smu_table; 534 struct smu_table *tables = smu_table->tables; 535 int table_size; 536 537 table_size = get_table_size(smu); 538 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size, 539 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 540 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 541 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 542 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t), 543 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 544 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 545 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 546 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 547 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 548 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 549 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 550 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 551 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE, 552 AMDGPU_GEM_DOMAIN_VRAM); 553 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t), 554 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 555 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t), 556 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 557 558 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL); 559 if (!smu_table->metrics_table) 560 goto err0_out; 561 smu_table->metrics_time = 0; 562 563 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 564 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 565 if (!smu_table->gpu_metrics_table) 566 goto err1_out; 567 568 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 569 if (!smu_table->watermarks_table) 570 goto err2_out; 571 572 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL); 573 if (!smu_table->ecc_table) 574 goto err3_out; 575 576 smu_table->driver_smu_config_table = 577 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL); 578 if (!smu_table->driver_smu_config_table) 579 goto err4_out; 580 581 return 0; 582 583err4_out: 584 kfree(smu_table->ecc_table); 585err3_out: 586 kfree(smu_table->watermarks_table); 587err2_out: 588 kfree(smu_table->gpu_metrics_table); 589err1_out: 590 kfree(smu_table->metrics_table); 591err0_out: 592 return -ENOMEM; 593} 594 595static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu, 596 bool use_metrics_v3, 597 bool use_metrics_v2) 598{ 599 struct smu_table_context *smu_table= &smu->smu_table; 600 SmuMetricsExternal_t *metrics_ext = 601 (SmuMetricsExternal_t *)(smu_table->metrics_table); 602 uint32_t throttler_status = 0; 603 int i; 604 605 if (use_metrics_v3) { 606 for (i = 0; i < THROTTLER_COUNT; i++) 607 throttler_status |= 608 (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0); 609 } else if (use_metrics_v2) { 610 for (i = 0; i < THROTTLER_COUNT; i++) 611 throttler_status |= 612 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0); 613 } else { 614 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus; 615 } 616 617 return throttler_status; 618} 619 620static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table, 621 enum SMU_11_0_7_ODFEATURE_CAP cap) 622{ 623 return od_table->cap[cap]; 624} 625 626static int sienna_cichlid_get_power_limit(struct smu_context *smu, 627 uint32_t *current_power_limit, 628 uint32_t *default_power_limit, 629 uint32_t *max_power_limit, 630 uint32_t *min_power_limit) 631{ 632 struct smu_11_0_7_powerplay_table *powerplay_table = 633 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table; 634 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings; 635 uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0; 636 uint16_t *table_member; 637 638 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member); 639 640 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { 641 power_limit = 642 table_member[PPT_THROTTLER_PPT0]; 643 } 644 645 if (current_power_limit) 646 *current_power_limit = power_limit; 647 if (default_power_limit) 648 *default_power_limit = power_limit; 649 650 if (powerplay_table) { 651 if (smu->od_enabled && 652 sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_POWER_LIMIT)) { 653 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]); 654 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]); 655 } else if ((sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_POWER_LIMIT))) { 656 od_percent_upper = 0; 657 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]); 658 } 659 } 660 661 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n", 662 od_percent_upper, od_percent_lower, power_limit); 663 664 if (max_power_limit) { 665 *max_power_limit = power_limit * (100 + od_percent_upper); 666 *max_power_limit /= 100; 667 } 668 669 if (min_power_limit) { 670 *min_power_limit = power_limit * (100 - od_percent_lower); 671 *min_power_limit /= 100; 672 } 673 return 0; 674} 675 676static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu, 677 uint32_t *apu_percent, 678 uint32_t *dgpu_percent) 679{ 680 struct smu_table_context *smu_table = &smu->smu_table; 681 SmuMetrics_V4_t *metrics_v4 = 682 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4); 683 uint16_t powerRatio = 0; 684 uint16_t apu_power_limit = 0; 685 uint16_t dgpu_power_limit = 0; 686 uint32_t apu_boost = 0; 687 uint32_t dgpu_boost = 0; 688 uint32_t cur_power_limit; 689 690 if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) { 691 sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL, NULL); 692 apu_power_limit = metrics_v4->ApuSTAPMLimit; 693 dgpu_power_limit = cur_power_limit; 694 powerRatio = (((apu_power_limit + 695 dgpu_power_limit) * 100) / 696 metrics_v4->ApuSTAPMSmartShiftLimit); 697 if (powerRatio > 100) { 698 apu_power_limit = (apu_power_limit * 100) / 699 powerRatio; 700 dgpu_power_limit = (dgpu_power_limit * 100) / 701 powerRatio; 702 } 703 if (metrics_v4->AverageApuSocketPower > apu_power_limit && 704 apu_power_limit != 0) { 705 apu_boost = ((metrics_v4->AverageApuSocketPower - 706 apu_power_limit) * 100) / 707 apu_power_limit; 708 if (apu_boost > 100) 709 apu_boost = 100; 710 } 711 712 if (metrics_v4->AverageSocketPower > dgpu_power_limit && 713 dgpu_power_limit != 0) { 714 dgpu_boost = ((metrics_v4->AverageSocketPower - 715 dgpu_power_limit) * 100) / 716 dgpu_power_limit; 717 if (dgpu_boost > 100) 718 dgpu_boost = 100; 719 } 720 721 if (dgpu_boost >= apu_boost) 722 apu_boost = 0; 723 else 724 dgpu_boost = 0; 725 } 726 *apu_percent = apu_boost; 727 *dgpu_percent = dgpu_boost; 728} 729 730static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu, 731 MetricsMember_t member, 732 uint32_t *value) 733{ 734 struct smu_table_context *smu_table= &smu->smu_table; 735 SmuMetrics_t *metrics = 736 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 737 SmuMetrics_V2_t *metrics_v2 = 738 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2); 739 SmuMetrics_V3_t *metrics_v3 = 740 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3); 741 bool use_metrics_v2 = false; 742 bool use_metrics_v3 = false; 743 uint16_t average_gfx_activity; 744 int ret = 0; 745 uint32_t apu_percent = 0; 746 uint32_t dgpu_percent = 0; 747 748 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) { 749 case IP_VERSION(11, 0, 7): 750 if (smu->smc_fw_version >= 0x3A4900) 751 use_metrics_v3 = true; 752 else if (smu->smc_fw_version >= 0x3A4300) 753 use_metrics_v2 = true; 754 break; 755 case IP_VERSION(11, 0, 11): 756 if (smu->smc_fw_version >= 0x412D00) 757 use_metrics_v2 = true; 758 break; 759 case IP_VERSION(11, 0, 12): 760 if (smu->smc_fw_version >= 0x3B2300) 761 use_metrics_v2 = true; 762 break; 763 case IP_VERSION(11, 0, 13): 764 if (smu->smc_fw_version >= 0x491100) 765 use_metrics_v2 = true; 766 break; 767 default: 768 break; 769 } 770 771 ret = smu_cmn_get_metrics_table(smu, 772 NULL, 773 false); 774 if (ret) 775 return ret; 776 777 switch (member) { 778 case METRICS_CURR_GFXCLK: 779 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] : 780 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : 781 metrics->CurrClock[PPCLK_GFXCLK]; 782 break; 783 case METRICS_CURR_SOCCLK: 784 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] : 785 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : 786 metrics->CurrClock[PPCLK_SOCCLK]; 787 break; 788 case METRICS_CURR_UCLK: 789 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] : 790 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : 791 metrics->CurrClock[PPCLK_UCLK]; 792 break; 793 case METRICS_CURR_VCLK: 794 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] : 795 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : 796 metrics->CurrClock[PPCLK_VCLK_0]; 797 break; 798 case METRICS_CURR_VCLK1: 799 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] : 800 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : 801 metrics->CurrClock[PPCLK_VCLK_1]; 802 break; 803 case METRICS_CURR_DCLK: 804 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] : 805 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : 806 metrics->CurrClock[PPCLK_DCLK_0]; 807 break; 808 case METRICS_CURR_DCLK1: 809 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] : 810 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : 811 metrics->CurrClock[PPCLK_DCLK_1]; 812 break; 813 case METRICS_CURR_DCEFCLK: 814 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] : 815 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] : 816 metrics->CurrClock[PPCLK_DCEFCLK]; 817 break; 818 case METRICS_CURR_FCLK: 819 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] : 820 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] : 821 metrics->CurrClock[PPCLK_FCLK]; 822 break; 823 case METRICS_AVERAGE_GFXCLK: 824 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 825 use_metrics_v2 ? metrics_v2->AverageGfxActivity : 826 metrics->AverageGfxActivity; 827 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD) 828 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs : 829 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : 830 metrics->AverageGfxclkFrequencyPostDs; 831 else 832 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs : 833 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : 834 metrics->AverageGfxclkFrequencyPreDs; 835 break; 836 case METRICS_AVERAGE_FCLK: 837 *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs : 838 use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs : 839 metrics->AverageFclkFrequencyPostDs; 840 break; 841 case METRICS_AVERAGE_UCLK: 842 *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs : 843 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : 844 metrics->AverageUclkFrequencyPostDs; 845 break; 846 case METRICS_AVERAGE_GFXACTIVITY: 847 *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 848 use_metrics_v2 ? metrics_v2->AverageGfxActivity : 849 metrics->AverageGfxActivity; 850 break; 851 case METRICS_AVERAGE_MEMACTIVITY: 852 *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity : 853 use_metrics_v2 ? metrics_v2->AverageUclkActivity : 854 metrics->AverageUclkActivity; 855 break; 856 case METRICS_AVERAGE_SOCKETPOWER: 857 *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 : 858 use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 : 859 metrics->AverageSocketPower << 8; 860 break; 861 case METRICS_TEMPERATURE_EDGE: 862 *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge : 863 use_metrics_v2 ? metrics_v2->TemperatureEdge : 864 metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 865 break; 866 case METRICS_TEMPERATURE_HOTSPOT: 867 *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot : 868 use_metrics_v2 ? metrics_v2->TemperatureHotspot : 869 metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 870 break; 871 case METRICS_TEMPERATURE_MEM: 872 *value = (use_metrics_v3 ? metrics_v3->TemperatureMem : 873 use_metrics_v2 ? metrics_v2->TemperatureMem : 874 metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 875 break; 876 case METRICS_TEMPERATURE_VRGFX: 877 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx : 878 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : 879 metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 880 break; 881 case METRICS_TEMPERATURE_VRSOC: 882 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc : 883 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : 884 metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 885 break; 886 case METRICS_THROTTLER_STATUS: 887 *value = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2); 888 break; 889 case METRICS_CURR_FANSPEED: 890 *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed : 891 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed; 892 break; 893 case METRICS_UNIQUE_ID_UPPER32: 894 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */ 895 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0; 896 break; 897 case METRICS_UNIQUE_ID_LOWER32: 898 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */ 899 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0; 900 break; 901 case METRICS_SS_APU_SHARE: 902 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent); 903 *value = apu_percent; 904 break; 905 case METRICS_SS_DGPU_SHARE: 906 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent); 907 *value = dgpu_percent; 908 break; 909 910 default: 911 *value = UINT_MAX; 912 break; 913 } 914 915 return ret; 916 917} 918 919static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu) 920{ 921 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 922 923 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 924 GFP_KERNEL); 925 if (!smu_dpm->dpm_context) 926 return -ENOMEM; 927 928 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 929 930 return 0; 931} 932 933static void sienna_cichlid_stb_init(struct smu_context *smu); 934 935static int sienna_cichlid_init_smc_tables(struct smu_context *smu) 936{ 937 struct amdgpu_device *adev = smu->adev; 938 int ret = 0; 939 940 ret = sienna_cichlid_tables_init(smu); 941 if (ret) 942 return ret; 943 944 ret = sienna_cichlid_allocate_dpm_context(smu); 945 if (ret) 946 return ret; 947 948 if (!amdgpu_sriov_vf(adev)) 949 sienna_cichlid_stb_init(smu); 950 951 return smu_v11_0_init_smc_tables(smu); 952} 953 954static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) 955{ 956 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 957 struct smu_11_0_dpm_table *dpm_table; 958 struct amdgpu_device *adev = smu->adev; 959 int i, ret = 0; 960 DpmDescriptor_t *table_member; 961 962 /* socclk dpm table setup */ 963 dpm_table = &dpm_context->dpm_tables.soc_table; 964 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member); 965 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 966 ret = smu_v11_0_set_single_dpm_table(smu, 967 SMU_SOCCLK, 968 dpm_table); 969 if (ret) 970 return ret; 971 dpm_table->is_fine_grained = 972 !table_member[PPCLK_SOCCLK].SnapToDiscrete; 973 } else { 974 dpm_table->count = 1; 975 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 976 dpm_table->dpm_levels[0].enabled = true; 977 dpm_table->min = dpm_table->dpm_levels[0].value; 978 dpm_table->max = dpm_table->dpm_levels[0].value; 979 } 980 981 /* gfxclk dpm table setup */ 982 dpm_table = &dpm_context->dpm_tables.gfx_table; 983 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 984 ret = smu_v11_0_set_single_dpm_table(smu, 985 SMU_GFXCLK, 986 dpm_table); 987 if (ret) 988 return ret; 989 dpm_table->is_fine_grained = 990 !table_member[PPCLK_GFXCLK].SnapToDiscrete; 991 } else { 992 dpm_table->count = 1; 993 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 994 dpm_table->dpm_levels[0].enabled = true; 995 dpm_table->min = dpm_table->dpm_levels[0].value; 996 dpm_table->max = dpm_table->dpm_levels[0].value; 997 } 998 999 /* uclk dpm table setup */ 1000 dpm_table = &dpm_context->dpm_tables.uclk_table; 1001 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1002 ret = smu_v11_0_set_single_dpm_table(smu, 1003 SMU_UCLK, 1004 dpm_table); 1005 if (ret) 1006 return ret; 1007 dpm_table->is_fine_grained = 1008 !table_member[PPCLK_UCLK].SnapToDiscrete; 1009 } else { 1010 dpm_table->count = 1; 1011 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 1012 dpm_table->dpm_levels[0].enabled = true; 1013 dpm_table->min = dpm_table->dpm_levels[0].value; 1014 dpm_table->max = dpm_table->dpm_levels[0].value; 1015 } 1016 1017 /* fclk dpm table setup */ 1018 dpm_table = &dpm_context->dpm_tables.fclk_table; 1019 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 1020 ret = smu_v11_0_set_single_dpm_table(smu, 1021 SMU_FCLK, 1022 dpm_table); 1023 if (ret) 1024 return ret; 1025 dpm_table->is_fine_grained = 1026 !table_member[PPCLK_FCLK].SnapToDiscrete; 1027 } else { 1028 dpm_table->count = 1; 1029 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 1030 dpm_table->dpm_levels[0].enabled = true; 1031 dpm_table->min = dpm_table->dpm_levels[0].value; 1032 dpm_table->max = dpm_table->dpm_levels[0].value; 1033 } 1034 1035 /* vclk0/1 dpm table setup */ 1036 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1037 if (adev->vcn.harvest_config & (1 << i)) 1038 continue; 1039 1040 dpm_table = &dpm_context->dpm_tables.vclk_table; 1041 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1042 ret = smu_v11_0_set_single_dpm_table(smu, 1043 i ? SMU_VCLK1 : SMU_VCLK, 1044 dpm_table); 1045 if (ret) 1046 return ret; 1047 dpm_table->is_fine_grained = 1048 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete; 1049 } else { 1050 dpm_table->count = 1; 1051 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 1052 dpm_table->dpm_levels[0].enabled = true; 1053 dpm_table->min = dpm_table->dpm_levels[0].value; 1054 dpm_table->max = dpm_table->dpm_levels[0].value; 1055 } 1056 } 1057 1058 /* dclk0/1 dpm table setup */ 1059 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1060 if (adev->vcn.harvest_config & (1 << i)) 1061 continue; 1062 dpm_table = &dpm_context->dpm_tables.dclk_table; 1063 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1064 ret = smu_v11_0_set_single_dpm_table(smu, 1065 i ? SMU_DCLK1 : SMU_DCLK, 1066 dpm_table); 1067 if (ret) 1068 return ret; 1069 dpm_table->is_fine_grained = 1070 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete; 1071 } else { 1072 dpm_table->count = 1; 1073 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 1074 dpm_table->dpm_levels[0].enabled = true; 1075 dpm_table->min = dpm_table->dpm_levels[0].value; 1076 dpm_table->max = dpm_table->dpm_levels[0].value; 1077 } 1078 } 1079 1080 /* dcefclk dpm table setup */ 1081 dpm_table = &dpm_context->dpm_tables.dcef_table; 1082 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1083 ret = smu_v11_0_set_single_dpm_table(smu, 1084 SMU_DCEFCLK, 1085 dpm_table); 1086 if (ret) 1087 return ret; 1088 dpm_table->is_fine_grained = 1089 !table_member[PPCLK_DCEFCLK].SnapToDiscrete; 1090 } else { 1091 dpm_table->count = 1; 1092 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1093 dpm_table->dpm_levels[0].enabled = true; 1094 dpm_table->min = dpm_table->dpm_levels[0].value; 1095 dpm_table->max = dpm_table->dpm_levels[0].value; 1096 } 1097 1098 /* pixelclk dpm table setup */ 1099 dpm_table = &dpm_context->dpm_tables.pixel_table; 1100 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1101 ret = smu_v11_0_set_single_dpm_table(smu, 1102 SMU_PIXCLK, 1103 dpm_table); 1104 if (ret) 1105 return ret; 1106 dpm_table->is_fine_grained = 1107 !table_member[PPCLK_PIXCLK].SnapToDiscrete; 1108 } else { 1109 dpm_table->count = 1; 1110 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1111 dpm_table->dpm_levels[0].enabled = true; 1112 dpm_table->min = dpm_table->dpm_levels[0].value; 1113 dpm_table->max = dpm_table->dpm_levels[0].value; 1114 } 1115 1116 /* displayclk dpm table setup */ 1117 dpm_table = &dpm_context->dpm_tables.display_table; 1118 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1119 ret = smu_v11_0_set_single_dpm_table(smu, 1120 SMU_DISPCLK, 1121 dpm_table); 1122 if (ret) 1123 return ret; 1124 dpm_table->is_fine_grained = 1125 !table_member[PPCLK_DISPCLK].SnapToDiscrete; 1126 } else { 1127 dpm_table->count = 1; 1128 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1129 dpm_table->dpm_levels[0].enabled = true; 1130 dpm_table->min = dpm_table->dpm_levels[0].value; 1131 dpm_table->max = dpm_table->dpm_levels[0].value; 1132 } 1133 1134 /* phyclk dpm table setup */ 1135 dpm_table = &dpm_context->dpm_tables.phy_table; 1136 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1137 ret = smu_v11_0_set_single_dpm_table(smu, 1138 SMU_PHYCLK, 1139 dpm_table); 1140 if (ret) 1141 return ret; 1142 dpm_table->is_fine_grained = 1143 !table_member[PPCLK_PHYCLK].SnapToDiscrete; 1144 } else { 1145 dpm_table->count = 1; 1146 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1147 dpm_table->dpm_levels[0].enabled = true; 1148 dpm_table->min = dpm_table->dpm_levels[0].value; 1149 dpm_table->max = dpm_table->dpm_levels[0].value; 1150 } 1151 1152 return 0; 1153} 1154 1155static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, 1156 bool enable, 1157 int inst) 1158{ 1159 struct amdgpu_device *adev = smu->adev; 1160 int ret = 0; 1161 1162 if (adev->vcn.harvest_config & (1 << inst)) 1163 return ret; 1164 /* vcn dpm on is a prerequisite for vcn power gate messages */ 1165 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1166 ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1167 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, 1168 0x10000 * inst, NULL); 1169 } 1170 1171 return ret; 1172} 1173 1174static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 1175{ 1176 int ret = 0; 1177 1178 if (enable) { 1179 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1180 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 1181 if (ret) 1182 return ret; 1183 } 1184 } else { 1185 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1186 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 1187 if (ret) 1188 return ret; 1189 } 1190 } 1191 1192 return ret; 1193} 1194 1195static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu, 1196 enum smu_clk_type clk_type, 1197 uint32_t *value) 1198{ 1199 MetricsMember_t member_type; 1200 int clk_id = 0; 1201 1202 clk_id = smu_cmn_to_asic_specific_index(smu, 1203 CMN2ASIC_MAPPING_CLK, 1204 clk_type); 1205 if (clk_id < 0) 1206 return clk_id; 1207 1208 switch (clk_id) { 1209 case PPCLK_GFXCLK: 1210 member_type = METRICS_CURR_GFXCLK; 1211 break; 1212 case PPCLK_UCLK: 1213 member_type = METRICS_CURR_UCLK; 1214 break; 1215 case PPCLK_SOCCLK: 1216 member_type = METRICS_CURR_SOCCLK; 1217 break; 1218 case PPCLK_FCLK: 1219 member_type = METRICS_CURR_FCLK; 1220 break; 1221 case PPCLK_VCLK_0: 1222 member_type = METRICS_CURR_VCLK; 1223 break; 1224 case PPCLK_VCLK_1: 1225 member_type = METRICS_CURR_VCLK1; 1226 break; 1227 case PPCLK_DCLK_0: 1228 member_type = METRICS_CURR_DCLK; 1229 break; 1230 case PPCLK_DCLK_1: 1231 member_type = METRICS_CURR_DCLK1; 1232 break; 1233 case PPCLK_DCEFCLK: 1234 member_type = METRICS_CURR_DCEFCLK; 1235 break; 1236 default: 1237 return -EINVAL; 1238 } 1239 1240 return sienna_cichlid_get_smu_metrics_data(smu, 1241 member_type, 1242 value); 1243 1244} 1245 1246static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) 1247{ 1248 DpmDescriptor_t *dpm_desc = NULL; 1249 DpmDescriptor_t *table_member; 1250 uint32_t clk_index = 0; 1251 1252 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member); 1253 clk_index = smu_cmn_to_asic_specific_index(smu, 1254 CMN2ASIC_MAPPING_CLK, 1255 clk_type); 1256 dpm_desc = &table_member[clk_index]; 1257 1258 /* 0 - Fine grained DPM, 1 - Discrete DPM */ 1259 return dpm_desc->SnapToDiscrete == 0; 1260} 1261 1262static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table, 1263 enum SMU_11_0_7_ODSETTING_ID setting, 1264 uint32_t *min, uint32_t *max) 1265{ 1266 if (min) 1267 *min = od_table->min[setting]; 1268 if (max) 1269 *max = od_table->max[setting]; 1270} 1271 1272static int sienna_cichlid_print_clk_levels(struct smu_context *smu, 1273 enum smu_clk_type clk_type, char *buf) 1274{ 1275 struct amdgpu_device *adev = smu->adev; 1276 struct smu_table_context *table_context = &smu->smu_table; 1277 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1278 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1279 uint16_t *table_member; 1280 1281 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings; 1282 OverDriveTable_t *od_table = 1283 (OverDriveTable_t *)table_context->overdrive_table; 1284 int i, size = 0, ret = 0, start_offset = 0; 1285 uint32_t cur_value = 0, value = 0, count = 0; 1286 uint32_t freq_values[3] = {0}; 1287 uint32_t mark_index = 0; 1288 uint32_t gen_speed, lane_width; 1289 uint32_t min_value, max_value; 1290 1291 smu_cmn_get_sysfs_buf(&buf, &size); 1292 start_offset = size; 1293 1294 switch (clk_type) { 1295 case SMU_GFXCLK: 1296 case SMU_SCLK: 1297 case SMU_SOCCLK: 1298 case SMU_MCLK: 1299 case SMU_UCLK: 1300 case SMU_FCLK: 1301 case SMU_VCLK: 1302 case SMU_VCLK1: 1303 case SMU_DCLK: 1304 case SMU_DCLK1: 1305 case SMU_DCEFCLK: 1306 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value); 1307 if (ret) 1308 goto print_clk_out; 1309 1310 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); 1311 if (ret) 1312 goto print_clk_out; 1313 1314 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { 1315 for (i = 0; i < count; i++) { 1316 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); 1317 if (ret) 1318 goto print_clk_out; 1319 1320 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 1321 cur_value == value ? "*" : ""); 1322 } 1323 } else { 1324 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); 1325 if (ret) 1326 goto print_clk_out; 1327 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); 1328 if (ret) 1329 goto print_clk_out; 1330 1331 freq_values[1] = cur_value; 1332 mark_index = cur_value == freq_values[0] ? 0 : 1333 cur_value == freq_values[2] ? 2 : 1; 1334 1335 count = 3; 1336 if (mark_index != 1) { 1337 count = 2; 1338 freq_values[1] = freq_values[2]; 1339 } 1340 1341 for (i = 0; i < count; i++) { 1342 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i], 1343 cur_value == freq_values[i] ? "*" : ""); 1344 } 1345 1346 } 1347 break; 1348 case SMU_PCIE: 1349 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 1350 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1351 GET_PPTABLE_MEMBER(LclkFreq, &table_member); 1352 for (i = 0; i < NUM_LINK_LEVELS; i++) 1353 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1354 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : 1355 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : 1356 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : 1357 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", 1358 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : 1359 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : 1360 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : 1361 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : 1362 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : 1363 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", 1364 table_member[i], 1365 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && 1366 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1367 "*" : ""); 1368 break; 1369 case SMU_OD_SCLK: 1370 if (!smu->od_enabled || !od_table || !od_settings) 1371 break; 1372 1373 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) 1374 break; 1375 1376 size += sysfs_emit_at(buf, size, "OD_SCLK:\n"); 1377 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax); 1378 break; 1379 1380 case SMU_OD_MCLK: 1381 if (!smu->od_enabled || !od_table || !od_settings) 1382 break; 1383 1384 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) 1385 break; 1386 1387 size += sysfs_emit_at(buf, size, "OD_MCLK:\n"); 1388 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax); 1389 break; 1390 1391 case SMU_OD_VDDGFX_OFFSET: 1392 if (!smu->od_enabled || !od_table || !od_settings) 1393 break; 1394 1395 /* 1396 * OD GFX Voltage Offset functionality is supported only by 58.41.0 1397 * and onwards SMU firmwares. 1398 */ 1399 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == 1400 IP_VERSION(11, 0, 7)) && 1401 (smu->smc_fw_version < 0x003a2900)) 1402 break; 1403 1404 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n"); 1405 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset); 1406 break; 1407 1408 case SMU_OD_RANGE: 1409 if (!smu->od_enabled || !od_table || !od_settings) 1410 break; 1411 1412 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1413 1414 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) { 1415 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN, 1416 &min_value, NULL); 1417 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX, 1418 NULL, &max_value); 1419 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 1420 min_value, max_value); 1421 } 1422 1423 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) { 1424 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN, 1425 &min_value, NULL); 1426 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX, 1427 NULL, &max_value); 1428 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n", 1429 min_value, max_value); 1430 } 1431 break; 1432 1433 default: 1434 break; 1435 } 1436 1437print_clk_out: 1438 return size - start_offset; 1439} 1440 1441static int sienna_cichlid_force_clk_levels(struct smu_context *smu, 1442 enum smu_clk_type clk_type, uint32_t mask) 1443{ 1444 int ret = 0; 1445 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 1446 1447 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1448 soft_max_level = mask ? (fls(mask) - 1) : 0; 1449 1450 switch (clk_type) { 1451 case SMU_GFXCLK: 1452 case SMU_SCLK: 1453 case SMU_SOCCLK: 1454 case SMU_MCLK: 1455 case SMU_UCLK: 1456 case SMU_FCLK: 1457 /* There is only 2 levels for fine grained DPM */ 1458 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { 1459 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1460 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1461 } 1462 1463 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 1464 if (ret) 1465 goto forec_level_out; 1466 1467 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 1468 if (ret) 1469 goto forec_level_out; 1470 1471 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false); 1472 if (ret) 1473 goto forec_level_out; 1474 break; 1475 case SMU_DCEFCLK: 1476 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n"); 1477 break; 1478 default: 1479 break; 1480 } 1481 1482forec_level_out: 1483 return 0; 1484} 1485 1486static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu) 1487{ 1488 struct smu_11_0_dpm_context *dpm_context = 1489 smu->smu_dpm.dpm_context; 1490 struct smu_11_0_dpm_table *gfx_table = 1491 &dpm_context->dpm_tables.gfx_table; 1492 struct smu_11_0_dpm_table *mem_table = 1493 &dpm_context->dpm_tables.uclk_table; 1494 struct smu_11_0_dpm_table *soc_table = 1495 &dpm_context->dpm_tables.soc_table; 1496 struct smu_umd_pstate_table *pstate_table = 1497 &smu->pstate_table; 1498 struct amdgpu_device *adev = smu->adev; 1499 1500 pstate_table->gfxclk_pstate.min = gfx_table->min; 1501 pstate_table->gfxclk_pstate.peak = gfx_table->max; 1502 1503 pstate_table->uclk_pstate.min = mem_table->min; 1504 pstate_table->uclk_pstate.peak = mem_table->max; 1505 1506 pstate_table->socclk_pstate.min = soc_table->min; 1507 pstate_table->socclk_pstate.peak = soc_table->max; 1508 1509 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1510 case IP_VERSION(11, 0, 7): 1511 case IP_VERSION(11, 0, 11): 1512 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK; 1513 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK; 1514 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK; 1515 break; 1516 case IP_VERSION(11, 0, 12): 1517 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK; 1518 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK; 1519 pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK; 1520 break; 1521 case IP_VERSION(11, 0, 13): 1522 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK; 1523 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK; 1524 pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK; 1525 break; 1526 default: 1527 break; 1528 } 1529 1530 return 0; 1531} 1532 1533static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu) 1534{ 1535 int ret = 0; 1536 uint32_t max_freq = 0; 1537 1538 /* Sienna_Cichlid do not support to change display num currently */ 1539 return 0; 1540#if 0 1541 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL); 1542 if (ret) 1543 return ret; 1544#endif 1545 1546 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1547 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); 1548 if (ret) 1549 return ret; 1550 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); 1551 if (ret) 1552 return ret; 1553 } 1554 1555 return ret; 1556} 1557 1558static int sienna_cichlid_display_config_changed(struct smu_context *smu) 1559{ 1560 int ret = 0; 1561 1562 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1563 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && 1564 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 1565#if 0 1566 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 1567 smu->display_config->num_display, 1568 NULL); 1569#endif 1570 if (ret) 1571 return ret; 1572 } 1573 1574 return ret; 1575} 1576 1577static bool sienna_cichlid_is_dpm_running(struct smu_context *smu) 1578{ 1579 int ret = 0; 1580 uint64_t feature_enabled; 1581 1582 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1583 if (ret) 1584 return false; 1585 1586 return !!(feature_enabled & SMC_DPM_FEATURE); 1587} 1588 1589static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu, 1590 uint32_t *speed) 1591{ 1592 if (!speed) 1593 return -EINVAL; 1594 1595 /* 1596 * For Sienna_Cichlid and later, the fan speed(rpm) reported 1597 * by pmfw is always trustable(even when the fan control feature 1598 * disabled or 0 RPM kicked in). 1599 */ 1600 return sienna_cichlid_get_smu_metrics_data(smu, 1601 METRICS_CURR_FANSPEED, 1602 speed); 1603} 1604 1605static int sienna_cichlid_get_fan_parameters(struct smu_context *smu) 1606{ 1607 uint16_t *table_member; 1608 1609 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member); 1610 smu->fan_max_rpm = *table_member; 1611 1612 return 0; 1613} 1614 1615static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf) 1616{ 1617 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1618 DpmActivityMonitorCoeffInt_t *activity_monitor = 1619 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1620 uint32_t i, size = 0; 1621 int16_t workload_type = 0; 1622 static const char *title[] = { 1623 "PROFILE_INDEX(NAME)", 1624 "CLOCK_TYPE(NAME)", 1625 "FPS", 1626 "MinFreqType", 1627 "MinActiveFreqType", 1628 "MinActiveFreq", 1629 "BoosterFreqType", 1630 "BoosterFreq", 1631 "PD_Data_limit_c", 1632 "PD_Data_error_coeff", 1633 "PD_Data_error_rate_coeff"}; 1634 int result = 0; 1635 1636 if (!buf) 1637 return -EINVAL; 1638 1639 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 1640 title[0], title[1], title[2], title[3], title[4], title[5], 1641 title[6], title[7], title[8], title[9], title[10]); 1642 1643 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1644 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1645 workload_type = smu_cmn_to_asic_specific_index(smu, 1646 CMN2ASIC_MAPPING_WORKLOAD, 1647 i); 1648 if (workload_type < 0) 1649 return -EINVAL; 1650 1651 result = smu_cmn_update_table(smu, 1652 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, 1653 (void *)(&activity_monitor_external), false); 1654 if (result) { 1655 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1656 return result; 1657 } 1658 1659 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n", 1660 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1661 1662 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1663 " ", 1664 0, 1665 "GFXCLK", 1666 activity_monitor->Gfx_FPS, 1667 activity_monitor->Gfx_MinFreqStep, 1668 activity_monitor->Gfx_MinActiveFreqType, 1669 activity_monitor->Gfx_MinActiveFreq, 1670 activity_monitor->Gfx_BoosterFreqType, 1671 activity_monitor->Gfx_BoosterFreq, 1672 activity_monitor->Gfx_PD_Data_limit_c, 1673 activity_monitor->Gfx_PD_Data_error_coeff, 1674 activity_monitor->Gfx_PD_Data_error_rate_coeff); 1675 1676 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1677 " ", 1678 1, 1679 "SOCCLK", 1680 activity_monitor->Fclk_FPS, 1681 activity_monitor->Fclk_MinFreqStep, 1682 activity_monitor->Fclk_MinActiveFreqType, 1683 activity_monitor->Fclk_MinActiveFreq, 1684 activity_monitor->Fclk_BoosterFreqType, 1685 activity_monitor->Fclk_BoosterFreq, 1686 activity_monitor->Fclk_PD_Data_limit_c, 1687 activity_monitor->Fclk_PD_Data_error_coeff, 1688 activity_monitor->Fclk_PD_Data_error_rate_coeff); 1689 1690 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1691 " ", 1692 2, 1693 "MEMCLK", 1694 activity_monitor->Mem_FPS, 1695 activity_monitor->Mem_MinFreqStep, 1696 activity_monitor->Mem_MinActiveFreqType, 1697 activity_monitor->Mem_MinActiveFreq, 1698 activity_monitor->Mem_BoosterFreqType, 1699 activity_monitor->Mem_BoosterFreq, 1700 activity_monitor->Mem_PD_Data_limit_c, 1701 activity_monitor->Mem_PD_Data_error_coeff, 1702 activity_monitor->Mem_PD_Data_error_rate_coeff); 1703 } 1704 1705 return size; 1706} 1707 1708#define SIENNA_CICHLID_CUSTOM_PARAMS_COUNT 10 1709#define SIENNA_CICHLID_CUSTOM_PARAMS_CLOCK_COUNT 3 1710#define SIENNA_CICHLID_CUSTOM_PARAMS_SIZE (SIENNA_CICHLID_CUSTOM_PARAMS_CLOCK_COUNT * SIENNA_CICHLID_CUSTOM_PARAMS_COUNT * sizeof(long)) 1711 1712static int sienna_cichlid_set_power_profile_mode_coeff(struct smu_context *smu, 1713 long *input) 1714{ 1715 1716 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1717 DpmActivityMonitorCoeffInt_t *activity_monitor = 1718 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1719 int ret, idx; 1720 1721 ret = smu_cmn_update_table(smu, 1722 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1723 (void *)(&activity_monitor_external), false); 1724 if (ret) { 1725 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1726 return ret; 1727 } 1728 1729 idx = 0 * SIENNA_CICHLID_CUSTOM_PARAMS_COUNT; 1730 if (input[idx]) { 1731 /* Gfxclk */ 1732 activity_monitor->Gfx_FPS = input[idx + 1]; 1733 activity_monitor->Gfx_MinFreqStep = input[idx + 2]; 1734 activity_monitor->Gfx_MinActiveFreqType = input[idx + 3]; 1735 activity_monitor->Gfx_MinActiveFreq = input[idx + 4]; 1736 activity_monitor->Gfx_BoosterFreqType = input[idx + 5]; 1737 activity_monitor->Gfx_BoosterFreq = input[idx + 6]; 1738 activity_monitor->Gfx_PD_Data_limit_c = input[idx + 7]; 1739 activity_monitor->Gfx_PD_Data_error_coeff = input[idx + 8]; 1740 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[idx + 9]; 1741 } 1742 idx = 1 * SIENNA_CICHLID_CUSTOM_PARAMS_COUNT; 1743 if (input[idx]) { 1744 /* Socclk */ 1745 activity_monitor->Fclk_FPS = input[idx + 1]; 1746 activity_monitor->Fclk_MinFreqStep = input[idx + 2]; 1747 activity_monitor->Fclk_MinActiveFreqType = input[idx + 3]; 1748 activity_monitor->Fclk_MinActiveFreq = input[idx + 4]; 1749 activity_monitor->Fclk_BoosterFreqType = input[idx + 5]; 1750 activity_monitor->Fclk_BoosterFreq = input[idx + 6]; 1751 activity_monitor->Fclk_PD_Data_limit_c = input[idx + 7]; 1752 activity_monitor->Fclk_PD_Data_error_coeff = input[idx + 8]; 1753 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[idx + 9]; 1754 } 1755 idx = 2 * SIENNA_CICHLID_CUSTOM_PARAMS_COUNT; 1756 if (input[idx]) { 1757 /* Memclk */ 1758 activity_monitor->Mem_FPS = input[idx + 1]; 1759 activity_monitor->Mem_MinFreqStep = input[idx + 2]; 1760 activity_monitor->Mem_MinActiveFreqType = input[idx + 3]; 1761 activity_monitor->Mem_MinActiveFreq = input[idx + 4]; 1762 activity_monitor->Mem_BoosterFreqType = input[idx + 5]; 1763 activity_monitor->Mem_BoosterFreq = input[idx + 6]; 1764 activity_monitor->Mem_PD_Data_limit_c = input[idx + 7]; 1765 activity_monitor->Mem_PD_Data_error_coeff = input[idx + 8]; 1766 activity_monitor->Mem_PD_Data_error_rate_coeff = input[idx + 9]; 1767 } 1768 1769 ret = smu_cmn_update_table(smu, 1770 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1771 (void *)(&activity_monitor_external), true); 1772 if (ret) { 1773 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1774 return ret; 1775 } 1776 1777 return ret; 1778} 1779 1780static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, 1781 u32 workload_mask, 1782 long *custom_params, 1783 u32 custom_params_max_idx) 1784{ 1785 u32 backend_workload_mask = 0; 1786 int ret, idx = -1, i; 1787 1788 smu_cmn_get_backend_workload_mask(smu, workload_mask, 1789 &backend_workload_mask); 1790 1791 if (workload_mask & (1 << PP_SMC_POWER_PROFILE_CUSTOM)) { 1792 if (!smu->custom_profile_params) { 1793 smu->custom_profile_params = 1794 kzalloc(SIENNA_CICHLID_CUSTOM_PARAMS_SIZE, GFP_KERNEL); 1795 if (!smu->custom_profile_params) 1796 return -ENOMEM; 1797 } 1798 if (custom_params && custom_params_max_idx) { 1799 if (custom_params_max_idx != SIENNA_CICHLID_CUSTOM_PARAMS_COUNT) 1800 return -EINVAL; 1801 if (custom_params[0] >= SIENNA_CICHLID_CUSTOM_PARAMS_CLOCK_COUNT) 1802 return -EINVAL; 1803 idx = custom_params[0] * SIENNA_CICHLID_CUSTOM_PARAMS_COUNT; 1804 smu->custom_profile_params[idx] = 1; 1805 for (i = 1; i < custom_params_max_idx; i++) 1806 smu->custom_profile_params[idx + i] = custom_params[i]; 1807 } 1808 ret = sienna_cichlid_set_power_profile_mode_coeff(smu, 1809 smu->custom_profile_params); 1810 if (ret) { 1811 if (idx != -1) 1812 smu->custom_profile_params[idx] = 0; 1813 return ret; 1814 } 1815 } else if (smu->custom_profile_params) { 1816 memset(smu->custom_profile_params, 0, SIENNA_CICHLID_CUSTOM_PARAMS_SIZE); 1817 } 1818 1819 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1820 backend_workload_mask, NULL); 1821 if (ret) { 1822 dev_err(smu->adev->dev, "Failed to set workload mask 0x%08x\n", 1823 workload_mask); 1824 if (idx != -1) 1825 smu->custom_profile_params[idx] = 0; 1826 return ret; 1827 } 1828 1829 return ret; 1830} 1831 1832static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu) 1833{ 1834 struct smu_clocks min_clocks = {0}; 1835 struct pp_display_clock_request clock_req; 1836 int ret = 0; 1837 1838 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; 1839 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; 1840 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; 1841 1842 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1843 clock_req.clock_type = amd_pp_dcef_clock; 1844 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; 1845 1846 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); 1847 if (!ret) { 1848 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) { 1849 ret = smu_cmn_send_smc_msg_with_param(smu, 1850 SMU_MSG_SetMinDeepSleepDcefclk, 1851 min_clocks.dcef_clock_in_sr/100, 1852 NULL); 1853 if (ret) { 1854 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!"); 1855 return ret; 1856 } 1857 } 1858 } else { 1859 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!"); 1860 } 1861 } 1862 1863 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1864 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); 1865 if (ret) { 1866 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); 1867 return ret; 1868 } 1869 } 1870 1871 return 0; 1872} 1873 1874static int sienna_cichlid_set_watermarks_table(struct smu_context *smu, 1875 struct pp_smu_wm_range_sets *clock_ranges) 1876{ 1877 Watermarks_t *table = smu->smu_table.watermarks_table; 1878 int ret = 0; 1879 int i; 1880 1881 if (clock_ranges) { 1882 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1883 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1884 return -EINVAL; 1885 1886 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1887 table->WatermarkRow[WM_DCEFCLK][i].MinClock = 1888 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1889 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = 1890 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1891 table->WatermarkRow[WM_DCEFCLK][i].MinUclk = 1892 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1893 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = 1894 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1895 1896 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = 1897 clock_ranges->reader_wm_sets[i].wm_inst; 1898 } 1899 1900 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1901 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1902 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1903 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1904 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1905 table->WatermarkRow[WM_SOCCLK][i].MinUclk = 1906 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1907 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = 1908 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1909 1910 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1911 clock_ranges->writer_wm_sets[i].wm_inst; 1912 } 1913 1914 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1915 } 1916 1917 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1918 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1919 ret = smu_cmn_write_watermarks_table(smu); 1920 if (ret) { 1921 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1922 return ret; 1923 } 1924 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1925 } 1926 1927 return 0; 1928} 1929 1930static int sienna_cichlid_read_sensor(struct smu_context *smu, 1931 enum amd_pp_sensors sensor, 1932 void *data, uint32_t *size) 1933{ 1934 int ret = 0; 1935 uint16_t *temp; 1936 struct amdgpu_device *adev = smu->adev; 1937 1938 if(!data || !size) 1939 return -EINVAL; 1940 1941 switch (sensor) { 1942 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 1943 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp); 1944 *(uint16_t *)data = *temp; 1945 *size = 4; 1946 break; 1947 case AMDGPU_PP_SENSOR_MEM_LOAD: 1948 ret = sienna_cichlid_get_smu_metrics_data(smu, 1949 METRICS_AVERAGE_MEMACTIVITY, 1950 (uint32_t *)data); 1951 *size = 4; 1952 break; 1953 case AMDGPU_PP_SENSOR_GPU_LOAD: 1954 ret = sienna_cichlid_get_smu_metrics_data(smu, 1955 METRICS_AVERAGE_GFXACTIVITY, 1956 (uint32_t *)data); 1957 *size = 4; 1958 break; 1959 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 1960 ret = sienna_cichlid_get_smu_metrics_data(smu, 1961 METRICS_AVERAGE_SOCKETPOWER, 1962 (uint32_t *)data); 1963 *size = 4; 1964 break; 1965 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1966 ret = sienna_cichlid_get_smu_metrics_data(smu, 1967 METRICS_TEMPERATURE_HOTSPOT, 1968 (uint32_t *)data); 1969 *size = 4; 1970 break; 1971 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1972 ret = sienna_cichlid_get_smu_metrics_data(smu, 1973 METRICS_TEMPERATURE_EDGE, 1974 (uint32_t *)data); 1975 *size = 4; 1976 break; 1977 case AMDGPU_PP_SENSOR_MEM_TEMP: 1978 ret = sienna_cichlid_get_smu_metrics_data(smu, 1979 METRICS_TEMPERATURE_MEM, 1980 (uint32_t *)data); 1981 *size = 4; 1982 break; 1983 case AMDGPU_PP_SENSOR_GFX_MCLK: 1984 ret = sienna_cichlid_get_smu_metrics_data(smu, 1985 METRICS_CURR_UCLK, 1986 (uint32_t *)data); 1987 *(uint32_t *)data *= 100; 1988 *size = 4; 1989 break; 1990 case AMDGPU_PP_SENSOR_GFX_SCLK: 1991 ret = sienna_cichlid_get_smu_metrics_data(smu, 1992 METRICS_AVERAGE_GFXCLK, 1993 (uint32_t *)data); 1994 *(uint32_t *)data *= 100; 1995 *size = 4; 1996 break; 1997 case AMDGPU_PP_SENSOR_VDDGFX: 1998 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); 1999 *size = 4; 2000 break; 2001 case AMDGPU_PP_SENSOR_SS_APU_SHARE: 2002 if (amdgpu_ip_version(adev, MP1_HWIP, 0) != 2003 IP_VERSION(11, 0, 7)) { 2004 ret = sienna_cichlid_get_smu_metrics_data(smu, 2005 METRICS_SS_APU_SHARE, (uint32_t *)data); 2006 *size = 4; 2007 } else { 2008 ret = -EOPNOTSUPP; 2009 } 2010 break; 2011 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE: 2012 if (amdgpu_ip_version(adev, MP1_HWIP, 0) != 2013 IP_VERSION(11, 0, 7)) { 2014 ret = sienna_cichlid_get_smu_metrics_data(smu, 2015 METRICS_SS_DGPU_SHARE, (uint32_t *)data); 2016 *size = 4; 2017 } else { 2018 ret = -EOPNOTSUPP; 2019 } 2020 break; 2021 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 2022 default: 2023 ret = -EOPNOTSUPP; 2024 break; 2025 } 2026 2027 return ret; 2028} 2029 2030static void sienna_cichlid_get_unique_id(struct smu_context *smu) 2031{ 2032 struct amdgpu_device *adev = smu->adev; 2033 uint32_t upper32 = 0, lower32 = 0; 2034 2035 /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */ 2036 if (smu->smc_fw_version < 0x3A5300 || 2037 amdgpu_ip_version(smu->adev, MP1_HWIP, 0) != IP_VERSION(11, 0, 7)) 2038 return; 2039 2040 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32)) 2041 goto out; 2042 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32)) 2043 goto out; 2044 2045out: 2046 2047 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 2048} 2049 2050static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) 2051{ 2052 uint32_t num_discrete_levels = 0; 2053 uint16_t *dpm_levels = NULL; 2054 uint16_t i = 0; 2055 struct smu_table_context *table_context = &smu->smu_table; 2056 DpmDescriptor_t *table_member1; 2057 uint16_t *table_member2; 2058 2059 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) 2060 return -EINVAL; 2061 2062 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1); 2063 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels; 2064 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2); 2065 dpm_levels = table_member2; 2066 2067 if (num_discrete_levels == 0 || dpm_levels == NULL) 2068 return -EINVAL; 2069 2070 *num_states = num_discrete_levels; 2071 for (i = 0; i < num_discrete_levels; i++) { 2072 /* convert to khz */ 2073 *clocks_in_khz = (*dpm_levels) * 1000; 2074 clocks_in_khz++; 2075 dpm_levels++; 2076 } 2077 2078 return 0; 2079} 2080 2081static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu, 2082 struct smu_temperature_range *range) 2083{ 2084 struct smu_table_context *table_context = &smu->smu_table; 2085 struct smu_11_0_7_powerplay_table *powerplay_table = 2086 table_context->power_play_table; 2087 uint16_t *table_member; 2088 uint16_t temp_edge, temp_hotspot, temp_mem; 2089 2090 if (!range) 2091 return -EINVAL; 2092 2093 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); 2094 2095 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member); 2096 temp_edge = table_member[TEMP_EDGE]; 2097 temp_hotspot = table_member[TEMP_HOTSPOT]; 2098 temp_mem = table_member[TEMP_MEM]; 2099 2100 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2101 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) * 2102 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2103 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2104 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) * 2105 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2106 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2107 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)* 2108 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2109 2110 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 2111 2112 return 0; 2113} 2114 2115static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu, 2116 bool disable_memory_clock_switch) 2117{ 2118 int ret = 0; 2119 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = 2120 (struct smu_11_0_max_sustainable_clocks *) 2121 smu->smu_table.max_sustainable_clocks; 2122 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; 2123 uint32_t max_memory_clock = max_sustainable_clocks->uclock; 2124 2125 if(smu->disable_uclk_switch == disable_memory_clock_switch) 2126 return 0; 2127 2128 if(disable_memory_clock_switch) 2129 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); 2130 else 2131 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); 2132 2133 if(!ret) 2134 smu->disable_uclk_switch = disable_memory_clock_switch; 2135 2136 return ret; 2137} 2138 2139static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu, 2140 uint8_t pcie_gen_cap, 2141 uint8_t pcie_width_cap) 2142{ 2143 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 2144 struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table; 2145 uint8_t *table_member1, *table_member2; 2146 uint8_t min_gen_speed, max_gen_speed; 2147 uint8_t min_lane_width, max_lane_width; 2148 uint32_t smu_pcie_arg; 2149 int ret = 0; 2150 int i; 2151 2152 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1); 2153 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2); 2154 2155 min_gen_speed = max_t(uint8_t, 0, table_member1[0]); 2156 max_gen_speed = min(pcie_gen_cap, table_member1[1]); 2157 min_gen_speed = min_gen_speed > max_gen_speed ? 2158 max_gen_speed : min_gen_speed; 2159 min_lane_width = max_t(uint8_t, 1, table_member2[0]); 2160 max_lane_width = min(pcie_width_cap, table_member2[1]); 2161 min_lane_width = min_lane_width > max_lane_width ? 2162 max_lane_width : min_lane_width; 2163 2164 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { 2165 pcie_table->pcie_gen[0] = max_gen_speed; 2166 pcie_table->pcie_lane[0] = max_lane_width; 2167 } else { 2168 pcie_table->pcie_gen[0] = min_gen_speed; 2169 pcie_table->pcie_lane[0] = min_lane_width; 2170 } 2171 pcie_table->pcie_gen[1] = max_gen_speed; 2172 pcie_table->pcie_lane[1] = max_lane_width; 2173 2174 for (i = 0; i < NUM_LINK_LEVELS; i++) { 2175 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK) || 2176 table_member1[i] > pcie_gen_cap || table_member2[i] > pcie_width_cap) { 2177 smu_pcie_arg = (i << 16 | 2178 pcie_table->pcie_gen[i] << 8 | 2179 pcie_table->pcie_lane[i]); 2180 2181 ret = smu_cmn_send_smc_msg_with_param(smu, 2182 SMU_MSG_OverridePcieParameters, 2183 smu_pcie_arg, 2184 NULL); 2185 if (ret) 2186 break; 2187 } 2188 } 2189 2190 return ret; 2191} 2192 2193static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu, 2194 enum smu_clk_type clk_type, 2195 uint32_t *min, uint32_t *max) 2196{ 2197 return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max); 2198} 2199 2200static void sienna_cichlid_dump_od_table(struct smu_context *smu, 2201 OverDriveTable_t *od_table) 2202{ 2203 struct amdgpu_device *adev = smu->adev; 2204 2205 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, 2206 od_table->GfxclkFmax); 2207 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin, 2208 od_table->UclkFmax); 2209 2210 if (!((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7)) && 2211 (smu->smc_fw_version < 0x003a2900))) 2212 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset); 2213} 2214 2215static int sienna_cichlid_set_default_od_settings(struct smu_context *smu) 2216{ 2217 OverDriveTable_t *od_table = 2218 (OverDriveTable_t *)smu->smu_table.overdrive_table; 2219 OverDriveTable_t *boot_od_table = 2220 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table; 2221 OverDriveTable_t *user_od_table = 2222 (OverDriveTable_t *)smu->smu_table.user_overdrive_table; 2223 OverDriveTable_t user_od_table_bak; 2224 int ret = 0; 2225 2226 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 2227 0, (void *)boot_od_table, false); 2228 if (ret) { 2229 dev_err(smu->adev->dev, "Failed to get overdrive table!\n"); 2230 return ret; 2231 } 2232 2233 sienna_cichlid_dump_od_table(smu, boot_od_table); 2234 2235 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t)); 2236 2237 /* 2238 * For S3/S4/Runpm resume, we need to setup those overdrive tables again, 2239 * but we have to preserve user defined values in "user_od_table". 2240 */ 2241 if (!smu->adev->in_suspend) { 2242 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t)); 2243 smu->user_dpm_profile.user_od = false; 2244 } else if (smu->user_dpm_profile.user_od) { 2245 memcpy(&user_od_table_bak, user_od_table, sizeof(OverDriveTable_t)); 2246 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t)); 2247 user_od_table->GfxclkFmin = user_od_table_bak.GfxclkFmin; 2248 user_od_table->GfxclkFmax = user_od_table_bak.GfxclkFmax; 2249 user_od_table->UclkFmin = user_od_table_bak.UclkFmin; 2250 user_od_table->UclkFmax = user_od_table_bak.UclkFmax; 2251 user_od_table->VddGfxOffset = user_od_table_bak.VddGfxOffset; 2252 } 2253 2254 return 0; 2255} 2256 2257static int sienna_cichlid_od_setting_check_range(struct smu_context *smu, 2258 struct smu_11_0_7_overdrive_table *od_table, 2259 enum SMU_11_0_7_ODSETTING_ID setting, 2260 uint32_t value) 2261{ 2262 if (value < od_table->min[setting]) { 2263 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", 2264 setting, value, od_table->min[setting]); 2265 return -EINVAL; 2266 } 2267 if (value > od_table->max[setting]) { 2268 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", 2269 setting, value, od_table->max[setting]); 2270 return -EINVAL; 2271 } 2272 2273 return 0; 2274} 2275 2276static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu, 2277 enum PP_OD_DPM_TABLE_COMMAND type, 2278 long input[], uint32_t size) 2279{ 2280 struct smu_table_context *table_context = &smu->smu_table; 2281 OverDriveTable_t *od_table = 2282 (OverDriveTable_t *)table_context->overdrive_table; 2283 struct smu_11_0_7_overdrive_table *od_settings = 2284 (struct smu_11_0_7_overdrive_table *)smu->od_settings; 2285 struct amdgpu_device *adev = smu->adev; 2286 enum SMU_11_0_7_ODSETTING_ID freq_setting; 2287 uint16_t *freq_ptr; 2288 int i, ret = 0; 2289 2290 if (!smu->od_enabled) { 2291 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n"); 2292 return -EINVAL; 2293 } 2294 2295 if (!smu->od_settings) { 2296 dev_err(smu->adev->dev, "OD board limits are not set!\n"); 2297 return -ENOENT; 2298 } 2299 2300 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { 2301 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n"); 2302 return -EINVAL; 2303 } 2304 2305 switch (type) { 2306 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2307 if (!sienna_cichlid_is_od_feature_supported(od_settings, 2308 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) { 2309 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n"); 2310 return -ENOTSUPP; 2311 } 2312 2313 for (i = 0; i < size; i += 2) { 2314 if (i + 2 > size) { 2315 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 2316 return -EINVAL; 2317 } 2318 2319 switch (input[i]) { 2320 case 0: 2321 if (input[i + 1] > od_table->GfxclkFmax) { 2322 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n", 2323 input[i + 1], od_table->GfxclkFmax); 2324 return -EINVAL; 2325 } 2326 2327 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN; 2328 freq_ptr = &od_table->GfxclkFmin; 2329 break; 2330 2331 case 1: 2332 if (input[i + 1] < od_table->GfxclkFmin) { 2333 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n", 2334 input[i + 1], od_table->GfxclkFmin); 2335 return -EINVAL; 2336 } 2337 2338 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX; 2339 freq_ptr = &od_table->GfxclkFmax; 2340 break; 2341 2342 default: 2343 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]); 2344 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2345 return -EINVAL; 2346 } 2347 2348 ret = sienna_cichlid_od_setting_check_range(smu, od_settings, 2349 freq_setting, input[i + 1]); 2350 if (ret) 2351 return ret; 2352 2353 *freq_ptr = (uint16_t)input[i + 1]; 2354 } 2355 break; 2356 2357 case PP_OD_EDIT_MCLK_VDDC_TABLE: 2358 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) { 2359 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n"); 2360 return -ENOTSUPP; 2361 } 2362 2363 for (i = 0; i < size; i += 2) { 2364 if (i + 2 > size) { 2365 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 2366 return -EINVAL; 2367 } 2368 2369 switch (input[i]) { 2370 case 0: 2371 if (input[i + 1] > od_table->UclkFmax) { 2372 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n", 2373 input[i + 1], od_table->UclkFmax); 2374 return -EINVAL; 2375 } 2376 2377 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN; 2378 freq_ptr = &od_table->UclkFmin; 2379 break; 2380 2381 case 1: 2382 if (input[i + 1] < od_table->UclkFmin) { 2383 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n", 2384 input[i + 1], od_table->UclkFmin); 2385 return -EINVAL; 2386 } 2387 2388 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX; 2389 freq_ptr = &od_table->UclkFmax; 2390 break; 2391 2392 default: 2393 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]); 2394 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2395 return -EINVAL; 2396 } 2397 2398 ret = sienna_cichlid_od_setting_check_range(smu, od_settings, 2399 freq_setting, input[i + 1]); 2400 if (ret) 2401 return ret; 2402 2403 *freq_ptr = (uint16_t)input[i + 1]; 2404 } 2405 break; 2406 2407 case PP_OD_RESTORE_DEFAULT_TABLE: 2408 memcpy(table_context->overdrive_table, 2409 table_context->boot_overdrive_table, 2410 sizeof(OverDriveTable_t)); 2411 fallthrough; 2412 2413 case PP_OD_COMMIT_DPM_TABLE: 2414 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) { 2415 sienna_cichlid_dump_od_table(smu, od_table); 2416 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true); 2417 if (ret) { 2418 dev_err(smu->adev->dev, "Failed to import overdrive table!\n"); 2419 return ret; 2420 } 2421 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t)); 2422 smu->user_dpm_profile.user_od = true; 2423 2424 if (!memcmp(table_context->user_overdrive_table, 2425 table_context->boot_overdrive_table, 2426 sizeof(OverDriveTable_t))) 2427 smu->user_dpm_profile.user_od = false; 2428 } 2429 break; 2430 2431 case PP_OD_EDIT_VDDGFX_OFFSET: 2432 if (size != 1) { 2433 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2434 return -EINVAL; 2435 } 2436 2437 /* 2438 * OD GFX Voltage Offset functionality is supported only by 58.41.0 2439 * and onwards SMU firmwares. 2440 */ 2441 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == 2442 IP_VERSION(11, 0, 7)) && 2443 (smu->smc_fw_version < 0x003a2900)) { 2444 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported " 2445 "only by 58.41.0 and onwards SMU firmwares!\n"); 2446 return -EOPNOTSUPP; 2447 } 2448 2449 od_table->VddGfxOffset = (int16_t)input[0]; 2450 2451 sienna_cichlid_dump_od_table(smu, od_table); 2452 break; 2453 2454 default: 2455 return -ENOSYS; 2456 } 2457 2458 return ret; 2459} 2460 2461static int sienna_cichlid_restore_user_od_settings(struct smu_context *smu) 2462{ 2463 struct smu_table_context *table_context = &smu->smu_table; 2464 OverDriveTable_t *od_table = table_context->overdrive_table; 2465 OverDriveTable_t *user_od_table = table_context->user_overdrive_table; 2466 int res; 2467 2468 res = smu_v11_0_restore_user_od_settings(smu); 2469 if (res == 0) 2470 memcpy(od_table, user_od_table, sizeof(OverDriveTable_t)); 2471 2472 return res; 2473} 2474 2475static int sienna_cichlid_run_btc(struct smu_context *smu) 2476{ 2477 int res; 2478 2479 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 2480 if (res) 2481 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 2482 2483 return res; 2484} 2485 2486static int sienna_cichlid_baco_enter(struct smu_context *smu) 2487{ 2488 struct amdgpu_device *adev = smu->adev; 2489 2490 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) 2491 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); 2492 else 2493 return smu_v11_0_baco_enter(smu); 2494} 2495 2496static int sienna_cichlid_baco_exit(struct smu_context *smu) 2497{ 2498 struct amdgpu_device *adev = smu->adev; 2499 2500 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) { 2501 /* Wait for PMFW handling for the Dstate change */ 2502 msleep(10); 2503 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); 2504 } else { 2505 return smu_v11_0_baco_exit(smu); 2506 } 2507} 2508 2509static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu) 2510{ 2511 struct amdgpu_device *adev = smu->adev; 2512 uint32_t val; 2513 uint32_t smu_version; 2514 int ret; 2515 2516 /** 2517 * SRIOV env will not support SMU mode1 reset 2518 * PM FW support mode1 reset from 58.26 2519 */ 2520 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 2521 if (ret) 2522 return false; 2523 2524 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00)) 2525 return false; 2526 2527 /** 2528 * mode1 reset relies on PSP, so we should check if 2529 * PSP is alive. 2530 */ 2531 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 2532 return val != 0x0; 2533} 2534 2535static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap, 2536 struct i2c_msg *msg, int num_msgs) 2537{ 2538 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 2539 struct amdgpu_device *adev = smu_i2c->adev; 2540 struct smu_context *smu = adev->powerplay.pp_handle; 2541 struct smu_table_context *smu_table = &smu->smu_table; 2542 struct smu_table *table = &smu_table->driver_table; 2543 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 2544 int i, j, r, c; 2545 u16 dir; 2546 2547 if (!adev->pm.dpm_enabled) 2548 return -EBUSY; 2549 2550 req = kzalloc(sizeof(*req), GFP_KERNEL); 2551 if (!req) 2552 return -ENOMEM; 2553 2554 req->I2CcontrollerPort = smu_i2c->port; 2555 req->I2CSpeed = I2C_SPEED_FAST_400K; 2556 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 2557 dir = msg[0].flags & I2C_M_RD; 2558 2559 for (c = i = 0; i < num_msgs; i++) { 2560 for (j = 0; j < msg[i].len; j++, c++) { 2561 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 2562 2563 if (!(msg[i].flags & I2C_M_RD)) { 2564 /* write */ 2565 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK; 2566 cmd->ReadWriteData = msg[i].buf[j]; 2567 } 2568 2569 if ((dir ^ msg[i].flags) & I2C_M_RD) { 2570 /* The direction changes. 2571 */ 2572 dir = msg[i].flags & I2C_M_RD; 2573 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 2574 } 2575 2576 req->NumCmds++; 2577 2578 /* 2579 * Insert STOP if we are at the last byte of either last 2580 * message for the transaction or the client explicitly 2581 * requires a STOP at this particular message. 2582 */ 2583 if ((j == msg[i].len - 1) && 2584 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 2585 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 2586 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 2587 } 2588 } 2589 } 2590 mutex_lock(&adev->pm.mutex); 2591 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 2592 if (r) 2593 goto fail; 2594 2595 for (c = i = 0; i < num_msgs; i++) { 2596 if (!(msg[i].flags & I2C_M_RD)) { 2597 c += msg[i].len; 2598 continue; 2599 } 2600 for (j = 0; j < msg[i].len; j++, c++) { 2601 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 2602 2603 msg[i].buf[j] = cmd->ReadWriteData; 2604 } 2605 } 2606 r = num_msgs; 2607fail: 2608 mutex_unlock(&adev->pm.mutex); 2609 kfree(req); 2610 return r; 2611} 2612 2613static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap) 2614{ 2615 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 2616} 2617 2618 2619static const struct i2c_algorithm sienna_cichlid_i2c_algo = { 2620 .master_xfer = sienna_cichlid_i2c_xfer, 2621 .functionality = sienna_cichlid_i2c_func, 2622}; 2623 2624static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = { 2625 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 2626 .max_read_len = MAX_SW_I2C_COMMANDS, 2627 .max_write_len = MAX_SW_I2C_COMMANDS, 2628 .max_comb_1st_msg_len = 2, 2629 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 2630}; 2631 2632static int sienna_cichlid_i2c_control_init(struct smu_context *smu) 2633{ 2634 struct amdgpu_device *adev = smu->adev; 2635 int res, i; 2636 2637 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 2638 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 2639 struct i2c_adapter *control = &smu_i2c->adapter; 2640 2641 smu_i2c->adev = adev; 2642 smu_i2c->port = i; 2643 mutex_init(&smu_i2c->mutex); 2644 control->owner = THIS_MODULE; 2645 control->class = I2C_CLASS_HWMON; 2646 control->dev.parent = &adev->pdev->dev; 2647 control->algo = &sienna_cichlid_i2c_algo; 2648 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); 2649 control->quirks = &sienna_cichlid_i2c_control_quirks; 2650 i2c_set_adapdata(control, smu_i2c); 2651 2652 res = devm_i2c_add_adapter(adev->dev, control); 2653 if (res) { 2654 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 2655 return res; 2656 } 2657 } 2658 /* assign the buses used for the FRU EEPROM and RAS EEPROM */ 2659 /* XXX ideally this would be something in a vbios data table */ 2660 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; 2661 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 2662 2663 return 0; 2664} 2665 2666static void sienna_cichlid_i2c_control_fini(struct smu_context *smu) 2667{ 2668 struct amdgpu_device *adev = smu->adev; 2669 2670 adev->pm.ras_eeprom_i2c_bus = NULL; 2671 adev->pm.fru_eeprom_i2c_bus = NULL; 2672} 2673 2674static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, 2675 void **table) 2676{ 2677 struct smu_table_context *smu_table = &smu->smu_table; 2678 struct gpu_metrics_v1_3 *gpu_metrics = 2679 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 2680 SmuMetricsExternal_t metrics_external; 2681 SmuMetrics_t *metrics = 2682 &(metrics_external.SmuMetrics); 2683 SmuMetrics_V2_t *metrics_v2 = 2684 &(metrics_external.SmuMetrics_V2); 2685 SmuMetrics_V3_t *metrics_v3 = 2686 &(metrics_external.SmuMetrics_V3); 2687 struct amdgpu_device *adev = smu->adev; 2688 bool use_metrics_v2 = false; 2689 bool use_metrics_v3 = false; 2690 uint16_t average_gfx_activity; 2691 int ret = 0; 2692 2693 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) { 2694 case IP_VERSION(11, 0, 7): 2695 if (smu->smc_fw_version >= 0x3A4900) 2696 use_metrics_v3 = true; 2697 else if (smu->smc_fw_version >= 0x3A4300) 2698 use_metrics_v2 = true; 2699 break; 2700 case IP_VERSION(11, 0, 11): 2701 if (smu->smc_fw_version >= 0x412D00) 2702 use_metrics_v2 = true; 2703 break; 2704 case IP_VERSION(11, 0, 12): 2705 if (smu->smc_fw_version >= 0x3B2300) 2706 use_metrics_v2 = true; 2707 break; 2708 case IP_VERSION(11, 0, 13): 2709 if (smu->smc_fw_version >= 0x491100) 2710 use_metrics_v2 = true; 2711 break; 2712 default: 2713 break; 2714 } 2715 2716 ret = smu_cmn_get_metrics_table(smu, 2717 &metrics_external, 2718 true); 2719 if (ret) 2720 return ret; 2721 2722 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 2723 2724 gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge : 2725 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge; 2726 gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot : 2727 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot; 2728 gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem : 2729 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem; 2730 gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx : 2731 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx; 2732 gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc : 2733 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc; 2734 gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 : 2735 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0; 2736 2737 gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 2738 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity; 2739 gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity : 2740 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity; 2741 gpu_metrics->average_mm_activity = use_metrics_v3 ? 2742 (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 : 2743 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage; 2744 2745 gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower : 2746 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower; 2747 gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator : 2748 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator; 2749 2750 if (metrics->CurrGfxVoltageOffset) 2751 gpu_metrics->voltage_gfx = 2752 (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100; 2753 if (metrics->CurrMemVidOffset) 2754 gpu_metrics->voltage_mem = 2755 (155000 - 625 * metrics->CurrMemVidOffset) / 100; 2756 if (metrics->CurrSocVoltageOffset) 2757 gpu_metrics->voltage_soc = 2758 (155000 - 625 * metrics->CurrSocVoltageOffset) / 100; 2759 2760 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 2761 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity; 2762 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD) 2763 gpu_metrics->average_gfxclk_frequency = 2764 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs : 2765 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : 2766 metrics->AverageGfxclkFrequencyPostDs; 2767 else 2768 gpu_metrics->average_gfxclk_frequency = 2769 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs : 2770 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : 2771 metrics->AverageGfxclkFrequencyPreDs; 2772 2773 gpu_metrics->average_uclk_frequency = 2774 use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs : 2775 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : 2776 metrics->AverageUclkFrequencyPostDs; 2777 gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency : 2778 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency; 2779 gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency : 2780 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency; 2781 gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency : 2782 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency; 2783 gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency : 2784 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency; 2785 2786 gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] : 2787 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK]; 2788 gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] : 2789 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK]; 2790 gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] : 2791 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK]; 2792 gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] : 2793 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0]; 2794 gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] : 2795 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0]; 2796 gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] : 2797 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1]; 2798 gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] : 2799 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1]; 2800 2801 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2); 2802 gpu_metrics->indep_throttle_status = 2803 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status, 2804 sienna_cichlid_throttler_map); 2805 2806 gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed : 2807 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed; 2808 2809 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7)) && 2810 smu->smc_fw_version > 0x003A1E00) || 2811 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 11)) && 2812 smu->smc_fw_version > 0x00410400)) { 2813 gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth : 2814 use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth; 2815 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate : 2816 use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate]; 2817 } else { 2818 gpu_metrics->pcie_link_width = 2819 smu_v11_0_get_current_pcie_link_width(smu); 2820 gpu_metrics->pcie_link_speed = 2821 smu_v11_0_get_current_pcie_link_speed(smu); 2822 } 2823 2824 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2825 2826 *table = (void *)gpu_metrics; 2827 2828 return sizeof(struct gpu_metrics_v1_3); 2829} 2830 2831static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu) 2832{ 2833 int ret = 0; 2834 2835 if (smu->smc_fw_version < SUPPORT_ECCTABLE_SMU_VERSION) 2836 ret = -EOPNOTSUPP; 2837 2838 return ret; 2839} 2840 2841static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu, 2842 void *table) 2843{ 2844 struct smu_table_context *smu_table = &smu->smu_table; 2845 EccInfoTable_t *ecc_table = NULL; 2846 struct ecc_info_per_ch *ecc_info_per_channel = NULL; 2847 int i, ret = 0; 2848 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table; 2849 2850 ret = sienna_cichlid_check_ecc_table_support(smu); 2851 if (ret) 2852 return ret; 2853 2854 ret = smu_cmn_update_table(smu, 2855 SMU_TABLE_ECCINFO, 2856 0, 2857 smu_table->ecc_table, 2858 false); 2859 if (ret) { 2860 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n"); 2861 return ret; 2862 } 2863 2864 ecc_table = (EccInfoTable_t *)smu_table->ecc_table; 2865 2866 for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) { 2867 ecc_info_per_channel = &(eccinfo->ecc[i]); 2868 ecc_info_per_channel->ce_count_lo_chip = 2869 ecc_table->EccInfo[i].ce_count_lo_chip; 2870 ecc_info_per_channel->ce_count_hi_chip = 2871 ecc_table->EccInfo[i].ce_count_hi_chip; 2872 ecc_info_per_channel->mca_umc_status = 2873 ecc_table->EccInfo[i].mca_umc_status; 2874 ecc_info_per_channel->mca_umc_addr = 2875 ecc_table->EccInfo[i].mca_umc_addr; 2876 } 2877 2878 return ret; 2879} 2880static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu) 2881{ 2882 uint16_t *mgpu_fan_boost_limit_rpm; 2883 2884 GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm); 2885 /* 2886 * Skip the MGpuFanBoost setting for those ASICs 2887 * which do not support it 2888 */ 2889 if (*mgpu_fan_boost_limit_rpm == 0) 2890 return 0; 2891 2892 return smu_cmn_send_smc_msg_with_param(smu, 2893 SMU_MSG_SetMGpuFanBoostLimitRpm, 2894 0, 2895 NULL); 2896} 2897 2898static int sienna_cichlid_gpo_control(struct smu_context *smu, 2899 bool enablement) 2900{ 2901 int ret = 0; 2902 2903 2904 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) { 2905 2906 if (enablement) { 2907 if (smu->smc_fw_version < 0x003a2500) { 2908 ret = smu_cmn_send_smc_msg_with_param(smu, 2909 SMU_MSG_SetGpoFeaturePMask, 2910 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK, 2911 NULL); 2912 } else { 2913 ret = smu_cmn_send_smc_msg_with_param(smu, 2914 SMU_MSG_DisallowGpo, 2915 0, 2916 NULL); 2917 } 2918 } else { 2919 if (smu->smc_fw_version < 0x003a2500) { 2920 ret = smu_cmn_send_smc_msg_with_param(smu, 2921 SMU_MSG_SetGpoFeaturePMask, 2922 0, 2923 NULL); 2924 } else { 2925 ret = smu_cmn_send_smc_msg_with_param(smu, 2926 SMU_MSG_DisallowGpo, 2927 1, 2928 NULL); 2929 } 2930 } 2931 } 2932 2933 return ret; 2934} 2935 2936static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu) 2937{ 2938 /* 2939 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45 2940 * onwards PMFWs. 2941 */ 2942 if (smu->smc_fw_version < 0x003A2D00) 2943 return 0; 2944 2945 return smu_cmn_send_smc_msg_with_param(smu, 2946 SMU_MSG_Enable2ndUSB20Port, 2947 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ? 2948 1 : 0, 2949 NULL); 2950} 2951 2952static int sienna_cichlid_system_features_control(struct smu_context *smu, 2953 bool en) 2954{ 2955 int ret = 0; 2956 2957 if (en) { 2958 ret = sienna_cichlid_notify_2nd_usb20_port(smu); 2959 if (ret) 2960 return ret; 2961 } 2962 2963 return smu_v11_0_system_features_control(smu, en); 2964} 2965 2966static int sienna_cichlid_set_mp1_state(struct smu_context *smu, 2967 enum pp_mp1_state mp1_state) 2968{ 2969 int ret; 2970 2971 switch (mp1_state) { 2972 case PP_MP1_STATE_UNLOAD: 2973 ret = smu_cmn_set_mp1_state(smu, mp1_state); 2974 break; 2975 default: 2976 /* Ignore others */ 2977 ret = 0; 2978 } 2979 2980 return ret; 2981} 2982 2983static void sienna_cichlid_stb_init(struct smu_context *smu) 2984{ 2985 struct amdgpu_device *adev = smu->adev; 2986 uint32_t reg; 2987 2988 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START); 2989 smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE); 2990 2991 /* STB is disabled */ 2992 if (!smu->stb_context.enabled) 2993 return; 2994 2995 spin_lock_init(&smu->stb_context.lock); 2996 2997 /* STB buffer size in bytes as function of FIFO depth */ 2998 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO); 2999 smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH); 3000 smu->stb_context.stb_buf_size *= SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES; 3001 3002 dev_info(smu->adev->dev, "STB initialized to %d entries", 3003 smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES); 3004 3005} 3006 3007static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu, 3008 struct config_table_setting *table) 3009{ 3010 struct amdgpu_device *adev = smu->adev; 3011 3012 if (!table) 3013 return -EINVAL; 3014 3015 table->gfxclk_average_tau = 10; 3016 table->socclk_average_tau = 10; 3017 table->fclk_average_tau = 10; 3018 table->uclk_average_tau = 10; 3019 table->gfx_activity_average_tau = 10; 3020 table->mem_activity_average_tau = 10; 3021 table->socket_power_average_tau = 100; 3022 if (amdgpu_ip_version(adev, MP1_HWIP, 0) != IP_VERSION(11, 0, 7)) 3023 table->apu_socket_power_average_tau = 100; 3024 3025 return 0; 3026} 3027 3028static int sienna_cichlid_set_config_table(struct smu_context *smu, 3029 struct config_table_setting *table) 3030{ 3031 DriverSmuConfigExternal_t driver_smu_config_table; 3032 3033 if (!table) 3034 return -EINVAL; 3035 3036 memset(&driver_smu_config_table, 3037 0, 3038 sizeof(driver_smu_config_table)); 3039 driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau = 3040 table->gfxclk_average_tau; 3041 driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau = 3042 table->fclk_average_tau; 3043 driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau = 3044 table->uclk_average_tau; 3045 driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau = 3046 table->gfx_activity_average_tau; 3047 driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau = 3048 table->mem_activity_average_tau; 3049 driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau = 3050 table->socket_power_average_tau; 3051 3052 return smu_cmn_update_table(smu, 3053 SMU_TABLE_DRIVER_SMU_CONFIG, 3054 0, 3055 (void *)&driver_smu_config_table, 3056 true); 3057} 3058 3059static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu, 3060 void *buf, 3061 uint32_t size) 3062{ 3063 uint32_t *p = buf; 3064 struct amdgpu_device *adev = smu->adev; 3065 3066 /* No need to disable interrupts for now as we don't lock it yet from ISR */ 3067 spin_lock(&smu->stb_context.lock); 3068 3069 /* 3070 * Read the STB FIFO in units of 32bit since this is the accessor window 3071 * (register width) we have. 3072 */ 3073 buf = ((char *) buf) + size; 3074 while ((void *)p < buf) 3075 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3)); 3076 3077 spin_unlock(&smu->stb_context.lock); 3078 3079 return 0; 3080} 3081 3082static int sienna_cichlid_mode2_reset(struct smu_context *smu) 3083{ 3084 int ret = 0, index; 3085 struct amdgpu_device *adev = smu->adev; 3086 int timeout = 100; 3087 3088 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 3089 SMU_MSG_DriverMode2Reset); 3090 3091 mutex_lock(&smu->message_lock); 3092 3093 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, 3094 SMU_RESET_MODE_2); 3095 3096 ret = smu_cmn_wait_for_response(smu); 3097 while (ret != 0 && timeout) { 3098 ret = smu_cmn_wait_for_response(smu); 3099 /* Wait a bit more time for getting ACK */ 3100 if (ret != 0) { 3101 --timeout; 3102 usleep_range(500, 1000); 3103 continue; 3104 } else { 3105 break; 3106 } 3107 } 3108 3109 if (!timeout) { 3110 dev_err(adev->dev, 3111 "failed to send mode2 message \tparam: 0x%08x response %#x\n", 3112 SMU_RESET_MODE_2, ret); 3113 goto out; 3114 } 3115 3116 dev_info(smu->adev->dev, "restore config space...\n"); 3117 /* Restore the config space saved during init */ 3118 amdgpu_device_load_pci_state(adev->pdev); 3119out: 3120 mutex_unlock(&smu->message_lock); 3121 3122 return ret; 3123} 3124 3125static const struct pptable_funcs sienna_cichlid_ppt_funcs = { 3126 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask, 3127 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table, 3128 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable, 3129 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable, 3130 .i2c_init = sienna_cichlid_i2c_control_init, 3131 .i2c_fini = sienna_cichlid_i2c_control_fini, 3132 .print_clk_levels = sienna_cichlid_print_clk_levels, 3133 .force_clk_levels = sienna_cichlid_force_clk_levels, 3134 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk, 3135 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed, 3136 .display_config_changed = sienna_cichlid_display_config_changed, 3137 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config, 3138 .is_dpm_running = sienna_cichlid_is_dpm_running, 3139 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm, 3140 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm, 3141 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode, 3142 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode, 3143 .set_watermarks_table = sienna_cichlid_set_watermarks_table, 3144 .read_sensor = sienna_cichlid_read_sensor, 3145 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states, 3146 .set_performance_level = smu_v11_0_set_performance_level, 3147 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range, 3148 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch, 3149 .get_power_limit = sienna_cichlid_get_power_limit, 3150 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters, 3151 .init_microcode = smu_v11_0_init_microcode, 3152 .load_microcode = smu_v11_0_load_microcode, 3153 .fini_microcode = smu_v11_0_fini_microcode, 3154 .init_smc_tables = sienna_cichlid_init_smc_tables, 3155 .fini_smc_tables = smu_v11_0_fini_smc_tables, 3156 .init_power = smu_v11_0_init_power, 3157 .fini_power = smu_v11_0_fini_power, 3158 .check_fw_status = smu_v11_0_check_fw_status, 3159 .setup_pptable = sienna_cichlid_setup_pptable, 3160 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 3161 .check_fw_version = smu_v11_0_check_fw_version, 3162 .write_pptable = smu_cmn_write_pptable, 3163 .set_driver_table_location = smu_v11_0_set_driver_table_location, 3164 .set_tool_table_location = smu_v11_0_set_tool_table_location, 3165 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 3166 .system_features_control = sienna_cichlid_system_features_control, 3167 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 3168 .send_smc_msg = smu_cmn_send_smc_msg, 3169 .init_display_count = NULL, 3170 .set_allowed_mask = smu_v11_0_set_allowed_mask, 3171 .get_enabled_mask = smu_cmn_get_enabled_mask, 3172 .feature_is_enabled = smu_cmn_feature_is_enabled, 3173 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 3174 .notify_display_change = NULL, 3175 .set_power_limit = smu_v11_0_set_power_limit, 3176 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, 3177 .enable_thermal_alert = smu_v11_0_enable_thermal_alert, 3178 .disable_thermal_alert = smu_v11_0_disable_thermal_alert, 3179 .set_min_dcef_deep_sleep = NULL, 3180 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, 3181 .get_fan_control_mode = smu_v11_0_get_fan_control_mode, 3182 .set_fan_control_mode = smu_v11_0_set_fan_control_mode, 3183 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm, 3184 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm, 3185 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, 3186 .gfx_off_control = smu_v11_0_gfx_off_control, 3187 .register_irq_handler = smu_v11_0_register_irq_handler, 3188 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, 3189 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, 3190 .get_bamaco_support = smu_v11_0_get_bamaco_support, 3191 .baco_enter = sienna_cichlid_baco_enter, 3192 .baco_exit = sienna_cichlid_baco_exit, 3193 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported, 3194 .mode1_reset = smu_v11_0_mode1_reset, 3195 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq, 3196 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, 3197 .set_default_od_settings = sienna_cichlid_set_default_od_settings, 3198 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table, 3199 .restore_user_od_settings = sienna_cichlid_restore_user_od_settings, 3200 .run_btc = sienna_cichlid_run_btc, 3201 .set_power_source = smu_v11_0_set_power_source, 3202 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 3203 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 3204 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics, 3205 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost, 3206 .gfx_ulv_control = smu_v11_0_gfx_ulv_control, 3207 .deep_sleep_control = smu_v11_0_deep_sleep_control, 3208 .get_fan_parameters = sienna_cichlid_get_fan_parameters, 3209 .interrupt_work = smu_v11_0_interrupt_work, 3210 .gpo_control = sienna_cichlid_gpo_control, 3211 .set_mp1_state = sienna_cichlid_set_mp1_state, 3212 .stb_collect_info = sienna_cichlid_stb_get_data_direct, 3213 .get_ecc_info = sienna_cichlid_get_ecc_info, 3214 .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings, 3215 .set_config_table = sienna_cichlid_set_config_table, 3216 .get_unique_id = sienna_cichlid_get_unique_id, 3217 .mode2_reset = sienna_cichlid_mode2_reset, 3218}; 3219 3220void sienna_cichlid_set_ppt_funcs(struct smu_context *smu) 3221{ 3222 smu->ppt_funcs = &sienna_cichlid_ppt_funcs; 3223 smu->message_map = sienna_cichlid_message_map; 3224 smu->clock_map = sienna_cichlid_clk_map; 3225 smu->feature_map = sienna_cichlid_feature_mask_map; 3226 smu->table_map = sienna_cichlid_table_map; 3227 smu->pwr_src_map = sienna_cichlid_pwr_src_map; 3228 smu->workload_map = sienna_cichlid_workload_map; 3229 smu_v11_0_set_smu_mailbox_registers(smu); 3230}
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