arcturus_ppt.c

   1/*
   2 * Copyright 2019 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#define SWSMU_CODE_LAYER_L2
  25
  26#include <linux/firmware.h>
  27#include "amdgpu.h"
  28#include "amdgpu_dpm.h"
  29#include "amdgpu_smu.h"
  30#include "atomfirmware.h"
  31#include "amdgpu_atomfirmware.h"
  32#include "amdgpu_atombios.h"
  33#include "smu_v11_0.h"
  34#include "smu11_driver_if_arcturus.h"
  35#include "soc15_common.h"
  36#include "atom.h"
  37#include "arcturus_ppt.h"
  38#include "smu_v11_0_pptable.h"
  39#include "arcturus_ppsmc.h"
  40#include "nbio/nbio_7_4_offset.h"
  41#include "nbio/nbio_7_4_sh_mask.h"
  42#include "thm/thm_11_0_2_offset.h"
  43#include "thm/thm_11_0_2_sh_mask.h"
  44#include "amdgpu_xgmi.h"
  45#include <linux/i2c.h>
  46#include <linux/pci.h>
  47#include "amdgpu_ras.h"
  48#include "smu_cmn.h"
  49
  50/*
  51 * DO NOT use these for err/warn/info/debug messages.
  52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53 * They are more MGPU friendly.
  54 */
  55#undef pr_err
  56#undef pr_warn
  57#undef pr_info
  58#undef pr_debug
  59
  60#define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
  61	[smu_feature] = {1, (arcturus_feature)}
  62
  63#define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  64#define SMU_FEATURES_LOW_SHIFT       0
  65#define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  66#define SMU_FEATURES_HIGH_SHIFT      32
  67
  68#define SMC_DPM_FEATURE ( \
  69	FEATURE_DPM_PREFETCHER_MASK | \
  70	FEATURE_DPM_GFXCLK_MASK | \
  71	FEATURE_DPM_UCLK_MASK | \
  72	FEATURE_DPM_SOCCLK_MASK | \
  73	FEATURE_DPM_MP0CLK_MASK | \
  74	FEATURE_DPM_FCLK_MASK | \
  75	FEATURE_DPM_XGMI_MASK)
  76
  77/* possible frequency drift (1Mhz) */
  78#define EPSILON				1
  79
  80#define smnPCIE_ESM_CTRL			0x111003D0
  81
  82#define mmCG_FDO_CTRL0_ARCT			0x8B
  83#define mmCG_FDO_CTRL0_ARCT_BASE_IDX		0
  84
  85#define mmCG_FDO_CTRL1_ARCT			0x8C
  86#define mmCG_FDO_CTRL1_ARCT_BASE_IDX		0
  87
  88#define mmCG_FDO_CTRL2_ARCT			0x8D
  89#define mmCG_FDO_CTRL2_ARCT_BASE_IDX		0
  90
  91#define mmCG_TACH_CTRL_ARCT			0x8E
  92#define mmCG_TACH_CTRL_ARCT_BASE_IDX		0
  93
  94#define mmCG_TACH_STATUS_ARCT			0x8F
  95#define mmCG_TACH_STATUS_ARCT_BASE_IDX		0
  96
  97#define mmCG_THERMAL_STATUS_ARCT		0x90
  98#define mmCG_THERMAL_STATUS_ARCT_BASE_IDX	0
  99
 100static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
 101	MSG_MAP(TestMessage,			     PPSMC_MSG_TestMessage,			0),
 102	MSG_MAP(GetSmuVersion,			     PPSMC_MSG_GetSmuVersion,			1),
 103	MSG_MAP(GetDriverIfVersion,		     PPSMC_MSG_GetDriverIfVersion,		1),
 104	MSG_MAP(SetAllowedFeaturesMaskLow,	     PPSMC_MSG_SetAllowedFeaturesMaskLow,	0),
 105	MSG_MAP(SetAllowedFeaturesMaskHigh,	     PPSMC_MSG_SetAllowedFeaturesMaskHigh,	0),
 106	MSG_MAP(EnableAllSmuFeatures,		     PPSMC_MSG_EnableAllSmuFeatures,		0),
 107	MSG_MAP(DisableAllSmuFeatures,		     PPSMC_MSG_DisableAllSmuFeatures,		0),
 108	MSG_MAP(EnableSmuFeaturesLow,		     PPSMC_MSG_EnableSmuFeaturesLow,		1),
 109	MSG_MAP(EnableSmuFeaturesHigh,		     PPSMC_MSG_EnableSmuFeaturesHigh,		1),
 110	MSG_MAP(DisableSmuFeaturesLow,		     PPSMC_MSG_DisableSmuFeaturesLow,		0),
 111	MSG_MAP(DisableSmuFeaturesHigh,		     PPSMC_MSG_DisableSmuFeaturesHigh,		0),
 112	MSG_MAP(GetEnabledSmuFeaturesLow,	     PPSMC_MSG_GetEnabledSmuFeaturesLow,	0),
 113	MSG_MAP(GetEnabledSmuFeaturesHigh,	     PPSMC_MSG_GetEnabledSmuFeaturesHigh,	0),
 114	MSG_MAP(SetDriverDramAddrHigh,		     PPSMC_MSG_SetDriverDramAddrHigh,		1),
 115	MSG_MAP(SetDriverDramAddrLow,		     PPSMC_MSG_SetDriverDramAddrLow,		1),
 116	MSG_MAP(SetToolsDramAddrHigh,		     PPSMC_MSG_SetToolsDramAddrHigh,		0),
 117	MSG_MAP(SetToolsDramAddrLow,		     PPSMC_MSG_SetToolsDramAddrLow,		0),
 118	MSG_MAP(TransferTableSmu2Dram,		     PPSMC_MSG_TransferTableSmu2Dram,		1),
 119	MSG_MAP(TransferTableDram2Smu,		     PPSMC_MSG_TransferTableDram2Smu,		0),
 120	MSG_MAP(UseDefaultPPTable,		     PPSMC_MSG_UseDefaultPPTable,		0),
 121	MSG_MAP(UseBackupPPTable,		     PPSMC_MSG_UseBackupPPTable,		0),
 122	MSG_MAP(SetSystemVirtualDramAddrHigh,	     PPSMC_MSG_SetSystemVirtualDramAddrHigh,	0),
 123	MSG_MAP(SetSystemVirtualDramAddrLow,	     PPSMC_MSG_SetSystemVirtualDramAddrLow,	0),
 124	MSG_MAP(EnterBaco,			     PPSMC_MSG_EnterBaco,			0),
 125	MSG_MAP(ExitBaco,			     PPSMC_MSG_ExitBaco,			0),
 126	MSG_MAP(ArmD3,				     PPSMC_MSG_ArmD3,				0),
 127	MSG_MAP(SetSoftMinByFreq,		     PPSMC_MSG_SetSoftMinByFreq,		0),
 128	MSG_MAP(SetSoftMaxByFreq,		     PPSMC_MSG_SetSoftMaxByFreq,		0),
 129	MSG_MAP(SetHardMinByFreq,		     PPSMC_MSG_SetHardMinByFreq,		0),
 130	MSG_MAP(SetHardMaxByFreq,		     PPSMC_MSG_SetHardMaxByFreq,		0),
 131	MSG_MAP(GetMinDpmFreq,			     PPSMC_MSG_GetMinDpmFreq,			0),
 132	MSG_MAP(GetMaxDpmFreq,			     PPSMC_MSG_GetMaxDpmFreq,			0),
 133	MSG_MAP(GetDpmFreqByIndex,		     PPSMC_MSG_GetDpmFreqByIndex,		1),
 134	MSG_MAP(SetWorkloadMask,		     PPSMC_MSG_SetWorkloadMask,			1),
 135	MSG_MAP(SetDfSwitchType,		     PPSMC_MSG_SetDfSwitchType,			0),
 136	MSG_MAP(GetVoltageByDpm,		     PPSMC_MSG_GetVoltageByDpm,			0),
 137	MSG_MAP(GetVoltageByDpmOverdrive,	     PPSMC_MSG_GetVoltageByDpmOverdrive,	0),
 138	MSG_MAP(SetPptLimit,			     PPSMC_MSG_SetPptLimit,			0),
 139	MSG_MAP(GetPptLimit,			     PPSMC_MSG_GetPptLimit,			1),
 140	MSG_MAP(PowerUpVcn0,			     PPSMC_MSG_PowerUpVcn0,			0),
 141	MSG_MAP(PowerDownVcn0,			     PPSMC_MSG_PowerDownVcn0,			0),
 142	MSG_MAP(PowerUpVcn1,			     PPSMC_MSG_PowerUpVcn1,			0),
 143	MSG_MAP(PowerDownVcn1,			     PPSMC_MSG_PowerDownVcn1,			0),
 144	MSG_MAP(PrepareMp1ForUnload,		     PPSMC_MSG_PrepareMp1ForUnload,		0),
 145	MSG_MAP(PrepareMp1ForReset,		     PPSMC_MSG_PrepareMp1ForReset,		0),
 146	MSG_MAP(PrepareMp1ForShutdown,		     PPSMC_MSG_PrepareMp1ForShutdown,		0),
 147	MSG_MAP(SoftReset,			     PPSMC_MSG_SoftReset,			0),
 148	MSG_MAP(RunAfllBtc,			     PPSMC_MSG_RunAfllBtc,			0),
 149	MSG_MAP(RunDcBtc,			     PPSMC_MSG_RunDcBtc,			0),
 150	MSG_MAP(DramLogSetDramAddrHigh,		     PPSMC_MSG_DramLogSetDramAddrHigh,		0),
 151	MSG_MAP(DramLogSetDramAddrLow,		     PPSMC_MSG_DramLogSetDramAddrLow,		0),
 152	MSG_MAP(DramLogSetDramSize,		     PPSMC_MSG_DramLogSetDramSize,		0),
 153	MSG_MAP(GetDebugData,			     PPSMC_MSG_GetDebugData,			0),
 154	MSG_MAP(WaflTest,			     PPSMC_MSG_WaflTest,			0),
 155	MSG_MAP(SetXgmiMode,			     PPSMC_MSG_SetXgmiMode,			0),
 156	MSG_MAP(SetMemoryChannelEnable,		     PPSMC_MSG_SetMemoryChannelEnable,		0),
 157	MSG_MAP(DFCstateControl,		     PPSMC_MSG_DFCstateControl,			0),
 158	MSG_MAP(GmiPwrDnControl,		     PPSMC_MSG_GmiPwrDnControl,			0),
 159	MSG_MAP(ReadSerialNumTop32,		     PPSMC_MSG_ReadSerialNumTop32,		1),
 160	MSG_MAP(ReadSerialNumBottom32,		     PPSMC_MSG_ReadSerialNumBottom32,		1),
 161	MSG_MAP(LightSBR,			     PPSMC_MSG_LightSBR,			0),
 162};
 163
 164static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
 165	CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 166	CLK_MAP(SCLK,	PPCLK_GFXCLK),
 167	CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 168	CLK_MAP(FCLK, PPCLK_FCLK),
 169	CLK_MAP(UCLK, PPCLK_UCLK),
 170	CLK_MAP(MCLK, PPCLK_UCLK),
 171	CLK_MAP(DCLK, PPCLK_DCLK),
 172	CLK_MAP(VCLK, PPCLK_VCLK),
 173};
 174
 175static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
 176	FEA_MAP(DPM_PREFETCHER),
 177	FEA_MAP(DPM_GFXCLK),
 178	FEA_MAP(DPM_UCLK),
 179	FEA_MAP(DPM_SOCCLK),
 180	FEA_MAP(DPM_FCLK),
 181	FEA_MAP(DPM_MP0CLK),
 182	FEA_MAP(DPM_XGMI),
 183	FEA_MAP(DS_GFXCLK),
 184	FEA_MAP(DS_SOCCLK),
 185	FEA_MAP(DS_LCLK),
 186	FEA_MAP(DS_FCLK),
 187	FEA_MAP(DS_UCLK),
 188	FEA_MAP(GFX_ULV),
 189	ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT),
 190	FEA_MAP(RSMU_SMN_CG),
 191	FEA_MAP(WAFL_CG),
 192	FEA_MAP(PPT),
 193	FEA_MAP(TDC),
 194	FEA_MAP(APCC_PLUS),
 195	FEA_MAP(VR0HOT),
 196	FEA_MAP(VR1HOT),
 197	FEA_MAP(FW_CTF),
 198	FEA_MAP(FAN_CONTROL),
 199	FEA_MAP(THERMAL),
 200	FEA_MAP(OUT_OF_BAND_MONITOR),
 201	FEA_MAP(TEMP_DEPENDENT_VMIN),
 202};
 203
 204static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
 205	TAB_MAP(PPTABLE),
 206	TAB_MAP(AVFS),
 207	TAB_MAP(AVFS_PSM_DEBUG),
 208	TAB_MAP(AVFS_FUSE_OVERRIDE),
 209	TAB_MAP(PMSTATUSLOG),
 210	TAB_MAP(SMU_METRICS),
 211	TAB_MAP(DRIVER_SMU_CONFIG),
 212	TAB_MAP(OVERDRIVE),
 213	TAB_MAP(I2C_COMMANDS),
 214	TAB_MAP(ACTIVITY_MONITOR_COEFF),
 215};
 216
 217static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 218	PWR_MAP(AC),
 219	PWR_MAP(DC),
 220};
 221
 222static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 223	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,	WORKLOAD_PPLIB_DEFAULT_BIT),
 224	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,		WORKLOAD_PPLIB_POWER_SAVING_BIT),
 225	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,		WORKLOAD_PPLIB_VIDEO_BIT),
 226	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,		WORKLOAD_PPLIB_COMPUTE_BIT),
 227	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
 228};
 229
 230static const uint8_t arcturus_throttler_map[] = {
 231	[THROTTLER_TEMP_EDGE_BIT]	= (SMU_THROTTLER_TEMP_EDGE_BIT),
 232	[THROTTLER_TEMP_HOTSPOT_BIT]	= (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 233	[THROTTLER_TEMP_MEM_BIT]	= (SMU_THROTTLER_TEMP_MEM_BIT),
 234	[THROTTLER_TEMP_VR_GFX_BIT]	= (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 235	[THROTTLER_TEMP_VR_MEM_BIT]	= (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 236	[THROTTLER_TEMP_VR_SOC_BIT]	= (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 237	[THROTTLER_TDC_GFX_BIT]		= (SMU_THROTTLER_TDC_GFX_BIT),
 238	[THROTTLER_TDC_SOC_BIT]		= (SMU_THROTTLER_TDC_SOC_BIT),
 239	[THROTTLER_PPT0_BIT]		= (SMU_THROTTLER_PPT0_BIT),
 240	[THROTTLER_PPT1_BIT]		= (SMU_THROTTLER_PPT1_BIT),
 241	[THROTTLER_PPT2_BIT]		= (SMU_THROTTLER_PPT2_BIT),
 242	[THROTTLER_PPT3_BIT]		= (SMU_THROTTLER_PPT3_BIT),
 243	[THROTTLER_PPM_BIT]		= (SMU_THROTTLER_PPM_BIT),
 244	[THROTTLER_FIT_BIT]		= (SMU_THROTTLER_FIT_BIT),
 245	[THROTTLER_APCC_BIT]		= (SMU_THROTTLER_APCC_BIT),
 246	[THROTTLER_VRHOT0_BIT]		= (SMU_THROTTLER_VRHOT0_BIT),
 247	[THROTTLER_VRHOT1_BIT]		= (SMU_THROTTLER_VRHOT1_BIT),
 248};
 249
 250static int arcturus_tables_init(struct smu_context *smu)
 251{
 252	struct smu_table_context *smu_table = &smu->smu_table;
 253	struct smu_table *tables = smu_table->tables;
 254
 255	SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 256		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 257
 258	SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 259		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 260
 261	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 262		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 263
 264	SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 265			       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 266
 267	SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 268		       sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 269		       AMDGPU_GEM_DOMAIN_VRAM);
 270
 271	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 272	if (!smu_table->metrics_table)
 273		return -ENOMEM;
 274	smu_table->metrics_time = 0;
 275
 276	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 277	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 278	if (!smu_table->gpu_metrics_table) {
 279		kfree(smu_table->metrics_table);
 280		return -ENOMEM;
 281	}
 282
 283	return 0;
 284}
 285
 286static int arcturus_select_plpd_policy(struct smu_context *smu, int level)
 287{
 288	/* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */
 289	if (smu->smc_fw_version < 0x00361700) {
 290		dev_err(smu->adev->dev,
 291			"XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");
 292		return -EINVAL;
 293	}
 294
 295	if (level == XGMI_PLPD_DEFAULT)
 296		return smu_cmn_send_smc_msg_with_param(
 297			smu, SMU_MSG_GmiPwrDnControl, 1, NULL);
 298	else if (level == XGMI_PLPD_DISALLOW)
 299		return smu_cmn_send_smc_msg_with_param(
 300			smu, SMU_MSG_GmiPwrDnControl, 0, NULL);
 301	else
 302		return -EINVAL;
 303}
 304
 305static int arcturus_allocate_dpm_context(struct smu_context *smu)
 306{
 307	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 308	struct smu_dpm_policy *policy;
 309
 310	smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 311				       GFP_KERNEL);
 312	if (!smu_dpm->dpm_context)
 313		return -ENOMEM;
 314	smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 315
 316	smu_dpm->dpm_policies =
 317		kzalloc(sizeof(struct smu_dpm_policy_ctxt), GFP_KERNEL);
 318
 319	if (!smu_dpm->dpm_policies)
 320		return -ENOMEM;
 321
 322	policy = &(smu_dpm->dpm_policies->policies[0]);
 323	policy->policy_type = PP_PM_POLICY_XGMI_PLPD;
 324	policy->level_mask = BIT(XGMI_PLPD_DISALLOW) | BIT(XGMI_PLPD_DEFAULT);
 325	policy->current_level = XGMI_PLPD_DEFAULT;
 326	policy->set_policy = arcturus_select_plpd_policy;
 327	smu_cmn_generic_plpd_policy_desc(policy);
 328	smu_dpm->dpm_policies->policy_mask |= BIT(PP_PM_POLICY_XGMI_PLPD);
 329
 330	return 0;
 331}
 332
 333static int arcturus_init_smc_tables(struct smu_context *smu)
 334{
 335	int ret = 0;
 336
 337	ret = arcturus_tables_init(smu);
 338	if (ret)
 339		return ret;
 340
 341	ret = arcturus_allocate_dpm_context(smu);
 342	if (ret)
 343		return ret;
 344
 345	return smu_v11_0_init_smc_tables(smu);
 346}
 347
 348static int
 349arcturus_get_allowed_feature_mask(struct smu_context *smu,
 350				  uint32_t *feature_mask, uint32_t num)
 351{
 352	if (num > 2)
 353		return -EINVAL;
 354
 355	/* pptable will handle the features to enable */
 356	memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 357
 358	return 0;
 359}
 360
 361static int arcturus_set_default_dpm_table(struct smu_context *smu)
 362{
 363	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 364	PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 365	struct smu_11_0_dpm_table *dpm_table = NULL;
 366	int ret = 0;
 367
 368	/* socclk dpm table setup */
 369	dpm_table = &dpm_context->dpm_tables.soc_table;
 370	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 371		ret = smu_v11_0_set_single_dpm_table(smu,
 372						     SMU_SOCCLK,
 373						     dpm_table);
 374		if (ret)
 375			return ret;
 376		dpm_table->is_fine_grained =
 377			!driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 378	} else {
 379		dpm_table->count = 1;
 380		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 381		dpm_table->dpm_levels[0].enabled = true;
 382		dpm_table->min = dpm_table->dpm_levels[0].value;
 383		dpm_table->max = dpm_table->dpm_levels[0].value;
 384	}
 385
 386	/* gfxclk dpm table setup */
 387	dpm_table = &dpm_context->dpm_tables.gfx_table;
 388	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 389		ret = smu_v11_0_set_single_dpm_table(smu,
 390						     SMU_GFXCLK,
 391						     dpm_table);
 392		if (ret)
 393			return ret;
 394		dpm_table->is_fine_grained =
 395			!driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
 396	} else {
 397		dpm_table->count = 1;
 398		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 399		dpm_table->dpm_levels[0].enabled = true;
 400		dpm_table->min = dpm_table->dpm_levels[0].value;
 401		dpm_table->max = dpm_table->dpm_levels[0].value;
 402	}
 403
 404	/* memclk dpm table setup */
 405	dpm_table = &dpm_context->dpm_tables.uclk_table;
 406	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 407		ret = smu_v11_0_set_single_dpm_table(smu,
 408						     SMU_UCLK,
 409						     dpm_table);
 410		if (ret)
 411			return ret;
 412		dpm_table->is_fine_grained =
 413			!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
 414	} else {
 415		dpm_table->count = 1;
 416		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 417		dpm_table->dpm_levels[0].enabled = true;
 418		dpm_table->min = dpm_table->dpm_levels[0].value;
 419		dpm_table->max = dpm_table->dpm_levels[0].value;
 420	}
 421
 422	/* fclk dpm table setup */
 423	dpm_table = &dpm_context->dpm_tables.fclk_table;
 424	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 425		ret = smu_v11_0_set_single_dpm_table(smu,
 426						     SMU_FCLK,
 427						     dpm_table);
 428		if (ret)
 429			return ret;
 430		dpm_table->is_fine_grained =
 431			!driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
 432	} else {
 433		dpm_table->count = 1;
 434		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 435		dpm_table->dpm_levels[0].enabled = true;
 436		dpm_table->min = dpm_table->dpm_levels[0].value;
 437		dpm_table->max = dpm_table->dpm_levels[0].value;
 438	}
 439
 440	/* XGMI PLPD is supported by 54.23.0 and onwards */
 441	if (smu->smc_fw_version < 0x00361700) {
 442		struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 443
 444		smu_dpm->dpm_policies->policy_mask &=
 445			~BIT(PP_PM_POLICY_XGMI_PLPD);
 446	}
 447
 448	return 0;
 449}
 450
 451static void arcturus_check_bxco_support(struct smu_context *smu)
 452{
 453	struct smu_table_context *table_context = &smu->smu_table;
 454	struct smu_11_0_powerplay_table *powerplay_table =
 455		table_context->power_play_table;
 456	struct smu_baco_context *smu_baco = &smu->smu_baco;
 457	struct amdgpu_device *adev = smu->adev;
 458	uint32_t val;
 459
 460	if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 461	    powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
 462		val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
 463		smu_baco->platform_support =
 464			(val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
 465									false;
 466	}
 467}
 468
 469static void arcturus_check_fan_support(struct smu_context *smu)
 470{
 471	struct smu_table_context *table_context = &smu->smu_table;
 472	PPTable_t *pptable = table_context->driver_pptable;
 473
 474	/* No sort of fan control possible if PPTable has it disabled */
 475	smu->adev->pm.no_fan =
 476		!(pptable->FeaturesToRun[0] & FEATURE_FAN_CONTROL_MASK);
 477	if (smu->adev->pm.no_fan)
 478		dev_info_once(smu->adev->dev,
 479			      "PMFW based fan control disabled");
 480}
 481
 482static int arcturus_check_powerplay_table(struct smu_context *smu)
 483{
 484	struct smu_table_context *table_context = &smu->smu_table;
 485	struct smu_11_0_powerplay_table *powerplay_table =
 486		table_context->power_play_table;
 487
 488	arcturus_check_bxco_support(smu);
 489	arcturus_check_fan_support(smu);
 490
 491	table_context->thermal_controller_type =
 492		powerplay_table->thermal_controller_type;
 493
 494	return 0;
 495}
 496
 497static int arcturus_store_powerplay_table(struct smu_context *smu)
 498{
 499	struct smu_table_context *table_context = &smu->smu_table;
 500	struct smu_11_0_powerplay_table *powerplay_table =
 501		table_context->power_play_table;
 502
 503	memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 504	       sizeof(PPTable_t));
 505
 506	return 0;
 507}
 508
 509static int arcturus_append_powerplay_table(struct smu_context *smu)
 510{
 511	struct smu_table_context *table_context = &smu->smu_table;
 512	PPTable_t *smc_pptable = table_context->driver_pptable;
 513	struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
 514	int index, ret;
 515
 516	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 517					   smc_dpm_info);
 518
 519	ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 520				      (uint8_t **)&smc_dpm_table);
 521	if (ret)
 522		return ret;
 523
 524	dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 525			smc_dpm_table->table_header.format_revision,
 526			smc_dpm_table->table_header.content_revision);
 527
 528	if ((smc_dpm_table->table_header.format_revision == 4) &&
 529	    (smc_dpm_table->table_header.content_revision == 6))
 530		smu_memcpy_trailing(smc_pptable, MaxVoltageStepGfx, BoardReserved,
 531				    smc_dpm_table, maxvoltagestepgfx);
 532	return 0;
 533}
 534
 535static int arcturus_setup_pptable(struct smu_context *smu)
 536{
 537	int ret = 0;
 538
 539	ret = smu_v11_0_setup_pptable(smu);
 540	if (ret)
 541		return ret;
 542
 543	ret = arcturus_store_powerplay_table(smu);
 544	if (ret)
 545		return ret;
 546
 547	ret = arcturus_append_powerplay_table(smu);
 548	if (ret)
 549		return ret;
 550
 551	ret = arcturus_check_powerplay_table(smu);
 552	if (ret)
 553		return ret;
 554
 555	return ret;
 556}
 557
 558static int arcturus_run_btc(struct smu_context *smu)
 559{
 560	int ret = 0;
 561
 562	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
 563	if (ret) {
 564		dev_err(smu->adev->dev, "RunAfllBtc failed!\n");
 565		return ret;
 566	}
 567
 568	return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 569}
 570
 571static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 572{
 573	struct smu_11_0_dpm_context *dpm_context =
 574				smu->smu_dpm.dpm_context;
 575	struct smu_11_0_dpm_table *gfx_table =
 576				&dpm_context->dpm_tables.gfx_table;
 577	struct smu_11_0_dpm_table *mem_table =
 578				&dpm_context->dpm_tables.uclk_table;
 579	struct smu_11_0_dpm_table *soc_table =
 580				&dpm_context->dpm_tables.soc_table;
 581	struct smu_umd_pstate_table *pstate_table =
 582				&smu->pstate_table;
 583
 584	pstate_table->gfxclk_pstate.min = gfx_table->min;
 585	pstate_table->gfxclk_pstate.peak = gfx_table->max;
 586
 587	pstate_table->uclk_pstate.min = mem_table->min;
 588	pstate_table->uclk_pstate.peak = mem_table->max;
 589
 590	pstate_table->socclk_pstate.min = soc_table->min;
 591	pstate_table->socclk_pstate.peak = soc_table->max;
 592
 593	if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
 594	    mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
 595	    soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
 596		pstate_table->gfxclk_pstate.standard =
 597			gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
 598		pstate_table->uclk_pstate.standard =
 599			mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
 600		pstate_table->socclk_pstate.standard =
 601			soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
 602	} else {
 603		pstate_table->gfxclk_pstate.standard =
 604			pstate_table->gfxclk_pstate.min;
 605		pstate_table->uclk_pstate.standard =
 606			pstate_table->uclk_pstate.min;
 607		pstate_table->socclk_pstate.standard =
 608			pstate_table->socclk_pstate.min;
 609	}
 610
 611	return 0;
 612}
 613
 614static void arcturus_get_clk_table(struct smu_context *smu,
 615				   struct pp_clock_levels_with_latency *clocks,
 616				   struct smu_11_0_dpm_table *dpm_table)
 617{
 618	uint32_t i;
 619
 620	clocks->num_levels = min_t(uint32_t,
 621				   dpm_table->count,
 622				   (uint32_t)PP_MAX_CLOCK_LEVELS);
 623
 624	for (i = 0; i < clocks->num_levels; i++) {
 625		clocks->data[i].clocks_in_khz =
 626			dpm_table->dpm_levels[i].value * 1000;
 627		clocks->data[i].latency_in_us = 0;
 628	}
 629}
 630
 631static int arcturus_freqs_in_same_level(int32_t frequency1,
 632					int32_t frequency2)
 633{
 634	return (abs(frequency1 - frequency2) <= EPSILON);
 635}
 636
 637static int arcturus_get_smu_metrics_data(struct smu_context *smu,
 638					 MetricsMember_t member,
 639					 uint32_t *value)
 640{
 641	struct smu_table_context *smu_table = &smu->smu_table;
 642	SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 643	int ret = 0;
 644
 645	ret = smu_cmn_get_metrics_table(smu,
 646					NULL,
 647					false);
 648	if (ret)
 649		return ret;
 650
 651	switch (member) {
 652	case METRICS_CURR_GFXCLK:
 653		*value = metrics->CurrClock[PPCLK_GFXCLK];
 654		break;
 655	case METRICS_CURR_SOCCLK:
 656		*value = metrics->CurrClock[PPCLK_SOCCLK];
 657		break;
 658	case METRICS_CURR_UCLK:
 659		*value = metrics->CurrClock[PPCLK_UCLK];
 660		break;
 661	case METRICS_CURR_VCLK:
 662		*value = metrics->CurrClock[PPCLK_VCLK];
 663		break;
 664	case METRICS_CURR_DCLK:
 665		*value = metrics->CurrClock[PPCLK_DCLK];
 666		break;
 667	case METRICS_CURR_FCLK:
 668		*value = metrics->CurrClock[PPCLK_FCLK];
 669		break;
 670	case METRICS_AVERAGE_GFXCLK:
 671		*value = metrics->AverageGfxclkFrequency;
 672		break;
 673	case METRICS_AVERAGE_SOCCLK:
 674		*value = metrics->AverageSocclkFrequency;
 675		break;
 676	case METRICS_AVERAGE_UCLK:
 677		*value = metrics->AverageUclkFrequency;
 678		break;
 679	case METRICS_AVERAGE_VCLK:
 680		*value = metrics->AverageVclkFrequency;
 681		break;
 682	case METRICS_AVERAGE_DCLK:
 683		*value = metrics->AverageDclkFrequency;
 684		break;
 685	case METRICS_AVERAGE_GFXACTIVITY:
 686		*value = metrics->AverageGfxActivity;
 687		break;
 688	case METRICS_AVERAGE_MEMACTIVITY:
 689		*value = metrics->AverageUclkActivity;
 690		break;
 691	case METRICS_AVERAGE_VCNACTIVITY:
 692		*value = metrics->VcnActivityPercentage;
 693		break;
 694	case METRICS_AVERAGE_SOCKETPOWER:
 695		*value = metrics->AverageSocketPower << 8;
 696		break;
 697	case METRICS_TEMPERATURE_EDGE:
 698		*value = metrics->TemperatureEdge *
 699			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 700		break;
 701	case METRICS_TEMPERATURE_HOTSPOT:
 702		*value = metrics->TemperatureHotspot *
 703			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 704		break;
 705	case METRICS_TEMPERATURE_MEM:
 706		*value = metrics->TemperatureHBM *
 707			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 708		break;
 709	case METRICS_TEMPERATURE_VRGFX:
 710		*value = metrics->TemperatureVrGfx *
 711			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 712		break;
 713	case METRICS_TEMPERATURE_VRSOC:
 714		*value = metrics->TemperatureVrSoc *
 715			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 716		break;
 717	case METRICS_TEMPERATURE_VRMEM:
 718		*value = metrics->TemperatureVrMem *
 719			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 720		break;
 721	case METRICS_THROTTLER_STATUS:
 722		*value = metrics->ThrottlerStatus;
 723		break;
 724	case METRICS_CURR_FANSPEED:
 725		*value = metrics->CurrFanSpeed;
 726		break;
 727	default:
 728		*value = UINT_MAX;
 729		break;
 730	}
 731
 732	return ret;
 733}
 734
 735static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
 736				       enum smu_clk_type clk_type,
 737				       uint32_t *value)
 738{
 739	MetricsMember_t member_type;
 740	int clk_id = 0;
 741
 742	if (!value)
 743		return -EINVAL;
 744
 745	clk_id = smu_cmn_to_asic_specific_index(smu,
 746						CMN2ASIC_MAPPING_CLK,
 747						clk_type);
 748	if (clk_id < 0)
 749		return -EINVAL;
 750
 751	switch (clk_id) {
 752	case PPCLK_GFXCLK:
 753		/*
 754		 * CurrClock[clk_id] can provide accurate
 755		 *   output only when the dpm feature is enabled.
 756		 * We can use Average_* for dpm disabled case.
 757		 *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
 758		 */
 759		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
 760			member_type = METRICS_CURR_GFXCLK;
 761		else
 762			member_type = METRICS_AVERAGE_GFXCLK;
 763		break;
 764	case PPCLK_UCLK:
 765		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
 766			member_type = METRICS_CURR_UCLK;
 767		else
 768			member_type = METRICS_AVERAGE_UCLK;
 769		break;
 770	case PPCLK_SOCCLK:
 771		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
 772			member_type = METRICS_CURR_SOCCLK;
 773		else
 774			member_type = METRICS_AVERAGE_SOCCLK;
 775		break;
 776	case PPCLK_VCLK:
 777		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
 778			member_type = METRICS_CURR_VCLK;
 779		else
 780			member_type = METRICS_AVERAGE_VCLK;
 781		break;
 782	case PPCLK_DCLK:
 783		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
 784			member_type = METRICS_CURR_DCLK;
 785		else
 786			member_type = METRICS_AVERAGE_DCLK;
 787		break;
 788	case PPCLK_FCLK:
 789		member_type = METRICS_CURR_FCLK;
 790		break;
 791	default:
 792		return -EINVAL;
 793	}
 794
 795	return arcturus_get_smu_metrics_data(smu,
 796					     member_type,
 797					     value);
 798}
 799
 800static int arcturus_emit_clk_levels(struct smu_context *smu,
 801				    enum smu_clk_type type, char *buf, int *offset)
 802{
 803	int ret = 0;
 804	struct pp_clock_levels_with_latency clocks;
 805	struct smu_11_0_dpm_table *single_dpm_table;
 806	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 807	struct smu_11_0_dpm_context *dpm_context = NULL;
 808	uint32_t gen_speed, lane_width;
 809	uint32_t i, cur_value = 0;
 810	bool freq_match;
 811	unsigned int clock_mhz;
 812	static const char attempt_string[] = "Attempt to get current";
 813
 814	if (amdgpu_ras_intr_triggered()) {
 815		*offset += sysfs_emit_at(buf, *offset, "unavailable\n");
 816		return -EBUSY;
 817	}
 818
 819	dpm_context = smu_dpm->dpm_context;
 820
 821	switch (type) {
 822	case SMU_SCLK:
 823		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &cur_value);
 824		if (ret) {
 825			dev_err(smu->adev->dev, "%s gfx clk Failed!", attempt_string);
 826			return ret;
 827		}
 828
 829		single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 830		arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 831
 832		break;
 833
 834	case SMU_MCLK:
 835		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &cur_value);
 836		if (ret) {
 837			dev_err(smu->adev->dev, "%s mclk Failed!", attempt_string);
 838			return ret;
 839		}
 840
 841		single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 842		arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 843
 844		break;
 845
 846	case SMU_SOCCLK:
 847		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &cur_value);
 848		if (ret) {
 849			dev_err(smu->adev->dev, "%s socclk Failed!", attempt_string);
 850			return ret;
 851		}
 852
 853		single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 854		arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 855
 856		break;
 857
 858	case SMU_FCLK:
 859		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &cur_value);
 860		if (ret) {
 861			dev_err(smu->adev->dev, "%s fclk Failed!", attempt_string);
 862			return ret;
 863		}
 864
 865		single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 866		arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 867
 868		break;
 869
 870	case SMU_VCLK:
 871		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_VCLK, &cur_value);
 872		if (ret) {
 873			dev_err(smu->adev->dev, "%s vclk Failed!", attempt_string);
 874			return ret;
 875		}
 876
 877		single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
 878		arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 879
 880		break;
 881
 882	case SMU_DCLK:
 883		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_DCLK, &cur_value);
 884		if (ret) {
 885			dev_err(smu->adev->dev, "%s dclk Failed!", attempt_string);
 886			return ret;
 887		}
 888
 889		single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
 890		arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 891
 892		break;
 893
 894	case SMU_PCIE:
 895		gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
 896		lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
 897		break;
 898
 899	default:
 900		return -EINVAL;
 901	}
 902
 903	switch (type) {
 904	case SMU_SCLK:
 905	case SMU_MCLK:
 906	case SMU_SOCCLK:
 907	case SMU_FCLK:
 908	case SMU_VCLK:
 909	case SMU_DCLK:
 910		/*
 911		 * For DPM disabled case, there will be only one clock level.
 912		 * And it's safe to assume that is always the current clock.
 913		 */
 914		for (i = 0; i < clocks.num_levels; i++) {
 915			clock_mhz = clocks.data[i].clocks_in_khz / 1000;
 916			freq_match = arcturus_freqs_in_same_level(clock_mhz, cur_value);
 917			freq_match |= (clocks.num_levels == 1);
 918
 919			*offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
 920				i, clock_mhz,
 921				freq_match ? "*" : "");
 922		}
 923		break;
 924
 925	case SMU_PCIE:
 926		*offset += sysfs_emit_at(buf, *offset, "0: %s %s %dMhz *\n",
 927				(gen_speed == 0) ? "2.5GT/s," :
 928				(gen_speed == 1) ? "5.0GT/s," :
 929				(gen_speed == 2) ? "8.0GT/s," :
 930				(gen_speed == 3) ? "16.0GT/s," : "",
 931				(lane_width == 1) ? "x1" :
 932				(lane_width == 2) ? "x2" :
 933				(lane_width == 3) ? "x4" :
 934				(lane_width == 4) ? "x8" :
 935				(lane_width == 5) ? "x12" :
 936				(lane_width == 6) ? "x16" : "",
 937				smu->smu_table.boot_values.lclk / 100);
 938		break;
 939
 940	default:
 941		return -EINVAL;
 942	}
 943
 944	return 0;
 945}
 946
 947static int arcturus_upload_dpm_level(struct smu_context *smu,
 948				     bool max,
 949				     uint32_t feature_mask,
 950				     uint32_t level)
 951{
 952	struct smu_11_0_dpm_context *dpm_context =
 953			smu->smu_dpm.dpm_context;
 954	uint32_t freq;
 955	int ret = 0;
 956
 957	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 958	    (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 959		freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
 960		ret = smu_cmn_send_smc_msg_with_param(smu,
 961			(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 962			(PPCLK_GFXCLK << 16) | (freq & 0xffff),
 963			NULL);
 964		if (ret) {
 965			dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
 966						max ? "max" : "min");
 967			return ret;
 968		}
 969	}
 970
 971	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 972	    (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 973		freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
 974		ret = smu_cmn_send_smc_msg_with_param(smu,
 975			(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 976			(PPCLK_UCLK << 16) | (freq & 0xffff),
 977			NULL);
 978		if (ret) {
 979			dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
 980						max ? "max" : "min");
 981			return ret;
 982		}
 983	}
 984
 985	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 986	    (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
 987		freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
 988		ret = smu_cmn_send_smc_msg_with_param(smu,
 989			(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 990			(PPCLK_SOCCLK << 16) | (freq & 0xffff),
 991			NULL);
 992		if (ret) {
 993			dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
 994						max ? "max" : "min");
 995			return ret;
 996		}
 997	}
 998
 999	return ret;
1000}
1001
1002static int arcturus_force_clk_levels(struct smu_context *smu,
1003			enum smu_clk_type type, uint32_t mask)
1004{
1005	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1006	struct smu_11_0_dpm_table *single_dpm_table = NULL;
1007	uint32_t soft_min_level, soft_max_level;
1008	int ret = 0;
1009
1010	if ((smu->smc_fw_version >= 0x361200) &&
1011	    (smu->smc_fw_version <= 0x361a00)) {
1012		dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1013		       "54.18 - 54.26(included) SMU firmwares\n");
1014		return -EOPNOTSUPP;
1015	}
1016
1017	soft_min_level = mask ? (ffs(mask) - 1) : 0;
1018	soft_max_level = mask ? (fls(mask) - 1) : 0;
1019
1020	switch (type) {
1021	case SMU_SCLK:
1022		single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1023		if (soft_max_level >= single_dpm_table->count) {
1024			dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
1025					soft_max_level, single_dpm_table->count - 1);
1026			ret = -EINVAL;
1027			break;
1028		}
1029
1030		ret = arcturus_upload_dpm_level(smu,
1031						false,
1032						FEATURE_DPM_GFXCLK_MASK,
1033						soft_min_level);
1034		if (ret) {
1035			dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
1036			break;
1037		}
1038
1039		ret = arcturus_upload_dpm_level(smu,
1040						true,
1041						FEATURE_DPM_GFXCLK_MASK,
1042						soft_max_level);
1043		if (ret)
1044			dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
1045
1046		break;
1047
1048	case SMU_MCLK:
1049	case SMU_SOCCLK:
1050	case SMU_FCLK:
1051		/*
1052		 * Should not arrive here since Arcturus does not
1053		 * support mclk/socclk/fclk softmin/softmax settings
1054		 */
1055		ret = -EINVAL;
1056		break;
1057
1058	default:
1059		break;
1060	}
1061
1062	return ret;
1063}
1064
1065static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
1066						struct smu_temperature_range *range)
1067{
1068	struct smu_table_context *table_context = &smu->smu_table;
1069	struct smu_11_0_powerplay_table *powerplay_table =
1070				table_context->power_play_table;
1071	PPTable_t *pptable = smu->smu_table.driver_pptable;
1072
1073	if (!range)
1074		return -EINVAL;
1075
1076	memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1077
1078	range->max = pptable->TedgeLimit *
1079		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1080	range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
1081		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1082	range->hotspot_crit_max = pptable->ThotspotLimit *
1083		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1084	range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1085		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1086	range->mem_crit_max = pptable->TmemLimit *
1087		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1088	range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1089		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1090	range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1091
1092	return 0;
1093}
1094
1095static int arcturus_read_sensor(struct smu_context *smu,
1096				enum amd_pp_sensors sensor,
1097				void *data, uint32_t *size)
1098{
1099	struct smu_table_context *table_context = &smu->smu_table;
1100	PPTable_t *pptable = table_context->driver_pptable;
1101	int ret = 0;
1102
1103	if (amdgpu_ras_intr_triggered())
1104		return 0;
1105
1106	if (!data || !size)
1107		return -EINVAL;
1108
1109	switch (sensor) {
1110	case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1111		*(uint32_t *)data = pptable->FanMaximumRpm;
1112		*size = 4;
1113		break;
1114	case AMDGPU_PP_SENSOR_MEM_LOAD:
1115		ret = arcturus_get_smu_metrics_data(smu,
1116						    METRICS_AVERAGE_MEMACTIVITY,
1117						    (uint32_t *)data);
1118		*size = 4;
1119		break;
1120	case AMDGPU_PP_SENSOR_GPU_LOAD:
1121		ret = arcturus_get_smu_metrics_data(smu,
1122						    METRICS_AVERAGE_GFXACTIVITY,
1123						    (uint32_t *)data);
1124		*size = 4;
1125		break;
1126	case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1127		ret = arcturus_get_smu_metrics_data(smu,
1128						    METRICS_AVERAGE_SOCKETPOWER,
1129						    (uint32_t *)data);
1130		*size = 4;
1131		break;
1132	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1133		ret = arcturus_get_smu_metrics_data(smu,
1134						    METRICS_TEMPERATURE_HOTSPOT,
1135						    (uint32_t *)data);
1136		*size = 4;
1137		break;
1138	case AMDGPU_PP_SENSOR_EDGE_TEMP:
1139		ret = arcturus_get_smu_metrics_data(smu,
1140						    METRICS_TEMPERATURE_EDGE,
1141						    (uint32_t *)data);
1142		*size = 4;
1143		break;
1144	case AMDGPU_PP_SENSOR_MEM_TEMP:
1145		ret = arcturus_get_smu_metrics_data(smu,
1146						    METRICS_TEMPERATURE_MEM,
1147						    (uint32_t *)data);
1148		*size = 4;
1149		break;
1150	case AMDGPU_PP_SENSOR_GFX_MCLK:
1151		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1152		/* the output clock frequency in 10K unit */
1153		*(uint32_t *)data *= 100;
1154		*size = 4;
1155		break;
1156	case AMDGPU_PP_SENSOR_GFX_SCLK:
1157		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1158		*(uint32_t *)data *= 100;
1159		*size = 4;
1160		break;
1161	case AMDGPU_PP_SENSOR_VDDGFX:
1162		ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1163		*size = 4;
1164		break;
1165	case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1166	default:
1167		ret = -EOPNOTSUPP;
1168		break;
1169	}
1170
1171	return ret;
1172}
1173
1174static int arcturus_set_fan_static_mode(struct smu_context *smu,
1175					uint32_t mode)
1176{
1177	struct amdgpu_device *adev = smu->adev;
1178
1179	WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
1180		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
1181				   CG_FDO_CTRL2, TMIN, 0));
1182	WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
1183		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
1184				   CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1185
1186	return 0;
1187}
1188
1189static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1190				      uint32_t *speed)
1191{
1192	struct amdgpu_device *adev = smu->adev;
1193	uint32_t crystal_clock_freq = 2500;
1194	uint32_t tach_status;
1195	uint64_t tmp64;
1196	int ret = 0;
1197
1198	if (!speed)
1199		return -EINVAL;
1200
1201	switch (smu_v11_0_get_fan_control_mode(smu)) {
1202	case AMD_FAN_CTRL_AUTO:
1203		ret = arcturus_get_smu_metrics_data(smu,
1204						    METRICS_CURR_FANSPEED,
1205						    speed);
1206		break;
1207	default:
1208		/*
1209		 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1210		 * detected via register retrieving. To workaround this, we will
1211		 * report the fan speed as 0 RPM if user just requested such.
1212		 */
1213		if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM)
1214		     && !smu->user_dpm_profile.fan_speed_rpm) {
1215			*speed = 0;
1216			return 0;
1217		}
1218
1219		tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1220		tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS_ARCT);
1221		if (tach_status) {
1222			do_div(tmp64, tach_status);
1223			*speed = (uint32_t)tmp64;
1224		} else {
1225			*speed = 0;
1226		}
1227
1228		break;
1229	}
1230
1231	return ret;
1232}
1233
1234static int arcturus_set_fan_speed_pwm(struct smu_context *smu,
1235				      uint32_t speed)
1236{
1237	struct amdgpu_device *adev = smu->adev;
1238	uint32_t duty100, duty;
1239	uint64_t tmp64;
1240
1241	speed = min_t(uint32_t, speed, 255);
1242
1243	duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
1244				CG_FDO_CTRL1, FMAX_DUTY100);
1245	if (!duty100)
1246		return -EINVAL;
1247
1248	tmp64 = (uint64_t)speed * duty100;
1249	do_div(tmp64, 255);
1250	duty = (uint32_t)tmp64;
1251
1252	WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT,
1253		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT),
1254				   CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1255
1256	return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1257}
1258
1259static int arcturus_set_fan_speed_rpm(struct smu_context *smu,
1260				      uint32_t speed)
1261{
1262	struct amdgpu_device *adev = smu->adev;
1263	/*
1264	 * crystal_clock_freq used for fan speed rpm calculation is
1265	 * always 25Mhz. So, hardcode it as 2500(in 10K unit).
1266	 */
1267	uint32_t crystal_clock_freq = 2500;
1268	uint32_t tach_period;
1269
1270	if (!speed || speed > UINT_MAX/8)
1271		return -EINVAL;
1272
1273	tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1274	WREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT,
1275		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT),
1276				   CG_TACH_CTRL, TARGET_PERIOD,
1277				   tach_period));
1278
1279	return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1280}
1281
1282static int arcturus_get_fan_speed_pwm(struct smu_context *smu,
1283				      uint32_t *speed)
1284{
1285	struct amdgpu_device *adev = smu->adev;
1286	uint32_t duty100, duty;
1287	uint64_t tmp64;
1288
1289	/*
1290	 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1291	 * detected via register retrieving. To workaround this, we will
1292	 * report the fan speed as 0 PWM if user just requested such.
1293	 */
1294	if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM)
1295	     && !smu->user_dpm_profile.fan_speed_pwm) {
1296		*speed = 0;
1297		return 0;
1298	}
1299
1300	duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
1301				CG_FDO_CTRL1, FMAX_DUTY100);
1302	duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS_ARCT),
1303				CG_THERMAL_STATUS, FDO_PWM_DUTY);
1304
1305	if (duty100) {
1306		tmp64 = (uint64_t)duty * 255;
1307		do_div(tmp64, duty100);
1308		*speed = min_t(uint32_t, tmp64, 255);
1309	} else {
1310		*speed = 0;
1311	}
1312
1313	return 0;
1314}
1315
1316static int arcturus_get_fan_parameters(struct smu_context *smu)
1317{
1318	PPTable_t *pptable = smu->smu_table.driver_pptable;
1319
1320	smu->fan_max_rpm = pptable->FanMaximumRpm;
1321
1322	return 0;
1323}
1324
1325static int arcturus_get_power_limit(struct smu_context *smu,
1326					uint32_t *current_power_limit,
1327					uint32_t *default_power_limit,
1328					uint32_t *max_power_limit,
1329					uint32_t *min_power_limit)
1330{
1331	PPTable_t *pptable = smu->smu_table.driver_pptable;
1332	uint32_t power_limit;
1333
1334	if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1335		/* the last hope to figure out the ppt limit */
1336		if (!pptable) {
1337			dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1338			return -EINVAL;
1339		}
1340		power_limit =
1341			pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1342	}
1343
1344	if (current_power_limit)
1345		*current_power_limit = power_limit;
1346	if (default_power_limit)
1347		*default_power_limit = power_limit;
1348	if (max_power_limit)
1349		*max_power_limit = power_limit;
1350	/*
1351	 * No lower bound is imposed on the limit. Any unreasonable limit set
1352	 * will result in frequent throttling.
1353	 */
1354	if (min_power_limit)
1355		*min_power_limit = 0;
1356
1357	return 0;
1358}
1359
1360static int arcturus_get_power_profile_mode(struct smu_context *smu,
1361					   char *buf)
1362{
1363	DpmActivityMonitorCoeffInt_t activity_monitor;
1364	static const char *title[] = {
1365			"PROFILE_INDEX(NAME)",
1366			"CLOCK_TYPE(NAME)",
1367			"FPS",
1368			"UseRlcBusy",
1369			"MinActiveFreqType",
1370			"MinActiveFreq",
1371			"BoosterFreqType",
1372			"BoosterFreq",
1373			"PD_Data_limit_c",
1374			"PD_Data_error_coeff",
1375			"PD_Data_error_rate_coeff"};
1376	uint32_t i, size = 0;
1377	int16_t workload_type = 0;
1378	int result = 0;
1379
1380	if (!buf)
1381		return -EINVAL;
1382
1383	if (smu->smc_fw_version >= 0x360d00)
1384		size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1385			title[0], title[1], title[2], title[3], title[4], title[5],
1386			title[6], title[7], title[8], title[9], title[10]);
1387	else
1388		size += sysfs_emit_at(buf, size, "%16s\n",
1389			title[0]);
1390
1391	for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1392		/*
1393		 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1394		 * Not all profile modes are supported on arcturus.
1395		 */
1396		workload_type = smu_cmn_to_asic_specific_index(smu,
1397							       CMN2ASIC_MAPPING_WORKLOAD,
1398							       i);
1399		if (workload_type < 0)
1400			continue;
1401
1402		if (smu->smc_fw_version >= 0x360d00) {
1403			result = smu_cmn_update_table(smu,
1404						  SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1405						  workload_type,
1406						  (void *)(&activity_monitor),
1407						  false);
1408			if (result) {
1409				dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1410				return result;
1411			}
1412		}
1413
1414		size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1415			i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1416
1417		if (smu->smc_fw_version >= 0x360d00) {
1418			size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1419				" ",
1420				0,
1421				"GFXCLK",
1422				activity_monitor.Gfx_FPS,
1423				activity_monitor.Gfx_UseRlcBusy,
1424				activity_monitor.Gfx_MinActiveFreqType,
1425				activity_monitor.Gfx_MinActiveFreq,
1426				activity_monitor.Gfx_BoosterFreqType,
1427				activity_monitor.Gfx_BoosterFreq,
1428				activity_monitor.Gfx_PD_Data_limit_c,
1429				activity_monitor.Gfx_PD_Data_error_coeff,
1430				activity_monitor.Gfx_PD_Data_error_rate_coeff);
1431
1432			size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1433				" ",
1434				1,
1435				"UCLK",
1436				activity_monitor.Mem_FPS,
1437				activity_monitor.Mem_UseRlcBusy,
1438				activity_monitor.Mem_MinActiveFreqType,
1439				activity_monitor.Mem_MinActiveFreq,
1440				activity_monitor.Mem_BoosterFreqType,
1441				activity_monitor.Mem_BoosterFreq,
1442				activity_monitor.Mem_PD_Data_limit_c,
1443				activity_monitor.Mem_PD_Data_error_coeff,
1444				activity_monitor.Mem_PD_Data_error_rate_coeff);
1445		}
1446	}
1447
1448	return size;
1449}
1450
1451#define ARCTURUS_CUSTOM_PARAMS_COUNT 10
1452#define ARCTURUS_CUSTOM_PARAMS_CLOCK_COUNT 2
1453#define ARCTURUS_CUSTOM_PARAMS_SIZE (ARCTURUS_CUSTOM_PARAMS_CLOCK_COUNT * ARCTURUS_CUSTOM_PARAMS_COUNT * sizeof(long))
1454
1455static int arcturus_set_power_profile_mode_coeff(struct smu_context *smu,
1456						 long *input)
1457{
1458	DpmActivityMonitorCoeffInt_t activity_monitor;
1459	int ret, idx;
1460
1461	ret = smu_cmn_update_table(smu,
1462				   SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1463				   WORKLOAD_PPLIB_CUSTOM_BIT,
1464				   (void *)(&activity_monitor),
1465				   false);
1466	if (ret) {
1467		dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1468		return ret;
1469	}
1470
1471	idx = 0 * ARCTURUS_CUSTOM_PARAMS_COUNT;
1472	if (input[idx]) {
1473		/* Gfxclk */
1474		activity_monitor.Gfx_FPS = input[idx + 1];
1475		activity_monitor.Gfx_UseRlcBusy = input[idx + 2];
1476		activity_monitor.Gfx_MinActiveFreqType = input[idx + 3];
1477		activity_monitor.Gfx_MinActiveFreq = input[idx + 4];
1478		activity_monitor.Gfx_BoosterFreqType = input[idx + 5];
1479		activity_monitor.Gfx_BoosterFreq = input[idx + 6];
1480		activity_monitor.Gfx_PD_Data_limit_c = input[idx + 7];
1481		activity_monitor.Gfx_PD_Data_error_coeff = input[idx + 8];
1482		activity_monitor.Gfx_PD_Data_error_rate_coeff = input[idx + 9];
1483	}
1484	idx = 1 * ARCTURUS_CUSTOM_PARAMS_COUNT;
1485	if (input[idx]) {
1486		/* Uclk */
1487		activity_monitor.Mem_FPS = input[idx + 1];
1488		activity_monitor.Mem_UseRlcBusy = input[idx + 2];
1489		activity_monitor.Mem_MinActiveFreqType = input[idx + 3];
1490		activity_monitor.Mem_MinActiveFreq = input[idx + 4];
1491		activity_monitor.Mem_BoosterFreqType = input[idx + 5];
1492		activity_monitor.Mem_BoosterFreq = input[idx + 6];
1493		activity_monitor.Mem_PD_Data_limit_c = input[idx + 7];
1494		activity_monitor.Mem_PD_Data_error_coeff = input[idx + 8];
1495		activity_monitor.Mem_PD_Data_error_rate_coeff = input[idx + 9];
1496	}
1497
1498	ret = smu_cmn_update_table(smu,
1499				   SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1500				   WORKLOAD_PPLIB_CUSTOM_BIT,
1501				   (void *)(&activity_monitor),
1502				   true);
1503	if (ret) {
1504		dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1505		return ret;
1506	}
1507
1508	return ret;
1509}
1510
1511static int arcturus_set_power_profile_mode(struct smu_context *smu,
1512					   u32 workload_mask,
1513					   long *custom_params,
1514					   u32 custom_params_max_idx)
1515{
1516	u32 backend_workload_mask = 0;
1517	int ret, idx = -1, i;
1518
1519	smu_cmn_get_backend_workload_mask(smu, workload_mask,
1520					  &backend_workload_mask);
1521
1522	if (workload_mask & (1 << PP_SMC_POWER_PROFILE_CUSTOM)) {
1523		if (smu->smc_fw_version < 0x360d00)
1524			return -EINVAL;
1525		if (!smu->custom_profile_params) {
1526			smu->custom_profile_params =
1527				kzalloc(ARCTURUS_CUSTOM_PARAMS_SIZE, GFP_KERNEL);
1528			if (!smu->custom_profile_params)
1529				return -ENOMEM;
1530		}
1531		if (custom_params && custom_params_max_idx) {
1532			if (custom_params_max_idx != ARCTURUS_CUSTOM_PARAMS_COUNT)
1533				return -EINVAL;
1534			if (custom_params[0] >= ARCTURUS_CUSTOM_PARAMS_CLOCK_COUNT)
1535				return -EINVAL;
1536			idx = custom_params[0] * ARCTURUS_CUSTOM_PARAMS_COUNT;
1537			smu->custom_profile_params[idx] = 1;
1538			for (i = 1; i < custom_params_max_idx; i++)
1539				smu->custom_profile_params[idx + i] = custom_params[i];
1540		}
1541		ret = arcturus_set_power_profile_mode_coeff(smu,
1542							    smu->custom_profile_params);
1543		if (ret) {
1544			if (idx != -1)
1545				smu->custom_profile_params[idx] = 0;
1546			return ret;
1547		}
1548	} else if (smu->custom_profile_params) {
1549		memset(smu->custom_profile_params, 0, ARCTURUS_CUSTOM_PARAMS_SIZE);
1550	}
1551
1552	ret = smu_cmn_send_smc_msg_with_param(smu,
1553					      SMU_MSG_SetWorkloadMask,
1554					      backend_workload_mask,
1555					      NULL);
1556	if (ret) {
1557		dev_err(smu->adev->dev, "Failed to set workload mask 0x%08x\n",
1558			workload_mask);
1559		if (idx != -1)
1560			smu->custom_profile_params[idx] = 0;
1561		return ret;
1562	}
1563
1564	return ret;
1565}
1566
1567static int arcturus_set_performance_level(struct smu_context *smu,
1568					  enum amd_dpm_forced_level level)
1569{
1570	switch (level) {
1571	case AMD_DPM_FORCED_LEVEL_HIGH:
1572	case AMD_DPM_FORCED_LEVEL_LOW:
1573	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1574	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1575	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1576	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1577		if ((smu->smc_fw_version >= 0x361200) &&
1578		    (smu->smc_fw_version <= 0x361a00)) {
1579			dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1580			       "54.18 - 54.26(included) SMU firmwares\n");
1581			return -EOPNOTSUPP;
1582		}
1583		break;
1584	default:
1585		break;
1586	}
1587
1588	return smu_v11_0_set_performance_level(smu, level);
1589}
1590
1591static bool arcturus_is_dpm_running(struct smu_context *smu)
1592{
1593	int ret = 0;
1594	uint64_t feature_enabled;
1595
1596	ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1597	if (ret)
1598		return false;
1599
1600	return !!(feature_enabled & SMC_DPM_FEATURE);
1601}
1602
1603static int arcturus_dpm_set_vcn_enable(struct smu_context *smu,
1604					bool enable,
1605					int inst)
1606{
1607	int ret = 0;
1608
1609	if (enable) {
1610		if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
1611			ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 1);
1612			if (ret) {
1613				dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
1614				return ret;
1615			}
1616		}
1617	} else {
1618		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
1619			ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 0);
1620			if (ret) {
1621				dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
1622				return ret;
1623			}
1624		}
1625	}
1626
1627	return ret;
1628}
1629
1630static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
1631			     struct i2c_msg *msg, int num_msgs)
1632{
1633	struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
1634	struct amdgpu_device *adev = smu_i2c->adev;
1635	struct smu_context *smu = adev->powerplay.pp_handle;
1636	struct smu_table_context *smu_table = &smu->smu_table;
1637	struct smu_table *table = &smu_table->driver_table;
1638	SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
1639	int i, j, r, c;
1640	u16 dir;
1641
1642	if (!adev->pm.dpm_enabled)
1643		return -EBUSY;
1644
1645	req = kzalloc(sizeof(*req), GFP_KERNEL);
1646	if (!req)
1647		return -ENOMEM;
1648
1649	req->I2CcontrollerPort = smu_i2c->port;
1650	req->I2CSpeed = I2C_SPEED_FAST_400K;
1651	req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
1652	dir = msg[0].flags & I2C_M_RD;
1653
1654	for (c = i = 0; i < num_msgs; i++) {
1655		for (j = 0; j < msg[i].len; j++, c++) {
1656			SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
1657
1658			if (!(msg[i].flags & I2C_M_RD)) {
1659				/* write */
1660				cmd->Cmd = I2C_CMD_WRITE;
1661				cmd->RegisterAddr = msg[i].buf[j];
1662			}
1663
1664			if ((dir ^ msg[i].flags) & I2C_M_RD) {
1665				/* The direction changes.
1666				 */
1667				dir = msg[i].flags & I2C_M_RD;
1668				cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
1669			}
1670
1671			req->NumCmds++;
1672
1673			/*
1674			 * Insert STOP if we are at the last byte of either last
1675			 * message for the transaction or the client explicitly
1676			 * requires a STOP at this particular message.
1677			 */
1678			if ((j == msg[i].len - 1) &&
1679			    ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
1680				cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
1681				cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
1682			}
1683		}
1684	}
1685	mutex_lock(&adev->pm.mutex);
1686	r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
1687	if (r)
1688		goto fail;
1689
1690	for (c = i = 0; i < num_msgs; i++) {
1691		if (!(msg[i].flags & I2C_M_RD)) {
1692			c += msg[i].len;
1693			continue;
1694		}
1695		for (j = 0; j < msg[i].len; j++, c++) {
1696			SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
1697
1698			msg[i].buf[j] = cmd->Data;
1699		}
1700	}
1701	r = num_msgs;
1702fail:
1703	mutex_unlock(&adev->pm.mutex);
1704	kfree(req);
1705	return r;
1706}
1707
1708static u32 arcturus_i2c_func(struct i2c_adapter *adap)
1709{
1710	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1711}
1712
1713
1714static const struct i2c_algorithm arcturus_i2c_algo = {
1715	.master_xfer = arcturus_i2c_xfer,
1716	.functionality = arcturus_i2c_func,
1717};
1718
1719
1720static const struct i2c_adapter_quirks arcturus_i2c_control_quirks = {
1721	.flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
1722	.max_read_len  = MAX_SW_I2C_COMMANDS,
1723	.max_write_len = MAX_SW_I2C_COMMANDS,
1724	.max_comb_1st_msg_len = 2,
1725	.max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
1726};
1727
1728static int arcturus_i2c_control_init(struct smu_context *smu)
1729{
1730	struct amdgpu_device *adev = smu->adev;
1731	int res, i;
1732
1733	for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
1734		struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1735		struct i2c_adapter *control = &smu_i2c->adapter;
1736
1737		smu_i2c->adev = adev;
1738		smu_i2c->port = i;
1739		mutex_init(&smu_i2c->mutex);
1740		control->owner = THIS_MODULE;
1741		control->class = I2C_CLASS_HWMON;
1742		control->dev.parent = &adev->pdev->dev;
1743		control->algo = &arcturus_i2c_algo;
1744		control->quirks = &arcturus_i2c_control_quirks;
1745		snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
1746		i2c_set_adapdata(control, smu_i2c);
1747
1748		res = devm_i2c_add_adapter(adev->dev, control);
1749		if (res) {
1750			DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
1751			return res;
1752		}
1753	}
1754
1755	adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
1756	adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
1757
1758	return 0;
1759}
1760
1761static void arcturus_i2c_control_fini(struct smu_context *smu)
1762{
1763	struct amdgpu_device *adev = smu->adev;
1764
1765	adev->pm.ras_eeprom_i2c_bus = NULL;
1766	adev->pm.fru_eeprom_i2c_bus = NULL;
1767}
1768
1769static void arcturus_get_unique_id(struct smu_context *smu)
1770{
1771	struct amdgpu_device *adev = smu->adev;
1772	uint32_t top32 = 0, bottom32 = 0;
1773	uint64_t id;
1774
1775	/* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
1776	if (smu->smc_fw_version < 0x361700) {
1777		dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n");
1778		return;
1779	}
1780
1781	/* Get the SN to turn into a Unique ID */
1782	smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
1783	smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
1784
1785	id = ((uint64_t)bottom32 << 32) | top32;
1786	adev->unique_id = id;
1787}
1788
1789static int arcturus_set_df_cstate(struct smu_context *smu,
1790				  enum pp_df_cstate state)
1791{
1792	struct amdgpu_device *adev = smu->adev;
1793
1794	/*
1795	 * Arcturus does not need the cstate disablement
1796	 * prerequisite for gpu reset.
1797	 */
1798	if (amdgpu_in_reset(adev) || adev->in_suspend)
1799		return 0;
1800
1801	/* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
1802	if (smu->smc_fw_version < 0x360F00) {
1803		dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
1804		return -EINVAL;
1805	}
1806
1807	return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
1808}
1809
1810static const struct throttling_logging_label {
1811	uint32_t feature_mask;
1812	const char *label;
1813} logging_label[] = {
1814	{(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
1815	{(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
1816	{(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
1817	{(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
1818	{(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
1819	{(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"},
1820	{(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"},
1821};
1822static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
1823{
1824	int ret;
1825	int throttler_idx, throttling_events = 0, buf_idx = 0;
1826	struct amdgpu_device *adev = smu->adev;
1827	uint32_t throttler_status;
1828	char log_buf[256];
1829
1830	ret = arcturus_get_smu_metrics_data(smu,
1831					    METRICS_THROTTLER_STATUS,
1832					    &throttler_status);
1833	if (ret)
1834		return;
1835
1836	memset(log_buf, 0, sizeof(log_buf));
1837	for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
1838	     throttler_idx++) {
1839		if (throttler_status & logging_label[throttler_idx].feature_mask) {
1840			throttling_events++;
1841			buf_idx += snprintf(log_buf + buf_idx,
1842					    sizeof(log_buf) - buf_idx,
1843					    "%s%s",
1844					    throttling_events > 1 ? " and " : "",
1845					    logging_label[throttler_idx].label);
1846			if (buf_idx >= sizeof(log_buf)) {
1847				dev_err(adev->dev, "buffer overflow!\n");
1848				log_buf[sizeof(log_buf) - 1] = '\0';
1849				break;
1850			}
1851		}
1852	}
1853
1854	dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
1855			log_buf);
1856	kgd2kfd_smi_event_throttle(smu->adev->kfd.dev,
1857		smu_cmn_get_indep_throttler_status(throttler_status,
1858						   arcturus_throttler_map));
1859}
1860
1861static uint16_t arcturus_get_current_pcie_link_speed(struct smu_context *smu)
1862{
1863	struct amdgpu_device *adev = smu->adev;
1864	uint32_t esm_ctrl;
1865
1866	/* TODO: confirm this on real target */
1867	esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
1868	if ((esm_ctrl >> 15) & 0x1)
1869		return (uint16_t)(((esm_ctrl >> 8) & 0x7F) + 128);
1870
1871	return smu_v11_0_get_current_pcie_link_speed(smu);
1872}
1873
1874static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
1875					void **table)
1876{
1877	struct smu_table_context *smu_table = &smu->smu_table;
1878	struct gpu_metrics_v1_3 *gpu_metrics =
1879		(struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1880	SmuMetrics_t metrics;
1881	int ret = 0;
1882
1883	ret = smu_cmn_get_metrics_table(smu,
1884					&metrics,
1885					false);
1886	if (ret)
1887		return ret;
1888
1889	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1890
1891	gpu_metrics->temperature_edge = metrics.TemperatureEdge;
1892	gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
1893	gpu_metrics->temperature_mem = metrics.TemperatureHBM;
1894	gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
1895	gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
1896	gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
1897
1898	gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1899	gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
1900	gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
1901
1902	gpu_metrics->average_socket_power = metrics.AverageSocketPower;
1903	gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
1904
1905	gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1906	gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1907	gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
1908	gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
1909	gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
1910
1911	gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
1912	gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
1913	gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
1914	gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
1915	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
1916
1917	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1918	gpu_metrics->indep_throttle_status =
1919			smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1920							   arcturus_throttler_map);
1921
1922	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
1923
1924	gpu_metrics->pcie_link_width =
1925			smu_v11_0_get_current_pcie_link_width(smu);
1926	gpu_metrics->pcie_link_speed =
1927			arcturus_get_current_pcie_link_speed(smu);
1928
1929	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1930
1931	*table = (void *)gpu_metrics;
1932
1933	return sizeof(struct gpu_metrics_v1_3);
1934}
1935
1936static const struct pptable_funcs arcturus_ppt_funcs = {
1937	/* init dpm */
1938	.get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
1939	/* btc */
1940	.run_btc = arcturus_run_btc,
1941	/* dpm/clk tables */
1942	.set_default_dpm_table = arcturus_set_default_dpm_table,
1943	.populate_umd_state_clk = arcturus_populate_umd_state_clk,
1944	.get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
1945	.emit_clk_levels = arcturus_emit_clk_levels,
1946	.force_clk_levels = arcturus_force_clk_levels,
1947	.read_sensor = arcturus_read_sensor,
1948	.get_fan_speed_pwm = arcturus_get_fan_speed_pwm,
1949	.get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
1950	.get_power_profile_mode = arcturus_get_power_profile_mode,
1951	.set_power_profile_mode = arcturus_set_power_profile_mode,
1952	.set_performance_level = arcturus_set_performance_level,
1953	.get_power_limit = arcturus_get_power_limit,
1954	.is_dpm_running = arcturus_is_dpm_running,
1955	.dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
1956	.i2c_init = arcturus_i2c_control_init,
1957	.i2c_fini = arcturus_i2c_control_fini,
1958	.get_unique_id = arcturus_get_unique_id,
1959	.init_microcode = smu_v11_0_init_microcode,
1960	.load_microcode = smu_v11_0_load_microcode,
1961	.fini_microcode = smu_v11_0_fini_microcode,
1962	.init_smc_tables = arcturus_init_smc_tables,
1963	.fini_smc_tables = smu_v11_0_fini_smc_tables,
1964	.init_power = smu_v11_0_init_power,
1965	.fini_power = smu_v11_0_fini_power,
1966	.check_fw_status = smu_v11_0_check_fw_status,
1967	/* pptable related */
1968	.setup_pptable = arcturus_setup_pptable,
1969	.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
1970	.check_fw_version = smu_v11_0_check_fw_version,
1971	.write_pptable = smu_cmn_write_pptable,
1972	.set_driver_table_location = smu_v11_0_set_driver_table_location,
1973	.set_tool_table_location = smu_v11_0_set_tool_table_location,
1974	.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
1975	.system_features_control = smu_v11_0_system_features_control,
1976	.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1977	.send_smc_msg = smu_cmn_send_smc_msg,
1978	.init_display_count = NULL,
1979	.set_allowed_mask = smu_v11_0_set_allowed_mask,
1980	.get_enabled_mask = smu_cmn_get_enabled_mask,
1981	.feature_is_enabled = smu_cmn_feature_is_enabled,
1982	.disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
1983	.notify_display_change = NULL,
1984	.set_power_limit = smu_v11_0_set_power_limit,
1985	.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
1986	.enable_thermal_alert = smu_v11_0_enable_thermal_alert,
1987	.disable_thermal_alert = smu_v11_0_disable_thermal_alert,
1988	.set_min_dcef_deep_sleep = NULL,
1989	.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
1990	.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
1991	.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
1992	.set_fan_speed_pwm = arcturus_set_fan_speed_pwm,
1993	.set_fan_speed_rpm = arcturus_set_fan_speed_rpm,
1994	.set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
1995	.gfx_off_control = smu_v11_0_gfx_off_control,
1996	.register_irq_handler = smu_v11_0_register_irq_handler,
1997	.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
1998	.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
1999	.get_bamaco_support = smu_v11_0_get_bamaco_support,
2000	.baco_enter = smu_v11_0_baco_enter,
2001	.baco_exit = smu_v11_0_baco_exit,
2002	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2003	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2004	.set_df_cstate = arcturus_set_df_cstate,
2005	.log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
2006	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2007	.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2008	.get_gpu_metrics = arcturus_get_gpu_metrics,
2009	.gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2010	.deep_sleep_control = smu_v11_0_deep_sleep_control,
2011	.get_fan_parameters = arcturus_get_fan_parameters,
2012	.interrupt_work = smu_v11_0_interrupt_work,
2013	.smu_handle_passthrough_sbr = smu_v11_0_handle_passthrough_sbr,
2014	.set_mp1_state = smu_cmn_set_mp1_state,
2015};
2016
2017void arcturus_set_ppt_funcs(struct smu_context *smu)
2018{
2019	smu->ppt_funcs = &arcturus_ppt_funcs;
2020	smu->message_map = arcturus_message_map;
2021	smu->clock_map = arcturus_clk_map;
2022	smu->feature_map = arcturus_feature_mask_map;
2023	smu->table_map = arcturus_table_map;
2024	smu->pwr_src_map = arcturus_pwr_src_map;
2025	smu->workload_map = arcturus_workload_map;
2026	smu_v11_0_set_smu_mailbox_registers(smu);
2027}