smu_v14_0_2_pptable.h

  1/*
  2 * Copyright 2023 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23
 24#ifndef SMU_14_0_2_PPTABLE_H
 25#define SMU_14_0_2_PPTABLE_H
 26
 27
 28#pragma pack(push, 1)
 29
 30#define SMU_14_0_2_TABLE_FORMAT_REVISION 23
 31#define SMU_14_0_2_CUSTOM_TABLE_FORMAT_REVISION 1
 32
 33// POWERPLAYTABLE::ulPlatformCaps
 34#define SMU_14_0_2_PP_PLATFORM_CAP_POWERPLAY        0x1     // This cap indicates whether CCC need to show Powerplay page.
 35#define SMU_14_0_2_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2     // This cap indicates whether power source notificaiton is done by SBIOS instead of OS.
 36#define SMU_14_0_2_PP_PLATFORM_CAP_HARDWAREDC       0x4     // This cap indicates whether DC mode notificaiton is done by GPIO pin directly.
 37#define SMU_14_0_2_PP_PLATFORM_CAP_BACO             0x8     // This cap indicates whether board supports the BACO circuitry.
 38#define SMU_14_0_2_PP_PLATFORM_CAP_MACO             0x10    // This cap indicates whether board supports the MACO circuitry.
 39#define SMU_14_0_2_PP_PLATFORM_CAP_SHADOWPSTATE     0x20    // This cap indicates whether board supports the Shadow Pstate.
 40#define SMU_14_0_2_PP_PLATFORM_CAP_LEDSUPPORTED     0x40    // This cap indicates whether board supports the LED.
 41#define SMU_14_0_2_PP_PLATFORM_CAP_MOBILEOVERDRIVE  0x80    // This cap indicates whether board supports the Mobile Overdrive.
 42
 43// SMU_14_0_2_PP_THERMALCONTROLLER - Thermal Controller Type
 44#define SMU_14_0_2_PP_THERMALCONTROLLER_NONE        0
 45
 46#define SMU_14_0_2_PP_OVERDRIVE_VERSION             0x1     // TODO: FIX OverDrive Version TBD
 47#define SMU_14_0_2_PP_CUSTOM_OVERDRIVE_VERSION 0x1
 48#define SMU_14_0_2_PP_POWERSAVINGCLOCK_VERSION      0x01    // Power Saving Clock Table Version 1.00
 49
 50enum SMU_14_0_2_OD_SW_FEATURE_CAP
 51{
 52    SMU_14_0_2_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT        = 0,
 53    SMU_14_0_2_ODCAP_POWER_MODE                     = 1,
 54    SMU_14_0_2_ODCAP_AUTO_UV_ENGINE                 = 2,
 55    SMU_14_0_2_ODCAP_AUTO_OC_ENGINE                 = 3,
 56    SMU_14_0_2_ODCAP_AUTO_OC_MEMORY                 = 4,
 57    SMU_14_0_2_ODCAP_MEMORY_TIMING_TUNE             = 5,
 58    SMU_14_0_2_ODCAP_MANUAL_AC_TIMING               = 6,
 59    SMU_14_0_2_ODCAP_AUTO_VF_CURVE_OPTIMIZER        = 7,
 60    SMU_14_0_2_ODCAP_AUTO_SOC_UV                    = 8,
 61    SMU_14_0_2_ODCAP_COUNT                          = 9,
 62};
 63
 64enum SMU_14_0_2_OD_SW_FEATURE_ID
 65{
 66    SMU_14_0_2_ODFEATURE_AUTO_FAN_ACOUSTIC_LIMIT      = 1 << SMU_14_0_2_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT,      // Auto Fan Acoustic RPM
 67    SMU_14_0_2_ODFEATURE_POWER_MODE                   = 1 << SMU_14_0_2_ODCAP_POWER_MODE,                   // Optimized GPU Power Mode
 68    SMU_14_0_2_ODFEATURE_AUTO_UV_ENGINE               = 1 << SMU_14_0_2_ODCAP_AUTO_UV_ENGINE,               // Auto Under Volt GFXCLK
 69    SMU_14_0_2_ODFEATURE_AUTO_OC_ENGINE               = 1 << SMU_14_0_2_ODCAP_AUTO_OC_ENGINE,               // Auto Over Clock GFXCLK
 70    SMU_14_0_2_ODFEATURE_AUTO_OC_MEMORY               = 1 << SMU_14_0_2_ODCAP_AUTO_OC_MEMORY,               // Auto Over Clock MCLK
 71    SMU_14_0_2_ODFEATURE_MEMORY_TIMING_TUNE           = 1 << SMU_14_0_2_ODCAP_MEMORY_TIMING_TUNE,           // Auto AC Timing Tuning
 72    SMU_14_0_2_ODFEATURE_MANUAL_AC_TIMING             = 1 << SMU_14_0_2_ODCAP_MANUAL_AC_TIMING,             // Manual fine grain AC Timing tuning
 73    SMU_14_0_2_ODFEATURE_AUTO_VF_CURVE_OPTIMIZER      = 1 << SMU_14_0_2_ODCAP_AUTO_VF_CURVE_OPTIMIZER,      // Fine grain auto VF curve tuning
 74    SMU_14_0_2_ODFEATURE_AUTO_SOC_UV                  = 1 << SMU_14_0_2_ODCAP_AUTO_SOC_UV,                  // Auto Unver Volt VDDSOC
 75};
 76
 77#define SMU_14_0_2_MAX_ODFEATURE 32 // Maximum Number of OD Features
 78
 79enum SMU_14_0_2_OD_SW_FEATURE_SETTING_ID
 80{
 81    SMU_14_0_2_ODSETTING_AUTO_FAN_ACOUSTIC_LIMIT    = 0,
 82    SMU_14_0_2_ODSETTING_POWER_MODE                 = 1,
 83    SMU_14_0_2_ODSETTING_AUTOUVENGINE               = 2,
 84    SMU_14_0_2_ODSETTING_AUTOOCENGINE               = 3,
 85    SMU_14_0_2_ODSETTING_AUTOOCMEMORY               = 4,
 86    SMU_14_0_2_ODSETTING_ACTIMING                   = 5,
 87    SMU_14_0_2_ODSETTING_MANUAL_AC_TIMING           = 6,
 88    SMU_14_0_2_ODSETTING_AUTO_VF_CURVE_OPTIMIZER    = 7,
 89    SMU_14_0_2_ODSETTING_AUTO_SOC_UV                = 8,
 90    SMU_14_0_2_ODSETTING_COUNT                      = 9,
 91};
 92#define SMU_14_0_2_MAX_ODSETTING 64 // Maximum Number of ODSettings
 93
 94enum SMU_14_0_2_PWRMODE_SETTING
 95{
 96    SMU_14_0_2_PMSETTING_POWER_LIMIT_QUIET = 0,
 97    SMU_14_0_2_PMSETTING_POWER_LIMIT_BALANCE,
 98    SMU_14_0_2_PMSETTING_POWER_LIMIT_TURBO,
 99    SMU_14_0_2_PMSETTING_POWER_LIMIT_RAGE,
100    SMU_14_0_2_PMSETTING_ACOUSTIC_TEMP_QUIET,
101    SMU_14_0_2_PMSETTING_ACOUSTIC_TEMP_BALANCE,
102    SMU_14_0_2_PMSETTING_ACOUSTIC_TEMP_TURBO,
103    SMU_14_0_2_PMSETTING_ACOUSTIC_TEMP_RAGE,
104    SMU_14_0_2_PMSETTING_ACOUSTIC_TARGET_RPM_QUIET,
105    SMU_14_0_2_PMSETTING_ACOUSTIC_TARGET_RPM_BALANCE,
106    SMU_14_0_2_PMSETTING_ACOUSTIC_TARGET_RPM_TURBO,
107    SMU_14_0_2_PMSETTING_ACOUSTIC_TARGET_RPM_RAGE,
108    SMU_14_0_2_PMSETTING_ACOUSTIC_LIMIT_RPM_QUIET,
109    SMU_14_0_2_PMSETTING_ACOUSTIC_LIMIT_RPM_BALANCE,
110    SMU_14_0_2_PMSETTING_ACOUSTIC_LIMIT_RPM_TURBO,
111    SMU_14_0_2_PMSETTING_ACOUSTIC_LIMIT_RPM_RAGE,
112	SMU_14_0_2_PMSETTING_COUNT
113};
114#define SMU_14_0_2_MAX_PMSETTING 32 // Maximum Number of PowerMode Settings
115
116enum SMU_14_0_2_overdrive_table_id
117{
118    SMU_14_0_2_OVERDRIVE_TABLE_BASIC    = 0,
119    SMU_14_0_2_OVERDRIVE_TABLE_ADVANCED = 1,
120    SMU_14_0_2_OVERDRIVE_TABLE_COUNT    = 2,
121};
122
123struct smu_14_0_2_overdrive_table
124{
125    uint8_t revision;                                                           // Revision = SMU_14_0_2_PP_OVERDRIVE_VERSION
126    uint8_t reserve[3];                                                         // Zero filled field reserved for future use
127    uint8_t cap[SMU_14_0_2_OVERDRIVE_TABLE_COUNT][SMU_14_0_2_MAX_ODFEATURE];    // OD feature support flags
128    int32_t max[SMU_14_0_2_OVERDRIVE_TABLE_COUNT][SMU_14_0_2_MAX_ODSETTING];    // maximum settings
129    int32_t min[SMU_14_0_2_OVERDRIVE_TABLE_COUNT][SMU_14_0_2_MAX_ODSETTING];    // minimum settings
130    int16_t pm_setting[SMU_14_0_2_MAX_PMSETTING];                               // Optimized power mode feature settings
131};
132
133enum smu_14_0_3_pptable_source {
134	PPTABLE_SOURCE_IFWI             = 0,
135	PPTABLE_SOURCE_DRIVER_HARDCODED = 1,
136	PPTABLE_SOURCE_PPGEN_REGISTRY   = 2,
137	PPTABLE_SOURCE_MAX              = PPTABLE_SOURCE_PPGEN_REGISTRY,
138};
139
140struct smu_14_0_2_powerplay_table
141{
142    struct atom_common_table_header header;                 // header.format_revision = 3 (HAS TO MATCH SMU_14_0_2_TABLE_FORMAT_REVISION), header.content_revision = ? structuresize is calculated by PPGen.
143    uint8_t table_revision;                                 // PPGen use only: table_revision = 3
144	uint8_t pptable_source;                      			// PPGen UI dropdown box
145    uint16_t pmfw_pptable_start_offset;                     // The start offset of the pmfw portion. i.e. start of PPTable_t (start of SkuTable_t)
146    uint16_t pmfw_pptable_size;                             // The total size of pmfw_pptable, i.e PPTable_t.
147	uint16_t pmfw_sku_table_start_offset;        			// DO NOT CHANGE ORDER; The absolute start offset of the SkuTable_t (within smu_14_0_3_powerplay_table).
148	uint16_t pmfw_sku_table_size;                			// DO NOT CHANGE ORDER; The size of SkuTable_t.
149	uint16_t pmfw_board_table_start_offset;                 // The start offset of the BoardTable_t
150	uint16_t pmfw_board_table_size;                         // The size of BoardTable_t.
151    uint16_t pmfw_custom_sku_table_start_offset;            // The start offset of the CustomSkuTable_t within pmfw_pptable.
152    uint16_t pmfw_custom_sku_table_size;                    // The size of the CustomSkuTable_t.
153    uint32_t golden_pp_id;                                  // PPGen use only: PP Table ID on the Golden Data Base
154    uint32_t golden_revision;                               // PPGen use only: PP Table Revision on the Golden Data Base
155    uint16_t format_id;                                     // PPGen use only: PPTable for different ASICs.
156    uint32_t platform_caps;                                 // POWERPLAYTABLE::ulPlatformCaps
157
158    uint8_t thermal_controller_type;                        // one of smu_14_0_2_PP_THERMALCONTROLLER
159
160    uint16_t small_power_limit1;
161    uint16_t small_power_limit2;
162    uint16_t boost_power_limit;                             // For Gemini Board, when the slave adapter is in BACO mode, the master adapter will use this boost power limit instead of the default power limit to boost the power limit.
163    uint16_t software_shutdown_temp;
164
165    uint8_t reserve[143];                                   // Zero filled field reserved for future use
166
167    struct smu_14_0_2_overdrive_table overdrive_table;
168
169    PPTable_t smc_pptable;                          // PPTable_t in driver_if.h -- as requested by PMFW, this offset should start at a 32-byte boundary, and the table_size above should remain at offset=6 bytes
170};
171
172enum SMU_14_0_2_CUSTOM_OD_SW_FEATURE_CAP {
173    SMU_14_0_2_CUSTOM_ODCAP_POWER_MODE = 0,
174	SMU_14_0_2_CUSTOM_ODCAP_COUNT
175};
176
177enum SMU_14_0_2_CUSTOM_OD_FEATURE_SETTING_ID {
178	SMU_14_0_2_CUSTOM_ODSETTING_POWER_MODE = 0,
179	SMU_14_0_2_CUSTOM_ODSETTING_COUNT,
180};
181
182struct smu_14_0_2_custom_overdrive_table {
183	uint8_t revision;
184	uint8_t reserve[3];
185	uint8_t cap[SMU_14_0_2_CUSTOM_ODCAP_COUNT];
186	int32_t max[SMU_14_0_2_CUSTOM_ODSETTING_COUNT];
187	int32_t min[SMU_14_0_2_CUSTOM_ODSETTING_COUNT];
188	int16_t pm_setting[SMU_14_0_2_PMSETTING_COUNT];
189};
190
191struct smu_14_0_3_custom_powerplay_table {
192    uint8_t custom_table_revision;
193    uint16_t custom_table_size;
194    uint16_t custom_sku_table_offset;
195    uint32_t custom_platform_caps;
196    uint16_t software_shutdown_temp;
197    struct smu_14_0_2_custom_overdrive_table custom_overdrive_table;
198    uint32_t reserve[8];
199    CustomSkuTable_t custom_sku_table_pmfw;
200};
201
202#pragma pack(pop)
203
204#endif