smu_v14_0.h

  1/*
  2 * Copyright 2023 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23#ifndef __SMU_V14_0_H__
 24#define __SMU_V14_0_H__
 25
 26#include "amdgpu_smu.h"
 27
 28#define SMU14_DRIVER_IF_VERSION_INV 0xFFFFFFFF
 29#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_0 0x7
 30#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_1 0x6
 31#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_2 0x2E
 32
 33#define FEATURE_MASK(feature) (1ULL << feature)
 34
 35/* MP Apertures */
 36#define MP0_Public			0x03800000
 37#define MP0_SRAM			0x03900000
 38#define MP1_Public			0x03b00000
 39#define MP1_SRAM			0x03c00004
 40
 41/* address block */
 42#define smnMP1_FIRMWARE_FLAGS_14_0_0	0x3010028
 43#define smnMP1_FIRMWARE_FLAGS		0x3010024
 44#define smnMP1_PUB_CTRL			0x3010d10
 45
 46#define MAX_DPM_LEVELS 16
 47#define MAX_PCIE_CONF 3
 48
 49#define SMU14_TOOL_SIZE			0x19000
 50
 51#define CTF_OFFSET_EDGE			5
 52#define CTF_OFFSET_HOTSPOT		5
 53#define CTF_OFFSET_MEM			5
 54
 55extern const int decoded_link_speed[5];
 56extern const int decoded_link_width[8];
 57
 58#define DECODE_GEN_SPEED(gen_speed_idx)		(decoded_link_speed[gen_speed_idx])
 59#define DECODE_LANE_WIDTH(lane_width_idx)	(decoded_link_width[lane_width_idx])
 60#define SMU_V14_SOFT_FREQ_ROUND(x)	((x) + 1)
 61
 62struct smu_14_0_max_sustainable_clocks {
 63	uint32_t display_clock;
 64	uint32_t phy_clock;
 65	uint32_t pixel_clock;
 66	uint32_t uclock;
 67	uint32_t dcef_clock;
 68	uint32_t soc_clock;
 69};
 70
 71struct smu_14_0_dpm_clk_level {
 72	bool				enabled;
 73	uint32_t			value;
 74};
 75
 76struct smu_14_0_dpm_table {
 77	uint32_t			min;        /* MHz */
 78	uint32_t			max;        /* MHz */
 79	uint32_t			count;
 80	bool				is_fine_grained;
 81	struct smu_14_0_dpm_clk_level	dpm_levels[MAX_DPM_LEVELS];
 82};
 83
 84struct smu_14_0_pcie_table {
 85	uint8_t  pcie_gen[MAX_PCIE_CONF];
 86	uint8_t  pcie_lane[MAX_PCIE_CONF];
 87	uint16_t clk_freq[MAX_PCIE_CONF];
 88	uint32_t num_of_link_levels;
 89};
 90
 91struct smu_14_0_dpm_tables {
 92	struct smu_14_0_dpm_table        soc_table;
 93	struct smu_14_0_dpm_table        gfx_table;
 94	struct smu_14_0_dpm_table        uclk_table;
 95	struct smu_14_0_dpm_table        eclk_table;
 96	struct smu_14_0_dpm_table        vclk_table;
 97	struct smu_14_0_dpm_table        dclk_table;
 98	struct smu_14_0_dpm_table        dcef_table;
 99	struct smu_14_0_dpm_table        pixel_table;
100	struct smu_14_0_dpm_table        display_table;
101	struct smu_14_0_dpm_table        phy_table;
102	struct smu_14_0_dpm_table        fclk_table;
103	struct smu_14_0_pcie_table       pcie_table;
104};
105
106struct smu_14_0_dpm_context {
107	struct smu_14_0_dpm_tables  dpm_tables;
108	uint32_t                    workload_policy_mask;
109	uint32_t                    dcef_min_ds_clk;
110};
111
112enum smu_14_0_power_state {
113	SMU_14_0_POWER_STATE__D0 = 0,
114	SMU_14_0_POWER_STATE__D1,
115	SMU_14_0_POWER_STATE__D3, /* Sleep*/
116	SMU_14_0_POWER_STATE__D4, /* Hibernate*/
117	SMU_14_0_POWER_STATE__D5, /* Power off*/
118};
119
120struct smu_14_0_power_context {
121	uint32_t	power_source;
122	uint8_t		in_power_limit_boost_mode;
123	enum smu_14_0_power_state power_state;
124};
125
126#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
127
128int smu_v14_0_init_microcode(struct smu_context *smu);
129
130void smu_v14_0_fini_microcode(struct smu_context *smu);
131
132int smu_v14_0_load_microcode(struct smu_context *smu);
133
134int smu_v14_0_init_smc_tables(struct smu_context *smu);
135
136int smu_v14_0_fini_smc_tables(struct smu_context *smu);
137
138int smu_v14_0_init_power(struct smu_context *smu);
139
140int smu_v14_0_fini_power(struct smu_context *smu);
141
142int smu_v14_0_check_fw_status(struct smu_context *smu);
143
144int smu_v14_0_setup_pptable(struct smu_context *smu);
145
146int smu_v14_0_get_vbios_bootup_values(struct smu_context *smu);
147
148int smu_v14_0_check_fw_version(struct smu_context *smu);
149
150int smu_v14_0_set_driver_table_location(struct smu_context *smu);
151
152int smu_v14_0_set_tool_table_location(struct smu_context *smu);
153
154int smu_v14_0_notify_memory_pool_location(struct smu_context *smu);
155
156int smu_v14_0_system_features_control(struct smu_context *smu,
157				      bool en);
158
159int smu_v14_0_set_allowed_mask(struct smu_context *smu);
160
161int smu_v14_0_notify_display_change(struct smu_context *smu);
162
163int smu_v14_0_get_current_power_limit(struct smu_context *smu,
164				      uint32_t *power_limit);
165
166int smu_v14_0_set_power_limit(struct smu_context *smu,
167			      enum smu_ppt_limit_type limit_type,
168			      uint32_t limit);
169
170int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable);
171
172int smu_v14_0_register_irq_handler(struct smu_context *smu);
173
174int smu_v14_0_baco_set_armd3_sequence(struct smu_context *smu,
175				      enum smu_baco_seq baco_seq);
176
177int smu_v14_0_get_bamaco_support(struct smu_context *smu);
178
179enum smu_baco_state smu_v14_0_baco_get_state(struct smu_context *smu);
180
181int smu_v14_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
182
183int smu_v14_0_baco_enter(struct smu_context *smu);
184int smu_v14_0_baco_exit(struct smu_context *smu);
185
186int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
187				    uint32_t *min, uint32_t *max);
188
189int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
190					  uint32_t min, uint32_t max, bool automatic);
191
192int smu_v14_0_set_hard_freq_limited_range(struct smu_context *smu,
193					  enum smu_clk_type clk_type,
194					  uint32_t min,
195					  uint32_t max);
196
197int smu_v14_0_set_performance_level(struct smu_context *smu,
198				    enum amd_dpm_forced_level level);
199
200int smu_v14_0_set_power_source(struct smu_context *smu,
201			       enum smu_power_src_type power_src);
202
203int smu_v14_0_set_single_dpm_table(struct smu_context *smu,
204				   enum smu_clk_type clk_type,
205				   struct smu_14_0_dpm_table *single_dpm_table);
206
207int smu_v14_0_gfx_ulv_control(struct smu_context *smu,
208			      bool enablement);
209
210int smu_v14_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
211			     uint64_t event_arg);
212
213int smu_v14_0_set_vcn_enable(struct smu_context *smu,
214			      bool enable,
215			      int inst);
216
217int smu_v14_0_set_jpeg_enable(struct smu_context *smu,
218			      bool enable);
219
220int smu_v14_0_init_pptable_microcode(struct smu_context *smu);
221
222int smu_v14_0_run_btc(struct smu_context *smu);
223
224int smu_v14_0_gpo_control(struct smu_context *smu,
225			  bool enablement);
226
227int smu_v14_0_deep_sleep_control(struct smu_context *smu,
228				 bool enablement);
229
230int smu_v14_0_set_gfx_power_up_by_imu(struct smu_context *smu);
231
232int smu_v14_0_set_default_dpm_tables(struct smu_context *smu);
233
234int smu_v14_0_get_pptable_from_firmware(struct smu_context *smu,
235					void **table,
236					uint32_t *size,
237					uint32_t pptable_id);
238
239int smu_v14_0_od_edit_dpm_table(struct smu_context *smu,
240				enum PP_OD_DPM_TABLE_COMMAND type,
241				long input[], uint32_t size);
242
243void smu_v14_0_set_smu_mailbox_registers(struct smu_context *smu);
244
245int smu_v14_0_enable_thermal_alert(struct smu_context *smu);
246
247int smu_v14_0_disable_thermal_alert(struct smu_context *smu);
248
249#endif
250#endif