smu_v13_0.h

  1/*
  2 * Copyright 2020 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23#ifndef __SMU_V13_0_H__
 24#define __SMU_V13_0_H__
 25
 26#include "amdgpu_smu.h"
 27
 28#define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms
 29
 30/* MP Apertures */
 31#define MP0_Public			0x03800000
 32#define MP0_SRAM			0x03900000
 33#define MP1_Public			0x03b00000
 34#define MP1_SRAM			0x03c00004
 35
 36/* address block */
 37#define smnMP1_FIRMWARE_FLAGS		0x3010024
 38#define smnMP1_V13_0_4_FIRMWARE_FLAGS	0x3010028
 39#define smnMP0_FW_INTF			0x30101c0
 40#define smnMP1_PUB_CTRL			0x3010b14
 41
 42#define TEMP_RANGE_MIN			(0)
 43#define TEMP_RANGE_MAX			(80 * 1000)
 44
 45#define SMU13_TOOL_SIZE			0x19000
 46
 47#define MAX_DPM_LEVELS 16
 48#define MAX_PCIE_CONF 3
 49
 50#define CTF_OFFSET_EDGE			5
 51#define CTF_OFFSET_HOTSPOT		5
 52#define CTF_OFFSET_MEM			5
 53
 54#define SMU_13_VCLK_SHIFT		16
 55
 56#define SMUQ10_TO_UINT(x) ((x) >> 10)
 57#define SMUQ10_FRAC(x) ((x) & 0x3ff)
 58#define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >= 0x200))
 59#define SMU_V13_SOFT_FREQ_ROUND(x)	((x) + 1)
 60
 61extern const int pmfw_decoded_link_speed[5];
 62extern const int pmfw_decoded_link_width[7];
 63
 64#define DECODE_GEN_SPEED(gen_speed_idx)		(pmfw_decoded_link_speed[gen_speed_idx])
 65#define DECODE_LANE_WIDTH(lane_width_idx)	(pmfw_decoded_link_width[lane_width_idx])
 66
 67struct smu_13_0_max_sustainable_clocks {
 68	uint32_t display_clock;
 69	uint32_t phy_clock;
 70	uint32_t pixel_clock;
 71	uint32_t uclock;
 72	uint32_t dcef_clock;
 73	uint32_t soc_clock;
 74};
 75
 76struct smu_13_0_dpm_clk_level {
 77	bool				enabled;
 78	uint32_t			value;
 79};
 80
 81struct smu_13_0_dpm_table {
 82	uint32_t			min;        /* MHz */
 83	uint32_t			max;        /* MHz */
 84	uint32_t			count;
 85	bool				is_fine_grained;
 86	struct smu_13_0_dpm_clk_level	dpm_levels[MAX_DPM_LEVELS];
 87};
 88
 89struct smu_13_0_pcie_table {
 90	uint8_t  pcie_gen[MAX_PCIE_CONF];
 91	uint8_t  pcie_lane[MAX_PCIE_CONF];
 92	uint16_t clk_freq[MAX_PCIE_CONF];
 93	uint32_t num_of_link_levels;
 94};
 95
 96struct smu_13_0_dpm_tables {
 97	struct smu_13_0_dpm_table        soc_table;
 98	struct smu_13_0_dpm_table        gfx_table;
 99	struct smu_13_0_dpm_table        uclk_table;
100	struct smu_13_0_dpm_table        eclk_table;
101	struct smu_13_0_dpm_table        vclk_table;
102	struct smu_13_0_dpm_table        dclk_table;
103	struct smu_13_0_dpm_table        dcef_table;
104	struct smu_13_0_dpm_table        pixel_table;
105	struct smu_13_0_dpm_table        display_table;
106	struct smu_13_0_dpm_table        phy_table;
107	struct smu_13_0_dpm_table        fclk_table;
108	struct smu_13_0_pcie_table       pcie_table;
109};
110
111struct smu_13_0_dpm_context {
112	struct smu_13_0_dpm_tables  dpm_tables;
113	uint32_t                    workload_policy_mask;
114	uint32_t                    dcef_min_ds_clk;
115	uint64_t                    caps;
116	uint32_t                    board_volt;
117};
118
119enum smu_13_0_power_state {
120	SMU_13_0_POWER_STATE__D0 = 0,
121	SMU_13_0_POWER_STATE__D1,
122	SMU_13_0_POWER_STATE__D3, /* Sleep*/
123	SMU_13_0_POWER_STATE__D4, /* Hibernate*/
124	SMU_13_0_POWER_STATE__D5, /* Power off*/
125};
126
127struct smu_13_0_power_context {
128	uint32_t	power_source;
129	uint8_t		in_power_limit_boost_mode;
130	enum smu_13_0_power_state power_state;
131	atomic_t	throttle_status;
132};
133
134#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
135
136int smu_v13_0_init_microcode(struct smu_context *smu);
137
138void smu_v13_0_fini_microcode(struct smu_context *smu);
139
140int smu_v13_0_load_microcode(struct smu_context *smu);
141
142int smu_v13_0_init_smc_tables(struct smu_context *smu);
143
144int smu_v13_0_fini_smc_tables(struct smu_context *smu);
145
146int smu_v13_0_init_power(struct smu_context *smu);
147
148int smu_v13_0_fini_power(struct smu_context *smu);
149
150int smu_v13_0_check_fw_status(struct smu_context *smu);
151
152int smu_v13_0_setup_pptable(struct smu_context *smu);
153
154int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu);
155
156int smu_v13_0_check_fw_version(struct smu_context *smu);
157
158int smu_v13_0_set_driver_table_location(struct smu_context *smu);
159
160int smu_v13_0_set_tool_table_location(struct smu_context *smu);
161
162int smu_v13_0_notify_memory_pool_location(struct smu_context *smu);
163
164int smu_v13_0_system_features_control(struct smu_context *smu,
165				      bool en);
166
167int smu_v13_0_set_allowed_mask(struct smu_context *smu);
168
169int smu_v13_0_notify_display_change(struct smu_context *smu);
170
171int smu_v13_0_get_current_power_limit(struct smu_context *smu,
172				      uint32_t *power_limit);
173
174int smu_v13_0_set_power_limit(struct smu_context *smu,
175			      enum smu_ppt_limit_type limit_type,
176			      uint32_t limit);
177
178int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu);
179
180int smu_v13_0_enable_thermal_alert(struct smu_context *smu);
181
182int smu_v13_0_disable_thermal_alert(struct smu_context *smu);
183
184int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);
185
186uint32_t
187smu_v13_0_get_fan_control_mode(struct smu_context *smu);
188
189int
190smu_v13_0_set_fan_control_mode(struct smu_context *smu,
191			       uint32_t mode);
192
193int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
194				uint32_t speed);
195
196int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
197				uint32_t speed);
198
199int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
200			      uint32_t pstate);
201
202int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable);
203
204int smu_v13_0_register_irq_handler(struct smu_context *smu);
205
206int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu);
207
208int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
209					       struct pp_smu_nv_clock_table *max_clocks);
210
211int smu_v13_0_get_bamaco_support(struct smu_context *smu);
212
213int smu_v13_0_baco_enter(struct smu_context *smu);
214int smu_v13_0_baco_exit(struct smu_context *smu);
215
216int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
217				    uint32_t *min, uint32_t *max);
218
219int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
220					  uint32_t min, uint32_t max, bool automatic);
221
222int smu_v13_0_set_performance_level(struct smu_context *smu,
223				    enum amd_dpm_forced_level level);
224
225int smu_v13_0_set_power_source(struct smu_context *smu,
226			       enum smu_power_src_type power_src);
227
228int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
229				   enum smu_clk_type clk_type,
230				   struct smu_13_0_dpm_table *single_dpm_table);
231
232int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
233				    enum smu_clk_type clk_type, uint16_t level,
234				    uint32_t *value);
235
236int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu);
237
238int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu);
239
240int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu);
241
242int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu);
243
244int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
245			      bool enablement);
246
247int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
248			     uint64_t event_arg);
249
250int smu_v13_0_set_vcn_enable(struct smu_context *smu,
251			      bool enable,
252			      int inst);
253
254int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
255			      bool enable);
256
257int smu_v13_0_init_pptable_microcode(struct smu_context *smu);
258
259int smu_v13_0_run_btc(struct smu_context *smu);
260
261int smu_v13_0_gpo_control(struct smu_context *smu,
262			  bool enablement);
263
264int smu_v13_0_deep_sleep_control(struct smu_context *smu,
265				 bool enablement);
266
267int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu);
268
269int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
270				enum PP_OD_DPM_TABLE_COMMAND type,
271				long input[],
272				uint32_t size);
273
274int smu_v13_0_set_default_dpm_tables(struct smu_context *smu);
275
276void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu);
277
278int smu_v13_0_mode1_reset(struct smu_context *smu);
279
280int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
281					void **table,
282					uint32_t *size,
283					uint32_t pptable_id);
284
285int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
286				     uint8_t pcie_gen_cap,
287				     uint8_t pcie_width_cap);
288
289int smu_v13_0_disable_pmfw_state(struct smu_context *smu);
290
291int smu_v13_0_enable_uclk_shadow(struct smu_context *smu, bool enable);
292
293int smu_v13_0_set_wbrf_exclusion_ranges(struct smu_context *smu,
294						 struct freq_band_range *exclusion_ranges);
295
296int smu_v13_0_get_boot_freq_by_index(struct smu_context *smu,
297				     enum smu_clk_type clk_type,
298				     uint32_t *value);
299
300void smu_v13_0_interrupt_work(struct smu_context *smu);
301void smu_v13_0_reset_custom_level(struct smu_context *smu);
302#endif
303#endif