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amdgpu_smu.c
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linux-6.19.14/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
1/* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23#define SWSMU_CODE_LAYER_L1 24 25#include <linux/firmware.h> 26#include <linux/pci.h> 27#include <linux/power_supply.h> 28#include <linux/reboot.h> 29 30#include "amdgpu.h" 31#include "amdgpu_smu.h" 32#include "smu_internal.h" 33#include "atom.h" 34#include "arcturus_ppt.h" 35#include "navi10_ppt.h" 36#include "sienna_cichlid_ppt.h" 37#include "renoir_ppt.h" 38#include "vangogh_ppt.h" 39#include "aldebaran_ppt.h" 40#include "yellow_carp_ppt.h" 41#include "cyan_skillfish_ppt.h" 42#include "smu_v13_0_0_ppt.h" 43#include "smu_v13_0_4_ppt.h" 44#include "smu_v13_0_5_ppt.h" 45#include "smu_v13_0_6_ppt.h" 46#include "smu_v13_0_7_ppt.h" 47#include "smu_v14_0_0_ppt.h" 48#include "smu_v14_0_2_ppt.h" 49#include "amd_pcie.h" 50 51/* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56#undef pr_err 57#undef pr_warn 58#undef pr_info 59#undef pr_debug 60 61static const struct amd_pm_funcs swsmu_pm_funcs; 62static int smu_force_smuclk_levels(struct smu_context *smu, 63 enum smu_clk_type clk_type, 64 uint32_t mask); 65static int smu_handle_task(struct smu_context *smu, 66 enum amd_dpm_forced_level level, 67 enum amd_pp_task task_id); 68static int smu_reset(struct smu_context *smu); 69static int smu_set_fan_speed_pwm(void *handle, u32 speed); 70static int smu_set_fan_control_mode(void *handle, u32 value); 71static int smu_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit); 72static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 73static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 74static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 75static void smu_power_profile_mode_get(struct smu_context *smu, 76 enum PP_SMC_POWER_PROFILE profile_mode); 77static void smu_power_profile_mode_put(struct smu_context *smu, 78 enum PP_SMC_POWER_PROFILE profile_mode); 79static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type); 80static int smu_od_edit_dpm_table(void *handle, 81 enum PP_OD_DPM_TABLE_COMMAND type, 82 long *input, uint32_t size); 83 84static int smu_sys_get_pp_feature_mask(void *handle, 85 char *buf) 86{ 87 struct smu_context *smu = handle; 88 89 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 90 return -EOPNOTSUPP; 91 92 return smu_get_pp_feature_mask(smu, buf); 93} 94 95static int smu_sys_set_pp_feature_mask(void *handle, 96 uint64_t new_mask) 97{ 98 struct smu_context *smu = handle; 99 100 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 101 return -EOPNOTSUPP; 102 103 return smu_set_pp_feature_mask(smu, new_mask); 104} 105 106int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 107{ 108 if (!smu->ppt_funcs->set_gfx_off_residency) 109 return -EINVAL; 110 111 return smu_set_gfx_off_residency(smu, value); 112} 113 114int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 115{ 116 if (!smu->ppt_funcs->get_gfx_off_residency) 117 return -EINVAL; 118 119 return smu_get_gfx_off_residency(smu, value); 120} 121 122int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 123{ 124 if (!smu->ppt_funcs->get_gfx_off_entrycount) 125 return -EINVAL; 126 127 return smu_get_gfx_off_entrycount(smu, value); 128} 129 130int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 131{ 132 if (!smu->ppt_funcs->get_gfx_off_status) 133 return -EINVAL; 134 135 *value = smu_get_gfx_off_status(smu); 136 137 return 0; 138} 139 140int smu_set_soft_freq_range(struct smu_context *smu, 141 enum pp_clock_type type, 142 uint32_t min, 143 uint32_t max) 144{ 145 enum smu_clk_type clk_type; 146 int ret = 0; 147 148 clk_type = smu_convert_to_smuclk(type); 149 if (clk_type == SMU_CLK_COUNT) 150 return -EINVAL; 151 152 if (smu->ppt_funcs->set_soft_freq_limited_range) 153 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 154 clk_type, 155 min, 156 max, 157 false); 158 159 return ret; 160} 161 162int smu_get_dpm_freq_range(struct smu_context *smu, 163 enum smu_clk_type clk_type, 164 uint32_t *min, 165 uint32_t *max) 166{ 167 int ret = -ENOTSUPP; 168 169 if (!min && !max) 170 return -EINVAL; 171 172 if (smu->ppt_funcs->get_dpm_ultimate_freq) 173 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 174 clk_type, 175 min, 176 max); 177 178 return ret; 179} 180 181int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 182{ 183 int ret = 0; 184 struct amdgpu_device *adev = smu->adev; 185 186 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 187 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 188 if (ret) 189 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 190 } 191 return ret; 192} 193 194static u32 smu_get_mclk(void *handle, bool low) 195{ 196 struct smu_context *smu = handle; 197 uint32_t clk_freq; 198 int ret = 0; 199 200 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 201 low ? &clk_freq : NULL, 202 !low ? &clk_freq : NULL); 203 if (ret) 204 return 0; 205 return clk_freq * 100; 206} 207 208static u32 smu_get_sclk(void *handle, bool low) 209{ 210 struct smu_context *smu = handle; 211 uint32_t clk_freq; 212 int ret = 0; 213 214 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 215 low ? &clk_freq : NULL, 216 !low ? &clk_freq : NULL); 217 if (ret) 218 return 0; 219 return clk_freq * 100; 220} 221 222static int smu_set_gfx_imu_enable(struct smu_context *smu) 223{ 224 struct amdgpu_device *adev = smu->adev; 225 226 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 227 return 0; 228 229 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 230 return 0; 231 232 return smu_set_gfx_power_up_by_imu(smu); 233} 234 235static bool is_vcn_enabled(struct amdgpu_device *adev) 236{ 237 int i; 238 239 for (i = 0; i < adev->num_ip_blocks; i++) { 240 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 241 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 242 !adev->ip_blocks[i].status.valid) 243 return false; 244 } 245 246 return true; 247} 248 249static int smu_dpm_set_vcn_enable(struct smu_context *smu, 250 bool enable, 251 int inst) 252{ 253 struct smu_power_context *smu_power = &smu->smu_power; 254 struct smu_power_gate *power_gate = &smu_power->power_gate; 255 int ret = 0; 256 257 /* 258 * don't poweron vcn/jpeg when they are skipped. 259 */ 260 if (!is_vcn_enabled(smu->adev)) 261 return 0; 262 263 if (!smu->ppt_funcs->dpm_set_vcn_enable) 264 return 0; 265 266 if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable) 267 return 0; 268 269 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst); 270 if (!ret) 271 atomic_set(&power_gate->vcn_gated[inst], !enable); 272 273 return ret; 274} 275 276static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 277 bool enable) 278{ 279 struct smu_power_context *smu_power = &smu->smu_power; 280 struct smu_power_gate *power_gate = &smu_power->power_gate; 281 int ret = 0; 282 283 if (!is_vcn_enabled(smu->adev)) 284 return 0; 285 286 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 287 return 0; 288 289 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 290 return 0; 291 292 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 293 if (!ret) 294 atomic_set(&power_gate->jpeg_gated, !enable); 295 296 return ret; 297} 298 299static int smu_dpm_set_vpe_enable(struct smu_context *smu, 300 bool enable) 301{ 302 struct smu_power_context *smu_power = &smu->smu_power; 303 struct smu_power_gate *power_gate = &smu_power->power_gate; 304 int ret = 0; 305 306 if (!smu->ppt_funcs->dpm_set_vpe_enable) 307 return 0; 308 309 if (atomic_read(&power_gate->vpe_gated) ^ enable) 310 return 0; 311 312 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 313 if (!ret) 314 atomic_set(&power_gate->vpe_gated, !enable); 315 316 return ret; 317} 318 319static int smu_dpm_set_isp_enable(struct smu_context *smu, 320 bool enable) 321{ 322 struct smu_power_context *smu_power = &smu->smu_power; 323 struct smu_power_gate *power_gate = &smu_power->power_gate; 324 int ret; 325 326 if (!smu->ppt_funcs->dpm_set_isp_enable) 327 return 0; 328 329 if (atomic_read(&power_gate->isp_gated) ^ enable) 330 return 0; 331 332 ret = smu->ppt_funcs->dpm_set_isp_enable(smu, enable); 333 if (!ret) 334 atomic_set(&power_gate->isp_gated, !enable); 335 336 return ret; 337} 338 339static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 340 bool enable) 341{ 342 struct smu_power_context *smu_power = &smu->smu_power; 343 struct smu_power_gate *power_gate = &smu_power->power_gate; 344 int ret = 0; 345 346 if (!smu->adev->enable_umsch_mm) 347 return 0; 348 349 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 350 return 0; 351 352 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 353 return 0; 354 355 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 356 if (!ret) 357 atomic_set(&power_gate->umsch_mm_gated, !enable); 358 359 return ret; 360} 361 362static int smu_set_mall_enable(struct smu_context *smu) 363{ 364 int ret = 0; 365 366 if (!smu->ppt_funcs->set_mall_enable) 367 return 0; 368 369 ret = smu->ppt_funcs->set_mall_enable(smu); 370 371 return ret; 372} 373 374/** 375 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 376 * 377 * @handle: smu_context pointer 378 * @block_type: the IP block to power gate/ungate 379 * @gate: to power gate if true, ungate otherwise 380 * @inst: the instance of the IP block to power gate/ungate 381 * 382 * This API uses no smu->mutex lock protection due to: 383 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 384 * This is guarded to be race condition free by the caller. 385 * 2. Or get called on user setting request of power_dpm_force_performance_level. 386 * Under this case, the smu->mutex lock protection is already enforced on 387 * the parent API smu_force_performance_level of the call path. 388 */ 389static int smu_dpm_set_power_gate(void *handle, 390 uint32_t block_type, 391 bool gate, 392 int inst) 393{ 394 struct smu_context *smu = handle; 395 int ret = 0; 396 397 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 398 dev_WARN(smu->adev->dev, 399 "SMU uninitialized but power %s requested for %u!\n", 400 gate ? "gate" : "ungate", block_type); 401 return -EOPNOTSUPP; 402 } 403 404 switch (block_type) { 405 /* 406 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 407 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 408 */ 409 case AMD_IP_BLOCK_TYPE_UVD: 410 case AMD_IP_BLOCK_TYPE_VCN: 411 ret = smu_dpm_set_vcn_enable(smu, !gate, inst); 412 if (ret) 413 dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n", 414 gate ? "gate" : "ungate", inst); 415 break; 416 case AMD_IP_BLOCK_TYPE_GFX: 417 ret = smu_gfx_off_control(smu, gate); 418 if (ret) 419 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 420 gate ? "enable" : "disable"); 421 break; 422 case AMD_IP_BLOCK_TYPE_SDMA: 423 ret = smu_powergate_sdma(smu, gate); 424 if (ret) 425 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 426 gate ? "gate" : "ungate"); 427 break; 428 case AMD_IP_BLOCK_TYPE_JPEG: 429 ret = smu_dpm_set_jpeg_enable(smu, !gate); 430 if (ret) 431 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 432 gate ? "gate" : "ungate"); 433 break; 434 case AMD_IP_BLOCK_TYPE_VPE: 435 ret = smu_dpm_set_vpe_enable(smu, !gate); 436 if (ret) 437 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 438 gate ? "gate" : "ungate"); 439 break; 440 case AMD_IP_BLOCK_TYPE_ISP: 441 ret = smu_dpm_set_isp_enable(smu, !gate); 442 if (ret) 443 dev_err(smu->adev->dev, "Failed to power %s ISP!\n", 444 gate ? "gate" : "ungate"); 445 break; 446 default: 447 dev_err(smu->adev->dev, "Unsupported block type!\n"); 448 return -EINVAL; 449 } 450 451 return ret; 452} 453 454/** 455 * smu_set_user_clk_dependencies - set user profile clock dependencies 456 * 457 * @smu: smu_context pointer 458 * @clk: enum smu_clk_type type 459 * 460 * Enable/Disable the clock dependency for the @clk type. 461 */ 462static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 463{ 464 if (smu->adev->in_suspend) 465 return; 466 467 if (clk == SMU_MCLK) { 468 smu->user_dpm_profile.clk_dependency = 0; 469 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 470 } else if (clk == SMU_FCLK) { 471 /* MCLK takes precedence over FCLK */ 472 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 473 return; 474 475 smu->user_dpm_profile.clk_dependency = 0; 476 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 477 } else if (clk == SMU_SOCCLK) { 478 /* MCLK takes precedence over SOCCLK */ 479 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 480 return; 481 482 smu->user_dpm_profile.clk_dependency = 0; 483 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 484 } else 485 /* Add clk dependencies here, if any */ 486 return; 487} 488 489/** 490 * smu_restore_dpm_user_profile - reinstate user dpm profile 491 * 492 * @smu: smu_context pointer 493 * 494 * Restore the saved user power configurations include power limit, 495 * clock frequencies, fan control mode and fan speed. 496 */ 497static void smu_restore_dpm_user_profile(struct smu_context *smu) 498{ 499 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 500 int ret = 0; 501 502 if (!smu->adev->in_suspend) 503 return; 504 505 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 506 return; 507 508 /* Enable restore flag */ 509 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 510 511 /* set the user dpm power limits */ 512 for (int i = SMU_DEFAULT_PPT_LIMIT; i < SMU_LIMIT_TYPE_COUNT; i++) { 513 if (!smu->user_dpm_profile.power_limits[i]) 514 continue; 515 ret = smu_set_power_limit(smu, i, 516 smu->user_dpm_profile.power_limits[i]); 517 if (ret) 518 dev_err(smu->adev->dev, "Failed to set %d power limit value\n", i); 519 } 520 521 /* set the user dpm clock configurations */ 522 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 523 enum smu_clk_type clk_type; 524 525 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 526 /* 527 * Iterate over smu clk type and force the saved user clk 528 * configs, skip if clock dependency is enabled 529 */ 530 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 531 smu->user_dpm_profile.clk_mask[clk_type]) { 532 ret = smu_force_smuclk_levels(smu, clk_type, 533 smu->user_dpm_profile.clk_mask[clk_type]); 534 if (ret) 535 dev_err(smu->adev->dev, 536 "Failed to set clock type = %d\n", clk_type); 537 } 538 } 539 } 540 541 /* set the user dpm fan configurations */ 542 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 543 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 544 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 545 if (ret != -EOPNOTSUPP) { 546 smu->user_dpm_profile.fan_speed_pwm = 0; 547 smu->user_dpm_profile.fan_speed_rpm = 0; 548 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 549 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 550 } 551 552 if (smu->user_dpm_profile.fan_speed_pwm) { 553 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 554 if (ret != -EOPNOTSUPP) 555 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 556 } 557 558 if (smu->user_dpm_profile.fan_speed_rpm) { 559 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 560 if (ret != -EOPNOTSUPP) 561 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 562 } 563 } 564 565 /* Restore user customized OD settings */ 566 if (smu->user_dpm_profile.user_od) { 567 if (smu->ppt_funcs->restore_user_od_settings) { 568 ret = smu->ppt_funcs->restore_user_od_settings(smu); 569 if (ret) 570 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 571 } 572 } 573 574 /* Disable restore flag */ 575 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 576} 577 578static int smu_get_power_num_states(void *handle, 579 struct pp_states_info *state_info) 580{ 581 if (!state_info) 582 return -EINVAL; 583 584 /* not support power state */ 585 memset(state_info, 0, sizeof(struct pp_states_info)); 586 state_info->nums = 1; 587 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 588 589 return 0; 590} 591 592bool is_support_sw_smu(struct amdgpu_device *adev) 593{ 594 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 595 if (adev->asic_type == CHIP_VEGA20) 596 return false; 597 598 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) && 599 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC)) 600 return true; 601 602 return false; 603} 604 605bool is_support_cclk_dpm(struct amdgpu_device *adev) 606{ 607 struct smu_context *smu = adev->powerplay.pp_handle; 608 609 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 610 return false; 611 612 return true; 613} 614 615int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg, 616 uint32_t param, uint32_t *read_arg) 617{ 618 struct smu_context *smu = adev->powerplay.pp_handle; 619 int ret = -EOPNOTSUPP; 620 621 if (!smu) 622 return ret; 623 624 if (smu->ppt_funcs && smu->ppt_funcs->ras_send_msg) 625 ret = smu->ppt_funcs->ras_send_msg(smu, msg, param, read_arg); 626 627 return ret; 628} 629 630static int smu_sys_get_pp_table(void *handle, 631 char **table) 632{ 633 struct smu_context *smu = handle; 634 struct smu_table_context *smu_table = &smu->smu_table; 635 636 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 637 return -EOPNOTSUPP; 638 639 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 640 return -EOPNOTSUPP; 641 642 if (smu_table->hardcode_pptable) 643 *table = smu_table->hardcode_pptable; 644 else 645 *table = smu_table->power_play_table; 646 647 return smu_table->power_play_table_size; 648} 649 650static int smu_sys_set_pp_table(void *handle, 651 const char *buf, 652 size_t size) 653{ 654 struct smu_context *smu = handle; 655 struct smu_table_context *smu_table = &smu->smu_table; 656 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 657 int ret = 0; 658 659 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 660 return -EOPNOTSUPP; 661 662 if (header->usStructureSize != size) { 663 dev_err(smu->adev->dev, "pp table size not matched !\n"); 664 return -EIO; 665 } 666 667 if (!smu_table->hardcode_pptable || smu_table->power_play_table_size < size) { 668 kfree(smu_table->hardcode_pptable); 669 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 670 if (!smu_table->hardcode_pptable) 671 return -ENOMEM; 672 } 673 674 memcpy(smu_table->hardcode_pptable, buf, size); 675 smu_table->power_play_table = smu_table->hardcode_pptable; 676 smu_table->power_play_table_size = size; 677 678 /* 679 * Special hw_fini action(for Navi1x, the DPMs disablement will be 680 * skipped) may be needed for custom pptable uploading. 681 */ 682 smu->uploading_custom_pp_table = true; 683 684 ret = smu_reset(smu); 685 if (ret) 686 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 687 688 smu->uploading_custom_pp_table = false; 689 690 return ret; 691} 692 693static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 694{ 695 struct smu_feature *feature = &smu->smu_feature; 696 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 697 int ret = 0; 698 699 /* 700 * With SCPM enabled, the allowed featuremasks setting(via 701 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 702 * That means there is no way to let PMFW knows the settings below. 703 * Thus, we just assume all the features are allowed under 704 * such scenario. 705 */ 706 if (smu->adev->scpm_enabled) { 707 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 708 return 0; 709 } 710 711 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 712 713 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 714 SMU_FEATURE_MAX/32); 715 if (ret) 716 return ret; 717 718 bitmap_or(feature->allowed, feature->allowed, 719 (unsigned long *)allowed_feature_mask, 720 feature->feature_num); 721 722 return ret; 723} 724 725static int smu_set_funcs(struct amdgpu_device *adev) 726{ 727 struct smu_context *smu = adev->powerplay.pp_handle; 728 729 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 730 smu->od_enabled = true; 731 732 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 733 case IP_VERSION(11, 0, 0): 734 case IP_VERSION(11, 0, 5): 735 case IP_VERSION(11, 0, 9): 736 navi10_set_ppt_funcs(smu); 737 break; 738 case IP_VERSION(11, 0, 7): 739 case IP_VERSION(11, 0, 11): 740 case IP_VERSION(11, 0, 12): 741 case IP_VERSION(11, 0, 13): 742 sienna_cichlid_set_ppt_funcs(smu); 743 break; 744 case IP_VERSION(12, 0, 0): 745 case IP_VERSION(12, 0, 1): 746 renoir_set_ppt_funcs(smu); 747 break; 748 case IP_VERSION(11, 5, 0): 749 case IP_VERSION(11, 5, 2): 750 vangogh_set_ppt_funcs(smu); 751 break; 752 case IP_VERSION(13, 0, 1): 753 case IP_VERSION(13, 0, 3): 754 case IP_VERSION(13, 0, 8): 755 yellow_carp_set_ppt_funcs(smu); 756 break; 757 case IP_VERSION(13, 0, 4): 758 case IP_VERSION(13, 0, 11): 759 smu_v13_0_4_set_ppt_funcs(smu); 760 break; 761 case IP_VERSION(13, 0, 5): 762 smu_v13_0_5_set_ppt_funcs(smu); 763 break; 764 case IP_VERSION(11, 0, 8): 765 cyan_skillfish_set_ppt_funcs(smu); 766 break; 767 case IP_VERSION(11, 0, 2): 768 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 769 arcturus_set_ppt_funcs(smu); 770 /* OD is not supported on Arcturus */ 771 smu->od_enabled = false; 772 break; 773 case IP_VERSION(13, 0, 2): 774 aldebaran_set_ppt_funcs(smu); 775 /* Enable pp_od_clk_voltage node */ 776 smu->od_enabled = true; 777 break; 778 case IP_VERSION(13, 0, 0): 779 case IP_VERSION(13, 0, 10): 780 smu_v13_0_0_set_ppt_funcs(smu); 781 break; 782 case IP_VERSION(13, 0, 6): 783 case IP_VERSION(13, 0, 14): 784 case IP_VERSION(13, 0, 12): 785 smu_v13_0_6_set_ppt_funcs(smu); 786 /* Enable pp_od_clk_voltage node */ 787 smu->od_enabled = true; 788 break; 789 case IP_VERSION(13, 0, 7): 790 smu_v13_0_7_set_ppt_funcs(smu); 791 break; 792 case IP_VERSION(14, 0, 0): 793 case IP_VERSION(14, 0, 1): 794 case IP_VERSION(14, 0, 4): 795 case IP_VERSION(14, 0, 5): 796 smu_v14_0_0_set_ppt_funcs(smu); 797 break; 798 case IP_VERSION(14, 0, 2): 799 case IP_VERSION(14, 0, 3): 800 smu_v14_0_2_set_ppt_funcs(smu); 801 break; 802 default: 803 return -EINVAL; 804 } 805 806 return 0; 807} 808 809static int smu_early_init(struct amdgpu_ip_block *ip_block) 810{ 811 struct amdgpu_device *adev = ip_block->adev; 812 struct smu_context *smu; 813 int r; 814 815 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 816 if (!smu) 817 return -ENOMEM; 818 819 smu->adev = adev; 820 smu->pm_enabled = !!amdgpu_dpm; 821 smu->is_apu = false; 822 smu->smu_baco.state = SMU_BACO_STATE_NONE; 823 smu->smu_baco.platform_support = false; 824 smu->smu_baco.maco_support = false; 825 smu->user_dpm_profile.fan_mode = -1; 826 smu->power_profile_mode = PP_SMC_POWER_PROFILE_UNKNOWN; 827 828 mutex_init(&smu->message_lock); 829 830 adev->powerplay.pp_handle = smu; 831 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 832 833 r = smu_set_funcs(adev); 834 if (r) 835 return r; 836 return smu_init_microcode(smu); 837} 838 839static int smu_set_default_dpm_table(struct smu_context *smu) 840{ 841 struct amdgpu_device *adev = smu->adev; 842 struct smu_power_context *smu_power = &smu->smu_power; 843 struct smu_power_gate *power_gate = &smu_power->power_gate; 844 int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i; 845 int ret = 0; 846 847 if (!smu->ppt_funcs->set_default_dpm_table) 848 return 0; 849 850 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 851 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 852 vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]); 853 } 854 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 855 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 856 857 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 858 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 859 ret = smu_dpm_set_vcn_enable(smu, true, i); 860 if (ret) 861 return ret; 862 } 863 } 864 865 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 866 ret = smu_dpm_set_jpeg_enable(smu, true); 867 if (ret) 868 goto err_out; 869 } 870 871 ret = smu->ppt_funcs->set_default_dpm_table(smu); 872 if (ret) 873 dev_err(smu->adev->dev, 874 "Failed to setup default dpm clock tables!\n"); 875 876 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 877 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 878err_out: 879 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 880 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 881 smu_dpm_set_vcn_enable(smu, !vcn_gate[i], i); 882 } 883 884 return ret; 885} 886 887static int smu_apply_default_config_table_settings(struct smu_context *smu) 888{ 889 struct amdgpu_device *adev = smu->adev; 890 int ret = 0; 891 892 ret = smu_get_default_config_table_settings(smu, 893 &adev->pm.config_table); 894 if (ret) 895 return ret; 896 897 return smu_set_config_table(smu, &adev->pm.config_table); 898} 899 900static int smu_late_init(struct amdgpu_ip_block *ip_block) 901{ 902 struct amdgpu_device *adev = ip_block->adev; 903 struct smu_context *smu = adev->powerplay.pp_handle; 904 int ret = 0; 905 906 smu_set_fine_grain_gfx_freq_parameters(smu); 907 908 if (!smu->pm_enabled) 909 return 0; 910 911 ret = smu_post_init(smu); 912 if (ret) { 913 dev_err(adev->dev, "Failed to post smu init!\n"); 914 return ret; 915 } 916 917 /* 918 * Explicitly notify PMFW the power mode the system in. Since 919 * the PMFW may boot the ASIC with a different mode. 920 * For those supporting ACDC switch via gpio, PMFW will 921 * handle the switch automatically. Driver involvement 922 * is unnecessary. 923 */ 924 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 925 smu_set_ac_dc(smu); 926 927 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 928 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 929 return 0; 930 931 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 932 ret = smu_set_default_od_settings(smu); 933 if (ret) { 934 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 935 return ret; 936 } 937 } 938 939 ret = smu_populate_umd_state_clk(smu); 940 if (ret) { 941 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 942 return ret; 943 } 944 945 ret = smu_get_asic_power_limits(smu, 946 &smu->current_power_limit, 947 &smu->default_power_limit, 948 &smu->max_power_limit, 949 &smu->min_power_limit); 950 if (ret) { 951 dev_err(adev->dev, "Failed to get asic power limits!\n"); 952 return ret; 953 } 954 955 if (!amdgpu_sriov_vf(adev)) 956 smu_get_unique_id(smu); 957 958 smu_get_fan_parameters(smu); 959 960 smu_handle_task(smu, 961 smu->smu_dpm.dpm_level, 962 AMD_PP_TASK_COMPLETE_INIT); 963 964 ret = smu_apply_default_config_table_settings(smu); 965 if (ret && (ret != -EOPNOTSUPP)) { 966 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 967 return ret; 968 } 969 970 smu_restore_dpm_user_profile(smu); 971 972 return 0; 973} 974 975static int smu_init_fb_allocations(struct smu_context *smu) 976{ 977 struct amdgpu_device *adev = smu->adev; 978 struct smu_table_context *smu_table = &smu->smu_table; 979 struct smu_table *tables = smu_table->tables; 980 struct smu_table *driver_table = &(smu_table->driver_table); 981 uint32_t max_table_size = 0; 982 int ret, i; 983 984 /* VRAM allocation for tool table */ 985 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 986 ret = amdgpu_bo_create_kernel(adev, 987 tables[SMU_TABLE_PMSTATUSLOG].size, 988 tables[SMU_TABLE_PMSTATUSLOG].align, 989 tables[SMU_TABLE_PMSTATUSLOG].domain, 990 &tables[SMU_TABLE_PMSTATUSLOG].bo, 991 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 992 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 993 if (ret) { 994 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 995 return ret; 996 } 997 } 998 999 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 1000 /* VRAM allocation for driver table */ 1001 for (i = 0; i < SMU_TABLE_COUNT; i++) { 1002 if (tables[i].size == 0) 1003 continue; 1004 1005 /* If one of the tables has VRAM domain restriction, keep it in 1006 * VRAM 1007 */ 1008 if ((tables[i].domain & 1009 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 1010 AMDGPU_GEM_DOMAIN_VRAM) 1011 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 1012 1013 if (i == SMU_TABLE_PMSTATUSLOG) 1014 continue; 1015 1016 if (max_table_size < tables[i].size) 1017 max_table_size = tables[i].size; 1018 } 1019 1020 driver_table->size = max_table_size; 1021 driver_table->align = PAGE_SIZE; 1022 1023 ret = amdgpu_bo_create_kernel(adev, 1024 driver_table->size, 1025 driver_table->align, 1026 driver_table->domain, 1027 &driver_table->bo, 1028 &driver_table->mc_address, 1029 &driver_table->cpu_addr); 1030 if (ret) { 1031 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 1032 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 1033 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 1034 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 1035 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1036 } 1037 1038 return ret; 1039} 1040 1041static int smu_fini_fb_allocations(struct smu_context *smu) 1042{ 1043 struct smu_table_context *smu_table = &smu->smu_table; 1044 struct smu_table *tables = smu_table->tables; 1045 struct smu_table *driver_table = &(smu_table->driver_table); 1046 1047 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 1048 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 1049 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 1050 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1051 1052 amdgpu_bo_free_kernel(&driver_table->bo, 1053 &driver_table->mc_address, 1054 &driver_table->cpu_addr); 1055 1056 return 0; 1057} 1058 1059static void smu_update_gpu_addresses(struct smu_context *smu) 1060{ 1061 struct smu_table_context *smu_table = &smu->smu_table; 1062 struct smu_table *pm_status_table = smu_table->tables + SMU_TABLE_PMSTATUSLOG; 1063 struct smu_table *driver_table = &(smu_table->driver_table); 1064 struct smu_table *dummy_read_1_table = &smu_table->dummy_read_1_table; 1065 1066 if (pm_status_table->bo) 1067 pm_status_table->mc_address = amdgpu_bo_fb_aper_addr(pm_status_table->bo); 1068 if (driver_table->bo) 1069 driver_table->mc_address = amdgpu_bo_fb_aper_addr(driver_table->bo); 1070 if (dummy_read_1_table->bo) 1071 dummy_read_1_table->mc_address = amdgpu_bo_fb_aper_addr(dummy_read_1_table->bo); 1072} 1073 1074/** 1075 * smu_alloc_memory_pool - allocate memory pool in the system memory 1076 * 1077 * @smu: amdgpu_device pointer 1078 * 1079 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 1080 * and DramLogSetDramAddr can notify it changed. 1081 * 1082 * Returns 0 on success, error on failure. 1083 */ 1084static int smu_alloc_memory_pool(struct smu_context *smu) 1085{ 1086 struct amdgpu_device *adev = smu->adev; 1087 struct smu_table_context *smu_table = &smu->smu_table; 1088 struct smu_table *memory_pool = &smu_table->memory_pool; 1089 uint64_t pool_size = smu->pool_size; 1090 int ret = 0; 1091 1092 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1093 return ret; 1094 1095 memory_pool->size = pool_size; 1096 memory_pool->align = PAGE_SIZE; 1097 memory_pool->domain = 1098 (adev->pm.smu_debug_mask & SMU_DEBUG_POOL_USE_VRAM) ? 1099 AMDGPU_GEM_DOMAIN_VRAM : 1100 AMDGPU_GEM_DOMAIN_GTT; 1101 1102 switch (pool_size) { 1103 case SMU_MEMORY_POOL_SIZE_256_MB: 1104 case SMU_MEMORY_POOL_SIZE_512_MB: 1105 case SMU_MEMORY_POOL_SIZE_1_GB: 1106 case SMU_MEMORY_POOL_SIZE_2_GB: 1107 ret = amdgpu_bo_create_kernel(adev, 1108 memory_pool->size, 1109 memory_pool->align, 1110 memory_pool->domain, 1111 &memory_pool->bo, 1112 &memory_pool->mc_address, 1113 &memory_pool->cpu_addr); 1114 if (ret) 1115 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1116 break; 1117 default: 1118 break; 1119 } 1120 1121 return ret; 1122} 1123 1124static int smu_free_memory_pool(struct smu_context *smu) 1125{ 1126 struct smu_table_context *smu_table = &smu->smu_table; 1127 struct smu_table *memory_pool = &smu_table->memory_pool; 1128 1129 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1130 return 0; 1131 1132 amdgpu_bo_free_kernel(&memory_pool->bo, 1133 &memory_pool->mc_address, 1134 &memory_pool->cpu_addr); 1135 1136 memset(memory_pool, 0, sizeof(struct smu_table)); 1137 1138 return 0; 1139} 1140 1141static int smu_alloc_dummy_read_table(struct smu_context *smu) 1142{ 1143 struct smu_table_context *smu_table = &smu->smu_table; 1144 struct smu_table *dummy_read_1_table = 1145 &smu_table->dummy_read_1_table; 1146 struct amdgpu_device *adev = smu->adev; 1147 int ret = 0; 1148 1149 if (!dummy_read_1_table->size) 1150 return 0; 1151 1152 ret = amdgpu_bo_create_kernel(adev, 1153 dummy_read_1_table->size, 1154 dummy_read_1_table->align, 1155 dummy_read_1_table->domain, 1156 &dummy_read_1_table->bo, 1157 &dummy_read_1_table->mc_address, 1158 &dummy_read_1_table->cpu_addr); 1159 if (ret) 1160 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1161 1162 return ret; 1163} 1164 1165static void smu_free_dummy_read_table(struct smu_context *smu) 1166{ 1167 struct smu_table_context *smu_table = &smu->smu_table; 1168 struct smu_table *dummy_read_1_table = 1169 &smu_table->dummy_read_1_table; 1170 1171 1172 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1173 &dummy_read_1_table->mc_address, 1174 &dummy_read_1_table->cpu_addr); 1175 1176 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1177} 1178 1179static int smu_smc_table_sw_init(struct smu_context *smu) 1180{ 1181 int ret; 1182 1183 /** 1184 * Create smu_table structure, and init smc tables such as 1185 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1186 */ 1187 ret = smu_init_smc_tables(smu); 1188 if (ret) { 1189 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1190 return ret; 1191 } 1192 1193 /** 1194 * Create smu_power_context structure, and allocate smu_dpm_context and 1195 * context size to fill the smu_power_context data. 1196 */ 1197 ret = smu_init_power(smu); 1198 if (ret) { 1199 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1200 return ret; 1201 } 1202 1203 /* 1204 * allocate vram bos to store smc table contents. 1205 */ 1206 ret = smu_init_fb_allocations(smu); 1207 if (ret) 1208 return ret; 1209 1210 ret = smu_alloc_memory_pool(smu); 1211 if (ret) 1212 return ret; 1213 1214 ret = smu_alloc_dummy_read_table(smu); 1215 if (ret) 1216 return ret; 1217 1218 ret = smu_i2c_init(smu); 1219 if (ret) 1220 return ret; 1221 1222 return 0; 1223} 1224 1225static int smu_smc_table_sw_fini(struct smu_context *smu) 1226{ 1227 int ret; 1228 1229 smu_i2c_fini(smu); 1230 1231 smu_free_dummy_read_table(smu); 1232 1233 ret = smu_free_memory_pool(smu); 1234 if (ret) 1235 return ret; 1236 1237 ret = smu_fini_fb_allocations(smu); 1238 if (ret) 1239 return ret; 1240 1241 ret = smu_fini_power(smu); 1242 if (ret) { 1243 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1244 return ret; 1245 } 1246 1247 ret = smu_fini_smc_tables(smu); 1248 if (ret) { 1249 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1250 return ret; 1251 } 1252 1253 return 0; 1254} 1255 1256static void smu_throttling_logging_work_fn(struct work_struct *work) 1257{ 1258 struct smu_context *smu = container_of(work, struct smu_context, 1259 throttling_logging_work); 1260 1261 smu_log_thermal_throttling(smu); 1262} 1263 1264static void smu_interrupt_work_fn(struct work_struct *work) 1265{ 1266 struct smu_context *smu = container_of(work, struct smu_context, 1267 interrupt_work); 1268 1269 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1270 smu->ppt_funcs->interrupt_work(smu); 1271} 1272 1273static void smu_swctf_delayed_work_handler(struct work_struct *work) 1274{ 1275 struct smu_context *smu = 1276 container_of(work, struct smu_context, swctf_delayed_work.work); 1277 struct smu_temperature_range *range = 1278 &smu->thermal_range; 1279 struct amdgpu_device *adev = smu->adev; 1280 uint32_t hotspot_tmp, size; 1281 1282 /* 1283 * If the hotspot temperature is confirmed as below SW CTF setting point 1284 * after the delay enforced, nothing will be done. 1285 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1286 */ 1287 if (range->software_shutdown_temp && 1288 smu->ppt_funcs->read_sensor && 1289 !smu->ppt_funcs->read_sensor(smu, 1290 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1291 &hotspot_tmp, 1292 &size) && 1293 hotspot_tmp / 1000 < range->software_shutdown_temp) 1294 return; 1295 1296 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1297 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1298 orderly_poweroff(true); 1299} 1300 1301static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1302{ 1303 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1304 struct smu_dpm_policy_ctxt *policy_ctxt; 1305 struct smu_dpm_policy *policy; 1306 1307 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1308 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1309 if (policy) 1310 policy->current_level = XGMI_PLPD_DEFAULT; 1311 return; 1312 } 1313 1314 /* PMFW put PLPD into default policy after enabling the feature */ 1315 if (smu_feature_is_enabled(smu, 1316 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1317 if (policy) 1318 policy->current_level = XGMI_PLPD_DEFAULT; 1319 } else { 1320 policy_ctxt = dpm_ctxt->dpm_policies; 1321 if (policy_ctxt) 1322 policy_ctxt->policy_mask &= 1323 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1324 } 1325} 1326 1327static void smu_init_power_profile(struct smu_context *smu) 1328{ 1329 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN) 1330 smu->power_profile_mode = 1331 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1332 smu_power_profile_mode_get(smu, smu->power_profile_mode); 1333} 1334 1335void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id) 1336{ 1337 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1338 1339 if (fea_id >= SMU_FEATURE_CAP_ID__COUNT) 1340 return; 1341 1342 set_bit(fea_id, fea_cap->cap_map); 1343} 1344 1345bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id) 1346{ 1347 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1348 1349 if (fea_id >= SMU_FEATURE_CAP_ID__COUNT) 1350 return false; 1351 1352 return test_bit(fea_id, fea_cap->cap_map); 1353} 1354 1355static void smu_feature_cap_init(struct smu_context *smu) 1356{ 1357 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1358 1359 bitmap_zero(fea_cap->cap_map, SMU_FEATURE_CAP_ID__COUNT); 1360} 1361 1362static int smu_sw_init(struct amdgpu_ip_block *ip_block) 1363{ 1364 struct amdgpu_device *adev = ip_block->adev; 1365 struct smu_context *smu = adev->powerplay.pp_handle; 1366 int i, ret; 1367 1368 smu->pool_size = adev->pm.smu_prv_buffer_size; 1369 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1370 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1371 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1372 1373 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1374 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1375 atomic64_set(&smu->throttle_int_counter, 0); 1376 smu->watermarks_bitmap = 0; 1377 1378 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1379 atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1); 1380 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1381 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1382 atomic_set(&smu->smu_power.power_gate.isp_gated, 1); 1383 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1384 1385 smu_init_power_profile(smu); 1386 smu->display_config = &adev->pm.pm_display_cfg; 1387 1388 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1389 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1390 1391 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1392 smu_swctf_delayed_work_handler); 1393 1394 smu_feature_cap_init(smu); 1395 1396 ret = smu_smc_table_sw_init(smu); 1397 if (ret) { 1398 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1399 return ret; 1400 } 1401 1402 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1403 ret = smu_get_vbios_bootup_values(smu); 1404 if (ret) { 1405 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1406 return ret; 1407 } 1408 1409 ret = smu_init_pptable_microcode(smu); 1410 if (ret) { 1411 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1412 return ret; 1413 } 1414 1415 ret = smu_register_irq_handler(smu); 1416 if (ret) { 1417 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1418 return ret; 1419 } 1420 1421 /* If there is no way to query fan control mode, fan control is not supported */ 1422 if (!smu->ppt_funcs->get_fan_control_mode) 1423 smu->adev->pm.no_fan = true; 1424 1425 return 0; 1426} 1427 1428static int smu_sw_fini(struct amdgpu_ip_block *ip_block) 1429{ 1430 struct amdgpu_device *adev = ip_block->adev; 1431 struct smu_context *smu = adev->powerplay.pp_handle; 1432 int ret; 1433 1434 ret = smu_smc_table_sw_fini(smu); 1435 if (ret) { 1436 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1437 return ret; 1438 } 1439 1440 if (smu->custom_profile_params) { 1441 kfree(smu->custom_profile_params); 1442 smu->custom_profile_params = NULL; 1443 } 1444 1445 smu_fini_microcode(smu); 1446 1447 return 0; 1448} 1449 1450static int smu_get_thermal_temperature_range(struct smu_context *smu) 1451{ 1452 struct amdgpu_device *adev = smu->adev; 1453 struct smu_temperature_range *range = 1454 &smu->thermal_range; 1455 int ret = 0; 1456 1457 if (!smu->ppt_funcs->get_thermal_temperature_range) 1458 return 0; 1459 1460 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1461 if (ret) 1462 return ret; 1463 1464 adev->pm.dpm.thermal.min_temp = range->min; 1465 adev->pm.dpm.thermal.max_temp = range->max; 1466 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1467 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1468 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1469 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1470 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1471 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1472 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1473 1474 return ret; 1475} 1476 1477/** 1478 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1479 * 1480 * @smu: smu_context pointer 1481 * 1482 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1483 * Returns 0 on success, error on failure. 1484 */ 1485static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1486{ 1487 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1488 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1489 struct amdgpu_device *adev = smu->adev; 1490 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1491 uint64_t start, end; 1492 int ret, i, j; 1493 1494 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1495 if (ret) { 1496 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1497 return ret; 1498 } 1499 1500 /* 1501 * The exclusion ranges array we got might be filled with holes and duplicate 1502 * entries. For example: 1503 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1504 * We need to do some sortups to eliminate those holes and duplicate entries. 1505 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1506 */ 1507 for (i = 0; i < num_of_wbrf_ranges; i++) { 1508 start = wifi_bands[i].start; 1509 end = wifi_bands[i].end; 1510 1511 /* get the last valid entry to fill the intermediate hole */ 1512 if (!start && !end) { 1513 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1514 if (wifi_bands[j].start && wifi_bands[j].end) 1515 break; 1516 1517 /* no valid entry left */ 1518 if (j <= i) 1519 break; 1520 1521 start = wifi_bands[i].start = wifi_bands[j].start; 1522 end = wifi_bands[i].end = wifi_bands[j].end; 1523 wifi_bands[j].start = 0; 1524 wifi_bands[j].end = 0; 1525 num_of_wbrf_ranges = j; 1526 } 1527 1528 /* eliminate duplicate entries */ 1529 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1530 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1531 wifi_bands[j].start = 0; 1532 wifi_bands[j].end = 0; 1533 } 1534 } 1535 } 1536 1537 /* Send the sorted wifi_bands to PMFW */ 1538 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1539 /* Try to set the wifi_bands again */ 1540 if (unlikely(ret == -EBUSY)) { 1541 mdelay(5); 1542 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1543 } 1544 1545 return ret; 1546} 1547 1548/** 1549 * smu_wbrf_event_handler - handle notify events 1550 * 1551 * @nb: notifier block 1552 * @action: event type 1553 * @_arg: event data 1554 * 1555 * Calls relevant amdgpu function in response to wbrf event 1556 * notification from kernel. 1557 */ 1558static int smu_wbrf_event_handler(struct notifier_block *nb, 1559 unsigned long action, void *_arg) 1560{ 1561 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1562 1563 switch (action) { 1564 case WBRF_CHANGED: 1565 schedule_delayed_work(&smu->wbrf_delayed_work, 1566 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1567 break; 1568 default: 1569 return NOTIFY_DONE; 1570 } 1571 1572 return NOTIFY_OK; 1573} 1574 1575/** 1576 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1577 * 1578 * @work: struct work_struct pointer 1579 * 1580 * Flood is over and driver will consume the latest exclusion ranges. 1581 */ 1582static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1583{ 1584 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1585 1586 smu_wbrf_handle_exclusion_ranges(smu); 1587} 1588 1589/** 1590 * smu_wbrf_support_check - check wbrf support 1591 * 1592 * @smu: smu_context pointer 1593 * 1594 * Verifies the ACPI interface whether wbrf is supported. 1595 */ 1596static void smu_wbrf_support_check(struct smu_context *smu) 1597{ 1598 struct amdgpu_device *adev = smu->adev; 1599 1600 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1601 acpi_amd_wbrf_supported_consumer(adev->dev); 1602 1603 if (smu->wbrf_supported) 1604 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1605} 1606 1607/** 1608 * smu_wbrf_init - init driver wbrf support 1609 * 1610 * @smu: smu_context pointer 1611 * 1612 * Verifies the AMD ACPI interfaces and registers with the wbrf 1613 * notifier chain if wbrf feature is supported. 1614 * Returns 0 on success, error on failure. 1615 */ 1616static int smu_wbrf_init(struct smu_context *smu) 1617{ 1618 int ret; 1619 1620 if (!smu->wbrf_supported) 1621 return 0; 1622 1623 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1624 1625 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1626 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1627 if (ret) 1628 return ret; 1629 1630 /* 1631 * Some wifiband exclusion ranges may be already there 1632 * before our driver loaded. To make sure our driver 1633 * is awared of those exclusion ranges. 1634 */ 1635 schedule_delayed_work(&smu->wbrf_delayed_work, 1636 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1637 1638 return 0; 1639} 1640 1641/** 1642 * smu_wbrf_fini - tear down driver wbrf support 1643 * 1644 * @smu: smu_context pointer 1645 * 1646 * Unregisters with the wbrf notifier chain. 1647 */ 1648static void smu_wbrf_fini(struct smu_context *smu) 1649{ 1650 if (!smu->wbrf_supported) 1651 return; 1652 1653 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1654 1655 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1656} 1657 1658static int smu_smc_hw_setup(struct smu_context *smu) 1659{ 1660 struct smu_feature *feature = &smu->smu_feature; 1661 struct amdgpu_device *adev = smu->adev; 1662 uint8_t pcie_gen = 0, pcie_width = 0; 1663 uint64_t features_supported; 1664 int ret = 0; 1665 1666 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1667 case IP_VERSION(11, 0, 7): 1668 case IP_VERSION(11, 0, 11): 1669 case IP_VERSION(11, 5, 0): 1670 case IP_VERSION(11, 5, 2): 1671 case IP_VERSION(11, 0, 12): 1672 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1673 dev_info(adev->dev, "dpm has been enabled\n"); 1674 ret = smu_system_features_control(smu, true); 1675 if (ret) { 1676 dev_err(adev->dev, "Failed system features control!\n"); 1677 return ret; 1678 } 1679 1680 return smu_enable_thermal_alert(smu); 1681 } 1682 break; 1683 default: 1684 break; 1685 } 1686 1687 ret = smu_init_display_count(smu, 0); 1688 if (ret) { 1689 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1690 return ret; 1691 } 1692 1693 ret = smu_set_driver_table_location(smu); 1694 if (ret) { 1695 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1696 return ret; 1697 } 1698 1699 /* 1700 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1701 */ 1702 ret = smu_set_tool_table_location(smu); 1703 if (ret) { 1704 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1705 return ret; 1706 } 1707 1708 /* 1709 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1710 * pool location. 1711 */ 1712 ret = smu_notify_memory_pool_location(smu); 1713 if (ret) { 1714 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1715 return ret; 1716 } 1717 1718 /* 1719 * It is assumed the pptable used before runpm is same as 1720 * the one used afterwards. Thus, we can reuse the stored 1721 * copy and do not need to resetup the pptable again. 1722 */ 1723 if (!adev->in_runpm) { 1724 ret = smu_setup_pptable(smu); 1725 if (ret) { 1726 dev_err(adev->dev, "Failed to setup pptable!\n"); 1727 return ret; 1728 } 1729 } 1730 1731 /* smu_dump_pptable(smu); */ 1732 1733 /* 1734 * With SCPM enabled, PSP is responsible for the PPTable transferring 1735 * (to SMU). Driver involvement is not needed and permitted. 1736 */ 1737 if (!adev->scpm_enabled) { 1738 /* 1739 * Copy pptable bo in the vram to smc with SMU MSGs such as 1740 * SetDriverDramAddr and TransferTableDram2Smu. 1741 */ 1742 ret = smu_write_pptable(smu); 1743 if (ret) { 1744 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1745 return ret; 1746 } 1747 } 1748 1749 /* issue Run*Btc msg */ 1750 ret = smu_run_btc(smu); 1751 if (ret) 1752 return ret; 1753 1754 /* Enable UclkShadow on wbrf supported */ 1755 if (smu->wbrf_supported) { 1756 ret = smu_enable_uclk_shadow(smu, true); 1757 if (ret) { 1758 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1759 return ret; 1760 } 1761 } 1762 1763 /* 1764 * With SCPM enabled, these actions(and relevant messages) are 1765 * not needed and permitted. 1766 */ 1767 if (!adev->scpm_enabled) { 1768 ret = smu_feature_set_allowed_mask(smu); 1769 if (ret) { 1770 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1771 return ret; 1772 } 1773 } 1774 1775 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) 1776 pcie_gen = 4; 1777 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1778 pcie_gen = 3; 1779 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1780 pcie_gen = 2; 1781 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1782 pcie_gen = 1; 1783 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1784 pcie_gen = 0; 1785 1786 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1787 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1788 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1789 */ 1790 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32) 1791 pcie_width = 7; 1792 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1793 pcie_width = 6; 1794 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1795 pcie_width = 5; 1796 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1797 pcie_width = 4; 1798 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1799 pcie_width = 3; 1800 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1801 pcie_width = 2; 1802 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1803 pcie_width = 1; 1804 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1805 if (ret) { 1806 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1807 return ret; 1808 } 1809 1810 ret = smu_system_features_control(smu, true); 1811 if (ret) { 1812 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1813 return ret; 1814 } 1815 1816 smu_init_xgmi_plpd_mode(smu); 1817 1818 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1819 if (ret) { 1820 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1821 return ret; 1822 } 1823 bitmap_copy(feature->supported, 1824 (unsigned long *)&features_supported, 1825 feature->feature_num); 1826 1827 if (!smu_is_dpm_running(smu)) 1828 dev_info(adev->dev, "dpm has been disabled\n"); 1829 1830 /* 1831 * Set initialized values (get from vbios) to dpm tables context such as 1832 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1833 * type of clks. 1834 */ 1835 ret = smu_set_default_dpm_table(smu); 1836 if (ret) { 1837 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1838 return ret; 1839 } 1840 1841 ret = smu_get_thermal_temperature_range(smu); 1842 if (ret) { 1843 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1844 return ret; 1845 } 1846 1847 ret = smu_enable_thermal_alert(smu); 1848 if (ret) { 1849 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1850 return ret; 1851 } 1852 1853 ret = smu_notify_display_change(smu); 1854 if (ret) { 1855 dev_err(adev->dev, "Failed to notify display change!\n"); 1856 return ret; 1857 } 1858 1859 /* 1860 * Set min deep sleep dce fclk with bootup value from vbios via 1861 * SetMinDeepSleepDcefclk MSG. 1862 */ 1863 ret = smu_set_min_dcef_deep_sleep(smu, 1864 smu->smu_table.boot_values.dcefclk / 100); 1865 if (ret) { 1866 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1867 return ret; 1868 } 1869 1870 /* Init wbrf support. Properly setup the notifier */ 1871 ret = smu_wbrf_init(smu); 1872 if (ret) 1873 dev_err(adev->dev, "Error during wbrf init call\n"); 1874 1875 return ret; 1876} 1877 1878static int smu_start_smc_engine(struct smu_context *smu) 1879{ 1880 struct amdgpu_device *adev = smu->adev; 1881 int ret = 0; 1882 1883 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 1884 smu_update_gpu_addresses(smu); 1885 1886 smu->smc_fw_state = SMU_FW_INIT; 1887 1888 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1889 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1890 if (smu->ppt_funcs->load_microcode) { 1891 ret = smu->ppt_funcs->load_microcode(smu); 1892 if (ret) 1893 return ret; 1894 } 1895 } 1896 } 1897 1898 if (smu->ppt_funcs->check_fw_status) { 1899 ret = smu->ppt_funcs->check_fw_status(smu); 1900 if (ret) { 1901 dev_err(adev->dev, "SMC is not ready\n"); 1902 return ret; 1903 } 1904 } 1905 1906 /* 1907 * Send msg GetDriverIfVersion to check if the return value is equal 1908 * with DRIVER_IF_VERSION of smc header. 1909 */ 1910 ret = smu_check_fw_version(smu); 1911 if (ret) 1912 return ret; 1913 1914 return ret; 1915} 1916 1917static int smu_hw_init(struct amdgpu_ip_block *ip_block) 1918{ 1919 int i, ret; 1920 struct amdgpu_device *adev = ip_block->adev; 1921 struct smu_context *smu = adev->powerplay.pp_handle; 1922 1923 if (amdgpu_sriov_multi_vf_mode(adev)) { 1924 smu->pm_enabled = false; 1925 return 0; 1926 } 1927 1928 ret = smu_start_smc_engine(smu); 1929 if (ret) { 1930 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1931 return ret; 1932 } 1933 1934 /* 1935 * Check whether wbrf is supported. This needs to be done 1936 * before SMU setup starts since part of SMU configuration 1937 * relies on this. 1938 */ 1939 smu_wbrf_support_check(smu); 1940 1941 if (smu->is_apu) { 1942 ret = smu_set_gfx_imu_enable(smu); 1943 if (ret) 1944 return ret; 1945 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1946 smu_dpm_set_vcn_enable(smu, true, i); 1947 smu_dpm_set_jpeg_enable(smu, true); 1948 smu_dpm_set_umsch_mm_enable(smu, true); 1949 smu_set_mall_enable(smu); 1950 smu_set_gfx_cgpg(smu, true); 1951 } 1952 1953 if (!smu->pm_enabled) 1954 return 0; 1955 1956 ret = smu_get_driver_allowed_feature_mask(smu); 1957 if (ret) 1958 return ret; 1959 1960 ret = smu_smc_hw_setup(smu); 1961 if (ret) { 1962 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1963 return ret; 1964 } 1965 1966 /* 1967 * Move maximum sustainable clock retrieving here considering 1968 * 1. It is not needed on resume(from S3). 1969 * 2. DAL settings come between .hw_init and .late_init of SMU. 1970 * And DAL needs to know the maximum sustainable clocks. Thus 1971 * it cannot be put in .late_init(). 1972 */ 1973 ret = smu_init_max_sustainable_clocks(smu); 1974 if (ret) { 1975 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1976 return ret; 1977 } 1978 1979 adev->pm.dpm_enabled = true; 1980 1981 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1982 1983 return 0; 1984} 1985 1986static int smu_disable_dpms(struct smu_context *smu) 1987{ 1988 struct amdgpu_device *adev = smu->adev; 1989 int ret = 0; 1990 bool use_baco = !smu->is_apu && 1991 ((amdgpu_in_reset(adev) && 1992 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1993 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1994 1995 /* 1996 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1997 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1998 */ 1999 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2000 case IP_VERSION(13, 0, 0): 2001 case IP_VERSION(13, 0, 7): 2002 case IP_VERSION(13, 0, 10): 2003 case IP_VERSION(14, 0, 2): 2004 case IP_VERSION(14, 0, 3): 2005 return 0; 2006 default: 2007 break; 2008 } 2009 2010 /* 2011 * For custom pptable uploading, skip the DPM features 2012 * disable process on Navi1x ASICs. 2013 * - As the gfx related features are under control of 2014 * RLC on those ASICs. RLC reinitialization will be 2015 * needed to reenable them. That will cost much more 2016 * efforts. 2017 * 2018 * - SMU firmware can handle the DPM reenablement 2019 * properly. 2020 */ 2021 if (smu->uploading_custom_pp_table) { 2022 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2023 case IP_VERSION(11, 0, 0): 2024 case IP_VERSION(11, 0, 5): 2025 case IP_VERSION(11, 0, 9): 2026 case IP_VERSION(11, 0, 7): 2027 case IP_VERSION(11, 0, 11): 2028 case IP_VERSION(11, 5, 0): 2029 case IP_VERSION(11, 5, 2): 2030 case IP_VERSION(11, 0, 12): 2031 case IP_VERSION(11, 0, 13): 2032 return 0; 2033 default: 2034 break; 2035 } 2036 } 2037 2038 /* 2039 * For Sienna_Cichlid, PMFW will handle the features disablement properly 2040 * on BACO in. Driver involvement is unnecessary. 2041 */ 2042 if (use_baco) { 2043 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2044 case IP_VERSION(11, 0, 7): 2045 case IP_VERSION(11, 0, 0): 2046 case IP_VERSION(11, 0, 5): 2047 case IP_VERSION(11, 0, 9): 2048 case IP_VERSION(13, 0, 7): 2049 return 0; 2050 default: 2051 break; 2052 } 2053 } 2054 2055 /* 2056 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 2057 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 2058 */ 2059 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 2060 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 2061 return 0; 2062 2063 /* vangogh s0ix */ 2064 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) || 2065 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2)) && 2066 adev->in_s0ix) 2067 return 0; 2068 2069 /* 2070 * For gpu reset, runpm and hibernation through BACO, 2071 * BACO feature has to be kept enabled. 2072 */ 2073 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 2074 ret = smu_disable_all_features_with_exception(smu, 2075 SMU_FEATURE_BACO_BIT); 2076 if (ret) 2077 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 2078 } else { 2079 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 2080 if (!adev->scpm_enabled) { 2081 ret = smu_system_features_control(smu, false); 2082 if (ret) 2083 dev_err(adev->dev, "Failed to disable smu features.\n"); 2084 } 2085 } 2086 2087 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 2088 * otherwise SMU will hang while interacting with RLC if RLC is halted 2089 * this is a WA for Vangogh asic which fix the SMU hang issue. 2090 */ 2091 ret = smu_notify_rlc_state(smu, false); 2092 if (ret) { 2093 dev_err(adev->dev, "Fail to notify rlc status!\n"); 2094 return ret; 2095 } 2096 2097 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 2098 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 2099 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 2100 adev->gfx.rlc.funcs->stop(adev); 2101 2102 return ret; 2103} 2104 2105static int smu_smc_hw_cleanup(struct smu_context *smu) 2106{ 2107 struct amdgpu_device *adev = smu->adev; 2108 int ret = 0; 2109 2110 smu_wbrf_fini(smu); 2111 2112 cancel_work_sync(&smu->throttling_logging_work); 2113 cancel_work_sync(&smu->interrupt_work); 2114 2115 ret = smu_disable_thermal_alert(smu); 2116 if (ret) { 2117 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 2118 return ret; 2119 } 2120 2121 cancel_delayed_work_sync(&smu->swctf_delayed_work); 2122 2123 ret = smu_disable_dpms(smu); 2124 if (ret) { 2125 dev_err(adev->dev, "Fail to disable dpm features!\n"); 2126 return ret; 2127 } 2128 2129 return 0; 2130} 2131 2132static int smu_reset_mp1_state(struct smu_context *smu) 2133{ 2134 struct amdgpu_device *adev = smu->adev; 2135 int ret = 0; 2136 2137 if ((!adev->in_runpm) && (!adev->in_suspend) && 2138 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == 2139 IP_VERSION(13, 0, 10) && 2140 !amdgpu_device_has_display_hardware(adev)) 2141 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2142 2143 return ret; 2144} 2145 2146static int smu_hw_fini(struct amdgpu_ip_block *ip_block) 2147{ 2148 struct amdgpu_device *adev = ip_block->adev; 2149 struct smu_context *smu = adev->powerplay.pp_handle; 2150 int i, ret; 2151 2152 if (amdgpu_sriov_multi_vf_mode(adev)) 2153 return 0; 2154 2155 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2156 smu_dpm_set_vcn_enable(smu, false, i); 2157 adev->vcn.inst[i].cur_state = AMD_PG_STATE_GATE; 2158 } 2159 smu_dpm_set_jpeg_enable(smu, false); 2160 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2161 smu_dpm_set_umsch_mm_enable(smu, false); 2162 2163 if (!smu->pm_enabled) 2164 return 0; 2165 2166 adev->pm.dpm_enabled = false; 2167 2168 ret = smu_smc_hw_cleanup(smu); 2169 if (ret) 2170 return ret; 2171 2172 ret = smu_reset_mp1_state(smu); 2173 if (ret) 2174 return ret; 2175 2176 return 0; 2177} 2178 2179static void smu_late_fini(struct amdgpu_ip_block *ip_block) 2180{ 2181 struct amdgpu_device *adev = ip_block->adev; 2182 struct smu_context *smu = adev->powerplay.pp_handle; 2183 2184 kfree(smu); 2185} 2186 2187static int smu_reset(struct smu_context *smu) 2188{ 2189 struct amdgpu_device *adev = smu->adev; 2190 struct amdgpu_ip_block *ip_block; 2191 int ret; 2192 2193 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC); 2194 if (!ip_block) 2195 return -EINVAL; 2196 2197 ret = smu_hw_fini(ip_block); 2198 if (ret) 2199 return ret; 2200 2201 ret = smu_hw_init(ip_block); 2202 if (ret) 2203 return ret; 2204 2205 ret = smu_late_init(ip_block); 2206 if (ret) 2207 return ret; 2208 2209 return 0; 2210} 2211 2212static int smu_suspend(struct amdgpu_ip_block *ip_block) 2213{ 2214 struct amdgpu_device *adev = ip_block->adev; 2215 struct smu_context *smu = adev->powerplay.pp_handle; 2216 int ret; 2217 uint64_t count; 2218 2219 if (amdgpu_sriov_multi_vf_mode(adev)) 2220 return 0; 2221 2222 if (!smu->pm_enabled) 2223 return 0; 2224 2225 adev->pm.dpm_enabled = false; 2226 2227 ret = smu_smc_hw_cleanup(smu); 2228 if (ret) 2229 return ret; 2230 2231 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2232 2233 smu_set_gfx_cgpg(smu, false); 2234 2235 /* 2236 * pwfw resets entrycount when device is suspended, so we save the 2237 * last value to be used when we resume to keep it consistent 2238 */ 2239 ret = smu_get_entrycount_gfxoff(smu, &count); 2240 if (!ret) 2241 adev->gfx.gfx_off_entrycount = count; 2242 2243 /* clear this on suspend so it will get reprogrammed on resume */ 2244 smu->workload_mask = 0; 2245 2246 return 0; 2247} 2248 2249static int smu_resume(struct amdgpu_ip_block *ip_block) 2250{ 2251 int ret; 2252 struct amdgpu_device *adev = ip_block->adev; 2253 struct smu_context *smu = adev->powerplay.pp_handle; 2254 2255 if (amdgpu_sriov_multi_vf_mode(adev)) 2256 return 0; 2257 2258 if (!smu->pm_enabled) 2259 return 0; 2260 2261 dev_info(adev->dev, "SMU is resuming...\n"); 2262 2263 ret = smu_start_smc_engine(smu); 2264 if (ret) { 2265 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2266 return ret; 2267 } 2268 2269 ret = smu_smc_hw_setup(smu); 2270 if (ret) { 2271 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2272 return ret; 2273 } 2274 2275 ret = smu_set_gfx_imu_enable(smu); 2276 if (ret) 2277 return ret; 2278 2279 smu_set_gfx_cgpg(smu, true); 2280 2281 smu->disable_uclk_switch = 0; 2282 2283 adev->pm.dpm_enabled = true; 2284 2285 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2286 2287 return 0; 2288} 2289 2290static int smu_display_configuration_change(void *handle, 2291 const struct amd_pp_display_configuration *display_config) 2292{ 2293 struct smu_context *smu = handle; 2294 2295 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2296 return -EOPNOTSUPP; 2297 2298 if (!display_config) 2299 return -EINVAL; 2300 2301 smu_set_min_dcef_deep_sleep(smu, 2302 display_config->min_dcef_deep_sleep_set_clk / 100); 2303 2304 return 0; 2305} 2306 2307static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2308 enum amd_clockgating_state state) 2309{ 2310 return 0; 2311} 2312 2313static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block, 2314 enum amd_powergating_state state) 2315{ 2316 return 0; 2317} 2318 2319static int smu_enable_umd_pstate(void *handle, 2320 enum amd_dpm_forced_level *level) 2321{ 2322 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2323 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2324 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2325 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2326 2327 struct smu_context *smu = (struct smu_context*)(handle); 2328 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2329 2330 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2331 return -EINVAL; 2332 2333 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2334 /* enter umd pstate, save current level, disable gfx cg*/ 2335 if (*level & profile_mode_mask) { 2336 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2337 smu_gpo_control(smu, false); 2338 smu_gfx_ulv_control(smu, false); 2339 smu_deep_sleep_control(smu, false); 2340 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2341 } 2342 } else { 2343 /* exit umd pstate, restore level, enable gfx cg*/ 2344 if (!(*level & profile_mode_mask)) { 2345 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2346 *level = smu_dpm_ctx->saved_dpm_level; 2347 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2348 smu_deep_sleep_control(smu, true); 2349 smu_gfx_ulv_control(smu, true); 2350 smu_gpo_control(smu, true); 2351 } 2352 } 2353 2354 return 0; 2355} 2356 2357static int smu_bump_power_profile_mode(struct smu_context *smu, 2358 long *custom_params, 2359 u32 custom_params_max_idx) 2360{ 2361 u32 workload_mask = 0; 2362 int i, ret = 0; 2363 2364 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 2365 if (smu->workload_refcount[i]) 2366 workload_mask |= 1 << i; 2367 } 2368 2369 if (smu->workload_mask == workload_mask) 2370 return 0; 2371 2372 if (smu->ppt_funcs->set_power_profile_mode) 2373 ret = smu->ppt_funcs->set_power_profile_mode(smu, workload_mask, 2374 custom_params, 2375 custom_params_max_idx); 2376 2377 if (!ret) 2378 smu->workload_mask = workload_mask; 2379 2380 return ret; 2381} 2382 2383static void smu_power_profile_mode_get(struct smu_context *smu, 2384 enum PP_SMC_POWER_PROFILE profile_mode) 2385{ 2386 smu->workload_refcount[profile_mode]++; 2387} 2388 2389static void smu_power_profile_mode_put(struct smu_context *smu, 2390 enum PP_SMC_POWER_PROFILE profile_mode) 2391{ 2392 if (smu->workload_refcount[profile_mode]) 2393 smu->workload_refcount[profile_mode]--; 2394} 2395 2396static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2397 enum amd_dpm_forced_level level, 2398 bool skip_display_settings) 2399{ 2400 int ret = 0; 2401 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2402 2403 if (!skip_display_settings) { 2404 ret = smu_display_config_changed(smu); 2405 if (ret) { 2406 dev_err(smu->adev->dev, "Failed to change display config!"); 2407 return ret; 2408 } 2409 } 2410 2411 ret = smu_apply_clocks_adjust_rules(smu); 2412 if (ret) { 2413 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2414 return ret; 2415 } 2416 2417 if (!skip_display_settings) { 2418 ret = smu_notify_smc_display_config(smu); 2419 if (ret) { 2420 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2421 return ret; 2422 } 2423 } 2424 2425 if (smu_dpm_ctx->dpm_level != level) { 2426 ret = smu_asic_set_performance_level(smu, level); 2427 if (ret) { 2428 if (ret == -EOPNOTSUPP) 2429 dev_info(smu->adev->dev, "set performance level %d not supported", 2430 level); 2431 else 2432 dev_err(smu->adev->dev, "Failed to set performance level %d", 2433 level); 2434 return ret; 2435 } 2436 2437 /* update the saved copy */ 2438 smu_dpm_ctx->dpm_level = level; 2439 } 2440 2441 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2442 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2443 smu_bump_power_profile_mode(smu, NULL, 0); 2444 2445 return ret; 2446} 2447 2448static int smu_handle_task(struct smu_context *smu, 2449 enum amd_dpm_forced_level level, 2450 enum amd_pp_task task_id) 2451{ 2452 int ret = 0; 2453 2454 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2455 return -EOPNOTSUPP; 2456 2457 switch (task_id) { 2458 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2459 ret = smu_pre_display_config_changed(smu); 2460 if (ret) 2461 return ret; 2462 ret = smu_adjust_power_state_dynamic(smu, level, false); 2463 break; 2464 case AMD_PP_TASK_COMPLETE_INIT: 2465 ret = smu_adjust_power_state_dynamic(smu, level, true); 2466 break; 2467 case AMD_PP_TASK_READJUST_POWER_STATE: 2468 ret = smu_adjust_power_state_dynamic(smu, level, true); 2469 break; 2470 default: 2471 break; 2472 } 2473 2474 return ret; 2475} 2476 2477static int smu_handle_dpm_task(void *handle, 2478 enum amd_pp_task task_id, 2479 enum amd_pm_state_type *user_state) 2480{ 2481 struct smu_context *smu = handle; 2482 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2483 2484 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2485 2486} 2487 2488static int smu_switch_power_profile(void *handle, 2489 enum PP_SMC_POWER_PROFILE type, 2490 bool enable) 2491{ 2492 struct smu_context *smu = handle; 2493 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2494 int ret; 2495 2496 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2497 return -EOPNOTSUPP; 2498 2499 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2500 return -EINVAL; 2501 2502 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2503 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2504 if (enable) 2505 smu_power_profile_mode_get(smu, type); 2506 else 2507 smu_power_profile_mode_put(smu, type); 2508 /* don't switch the active workload when paused */ 2509 if (smu->pause_workload) 2510 ret = 0; 2511 else 2512 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2513 if (ret) { 2514 if (enable) 2515 smu_power_profile_mode_put(smu, type); 2516 else 2517 smu_power_profile_mode_get(smu, type); 2518 return ret; 2519 } 2520 } 2521 2522 return 0; 2523} 2524 2525static int smu_pause_power_profile(void *handle, 2526 bool pause) 2527{ 2528 struct smu_context *smu = handle; 2529 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2530 u32 workload_mask = 1 << PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 2531 int ret; 2532 2533 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2534 return -EOPNOTSUPP; 2535 2536 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2537 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2538 smu->pause_workload = pause; 2539 2540 /* force to bootup default profile */ 2541 if (smu->pause_workload && smu->ppt_funcs->set_power_profile_mode) 2542 ret = smu->ppt_funcs->set_power_profile_mode(smu, 2543 workload_mask, 2544 NULL, 2545 0); 2546 else 2547 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2548 return ret; 2549 } 2550 2551 return 0; 2552} 2553 2554static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2555{ 2556 struct smu_context *smu = handle; 2557 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2558 2559 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2560 return -EOPNOTSUPP; 2561 2562 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2563 return -EINVAL; 2564 2565 return smu_dpm_ctx->dpm_level; 2566} 2567 2568static int smu_force_performance_level(void *handle, 2569 enum amd_dpm_forced_level level) 2570{ 2571 struct smu_context *smu = handle; 2572 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2573 int ret = 0; 2574 2575 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2576 return -EOPNOTSUPP; 2577 2578 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2579 return -EINVAL; 2580 2581 ret = smu_enable_umd_pstate(smu, &level); 2582 if (ret) 2583 return ret; 2584 2585 ret = smu_handle_task(smu, level, 2586 AMD_PP_TASK_READJUST_POWER_STATE); 2587 2588 /* reset user dpm clock state */ 2589 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2590 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2591 smu->user_dpm_profile.clk_dependency = 0; 2592 } 2593 2594 return ret; 2595} 2596 2597static int smu_set_display_count(void *handle, uint32_t count) 2598{ 2599 struct smu_context *smu = handle; 2600 2601 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2602 return -EOPNOTSUPP; 2603 2604 return smu_init_display_count(smu, count); 2605} 2606 2607static int smu_force_smuclk_levels(struct smu_context *smu, 2608 enum smu_clk_type clk_type, 2609 uint32_t mask) 2610{ 2611 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2612 int ret = 0; 2613 2614 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2615 return -EOPNOTSUPP; 2616 2617 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2618 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2619 return -EINVAL; 2620 } 2621 2622 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2623 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2624 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2625 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2626 smu_set_user_clk_dependencies(smu, clk_type); 2627 } 2628 } 2629 2630 return ret; 2631} 2632 2633static int smu_force_ppclk_levels(void *handle, 2634 enum pp_clock_type type, 2635 uint32_t mask) 2636{ 2637 struct smu_context *smu = handle; 2638 enum smu_clk_type clk_type; 2639 2640 switch (type) { 2641 case PP_SCLK: 2642 clk_type = SMU_SCLK; break; 2643 case PP_MCLK: 2644 clk_type = SMU_MCLK; break; 2645 case PP_PCIE: 2646 clk_type = SMU_PCIE; break; 2647 case PP_SOCCLK: 2648 clk_type = SMU_SOCCLK; break; 2649 case PP_FCLK: 2650 clk_type = SMU_FCLK; break; 2651 case PP_DCEFCLK: 2652 clk_type = SMU_DCEFCLK; break; 2653 case PP_VCLK: 2654 clk_type = SMU_VCLK; break; 2655 case PP_VCLK1: 2656 clk_type = SMU_VCLK1; break; 2657 case PP_DCLK: 2658 clk_type = SMU_DCLK; break; 2659 case PP_DCLK1: 2660 clk_type = SMU_DCLK1; break; 2661 case OD_SCLK: 2662 clk_type = SMU_OD_SCLK; break; 2663 case OD_MCLK: 2664 clk_type = SMU_OD_MCLK; break; 2665 case OD_VDDC_CURVE: 2666 clk_type = SMU_OD_VDDC_CURVE; break; 2667 case OD_RANGE: 2668 clk_type = SMU_OD_RANGE; break; 2669 default: 2670 return -EINVAL; 2671 } 2672 2673 return smu_force_smuclk_levels(smu, clk_type, mask); 2674} 2675 2676/* 2677 * On system suspending or resetting, the dpm_enabled 2678 * flag will be cleared. So that those SMU services which 2679 * are not supported will be gated. 2680 * However, the mp1 state setting should still be granted 2681 * even if the dpm_enabled cleared. 2682 */ 2683static int smu_set_mp1_state(void *handle, 2684 enum pp_mp1_state mp1_state) 2685{ 2686 struct smu_context *smu = handle; 2687 int ret = 0; 2688 2689 if (!smu->pm_enabled) 2690 return -EOPNOTSUPP; 2691 2692 if (smu->ppt_funcs && 2693 smu->ppt_funcs->set_mp1_state) 2694 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2695 2696 return ret; 2697} 2698 2699static int smu_set_df_cstate(void *handle, 2700 enum pp_df_cstate state) 2701{ 2702 struct smu_context *smu = handle; 2703 int ret = 0; 2704 2705 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2706 return -EOPNOTSUPP; 2707 2708 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2709 return 0; 2710 2711 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2712 if (ret) 2713 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2714 2715 return ret; 2716} 2717 2718int smu_write_watermarks_table(struct smu_context *smu) 2719{ 2720 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2721 return -EOPNOTSUPP; 2722 2723 return smu_set_watermarks_table(smu, NULL); 2724} 2725 2726static int smu_set_watermarks_for_clock_ranges(void *handle, 2727 struct pp_smu_wm_range_sets *clock_ranges) 2728{ 2729 struct smu_context *smu = handle; 2730 2731 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2732 return -EOPNOTSUPP; 2733 2734 if (smu->disable_watermark) 2735 return 0; 2736 2737 return smu_set_watermarks_table(smu, clock_ranges); 2738} 2739 2740int smu_set_ac_dc(struct smu_context *smu) 2741{ 2742 int ret = 0; 2743 2744 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2745 return -EOPNOTSUPP; 2746 2747 /* controlled by firmware */ 2748 if (smu->dc_controlled_by_gpio) 2749 return 0; 2750 2751 ret = smu_set_power_source(smu, 2752 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2753 SMU_POWER_SOURCE_DC); 2754 if (ret) 2755 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2756 smu->adev->pm.ac_power ? "AC" : "DC"); 2757 2758 return ret; 2759} 2760 2761const struct amd_ip_funcs smu_ip_funcs = { 2762 .name = "smu", 2763 .early_init = smu_early_init, 2764 .late_init = smu_late_init, 2765 .sw_init = smu_sw_init, 2766 .sw_fini = smu_sw_fini, 2767 .hw_init = smu_hw_init, 2768 .hw_fini = smu_hw_fini, 2769 .late_fini = smu_late_fini, 2770 .suspend = smu_suspend, 2771 .resume = smu_resume, 2772 .is_idle = NULL, 2773 .check_soft_reset = NULL, 2774 .wait_for_idle = NULL, 2775 .soft_reset = NULL, 2776 .set_clockgating_state = smu_set_clockgating_state, 2777 .set_powergating_state = smu_set_powergating_state, 2778}; 2779 2780const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2781 .type = AMD_IP_BLOCK_TYPE_SMC, 2782 .major = 11, 2783 .minor = 0, 2784 .rev = 0, 2785 .funcs = &smu_ip_funcs, 2786}; 2787 2788const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2789 .type = AMD_IP_BLOCK_TYPE_SMC, 2790 .major = 12, 2791 .minor = 0, 2792 .rev = 0, 2793 .funcs = &smu_ip_funcs, 2794}; 2795 2796const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2797 .type = AMD_IP_BLOCK_TYPE_SMC, 2798 .major = 13, 2799 .minor = 0, 2800 .rev = 0, 2801 .funcs = &smu_ip_funcs, 2802}; 2803 2804const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2805 .type = AMD_IP_BLOCK_TYPE_SMC, 2806 .major = 14, 2807 .minor = 0, 2808 .rev = 0, 2809 .funcs = &smu_ip_funcs, 2810}; 2811 2812const struct ras_smu_drv *smu_get_ras_smu_driver(void *handle) 2813{ 2814 struct smu_context *smu = (struct smu_context *)handle; 2815 const struct ras_smu_drv *tmp = NULL; 2816 int ret; 2817 2818 ret = smu_get_ras_smu_drv(smu, &tmp); 2819 2820 return ret ? NULL : tmp; 2821} 2822 2823static int smu_load_microcode(void *handle) 2824{ 2825 struct smu_context *smu = handle; 2826 struct amdgpu_device *adev = smu->adev; 2827 int ret = 0; 2828 2829 if (!smu->pm_enabled) 2830 return -EOPNOTSUPP; 2831 2832 /* This should be used for non PSP loading */ 2833 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2834 return 0; 2835 2836 if (smu->ppt_funcs->load_microcode) { 2837 ret = smu->ppt_funcs->load_microcode(smu); 2838 if (ret) { 2839 dev_err(adev->dev, "Load microcode failed\n"); 2840 return ret; 2841 } 2842 } 2843 2844 if (smu->ppt_funcs->check_fw_status) { 2845 ret = smu->ppt_funcs->check_fw_status(smu); 2846 if (ret) { 2847 dev_err(adev->dev, "SMC is not ready\n"); 2848 return ret; 2849 } 2850 } 2851 2852 return ret; 2853} 2854 2855static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2856{ 2857 int ret = 0; 2858 2859 if (smu->ppt_funcs->set_gfx_cgpg) 2860 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2861 2862 return ret; 2863} 2864 2865static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2866{ 2867 struct smu_context *smu = handle; 2868 int ret = 0; 2869 2870 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2871 return -EOPNOTSUPP; 2872 2873 if (!smu->ppt_funcs->set_fan_speed_rpm) 2874 return -EOPNOTSUPP; 2875 2876 if (speed == U32_MAX) 2877 return -EINVAL; 2878 2879 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2880 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2881 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2882 smu->user_dpm_profile.fan_speed_rpm = speed; 2883 2884 /* Override custom PWM setting as they cannot co-exist */ 2885 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2886 smu->user_dpm_profile.fan_speed_pwm = 0; 2887 } 2888 2889 return ret; 2890} 2891 2892/** 2893 * smu_get_power_limit - Request one of the SMU Power Limits 2894 * 2895 * @handle: pointer to smu context 2896 * @limit: requested limit is written back to this variable 2897 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2898 * @pp_power_type: &pp_power_type type of power 2899 * Return: 0 on success, <0 on error 2900 * 2901 */ 2902int smu_get_power_limit(void *handle, 2903 uint32_t *limit, 2904 enum pp_power_limit_level pp_limit_level, 2905 enum pp_power_type pp_power_type) 2906{ 2907 struct smu_context *smu = handle; 2908 struct amdgpu_device *adev = smu->adev; 2909 enum smu_ppt_limit_level limit_level; 2910 uint32_t limit_type; 2911 int ret = 0; 2912 2913 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2914 return -EOPNOTSUPP; 2915 2916 if (!limit) 2917 return -EINVAL; 2918 2919 switch (pp_power_type) { 2920 case PP_PWR_TYPE_SUSTAINED: 2921 limit_type = SMU_DEFAULT_PPT_LIMIT; 2922 break; 2923 case PP_PWR_TYPE_FAST: 2924 limit_type = SMU_FAST_PPT_LIMIT; 2925 break; 2926 default: 2927 return -EOPNOTSUPP; 2928 } 2929 2930 switch (pp_limit_level) { 2931 case PP_PWR_LIMIT_CURRENT: 2932 limit_level = SMU_PPT_LIMIT_CURRENT; 2933 break; 2934 case PP_PWR_LIMIT_DEFAULT: 2935 limit_level = SMU_PPT_LIMIT_DEFAULT; 2936 break; 2937 case PP_PWR_LIMIT_MAX: 2938 limit_level = SMU_PPT_LIMIT_MAX; 2939 break; 2940 case PP_PWR_LIMIT_MIN: 2941 limit_level = SMU_PPT_LIMIT_MIN; 2942 break; 2943 default: 2944 return -EOPNOTSUPP; 2945 } 2946 2947 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2948 if (smu->ppt_funcs->get_ppt_limit) 2949 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2950 else 2951 return -EOPNOTSUPP; 2952 } else { 2953 switch (limit_level) { 2954 case SMU_PPT_LIMIT_CURRENT: 2955 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2956 case IP_VERSION(13, 0, 2): 2957 case IP_VERSION(13, 0, 6): 2958 case IP_VERSION(13, 0, 12): 2959 case IP_VERSION(13, 0, 14): 2960 case IP_VERSION(11, 0, 7): 2961 case IP_VERSION(11, 0, 11): 2962 case IP_VERSION(11, 0, 12): 2963 case IP_VERSION(11, 0, 13): 2964 ret = smu_get_asic_power_limits(smu, 2965 &smu->current_power_limit, 2966 NULL, NULL, NULL); 2967 break; 2968 default: 2969 break; 2970 } 2971 *limit = smu->current_power_limit; 2972 break; 2973 case SMU_PPT_LIMIT_DEFAULT: 2974 *limit = smu->default_power_limit; 2975 break; 2976 case SMU_PPT_LIMIT_MAX: 2977 *limit = smu->max_power_limit; 2978 break; 2979 case SMU_PPT_LIMIT_MIN: 2980 *limit = smu->min_power_limit; 2981 break; 2982 default: 2983 return -EINVAL; 2984 } 2985 } 2986 2987 return ret; 2988} 2989 2990static int smu_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit) 2991{ 2992 struct smu_context *smu = handle; 2993 int ret = 0; 2994 2995 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2996 return -EOPNOTSUPP; 2997 2998 if (limit_type == SMU_DEFAULT_PPT_LIMIT) { 2999 if (!limit) 3000 limit = smu->current_power_limit; 3001 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 3002 dev_err(smu->adev->dev, 3003 "New power limit (%d) is out of range [%d,%d]\n", 3004 limit, smu->min_power_limit, smu->max_power_limit); 3005 return -EINVAL; 3006 } 3007 } 3008 3009 if (smu->ppt_funcs->set_power_limit) { 3010 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 3011 if (ret) 3012 return ret; 3013 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 3014 smu->user_dpm_profile.power_limits[limit_type] = limit; 3015 } 3016 3017 return 0; 3018} 3019 3020static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 3021{ 3022 int ret = 0; 3023 3024 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3025 return -EOPNOTSUPP; 3026 3027 if (smu->ppt_funcs->print_clk_levels) 3028 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 3029 3030 return ret; 3031} 3032 3033static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 3034{ 3035 enum smu_clk_type clk_type; 3036 3037 switch (type) { 3038 case PP_SCLK: 3039 clk_type = SMU_SCLK; break; 3040 case PP_MCLK: 3041 clk_type = SMU_MCLK; break; 3042 case PP_PCIE: 3043 clk_type = SMU_PCIE; break; 3044 case PP_SOCCLK: 3045 clk_type = SMU_SOCCLK; break; 3046 case PP_FCLK: 3047 clk_type = SMU_FCLK; break; 3048 case PP_DCEFCLK: 3049 clk_type = SMU_DCEFCLK; break; 3050 case PP_VCLK: 3051 clk_type = SMU_VCLK; break; 3052 case PP_VCLK1: 3053 clk_type = SMU_VCLK1; break; 3054 case PP_DCLK: 3055 clk_type = SMU_DCLK; break; 3056 case PP_DCLK1: 3057 clk_type = SMU_DCLK1; break; 3058 case PP_ISPICLK: 3059 clk_type = SMU_ISPICLK; 3060 break; 3061 case PP_ISPXCLK: 3062 clk_type = SMU_ISPXCLK; 3063 break; 3064 case OD_SCLK: 3065 clk_type = SMU_OD_SCLK; break; 3066 case OD_MCLK: 3067 clk_type = SMU_OD_MCLK; break; 3068 case OD_VDDC_CURVE: 3069 clk_type = SMU_OD_VDDC_CURVE; break; 3070 case OD_RANGE: 3071 clk_type = SMU_OD_RANGE; break; 3072 case OD_VDDGFX_OFFSET: 3073 clk_type = SMU_OD_VDDGFX_OFFSET; break; 3074 case OD_CCLK: 3075 clk_type = SMU_OD_CCLK; break; 3076 case OD_FAN_CURVE: 3077 clk_type = SMU_OD_FAN_CURVE; break; 3078 case OD_ACOUSTIC_LIMIT: 3079 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 3080 case OD_ACOUSTIC_TARGET: 3081 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 3082 case OD_FAN_TARGET_TEMPERATURE: 3083 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 3084 case OD_FAN_MINIMUM_PWM: 3085 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 3086 case OD_FAN_ZERO_RPM_ENABLE: 3087 clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break; 3088 case OD_FAN_ZERO_RPM_STOP_TEMP: 3089 clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break; 3090 default: 3091 clk_type = SMU_CLK_COUNT; break; 3092 } 3093 3094 return clk_type; 3095} 3096 3097static int smu_print_ppclk_levels(void *handle, 3098 enum pp_clock_type type, 3099 char *buf) 3100{ 3101 struct smu_context *smu = handle; 3102 enum smu_clk_type clk_type; 3103 3104 clk_type = smu_convert_to_smuclk(type); 3105 if (clk_type == SMU_CLK_COUNT) 3106 return -EINVAL; 3107 3108 return smu_print_smuclk_levels(smu, clk_type, buf); 3109} 3110 3111static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 3112{ 3113 struct smu_context *smu = handle; 3114 enum smu_clk_type clk_type; 3115 3116 clk_type = smu_convert_to_smuclk(type); 3117 if (clk_type == SMU_CLK_COUNT) 3118 return -EINVAL; 3119 3120 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3121 return -EOPNOTSUPP; 3122 3123 if (!smu->ppt_funcs->emit_clk_levels) 3124 return -ENOENT; 3125 3126 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 3127 3128} 3129 3130static int smu_od_edit_dpm_table(void *handle, 3131 enum PP_OD_DPM_TABLE_COMMAND type, 3132 long *input, uint32_t size) 3133{ 3134 struct smu_context *smu = handle; 3135 int ret = 0; 3136 3137 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3138 return -EOPNOTSUPP; 3139 3140 if (smu->ppt_funcs->od_edit_dpm_table) { 3141 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 3142 } 3143 3144 return ret; 3145} 3146 3147static int smu_read_sensor(void *handle, 3148 int sensor, 3149 void *data, 3150 int *size_arg) 3151{ 3152 struct smu_context *smu = handle; 3153 struct amdgpu_device *adev = smu->adev; 3154 struct smu_umd_pstate_table *pstate_table = 3155 &smu->pstate_table; 3156 int i, ret = 0; 3157 uint32_t *size, size_val; 3158 3159 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3160 return -EOPNOTSUPP; 3161 3162 if (!data || !size_arg) 3163 return -EINVAL; 3164 3165 size_val = *size_arg; 3166 size = &size_val; 3167 3168 if (smu->ppt_funcs->read_sensor) 3169 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 3170 goto unlock; 3171 3172 switch (sensor) { 3173 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 3174 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 3175 *size = 4; 3176 break; 3177 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 3178 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 3179 *size = 4; 3180 break; 3181 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 3182 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 3183 *size = 4; 3184 break; 3185 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 3186 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 3187 *size = 4; 3188 break; 3189 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 3190 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 3191 *size = 8; 3192 break; 3193 case AMDGPU_PP_SENSOR_UVD_POWER: 3194 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 3195 *size = 4; 3196 break; 3197 case AMDGPU_PP_SENSOR_VCE_POWER: 3198 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 3199 *size = 4; 3200 break; 3201 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 3202 *(uint32_t *)data = 0; 3203 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 3204 if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) { 3205 *(uint32_t *)data = 1; 3206 break; 3207 } 3208 } 3209 *size = 4; 3210 break; 3211 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 3212 *(uint32_t *)data = 0; 3213 *size = 4; 3214 break; 3215 default: 3216 *size = 0; 3217 ret = -EOPNOTSUPP; 3218 break; 3219 } 3220 3221unlock: 3222 // assign uint32_t to int 3223 *size_arg = size_val; 3224 3225 return ret; 3226} 3227 3228static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3229{ 3230 int ret = -EOPNOTSUPP; 3231 struct smu_context *smu = handle; 3232 3233 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3234 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3235 3236 return ret; 3237} 3238 3239static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3240{ 3241 int ret = -EOPNOTSUPP; 3242 struct smu_context *smu = handle; 3243 3244 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3245 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3246 3247 return ret; 3248} 3249 3250static int smu_get_power_profile_mode(void *handle, char *buf) 3251{ 3252 struct smu_context *smu = handle; 3253 3254 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3255 !smu->ppt_funcs->get_power_profile_mode) 3256 return -EOPNOTSUPP; 3257 if (!buf) 3258 return -EINVAL; 3259 3260 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3261} 3262 3263static int smu_set_power_profile_mode(void *handle, 3264 long *param, 3265 uint32_t param_size) 3266{ 3267 struct smu_context *smu = handle; 3268 bool custom = false; 3269 int ret = 0; 3270 3271 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3272 !smu->ppt_funcs->set_power_profile_mode) 3273 return -EOPNOTSUPP; 3274 3275 if (param[param_size] == PP_SMC_POWER_PROFILE_CUSTOM) { 3276 custom = true; 3277 /* clear frontend mask so custom changes propogate */ 3278 smu->workload_mask = 0; 3279 } 3280 3281 if ((param[param_size] != smu->power_profile_mode) || custom) { 3282 /* clear the old user preference */ 3283 smu_power_profile_mode_put(smu, smu->power_profile_mode); 3284 /* set the new user preference */ 3285 smu_power_profile_mode_get(smu, param[param_size]); 3286 ret = smu_bump_power_profile_mode(smu, 3287 custom ? param : NULL, 3288 custom ? param_size : 0); 3289 if (ret) 3290 smu_power_profile_mode_put(smu, param[param_size]); 3291 else 3292 /* store the user's preference */ 3293 smu->power_profile_mode = param[param_size]; 3294 } 3295 3296 return ret; 3297} 3298 3299static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3300{ 3301 struct smu_context *smu = handle; 3302 3303 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3304 return -EOPNOTSUPP; 3305 3306 if (!smu->ppt_funcs->get_fan_control_mode) 3307 return -EOPNOTSUPP; 3308 3309 if (!fan_mode) 3310 return -EINVAL; 3311 3312 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3313 3314 return 0; 3315} 3316 3317static int smu_set_fan_control_mode(void *handle, u32 value) 3318{ 3319 struct smu_context *smu = handle; 3320 int ret = 0; 3321 3322 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3323 return -EOPNOTSUPP; 3324 3325 if (!smu->ppt_funcs->set_fan_control_mode) 3326 return -EOPNOTSUPP; 3327 3328 if (value == U32_MAX) 3329 return -EINVAL; 3330 3331 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3332 if (ret) 3333 goto out; 3334 3335 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3336 smu->user_dpm_profile.fan_mode = value; 3337 3338 /* reset user dpm fan speed */ 3339 if (value != AMD_FAN_CTRL_MANUAL) { 3340 smu->user_dpm_profile.fan_speed_pwm = 0; 3341 smu->user_dpm_profile.fan_speed_rpm = 0; 3342 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3343 } 3344 } 3345 3346out: 3347 return ret; 3348} 3349 3350static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3351{ 3352 struct smu_context *smu = handle; 3353 int ret = 0; 3354 3355 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3356 return -EOPNOTSUPP; 3357 3358 if (!smu->ppt_funcs->get_fan_speed_pwm) 3359 return -EOPNOTSUPP; 3360 3361 if (!speed) 3362 return -EINVAL; 3363 3364 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3365 3366 return ret; 3367} 3368 3369static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3370{ 3371 struct smu_context *smu = handle; 3372 int ret = 0; 3373 3374 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3375 return -EOPNOTSUPP; 3376 3377 if (!smu->ppt_funcs->set_fan_speed_pwm) 3378 return -EOPNOTSUPP; 3379 3380 if (speed == U32_MAX) 3381 return -EINVAL; 3382 3383 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3384 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3385 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3386 smu->user_dpm_profile.fan_speed_pwm = speed; 3387 3388 /* Override custom RPM setting as they cannot co-exist */ 3389 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3390 smu->user_dpm_profile.fan_speed_rpm = 0; 3391 } 3392 3393 return ret; 3394} 3395 3396static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3397{ 3398 struct smu_context *smu = handle; 3399 int ret = 0; 3400 3401 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3402 return -EOPNOTSUPP; 3403 3404 if (!smu->ppt_funcs->get_fan_speed_rpm) 3405 return -EOPNOTSUPP; 3406 3407 if (!speed) 3408 return -EINVAL; 3409 3410 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3411 3412 return ret; 3413} 3414 3415static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3416{ 3417 struct smu_context *smu = handle; 3418 3419 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3420 return -EOPNOTSUPP; 3421 3422 return smu_set_min_dcef_deep_sleep(smu, clk); 3423} 3424 3425static int smu_get_clock_by_type_with_latency(void *handle, 3426 enum amd_pp_clock_type type, 3427 struct pp_clock_levels_with_latency *clocks) 3428{ 3429 struct smu_context *smu = handle; 3430 enum smu_clk_type clk_type; 3431 int ret = 0; 3432 3433 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3434 return -EOPNOTSUPP; 3435 3436 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3437 switch (type) { 3438 case amd_pp_sys_clock: 3439 clk_type = SMU_GFXCLK; 3440 break; 3441 case amd_pp_mem_clock: 3442 clk_type = SMU_MCLK; 3443 break; 3444 case amd_pp_dcef_clock: 3445 clk_type = SMU_DCEFCLK; 3446 break; 3447 case amd_pp_disp_clock: 3448 clk_type = SMU_DISPCLK; 3449 break; 3450 default: 3451 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3452 return -EINVAL; 3453 } 3454 3455 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3456 } 3457 3458 return ret; 3459} 3460 3461static int smu_display_clock_voltage_request(void *handle, 3462 struct pp_display_clock_request *clock_req) 3463{ 3464 struct smu_context *smu = handle; 3465 int ret = 0; 3466 3467 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3468 return -EOPNOTSUPP; 3469 3470 if (smu->ppt_funcs->display_clock_voltage_request) 3471 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3472 3473 return ret; 3474} 3475 3476 3477static int smu_display_disable_memory_clock_switch(void *handle, 3478 bool disable_memory_clock_switch) 3479{ 3480 struct smu_context *smu = handle; 3481 int ret = -EINVAL; 3482 3483 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3484 return -EOPNOTSUPP; 3485 3486 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3487 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3488 3489 return ret; 3490} 3491 3492static int smu_set_xgmi_pstate(void *handle, 3493 uint32_t pstate) 3494{ 3495 struct smu_context *smu = handle; 3496 int ret = 0; 3497 3498 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3499 return -EOPNOTSUPP; 3500 3501 if (smu->ppt_funcs->set_xgmi_pstate) 3502 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3503 3504 if (ret) 3505 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3506 3507 return ret; 3508} 3509 3510static int smu_get_baco_capability(void *handle) 3511{ 3512 struct smu_context *smu = handle; 3513 3514 if (!smu->pm_enabled) 3515 return false; 3516 3517 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3518 return false; 3519 3520 return smu->ppt_funcs->get_bamaco_support(smu); 3521} 3522 3523static int smu_baco_set_state(void *handle, int state) 3524{ 3525 struct smu_context *smu = handle; 3526 int ret = 0; 3527 3528 if (!smu->pm_enabled) 3529 return -EOPNOTSUPP; 3530 3531 if (state == 0) { 3532 if (smu->ppt_funcs->baco_exit) 3533 ret = smu->ppt_funcs->baco_exit(smu); 3534 } else if (state == 1) { 3535 if (smu->ppt_funcs->baco_enter) 3536 ret = smu->ppt_funcs->baco_enter(smu); 3537 } else { 3538 return -EINVAL; 3539 } 3540 3541 if (ret) 3542 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3543 (state)?"enter":"exit"); 3544 3545 return ret; 3546} 3547 3548bool smu_mode1_reset_is_support(struct smu_context *smu) 3549{ 3550 bool ret = false; 3551 3552 if (!smu->pm_enabled) 3553 return false; 3554 3555 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3556 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3557 3558 return ret; 3559} 3560 3561bool smu_link_reset_is_support(struct smu_context *smu) 3562{ 3563 if (!smu->pm_enabled) 3564 return false; 3565 3566 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__LINK_RESET); 3567} 3568 3569int smu_mode1_reset(struct smu_context *smu) 3570{ 3571 int ret = 0; 3572 3573 if (!smu->pm_enabled) 3574 return -EOPNOTSUPP; 3575 3576 if (smu->ppt_funcs->mode1_reset) 3577 ret = smu->ppt_funcs->mode1_reset(smu); 3578 3579 return ret; 3580} 3581 3582static int smu_mode2_reset(void *handle) 3583{ 3584 struct smu_context *smu = handle; 3585 int ret = 0; 3586 3587 if (!smu->pm_enabled) 3588 return -EOPNOTSUPP; 3589 3590 if (smu->ppt_funcs->mode2_reset) 3591 ret = smu->ppt_funcs->mode2_reset(smu); 3592 3593 if (ret) 3594 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3595 3596 return ret; 3597} 3598 3599int smu_link_reset(struct smu_context *smu) 3600{ 3601 int ret = 0; 3602 3603 if (!smu->pm_enabled) 3604 return -EOPNOTSUPP; 3605 3606 if (smu->ppt_funcs->link_reset) 3607 ret = smu->ppt_funcs->link_reset(smu); 3608 3609 return ret; 3610} 3611 3612static int smu_enable_gfx_features(void *handle) 3613{ 3614 struct smu_context *smu = handle; 3615 int ret = 0; 3616 3617 if (!smu->pm_enabled) 3618 return -EOPNOTSUPP; 3619 3620 if (smu->ppt_funcs->enable_gfx_features) 3621 ret = smu->ppt_funcs->enable_gfx_features(smu); 3622 3623 if (ret) 3624 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3625 3626 return ret; 3627} 3628 3629static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3630 struct pp_smu_nv_clock_table *max_clocks) 3631{ 3632 struct smu_context *smu = handle; 3633 int ret = 0; 3634 3635 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3636 return -EOPNOTSUPP; 3637 3638 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3639 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3640 3641 return ret; 3642} 3643 3644static int smu_get_uclk_dpm_states(void *handle, 3645 unsigned int *clock_values_in_khz, 3646 unsigned int *num_states) 3647{ 3648 struct smu_context *smu = handle; 3649 int ret = 0; 3650 3651 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3652 return -EOPNOTSUPP; 3653 3654 if (smu->ppt_funcs->get_uclk_dpm_states) 3655 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3656 3657 return ret; 3658} 3659 3660static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3661{ 3662 struct smu_context *smu = handle; 3663 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3664 3665 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3666 return -EOPNOTSUPP; 3667 3668 if (smu->ppt_funcs->get_current_power_state) 3669 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3670 3671 return pm_state; 3672} 3673 3674static int smu_get_dpm_clock_table(void *handle, 3675 struct dpm_clocks *clock_table) 3676{ 3677 struct smu_context *smu = handle; 3678 int ret = 0; 3679 3680 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3681 return -EOPNOTSUPP; 3682 3683 if (smu->ppt_funcs->get_dpm_clock_table) 3684 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3685 3686 return ret; 3687} 3688 3689static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3690{ 3691 struct smu_context *smu = handle; 3692 3693 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3694 return -EOPNOTSUPP; 3695 3696 if (!smu->ppt_funcs->get_gpu_metrics) 3697 return -EOPNOTSUPP; 3698 3699 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3700} 3701 3702static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3703 size_t size) 3704{ 3705 struct smu_context *smu = handle; 3706 3707 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3708 return -EOPNOTSUPP; 3709 3710 if (!smu->ppt_funcs->get_pm_metrics) 3711 return -EOPNOTSUPP; 3712 3713 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3714} 3715 3716static int smu_enable_mgpu_fan_boost(void *handle) 3717{ 3718 struct smu_context *smu = handle; 3719 int ret = 0; 3720 3721 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3722 return -EOPNOTSUPP; 3723 3724 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3725 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3726 3727 return ret; 3728} 3729 3730static int smu_gfx_state_change_set(void *handle, 3731 uint32_t state) 3732{ 3733 struct smu_context *smu = handle; 3734 int ret = 0; 3735 3736 if (smu->ppt_funcs->gfx_state_change_set) 3737 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3738 3739 return ret; 3740} 3741 3742int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3743{ 3744 int ret = 0; 3745 3746 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3747 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3748 3749 return ret; 3750} 3751 3752int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3753{ 3754 int ret = -EOPNOTSUPP; 3755 3756 if (smu->ppt_funcs && 3757 smu->ppt_funcs->get_ecc_info) 3758 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3759 3760 return ret; 3761 3762} 3763 3764static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3765{ 3766 struct smu_context *smu = handle; 3767 struct smu_table_context *smu_table = &smu->smu_table; 3768 struct smu_table *memory_pool = &smu_table->memory_pool; 3769 3770 if (!addr || !size) 3771 return -EINVAL; 3772 3773 *addr = NULL; 3774 *size = 0; 3775 if (memory_pool->bo) { 3776 *addr = memory_pool->cpu_addr; 3777 *size = memory_pool->size; 3778 } 3779 3780 return 0; 3781} 3782 3783static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3784 size_t *size) 3785{ 3786 size_t offset = *size; 3787 int level; 3788 3789 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3790 if (level == policy->current_level) 3791 offset += sysfs_emit_at(sysbuf, offset, 3792 "%d : %s*\n", level, 3793 policy->desc->get_desc(policy, level)); 3794 else 3795 offset += sysfs_emit_at(sysbuf, offset, 3796 "%d : %s\n", level, 3797 policy->desc->get_desc(policy, level)); 3798 } 3799 3800 *size = offset; 3801} 3802 3803ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3804 enum pp_pm_policy p_type, char *sysbuf) 3805{ 3806 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3807 struct smu_dpm_policy_ctxt *policy_ctxt; 3808 struct smu_dpm_policy *dpm_policy; 3809 size_t offset = 0; 3810 3811 policy_ctxt = dpm_ctxt->dpm_policies; 3812 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3813 !policy_ctxt->policy_mask) 3814 return -EOPNOTSUPP; 3815 3816 if (p_type == PP_PM_POLICY_NONE) 3817 return -EINVAL; 3818 3819 dpm_policy = smu_get_pm_policy(smu, p_type); 3820 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3821 return -ENOENT; 3822 3823 if (!sysbuf) 3824 return -EINVAL; 3825 3826 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3827 3828 return offset; 3829} 3830 3831struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3832 enum pp_pm_policy p_type) 3833{ 3834 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3835 struct smu_dpm_policy_ctxt *policy_ctxt; 3836 int i; 3837 3838 policy_ctxt = dpm_ctxt->dpm_policies; 3839 if (!policy_ctxt) 3840 return NULL; 3841 3842 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3843 if (policy_ctxt->policies[i].policy_type == p_type) 3844 return &policy_ctxt->policies[i]; 3845 } 3846 3847 return NULL; 3848} 3849 3850int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3851 int level) 3852{ 3853 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3854 struct smu_dpm_policy *dpm_policy = NULL; 3855 struct smu_dpm_policy_ctxt *policy_ctxt; 3856 int ret = -EOPNOTSUPP; 3857 3858 policy_ctxt = dpm_ctxt->dpm_policies; 3859 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3860 !policy_ctxt->policy_mask) 3861 return ret; 3862 3863 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3864 return -EINVAL; 3865 3866 dpm_policy = smu_get_pm_policy(smu, p_type); 3867 3868 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3869 return ret; 3870 3871 if (dpm_policy->current_level == level) 3872 return 0; 3873 3874 ret = dpm_policy->set_policy(smu, level); 3875 3876 if (!ret) 3877 dpm_policy->current_level = level; 3878 3879 return ret; 3880} 3881 3882static ssize_t smu_sys_get_temp_metrics(void *handle, enum smu_temp_metric_type type, void *table) 3883{ 3884 struct smu_context *smu = handle; 3885 struct smu_table_context *smu_table = &smu->smu_table; 3886 struct smu_table *tables = smu_table->tables; 3887 enum smu_table_id table_id; 3888 3889 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3890 return -EOPNOTSUPP; 3891 3892 if (!smu->smu_temp.temp_funcs || !smu->smu_temp.temp_funcs->get_temp_metrics) 3893 return -EOPNOTSUPP; 3894 3895 table_id = smu_metrics_get_temp_table_id(type); 3896 3897 if (table_id == SMU_TABLE_COUNT) 3898 return -EINVAL; 3899 3900 /* If the request is to get size alone, return the cached table size */ 3901 if (!table && tables[table_id].cache.size) 3902 return tables[table_id].cache.size; 3903 3904 if (smu_table_cache_is_valid(&tables[table_id])) { 3905 memcpy(table, tables[table_id].cache.buffer, 3906 tables[table_id].cache.size); 3907 return tables[table_id].cache.size; 3908 } 3909 3910 return smu->smu_temp.temp_funcs->get_temp_metrics(smu, type, table); 3911} 3912 3913static bool smu_temp_metrics_is_supported(void *handle, enum smu_temp_metric_type type) 3914{ 3915 struct smu_context *smu = handle; 3916 bool ret = false; 3917 3918 if (!smu->pm_enabled) 3919 return false; 3920 3921 if (smu->smu_temp.temp_funcs && smu->smu_temp.temp_funcs->temp_metrics_is_supported) 3922 ret = smu->smu_temp.temp_funcs->temp_metrics_is_supported(smu, type); 3923 3924 return ret; 3925} 3926 3927static ssize_t smu_sys_get_xcp_metrics(void *handle, int xcp_id, void *table) 3928{ 3929 struct smu_context *smu = handle; 3930 3931 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3932 return -EOPNOTSUPP; 3933 3934 if (!smu->adev->xcp_mgr || !smu->ppt_funcs->get_xcp_metrics) 3935 return -EOPNOTSUPP; 3936 3937 return smu->ppt_funcs->get_xcp_metrics(smu, xcp_id, table); 3938} 3939 3940static const struct amd_pm_funcs swsmu_pm_funcs = { 3941 /* export for sysfs */ 3942 .set_fan_control_mode = smu_set_fan_control_mode, 3943 .get_fan_control_mode = smu_get_fan_control_mode, 3944 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3945 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3946 .force_clock_level = smu_force_ppclk_levels, 3947 .print_clock_levels = smu_print_ppclk_levels, 3948 .emit_clock_levels = smu_emit_ppclk_levels, 3949 .force_performance_level = smu_force_performance_level, 3950 .read_sensor = smu_read_sensor, 3951 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3952 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3953 .get_performance_level = smu_get_performance_level, 3954 .get_current_power_state = smu_get_current_power_state, 3955 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3956 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3957 .get_pp_num_states = smu_get_power_num_states, 3958 .get_pp_table = smu_sys_get_pp_table, 3959 .set_pp_table = smu_sys_set_pp_table, 3960 .switch_power_profile = smu_switch_power_profile, 3961 .pause_power_profile = smu_pause_power_profile, 3962 /* export to amdgpu */ 3963 .dispatch_tasks = smu_handle_dpm_task, 3964 .load_firmware = smu_load_microcode, 3965 .set_powergating_by_smu = smu_dpm_set_power_gate, 3966 .set_power_limit = smu_set_power_limit, 3967 .get_power_limit = smu_get_power_limit, 3968 .get_power_profile_mode = smu_get_power_profile_mode, 3969 .set_power_profile_mode = smu_set_power_profile_mode, 3970 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3971 .set_mp1_state = smu_set_mp1_state, 3972 .gfx_state_change_set = smu_gfx_state_change_set, 3973 /* export to DC */ 3974 .get_sclk = smu_get_sclk, 3975 .get_mclk = smu_get_mclk, 3976 .display_configuration_change = smu_display_configuration_change, 3977 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3978 .display_clock_voltage_request = smu_display_clock_voltage_request, 3979 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3980 .set_active_display_count = smu_set_display_count, 3981 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3982 .get_asic_baco_capability = smu_get_baco_capability, 3983 .set_asic_baco_state = smu_baco_set_state, 3984 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3985 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3986 .asic_reset_mode_2 = smu_mode2_reset, 3987 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3988 .set_df_cstate = smu_set_df_cstate, 3989 .set_xgmi_pstate = smu_set_xgmi_pstate, 3990 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3991 .get_pm_metrics = smu_sys_get_pm_metrics, 3992 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3993 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3994 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3995 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3996 .get_dpm_clock_table = smu_get_dpm_clock_table, 3997 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3998 .get_xcp_metrics = smu_sys_get_xcp_metrics, 3999 .get_temp_metrics = smu_sys_get_temp_metrics, 4000 .temp_metrics_is_supported = smu_temp_metrics_is_supported, 4001}; 4002 4003int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 4004 uint64_t event_arg) 4005{ 4006 int ret = -EINVAL; 4007 4008 if (smu->ppt_funcs->wait_for_event) 4009 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 4010 4011 return ret; 4012} 4013 4014int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 4015{ 4016 4017 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 4018 return -EOPNOTSUPP; 4019 4020 /* Confirm the buffer allocated is of correct size */ 4021 if (size != smu->stb_context.stb_buf_size) 4022 return -EINVAL; 4023 4024 /* 4025 * No need to lock smu mutex as we access STB directly through MMIO 4026 * and not going through SMU messaging route (for now at least). 4027 * For registers access rely on implementation internal locking. 4028 */ 4029 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 4030} 4031 4032#if defined(CONFIG_DEBUG_FS) 4033 4034static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 4035{ 4036 struct amdgpu_device *adev = filp->f_inode->i_private; 4037 struct smu_context *smu = adev->powerplay.pp_handle; 4038 unsigned char *buf; 4039 int r; 4040 4041 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 4042 if (!buf) 4043 return -ENOMEM; 4044 4045 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 4046 if (r) 4047 goto out; 4048 4049 filp->private_data = buf; 4050 4051 return 0; 4052 4053out: 4054 kvfree(buf); 4055 return r; 4056} 4057 4058static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 4059 loff_t *pos) 4060{ 4061 struct amdgpu_device *adev = filp->f_inode->i_private; 4062 struct smu_context *smu = adev->powerplay.pp_handle; 4063 4064 4065 if (!filp->private_data) 4066 return -EINVAL; 4067 4068 return simple_read_from_buffer(buf, 4069 size, 4070 pos, filp->private_data, 4071 smu->stb_context.stb_buf_size); 4072} 4073 4074static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 4075{ 4076 kvfree(filp->private_data); 4077 filp->private_data = NULL; 4078 4079 return 0; 4080} 4081 4082/* 4083 * We have to define not only read method but also 4084 * open and release because .read takes up to PAGE_SIZE 4085 * data each time so and so is invoked multiple times. 4086 * We allocate the STB buffer in .open and release it 4087 * in .release 4088 */ 4089static const struct file_operations smu_stb_debugfs_fops = { 4090 .owner = THIS_MODULE, 4091 .open = smu_stb_debugfs_open, 4092 .read = smu_stb_debugfs_read, 4093 .release = smu_stb_debugfs_release, 4094 .llseek = default_llseek, 4095}; 4096 4097#endif 4098 4099void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 4100{ 4101#if defined(CONFIG_DEBUG_FS) 4102 4103 struct smu_context *smu = adev->powerplay.pp_handle; 4104 4105 if (!smu || (!smu->stb_context.stb_buf_size)) 4106 return; 4107 4108 debugfs_create_file_size("amdgpu_smu_stb_dump", 4109 S_IRUSR, 4110 adev_to_drm(adev)->primary->debugfs_root, 4111 adev, 4112 &smu_stb_debugfs_fops, 4113 smu->stb_context.stb_buf_size); 4114#endif 4115} 4116 4117int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 4118{ 4119 int ret = 0; 4120 4121 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 4122 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 4123 4124 return ret; 4125} 4126 4127int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 4128{ 4129 int ret = 0; 4130 4131 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 4132 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 4133 4134 return ret; 4135} 4136 4137int smu_send_rma_reason(struct smu_context *smu) 4138{ 4139 int ret = 0; 4140 4141 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 4142 ret = smu->ppt_funcs->send_rma_reason(smu); 4143 4144 return ret; 4145} 4146 4147/** 4148 * smu_reset_sdma_is_supported - Check if SDMA reset is supported by SMU 4149 * @smu: smu_context pointer 4150 * 4151 * This function checks if the SMU supports resetting the SDMA engine. 4152 * It returns true if supported, false otherwise. 4153 */ 4154bool smu_reset_sdma_is_supported(struct smu_context *smu) 4155{ 4156 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__SDMA_RESET); 4157} 4158 4159int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask) 4160{ 4161 int ret = 0; 4162 4163 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma) 4164 ret = smu->ppt_funcs->reset_sdma(smu, inst_mask); 4165 4166 return ret; 4167} 4168 4169bool smu_reset_vcn_is_supported(struct smu_context *smu) 4170{ 4171 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__VCN_RESET); 4172} 4173 4174int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask) 4175{ 4176 if (smu->ppt_funcs && smu->ppt_funcs->dpm_reset_vcn) 4177 smu->ppt_funcs->dpm_reset_vcn(smu, inst_mask); 4178 4179 return 0; 4180}
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