smu8_smumgr.h

 1/*
 2 * Copyright 2015 Advanced Micro Devices, Inc.
 3 *
 4 * Permission is hereby granted, free of charge, to any person obtaining a
 5 * copy of this software and associated documentation files (the "Software"),
 6 * to deal in the Software without restriction, including without limitation
 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 8 * and/or sell copies of the Software, and to permit persons to whom the
 9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef _SMU8_SMUMGR_H_
24#define _SMU8_SMUMGR_H_
25
26
27#define MAX_NUM_FIRMWARE                        8
28#define MAX_NUM_SCRATCH                         11
29#define SMU8_SCRATCH_SIZE_NONGFX_CLOCKGATING      1024
30#define SMU8_SCRATCH_SIZE_NONGFX_GOLDENSETTING    2048
31#define SMU8_SCRATCH_SIZE_SDMA_METADATA           1024
32#define SMU8_SCRATCH_SIZE_IH                      ((2*256+1)*4)
33
34#define SMU_EnabledFeatureScoreboard_SclkDpmOn    0x00200000
35
36enum smu8_scratch_entry {
37	SMU8_SCRATCH_ENTRY_UCODE_ID_SDMA0 = 0,
38	SMU8_SCRATCH_ENTRY_UCODE_ID_SDMA1,
39	SMU8_SCRATCH_ENTRY_UCODE_ID_CP_CE,
40	SMU8_SCRATCH_ENTRY_UCODE_ID_CP_PFP,
41	SMU8_SCRATCH_ENTRY_UCODE_ID_CP_ME,
42	SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
43	SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
44	SMU8_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG,
45	SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_G,
46	SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
47	SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
48	SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
49	SMU8_SCRATCH_ENTRY_UCODE_ID_DMCU_ERAM,
50	SMU8_SCRATCH_ENTRY_UCODE_ID_DMCU_IRAM,
51	SMU8_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
52	SMU8_SCRATCH_ENTRY_DATA_ID_SDMA_HALT,
53	SMU8_SCRATCH_ENTRY_DATA_ID_SYS_CLOCKGATING,
54	SMU8_SCRATCH_ENTRY_DATA_ID_SDMA_RING_REGS,
55	SMU8_SCRATCH_ENTRY_DATA_ID_NONGFX_REINIT,
56	SMU8_SCRATCH_ENTRY_DATA_ID_SDMA_START,
57	SMU8_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS,
58	SMU8_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE
59};
60
61struct smu8_buffer_entry {
62	uint32_t data_size;
63	uint64_t mc_addr;
64	void *kaddr;
65	enum smu8_scratch_entry firmware_ID;
66	struct amdgpu_bo *handle; /* as bo handle used when release bo */
67};
68
69struct smu8_register_index_data_pair {
70	uint32_t offset;
71	uint32_t value;
72};
73
74struct smu8_ih_meta_data {
75	uint32_t command;
76	struct smu8_register_index_data_pair register_index_value_pair[1];
77};
78
79struct smu8_smumgr {
80	uint8_t driver_buffer_length;
81	uint8_t scratch_buffer_length;
82	uint16_t toc_entry_used_count;
83	uint16_t toc_entry_initialize_index;
84	uint16_t toc_entry_power_profiling_index;
85	uint16_t toc_entry_aram;
86	uint16_t toc_entry_ih_register_restore_task_index;
87	uint16_t toc_entry_clock_table;
88	uint16_t ih_register_restore_task_size;
89	uint16_t smu_buffer_used_bytes;
90
91	struct smu8_buffer_entry toc_buffer;
92	struct smu8_buffer_entry smu_buffer;
93	struct smu8_buffer_entry firmware_buffer;
94	struct smu8_buffer_entry driver_buffer[MAX_NUM_FIRMWARE];
95	struct smu8_buffer_entry meta_data_buffer[MAX_NUM_FIRMWARE];
96	struct smu8_buffer_entry scratch_buffer[MAX_NUM_SCRATCH];
97};
98
99#endif