smu9_driver_if.h

  1/*
  2 * Copyright 2016 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23
 24#ifndef SMU9_DRIVER_IF_H
 25#define SMU9_DRIVER_IF_H
 26
 27#include "smu9.h"
 28
 29/**** IMPORTANT ***
 30 * SMU TEAM: Always increment the interface version if
 31 * any structure is changed in this file
 32 */
 33#define SMU9_DRIVER_IF_VERSION 0xE
 34
 35#define PPTABLE_V10_SMU_VERSION 1
 36
 37#define NUM_GFXCLK_DPM_LEVELS  8
 38#define NUM_UVD_DPM_LEVELS     8
 39#define NUM_VCE_DPM_LEVELS     8
 40#define NUM_MP0CLK_DPM_LEVELS  8
 41#define NUM_UCLK_DPM_LEVELS    4
 42#define NUM_SOCCLK_DPM_LEVELS  8
 43#define NUM_DCEFCLK_DPM_LEVELS 8
 44#define NUM_LINK_LEVELS        2
 45
 46#define MAX_GFXCLK_DPM_LEVEL  (NUM_GFXCLK_DPM_LEVELS  - 1)
 47#define MAX_UVD_DPM_LEVEL     (NUM_UVD_DPM_LEVELS     - 1)
 48#define MAX_VCE_DPM_LEVEL     (NUM_VCE_DPM_LEVELS     - 1)
 49#define MAX_MP0CLK_DPM_LEVEL  (NUM_MP0CLK_DPM_LEVELS  - 1)
 50#define MAX_UCLK_DPM_LEVEL    (NUM_UCLK_DPM_LEVELS    - 1)
 51#define MAX_SOCCLK_DPM_LEVEL  (NUM_SOCCLK_DPM_LEVELS  - 1)
 52#define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
 53#define MAX_LINK_DPM_LEVEL    (NUM_LINK_LEVELS        - 1)
 54
 55#define MIN_GFXCLK_DPM_LEVEL  0
 56#define MIN_UVD_DPM_LEVEL     0
 57#define MIN_VCE_DPM_LEVEL     0
 58#define MIN_MP0CLK_DPM_LEVEL  0
 59#define MIN_UCLK_DPM_LEVEL    0
 60#define MIN_SOCCLK_DPM_LEVEL  0
 61#define MIN_DCEFCLK_DPM_LEVEL 0
 62#define MIN_LINK_DPM_LEVEL    0
 63
 64#define NUM_EVV_VOLTAGE_LEVELS 8
 65#define MAX_EVV_VOLTAGE_LEVEL (NUM_EVV_VOLTAGE_LEVELS - 1)
 66#define MIN_EVV_VOLTAGE_LEVEL 0
 67
 68#define NUM_PSP_LEVEL_MAP 4
 69
 70/* Gemini Modes */
 71#define PPSMC_GeminiModeNone   0  /* Single GPU board */
 72#define PPSMC_GeminiModeMaster 1  /* Master GPU on a Gemini board */
 73#define PPSMC_GeminiModeSlave  2  /* Slave GPU on a Gemini board */
 74
 75/* Voltage Modes for DPMs */
 76#define VOLTAGE_MODE_AVFS_INTERPOLATE 0
 77#define VOLTAGE_MODE_AVFS_WORST_CASE  1
 78#define VOLTAGE_MODE_STATIC           2
 79
 80typedef struct {
 81  uint32_t FbMult; /* Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */
 82  uint32_t SsFbMult; /* Spread FB Mult: bit 8:0 int, bit 31:16 frac */
 83  uint16_t SsSlewFrac;
 84  uint8_t  SsOn;
 85  uint8_t  Did;      /* DID */
 86} PllSetting_t;
 87
 88typedef struct {
 89  int32_t a0;
 90  int32_t a1;
 91  int32_t a2;
 92
 93  uint8_t a0_shift;
 94  uint8_t a1_shift;
 95  uint8_t a2_shift;
 96  uint8_t padding;
 97} GbVdroopTable_t;
 98
 99typedef struct {
100  int32_t m1;
101  int32_t m2;
102  int32_t b;
103
104  uint8_t m1_shift;
105  uint8_t m2_shift;
106  uint8_t b_shift;
107  uint8_t padding;
108} QuadraticInt_t;
109
110#define NUM_DSPCLK_LEVELS 8
111
112typedef enum {
113  DSPCLK_DCEFCLK = 0,
114  DSPCLK_DISPCLK,
115  DSPCLK_PIXCLK,
116  DSPCLK_PHYCLK,
117  DSPCLK_COUNT,
118} DSPCLK_e;
119
120typedef struct {
121  uint16_t Freq; /* in MHz */
122  uint16_t Vid;  /* min voltage in SVI2 VID */
123} DisplayClockTable_t;
124
125#pragma pack(push, 1)
126typedef struct {
127  /* PowerTune */
128  uint16_t SocketPowerLimit; /* Watts */
129  uint16_t TdcLimit;         /* Amps */
130  uint16_t EdcLimit;         /* Amps */
131  uint16_t TedgeLimit;       /* Celcius */
132  uint16_t ThotspotLimit;    /* Celcius */
133  uint16_t ThbmLimit;        /* Celcius */
134  uint16_t Tvr_socLimit;     /* Celcius */
135  uint16_t Tvr_memLimit;     /* Celcius */
136  uint16_t Tliquid1Limit;    /* Celcius */
137  uint16_t Tliquid2Limit;    /* Celcius */
138  uint16_t TplxLimit;        /* Celcius */
139  uint16_t LoadLineResistance; /* in mOhms */
140  uint32_t FitLimit;         /* Failures in time (failures per million parts over the defined lifetime) */
141
142  /* External Component Communication Settings */
143  uint8_t  Liquid1_I2C_address;
144  uint8_t  Liquid2_I2C_address;
145  uint8_t  Vr_I2C_address;
146  uint8_t  Plx_I2C_address;
147
148  uint8_t  GeminiMode;
149  uint8_t  spare17[3];
150  uint32_t GeminiApertureHigh;
151  uint32_t GeminiApertureLow;
152
153  uint8_t  Liquid_I2C_LineSCL;
154  uint8_t  Liquid_I2C_LineSDA;
155  uint8_t  Vr_I2C_LineSCL;
156  uint8_t  Vr_I2C_LineSDA;
157  uint8_t  Plx_I2C_LineSCL;
158  uint8_t  Plx_I2C_LineSDA;
159  uint8_t  paddingx[2];
160
161  /* ULV Settings */
162  uint8_t  UlvOffsetVid;     /* SVI2 VID */
163  uint8_t  UlvSmnclkDid;     /* DID for ULV mode. 0 means CLK will not be modified in ULV. */
164  uint8_t  UlvMp1clkDid;     /* DID for ULV mode. 0 means CLK will not be modified in ULV. */
165  uint8_t  UlvGfxclkBypass;  /* 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV */
166
167  /* VDDCR_SOC Voltages */
168  uint8_t      SocVid[NUM_EVV_VOLTAGE_LEVELS];
169
170  /* This is the minimum voltage needed to run the SOC. */
171  uint8_t      MinVoltageVid; /* Minimum Voltage ("Vmin") of ASIC */
172  uint8_t      MaxVoltageVid; /* Maximum Voltage allowable */
173  uint8_t      MaxVidStep; /* Max VID step that SMU will request. Multiple steps are taken if voltage change exceeds this value. */
174  uint8_t      padding8;
175
176  uint8_t      UlvPhaseSheddingPsi0; /* set this to 1 to set PSI0/1 to 1 in ULV mode */
177  uint8_t      UlvPhaseSheddingPsi1; /* set this to 1 to set PSI0/1 to 1 in ULV mode */
178  uint8_t      padding8_2[2];
179
180  /* SOC Frequencies */
181  PllSetting_t GfxclkLevel[NUM_GFXCLK_DPM_LEVELS];
182
183  uint8_t      SocclkDid[NUM_SOCCLK_DPM_LEVELS];          /* DID */
184  uint8_t      SocDpmVoltageIndex[NUM_SOCCLK_DPM_LEVELS];
185
186  uint8_t      VclkDid[NUM_UVD_DPM_LEVELS];            /* DID */
187  uint8_t      DclkDid[NUM_UVD_DPM_LEVELS];            /* DID */
188  uint8_t      UvdDpmVoltageIndex[NUM_UVD_DPM_LEVELS];
189
190  uint8_t      EclkDid[NUM_VCE_DPM_LEVELS];            /* DID */
191  uint8_t      VceDpmVoltageIndex[NUM_VCE_DPM_LEVELS];
192
193  uint8_t      Mp0clkDid[NUM_MP0CLK_DPM_LEVELS];          /* DID */
194  uint8_t      Mp0DpmVoltageIndex[NUM_MP0CLK_DPM_LEVELS];
195
196  DisplayClockTable_t DisplayClockTable[DSPCLK_COUNT][NUM_DSPCLK_LEVELS];
197  QuadraticInt_t      DisplayClock2Gfxclk[DSPCLK_COUNT];
198
199  uint8_t      GfxDpmVoltageMode;
200  uint8_t      SocDpmVoltageMode;
201  uint8_t      UclkDpmVoltageMode;
202  uint8_t      UvdDpmVoltageMode;
203
204  uint8_t      VceDpmVoltageMode;
205  uint8_t      Mp0DpmVoltageMode;
206  uint8_t      DisplayDpmVoltageMode;
207  uint8_t      padding8_3;
208
209  uint16_t     GfxclkSlewRate;
210  uint16_t     padding;
211
212  uint32_t     LowGfxclkInterruptThreshold;  /* in units of 10KHz */
213
214  /* Alpha parameters for clock averages. ("255"=1) */
215  uint8_t      GfxclkAverageAlpha;
216  uint8_t      SocclkAverageAlpha;
217  uint8_t      UclkAverageAlpha;
218  uint8_t      GfxActivityAverageAlpha;
219
220  /* UCLK States */
221  uint8_t      MemVid[NUM_UCLK_DPM_LEVELS];    /* VID */
222  PllSetting_t UclkLevel[NUM_UCLK_DPM_LEVELS];   /* Full PLL settings */
223  uint8_t      MemSocVoltageIndex[NUM_UCLK_DPM_LEVELS];
224  uint8_t      LowestUclkReservedForUlv; /* Set this to 1 if UCLK DPM0 is reserved for ULV-mode only */
225  uint8_t      paddingUclk[3];
226  uint16_t     NumMemoryChannels;  /* Used for memory bandwidth calculations */
227  uint16_t     MemoryChannelWidth; /* Used for memory bandwidth calculations */
228
229  /* CKS Settings */
230  uint8_t      CksEnable[NUM_GFXCLK_DPM_LEVELS];
231  uint8_t      CksVidOffset[NUM_GFXCLK_DPM_LEVELS];
232
233  /* MP0 Mapping Table */
234  uint8_t      PspLevelMap[NUM_PSP_LEVEL_MAP];
235
236  /* Link DPM Settings */
237  uint8_t     PcieGenSpeed[NUM_LINK_LEVELS];           /* 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
238  uint8_t     PcieLaneCount[NUM_LINK_LEVELS];          /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
239  uint8_t     LclkDid[NUM_LINK_LEVELS];                /* Leave at 0 to use hardcoded values in FW */
240  uint8_t     paddingLinkDpm[2];
241
242  /* Fan Control */
243  uint16_t     FanStopTemp;          /* Celcius */
244  uint16_t     FanStartTemp;         /* Celcius */
245
246  uint16_t     FanGainEdge;
247  uint16_t     FanGainHotspot;
248  uint16_t     FanGainLiquid;
249  uint16_t     FanGainVrVddc;
250  uint16_t     FanGainVrMvdd;
251  uint16_t     FanGainPlx;
252  uint16_t     FanGainHbm;
253  uint16_t     FanPwmMin;
254  uint16_t     FanAcousticLimitRpm;
255  uint16_t     FanThrottlingRpm;
256  uint16_t     FanMaximumRpm;
257  uint16_t     FanTargetTemperature;
258  uint16_t     FanTargetGfxclk;
259  uint8_t      FanZeroRpmEnable;
260  uint8_t      FanSpare;
261
262  /* The following are AFC override parameters. Leave at 0 to use FW defaults. */
263  int16_t      FuzzyFan_ErrorSetDelta;
264  int16_t      FuzzyFan_ErrorRateSetDelta;
265  int16_t      FuzzyFan_PwmSetDelta;
266  uint16_t     FuzzyFan_Reserved;
267
268  /* GPIO Settings */
269  uint8_t      AcDcGpio;        /* GPIO pin configured for AC/DC switching */
270  uint8_t      AcDcPolarity;    /* GPIO polarity for AC/DC switching */
271  uint8_t      VR0HotGpio;      /* GPIO pin configured for VR0 HOT event */
272  uint8_t      VR0HotPolarity;  /* GPIO polarity for VR0 HOT event */
273  uint8_t      VR1HotGpio;      /* GPIO pin configured for VR1 HOT event */
274  uint8_t      VR1HotPolarity;  /* GPIO polarity for VR1 HOT event */
275  uint8_t      Padding1;       /* replace GPIO pin configured for CTF */
276  uint8_t      Padding2;       /* replace GPIO polarity for CTF */
277
278  /* LED Display Settings */
279  uint8_t      LedPin0;         /* GPIO number for LedPin[0] */
280  uint8_t      LedPin1;         /* GPIO number for LedPin[1] */
281  uint8_t      LedPin2;         /* GPIO number for LedPin[2] */
282  uint8_t      padding8_4;
283
284  /* AVFS */
285  uint8_t      OverrideBtcGbCksOn;
286  uint8_t      OverrideAvfsGbCksOn;
287  uint8_t      PaddingAvfs8[2];
288
289  GbVdroopTable_t BtcGbVdroopTableCksOn;
290  GbVdroopTable_t BtcGbVdroopTableCksOff;
291
292  QuadraticInt_t  AvfsGbCksOn;  /* Replacement equation */
293  QuadraticInt_t  AvfsGbCksOff; /* Replacement equation */
294
295  uint8_t      StaticVoltageOffsetVid[NUM_GFXCLK_DPM_LEVELS]; /* This values are added on to the final voltage calculation */
296
297  /* Ageing Guardband Parameters */
298  uint32_t     AConstant[3];
299  uint16_t     DC_tol_sigma;
300  uint16_t     Platform_mean;
301  uint16_t     Platform_sigma;
302  uint16_t     PSM_Age_CompFactor;
303
304  uint32_t     DpmLevelPowerDelta;
305
306  uint8_t      EnableBoostState;
307  uint8_t      AConstant_Shift;
308  uint8_t      DC_tol_sigma_Shift;
309  uint8_t      PSM_Age_CompFactor_Shift;
310
311  uint16_t     BoostStartTemperature;
312  uint16_t     BoostStopTemperature;
313
314  PllSetting_t GfxBoostState;
315
316  uint8_t      AcgEnable[NUM_GFXCLK_DPM_LEVELS];
317  GbVdroopTable_t AcgBtcGbVdroopTable;
318  QuadraticInt_t  AcgAvfsGb;
319
320  /* ACG Frequency Table, in Mhz */
321  uint32_t     AcgFreqTable[NUM_GFXCLK_DPM_LEVELS];
322
323  /* Padding - ignore */
324  uint32_t     MmHubPadding[3]; /* SMU internal use */
325
326} PPTable_t;
327#pragma pack(pop)
328
329typedef struct {
330  uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz)
331  uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz)
332  uint16_t MinUclk;
333  uint16_t MaxUclk;
334
335  uint8_t  WmSetting;
336  uint8_t  Padding[3];
337} WatermarkRowGeneric_t;
338
339#define NUM_WM_RANGES 4
340
341typedef enum {
342  WM_SOCCLK = 0,
343  WM_DCEFCLK,
344  WM_COUNT,
345} WM_CLOCK_e;
346
347typedef struct {
348  /* Watermarks */
349  WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
350
351  uint32_t     MmHubPadding[7]; /* SMU internal use */
352} Watermarks_t;
353
354#ifdef PPTABLE_V10_SMU_VERSION
355typedef struct {
356  float        AvfsGbCksOn[NUM_GFXCLK_DPM_LEVELS];
357  float        AcBtcGbCksOn[NUM_GFXCLK_DPM_LEVELS];
358  float        AvfsGbCksOff[NUM_GFXCLK_DPM_LEVELS];
359  float        AcBtcGbCksOff[NUM_GFXCLK_DPM_LEVELS];
360  float        DcBtcGb;
361
362  uint32_t     MmHubPadding[7]; /* SMU internal use */
363} AvfsTable_t;
364#else
365typedef struct {
366  uint32_t     AvfsGbCksOn[NUM_GFXCLK_DPM_LEVELS];
367  uint32_t     AcBtcGbCksOn[NUM_GFXCLK_DPM_LEVELS];
368  uint32_t     AvfsGbCksOff[NUM_GFXCLK_DPM_LEVELS];
369  uint32_t     AcBtcGbCksOff[NUM_GFXCLK_DPM_LEVELS];
370  uint32_t     DcBtcGb;
371
372  uint32_t     MmHubPadding[7]; /* SMU internal use */
373} AvfsTable_t;
374#endif
375
376typedef struct {
377  uint16_t avgPsmCount[30];
378  uint16_t minPsmCount[30];
379  float    avgPsmVoltage[30];
380  float    minPsmVoltage[30];
381
382  uint32_t MmHubPadding[7]; /* SMU internal use */
383} AvfsDebugTable_t;
384
385typedef struct {
386  uint8_t  AvfsEn;
387  uint8_t  AvfsVersion;
388  uint8_t  Padding[2];
389
390  int32_t VFT0_m1; /* Q8.24 */
391  int32_t VFT0_m2; /* Q12.12 */
392  int32_t VFT0_b;  /* Q32 */
393
394  int32_t VFT1_m1; /* Q8.16 */
395  int32_t VFT1_m2; /* Q12.12 */
396  int32_t VFT1_b;  /* Q32 */
397
398  int32_t VFT2_m1; /* Q8.16 */
399  int32_t VFT2_m2; /* Q12.12 */
400  int32_t VFT2_b;  /* Q32 */
401
402  int32_t AvfsGb0_m1; /* Q8.16 */
403  int32_t AvfsGb0_m2; /* Q12.12 */
404  int32_t AvfsGb0_b;  /* Q32 */
405
406  int32_t AcBtcGb_m1; /* Q8.24 */
407  int32_t AcBtcGb_m2; /* Q12.12 */
408  int32_t AcBtcGb_b;  /* Q32 */
409
410  uint32_t AvfsTempCold;
411  uint32_t AvfsTempMid;
412  uint32_t AvfsTempHot;
413
414  uint32_t InversionVoltage; /*  in mV with 2 fractional bits */
415
416  int32_t P2V_m1; /* Q8.24 */
417  int32_t P2V_m2; /* Q12.12 */
418  int32_t P2V_b;  /* Q32 */
419
420  uint32_t P2VCharzFreq; /* in 10KHz units */
421
422  uint32_t EnabledAvfsModules;
423
424  uint32_t MmHubPadding[7]; /* SMU internal use */
425} AvfsFuseOverride_t;
426
427/* These defines are used with the following messages:
428 * SMC_MSG_TransferTableDram2Smu
429 * SMC_MSG_TransferTableSmu2Dram
430 */
431#define TABLE_PPTABLE            0
432#define TABLE_WATERMARKS         1
433#define TABLE_AVFS               2
434#define TABLE_AVFS_PSM_DEBUG     3
435#define TABLE_AVFS_FUSE_OVERRIDE 4
436#define TABLE_PMSTATUSLOG        5
437#define TABLE_COUNT              6
438
439/* These defines are used with the SMC_MSG_SetUclkFastSwitch message. */
440#define UCLK_SWITCH_SLOW 0
441#define UCLK_SWITCH_FAST 1
442
443/* GFX DIDT Configuration */
444#define SQ_Enable_MASK 0x1
445#define SQ_IR_MASK 0x2
446#define SQ_PCC_MASK 0x4
447#define SQ_EDC_MASK 0x8
448
449#define TCP_Enable_MASK 0x100
450#define TCP_IR_MASK 0x200
451#define TCP_PCC_MASK 0x400
452#define TCP_EDC_MASK 0x800
453
454#define TD_Enable_MASK 0x10000
455#define TD_IR_MASK 0x20000
456#define TD_PCC_MASK 0x40000
457#define TD_EDC_MASK 0x80000
458
459#define DB_Enable_MASK 0x1000000
460#define DB_IR_MASK 0x2000000
461#define DB_PCC_MASK 0x4000000
462#define DB_EDC_MASK 0x8000000
463
464#define SQ_Enable_SHIFT 0
465#define SQ_IR_SHIFT 1
466#define SQ_PCC_SHIFT 2
467#define SQ_EDC_SHIFT 3
468
469#define TCP_Enable_SHIFT 8
470#define TCP_IR_SHIFT 9
471#define TCP_PCC_SHIFT 10
472#define TCP_EDC_SHIFT 11
473
474#define TD_Enable_SHIFT 16
475#define TD_IR_SHIFT 17
476#define TD_PCC_SHIFT 18
477#define TD_EDC_SHIFT 19
478
479#define DB_Enable_SHIFT 24
480#define DB_IR_SHIFT 25
481#define DB_PCC_SHIFT 26
482#define DB_EDC_SHIFT 27
483
484#define REMOVE_FMAX_MARGIN_BIT     0x0
485#define REMOVE_DCTOL_MARGIN_BIT    0x1
486#define REMOVE_PLATFORM_MARGIN_BIT 0x2
487
488#endif