FILE
hwmgr.h
File preview with syntax highlighting.
linux-6.19.14/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
1/* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef _HWMGR_H_ 24#define _HWMGR_H_ 25 26#include <linux/seq_file.h> 27#include "amd_powerplay.h" 28#include "hardwaremanager.h" 29#include "hwmgr_ppt.h" 30#include "ppatomctrl.h" 31#include "power_state.h" 32#include "smu_helper.h" 33 34struct pp_hwmgr; 35struct phm_fan_speed_info; 36struct pp_atomctrl_voltage_table; 37 38#define VOLTAGE_SCALE 4 39#define VOLTAGE_VID_OFFSET_SCALE1 625 40#define VOLTAGE_VID_OFFSET_SCALE2 100 41 42enum DISPLAY_GAP { 43 DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */ 44 DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */ 45 DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */ 46 DISPLAY_GAP_IGNORE = 3 /* Do not wait. */ 47}; 48typedef enum DISPLAY_GAP DISPLAY_GAP; 49 50enum BACO_STATE { 51 BACO_STATE_OUT = 0, 52 BACO_STATE_IN, 53}; 54 55struct vi_dpm_level { 56 bool enabled; 57 uint32_t value; 58 uint32_t param1; 59}; 60 61struct vi_dpm_table { 62 uint32_t count; 63 struct vi_dpm_level dpm_level[]; 64}; 65 66#define PCIE_PERF_REQ_REMOVE_REGISTRY 0 67#define PCIE_PERF_REQ_FORCE_LOWPOWER 1 68#define PCIE_PERF_REQ_GEN1 2 69#define PCIE_PERF_REQ_GEN2 3 70#define PCIE_PERF_REQ_GEN3 4 71 72enum PHM_BackEnd_Magic { 73 PHM_Dummy_Magic = 0xAA5555AA, 74 PHM_RV770_Magic = 0xDCBAABCD, 75 PHM_Kong_Magic = 0x239478DF, 76 PHM_NIslands_Magic = 0x736C494E, 77 PHM_Sumo_Magic = 0x8339FA11, 78 PHM_SIslands_Magic = 0x369431AC, 79 PHM_Trinity_Magic = 0x96751873, 80 PHM_CIslands_Magic = 0x38AC78B0, 81 PHM_Kv_Magic = 0xDCBBABC0, 82 PHM_VIslands_Magic = 0x20130307, 83 PHM_Cz_Magic = 0x67DCBA25, 84 PHM_Rv_Magic = 0x20161121 85}; 86 87struct phm_set_power_state_input { 88 const struct pp_hw_power_state *pcurrent_state; 89 const struct pp_hw_power_state *pnew_state; 90}; 91 92struct phm_clock_array { 93 uint32_t count; 94 uint32_t values[]; 95}; 96 97struct phm_clock_voltage_dependency_record { 98 uint32_t clk; 99 uint32_t v; 100}; 101 102struct phm_vceclock_voltage_dependency_record { 103 uint32_t ecclk; 104 uint32_t evclk; 105 uint32_t v; 106}; 107 108struct phm_uvdclock_voltage_dependency_record { 109 uint32_t vclk; 110 uint32_t dclk; 111 uint32_t v; 112}; 113 114struct phm_samuclock_voltage_dependency_record { 115 uint32_t samclk; 116 uint32_t v; 117}; 118 119struct phm_acpclock_voltage_dependency_record { 120 uint32_t acpclk; 121 uint32_t v; 122}; 123 124struct phm_clock_voltage_dependency_table { 125 uint32_t count; 126 struct phm_clock_voltage_dependency_record entries[]; 127}; 128 129struct phm_phase_shedding_limits_record { 130 uint32_t Voltage; 131 uint32_t Sclk; 132 uint32_t Mclk; 133}; 134 135struct phm_uvd_clock_voltage_dependency_record { 136 uint32_t vclk; 137 uint32_t dclk; 138 uint32_t v; 139}; 140 141struct phm_uvd_clock_voltage_dependency_table { 142 uint8_t count; 143 struct phm_uvd_clock_voltage_dependency_record entries[]; 144}; 145 146struct phm_acp_clock_voltage_dependency_record { 147 uint32_t acpclk; 148 uint32_t v; 149}; 150 151struct phm_acp_clock_voltage_dependency_table { 152 uint32_t count; 153 struct phm_acp_clock_voltage_dependency_record entries[]; 154}; 155 156struct phm_vce_clock_voltage_dependency_record { 157 uint32_t ecclk; 158 uint32_t evclk; 159 uint32_t v; 160}; 161 162struct phm_phase_shedding_limits_table { 163 uint32_t count; 164 struct phm_phase_shedding_limits_record entries[]; 165}; 166 167struct phm_vceclock_voltage_dependency_table { 168 uint8_t count; 169 struct phm_vceclock_voltage_dependency_record entries[]; 170}; 171 172struct phm_uvdclock_voltage_dependency_table { 173 uint8_t count; 174 struct phm_uvdclock_voltage_dependency_record entries[]; 175}; 176 177struct phm_samuclock_voltage_dependency_table { 178 uint8_t count; 179 struct phm_samuclock_voltage_dependency_record entries[]; 180}; 181 182struct phm_acpclock_voltage_dependency_table { 183 uint32_t count; 184 struct phm_acpclock_voltage_dependency_record entries[]; 185}; 186 187struct phm_vce_clock_voltage_dependency_table { 188 uint8_t count; 189 struct phm_vce_clock_voltage_dependency_record entries[]; 190}; 191 192 193enum SMU_ASIC_RESET_MODE { 194 SMU_ASIC_RESET_MODE_0, 195 SMU_ASIC_RESET_MODE_1, 196 SMU_ASIC_RESET_MODE_2, 197}; 198 199struct pp_smumgr_func { 200 char *name; 201 int (*smu_init)(struct pp_hwmgr *hwmgr); 202 int (*smu_fini)(struct pp_hwmgr *hwmgr); 203 int (*start_smu)(struct pp_hwmgr *hwmgr); 204 int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr, 205 uint32_t firmware); 206 int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr); 207 int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr, 208 uint32_t firmware); 209 uint32_t (*get_argument)(struct pp_hwmgr *hwmgr); 210 int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg); 211 int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr, 212 uint16_t msg, uint32_t parameter); 213 int (*download_pptable_settings)(struct pp_hwmgr *hwmgr, 214 void **table); 215 int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr); 216 int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type); 217 int (*process_firmware_header)(struct pp_hwmgr *hwmgr); 218 int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr); 219 int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr); 220 int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr); 221 int (*init_smc_table)(struct pp_hwmgr *hwmgr); 222 int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr); 223 int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr); 224 int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr); 225 uint32_t (*get_offsetof)(uint32_t type, uint32_t member); 226 uint32_t (*get_mac_definition)(uint32_t value); 227 bool (*is_dpm_running)(struct pp_hwmgr *hwmgr); 228 bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr); 229 int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting); 230 int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */ 231 int (*stop_smc)(struct pp_hwmgr *hwmgr); 232}; 233 234struct pp_hwmgr_func { 235 int (*backend_init)(struct pp_hwmgr *hw_mgr); 236 int (*backend_fini)(struct pp_hwmgr *hw_mgr); 237 int (*asic_setup)(struct pp_hwmgr *hw_mgr); 238 int (*get_power_state_size)(struct pp_hwmgr *hw_mgr); 239 240 int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr, 241 struct pp_power_state *prequest_ps, 242 const struct pp_power_state *pcurrent_ps); 243 244 int (*apply_clocks_adjust_rules)(struct pp_hwmgr *hwmgr); 245 246 int (*force_dpm_level)(struct pp_hwmgr *hw_mgr, 247 enum amd_dpm_forced_level level); 248 249 int (*dynamic_state_management_enable)( 250 struct pp_hwmgr *hw_mgr); 251 int (*dynamic_state_management_disable)( 252 struct pp_hwmgr *hw_mgr); 253 254 int (*patch_boot_state)(struct pp_hwmgr *hwmgr, 255 struct pp_hw_power_state *hw_ps); 256 257 int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr, 258 unsigned long, struct pp_power_state *); 259 int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr); 260 void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate); 261 void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate); 262 void (*powergate_acp)(struct pp_hwmgr *hwmgr, bool bgate); 263 uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low); 264 uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low); 265 int (*power_state_set)(struct pp_hwmgr *hwmgr, 266 const void *state); 267 int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr); 268 int (*pre_display_config_changed)(struct pp_hwmgr *hwmgr); 269 int (*display_config_changed)(struct pp_hwmgr *hwmgr); 270 int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr); 271 int (*update_clock_gatings)(struct pp_hwmgr *hwmgr, 272 const uint32_t *msg_id); 273 int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm); 274 int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm); 275 int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr); 276 int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info); 277 void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode); 278 uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr); 279 int (*set_fan_speed_pwm)(struct pp_hwmgr *hwmgr, uint32_t speed); 280 int (*get_fan_speed_pwm)(struct pp_hwmgr *hwmgr, uint32_t *speed); 281 int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t speed); 282 int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed); 283 int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr); 284 int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr); 285 int (*register_irq_handlers)(struct pp_hwmgr *hwmgr); 286 bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr); 287 int (*check_states_equal)(struct pp_hwmgr *hwmgr, 288 const struct pp_hw_power_state *pstate1, 289 const struct pp_hw_power_state *pstate2, 290 bool *equal); 291 int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr); 292 int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time, 293 bool cc6_disable, bool pstate_disable, 294 bool pstate_switch_disable); 295 int (*get_dal_power_level)(struct pp_hwmgr *hwmgr, 296 struct amd_pp_simple_clock_info *info); 297 int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *, 298 PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *); 299 int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr, 300 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info); 301 int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks); 302 int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr, 303 enum amd_pp_clock_type type, 304 struct pp_clock_levels_with_latency *clocks); 305 int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr, 306 enum amd_pp_clock_type type, 307 struct pp_clock_levels_with_voltage *clocks); 308 int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges); 309 int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr, 310 struct pp_display_clock_request *clock); 311 int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks); 312 int (*power_off_asic)(struct pp_hwmgr *hwmgr); 313 int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask); 314 int (*emit_clock_levels)(struct pp_hwmgr *hwmgr, 315 enum pp_clock_type type, char *buf, int *offset); 316 int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf); 317 int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable); 318 int (*get_sclk_od)(struct pp_hwmgr *hwmgr); 319 int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value); 320 int (*get_mclk_od)(struct pp_hwmgr *hwmgr); 321 int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value); 322 int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size); 323 int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable); 324 int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr); 325 int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count); 326 int (*set_min_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock); 327 int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range); 328 int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr, 329 uint32_t virtual_addr_low, 330 uint32_t virtual_addr_hi, 331 uint32_t mc_addr_low, 332 uint32_t mc_addr_hi, 333 uint32_t size); 334 int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr, 335 struct PP_TemperatureRange *range); 336 int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf); 337 int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size); 338 int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr, 339 enum PP_OD_DPM_TABLE_COMMAND type, 340 long *input, uint32_t size); 341 int (*set_fine_grain_clk_vol)(struct pp_hwmgr *hwmgr, 342 enum PP_OD_DPM_TABLE_COMMAND type, 343 long *input, uint32_t size); 344 int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n); 345 int (*powergate_mmhub)(struct pp_hwmgr *hwmgr); 346 int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr); 347 int (*powergate_sdma)(struct pp_hwmgr *hwmgr, bool bgate); 348 int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr); 349 int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock); 350 int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock); 351 int (*set_hard_min_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock); 352 int (*set_soft_max_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock); 353 int (*get_bamaco_support)(struct pp_hwmgr *hwmgr); 354 int (*get_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE *state); 355 int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state); 356 int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf); 357 int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks); 358 int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state); 359 int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode); 360 int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool acquire); 361 int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state); 362 int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate); 363 int (*disable_power_features_for_compute_performance)(struct pp_hwmgr *hwmgr, 364 bool disable); 365 ssize_t (*get_gpu_metrics)(struct pp_hwmgr *hwmgr, void **table); 366 int (*gfx_state_change)(struct pp_hwmgr *hwmgr, uint32_t state); 367}; 368 369struct pp_table_func { 370 int (*pptable_init)(struct pp_hwmgr *hw_mgr); 371 int (*pptable_fini)(struct pp_hwmgr *hw_mgr); 372 int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr); 373 int (*pptable_get_vce_state_table_entry)( 374 struct pp_hwmgr *hwmgr, 375 unsigned long i, 376 struct amd_vce_state *vce_state, 377 void **clock_info, 378 unsigned long *flag); 379}; 380 381union phm_cac_leakage_record { 382 struct { 383 uint16_t Vddc; /* in CI, we use it for StdVoltageHiSidd */ 384 uint32_t Leakage; /* in CI, we use it for StdVoltageLoSidd */ 385 }; 386 struct { 387 uint16_t Vddc1; 388 uint16_t Vddc2; 389 uint16_t Vddc3; 390 }; 391}; 392 393struct phm_cac_leakage_table { 394 uint32_t count; 395 union phm_cac_leakage_record entries[]; 396}; 397 398struct phm_samu_clock_voltage_dependency_record { 399 uint32_t samclk; 400 uint32_t v; 401}; 402 403 404struct phm_samu_clock_voltage_dependency_table { 405 uint8_t count; 406 struct phm_samu_clock_voltage_dependency_record entries[]; 407}; 408 409struct phm_cac_tdp_table { 410 uint16_t usTDP; 411 uint16_t usConfigurableTDP; 412 uint16_t usTDC; 413 uint16_t usBatteryPowerLimit; 414 uint16_t usSmallPowerLimit; 415 uint16_t usLowCACLeakage; 416 uint16_t usHighCACLeakage; 417 uint16_t usMaximumPowerDeliveryLimit; 418 uint16_t usEDCLimit; 419 uint16_t usOperatingTempMinLimit; 420 uint16_t usOperatingTempMaxLimit; 421 uint16_t usOperatingTempStep; 422 uint16_t usOperatingTempHyst; 423 uint16_t usDefaultTargetOperatingTemp; 424 uint16_t usTargetOperatingTemp; 425 uint16_t usPowerTuneDataSetID; 426 uint16_t usSoftwareShutdownTemp; 427 uint16_t usClockStretchAmount; 428 uint16_t usTemperatureLimitHotspot; 429 uint16_t usTemperatureLimitLiquid1; 430 uint16_t usTemperatureLimitLiquid2; 431 uint16_t usTemperatureLimitVrVddc; 432 uint16_t usTemperatureLimitVrMvdd; 433 uint16_t usTemperatureLimitPlx; 434 uint8_t ucLiquid1_I2C_address; 435 uint8_t ucLiquid2_I2C_address; 436 uint8_t ucLiquid_I2C_Line; 437 uint8_t ucVr_I2C_address; 438 uint8_t ucVr_I2C_Line; 439 uint8_t ucPlx_I2C_address; 440 uint8_t ucPlx_I2C_Line; 441 uint32_t usBoostPowerLimit; 442 uint8_t ucCKS_LDO_REFSEL; 443 uint8_t ucHotSpotOnly; 444}; 445 446struct phm_tdp_table { 447 uint16_t usTDP; 448 uint16_t usConfigurableTDP; 449 uint16_t usTDC; 450 uint16_t usBatteryPowerLimit; 451 uint16_t usSmallPowerLimit; 452 uint16_t usLowCACLeakage; 453 uint16_t usHighCACLeakage; 454 uint16_t usMaximumPowerDeliveryLimit; 455 uint16_t usEDCLimit; 456 uint16_t usOperatingTempMinLimit; 457 uint16_t usOperatingTempMaxLimit; 458 uint16_t usOperatingTempStep; 459 uint16_t usOperatingTempHyst; 460 uint16_t usDefaultTargetOperatingTemp; 461 uint16_t usTargetOperatingTemp; 462 uint16_t usPowerTuneDataSetID; 463 uint16_t usSoftwareShutdownTemp; 464 uint16_t usClockStretchAmount; 465 uint16_t usTemperatureLimitTedge; 466 uint16_t usTemperatureLimitHotspot; 467 uint16_t usTemperatureLimitLiquid1; 468 uint16_t usTemperatureLimitLiquid2; 469 uint16_t usTemperatureLimitHBM; 470 uint16_t usTemperatureLimitVrVddc; 471 uint16_t usTemperatureLimitVrMvdd; 472 uint16_t usTemperatureLimitPlx; 473 uint8_t ucLiquid1_I2C_address; 474 uint8_t ucLiquid2_I2C_address; 475 uint8_t ucLiquid_I2C_Line; 476 uint8_t ucVr_I2C_address; 477 uint8_t ucVr_I2C_Line; 478 uint8_t ucPlx_I2C_address; 479 uint8_t ucPlx_I2C_Line; 480 uint8_t ucLiquid_I2C_LineSDA; 481 uint8_t ucVr_I2C_LineSDA; 482 uint8_t ucPlx_I2C_LineSDA; 483 uint32_t usBoostPowerLimit; 484 uint16_t usBoostStartTemperature; 485 uint16_t usBoostStopTemperature; 486 uint32_t ulBoostClock; 487}; 488 489struct phm_ppm_table { 490 uint8_t ppm_design; 491 uint16_t cpu_core_number; 492 uint32_t platform_tdp; 493 uint32_t small_ac_platform_tdp; 494 uint32_t platform_tdc; 495 uint32_t small_ac_platform_tdc; 496 uint32_t apu_tdp; 497 uint32_t dgpu_tdp; 498 uint32_t dgpu_ulv_power; 499 uint32_t tj_max; 500}; 501 502struct phm_vq_budgeting_record { 503 uint32_t ulCUs; 504 uint32_t ulSustainableSOCPowerLimitLow; 505 uint32_t ulSustainableSOCPowerLimitHigh; 506 uint32_t ulMinSclkLow; 507 uint32_t ulMinSclkHigh; 508 uint8_t ucDispConfig; 509 uint32_t ulDClk; 510 uint32_t ulEClk; 511 uint32_t ulSustainableSclk; 512 uint32_t ulSustainableCUs; 513}; 514 515struct phm_vq_budgeting_table { 516 uint8_t numEntries; 517 struct phm_vq_budgeting_record entries[0]; 518}; 519 520struct phm_clock_and_voltage_limits { 521 uint32_t sclk; 522 uint32_t mclk; 523 uint32_t gfxclk; 524 uint16_t vddc; 525 uint16_t vddci; 526 uint16_t vddgfx; 527 uint16_t vddmem; 528}; 529 530/* Structure to hold PPTable information */ 531 532struct phm_ppt_v1_information { 533 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk; 534 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk; 535 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk; 536 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk; 537 struct phm_clock_array *valid_sclk_values; 538 struct phm_clock_array *valid_mclk_values; 539 struct phm_clock_array *valid_socclk_values; 540 struct phm_clock_array *valid_dcefclk_values; 541 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; 542 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac; 543 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl; 544 struct phm_ppm_table *ppm_parameter_table; 545 struct phm_cac_tdp_table *cac_dtp_table; 546 struct phm_tdp_table *tdp_table; 547 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table; 548 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; 549 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table; 550 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table; 551 struct phm_ppt_v1_pcie_table *pcie_table; 552 struct phm_ppt_v1_gpio_table *gpio_table; 553 uint16_t us_ulv_voltage_offset; 554 uint16_t us_ulv_smnclk_did; 555 uint16_t us_ulv_mp1clk_did; 556 uint16_t us_ulv_gfxclk_bypass; 557 uint16_t us_gfxclk_slew_rate; 558 uint16_t us_min_gfxclk_freq_limit; 559}; 560 561struct phm_ppt_v2_information { 562 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk; 563 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk; 564 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk; 565 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk; 566 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk; 567 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk; 568 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk; 569 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table; 570 571 struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl; 572 573 struct phm_clock_array *valid_sclk_values; 574 struct phm_clock_array *valid_mclk_values; 575 struct phm_clock_array *valid_socclk_values; 576 struct phm_clock_array *valid_dcefclk_values; 577 578 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; 579 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac; 580 581 struct phm_ppm_table *ppm_parameter_table; 582 struct phm_cac_tdp_table *cac_dtp_table; 583 struct phm_tdp_table *tdp_table; 584 585 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; 586 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table; 587 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table; 588 struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table; 589 590 struct phm_ppt_v1_pcie_table *pcie_table; 591 592 uint16_t us_ulv_voltage_offset; 593 uint16_t us_ulv_smnclk_did; 594 uint16_t us_ulv_mp1clk_did; 595 uint16_t us_ulv_gfxclk_bypass; 596 uint16_t us_gfxclk_slew_rate; 597 uint16_t us_min_gfxclk_freq_limit; 598 599 uint8_t uc_gfx_dpm_voltage_mode; 600 uint8_t uc_soc_dpm_voltage_mode; 601 uint8_t uc_uclk_dpm_voltage_mode; 602 uint8_t uc_uvd_dpm_voltage_mode; 603 uint8_t uc_vce_dpm_voltage_mode; 604 uint8_t uc_mp0_dpm_voltage_mode; 605 uint8_t uc_dcef_dpm_voltage_mode; 606}; 607 608struct phm_ppt_v3_information { 609 uint8_t uc_thermal_controller_type; 610 611 uint16_t us_small_power_limit1; 612 uint16_t us_small_power_limit2; 613 uint16_t us_boost_power_limit; 614 615 uint16_t us_od_turbo_power_limit; 616 uint16_t us_od_powersave_power_limit; 617 uint16_t us_software_shutdown_temp; 618 619 uint32_t *power_saving_clock_max; 620 uint32_t *power_saving_clock_min; 621 622 uint8_t *od_feature_capabilities; 623 uint32_t *od_settings_max; 624 uint32_t *od_settings_min; 625 626 void *smc_pptable; 627}; 628 629struct phm_dynamic_state_info { 630 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk; 631 struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk; 632 struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk; 633 struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk; 634 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl; 635 struct phm_clock_array *valid_sclk_values; 636 struct phm_clock_array *valid_mclk_values; 637 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; 638 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac; 639 uint32_t mclk_sclk_ratio; 640 uint32_t sclk_mclk_delta; 641 uint32_t vddc_vddci_delta; 642 uint32_t min_vddc_for_pcie_gen2; 643 struct phm_cac_leakage_table *cac_leakage_table; 644 struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table; 645 646 struct phm_vce_clock_voltage_dependency_table 647 *vce_clock_voltage_dependency_table; 648 struct phm_uvd_clock_voltage_dependency_table 649 *uvd_clock_voltage_dependency_table; 650 struct phm_acp_clock_voltage_dependency_table 651 *acp_clock_voltage_dependency_table; 652 struct phm_samu_clock_voltage_dependency_table 653 *samu_clock_voltage_dependency_table; 654 655 struct phm_ppm_table *ppm_parameter_table; 656 struct phm_cac_tdp_table *cac_dtp_table; 657 struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk; 658}; 659 660struct pp_fan_info { 661 bool bNoFan; 662 uint8_t ucTachometerPulsesPerRevolution; 663 uint32_t ulMinRPM; 664 uint32_t ulMaxRPM; 665}; 666 667struct pp_advance_fan_control_parameters { 668 uint16_t usTMin; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */ 669 uint16_t usTMed; /* The middle temperature where we change slopes. */ 670 uint16_t usTHigh; /* The high temperature for setting the second slope. */ 671 uint16_t usPWMMin; /* The minimum PWM value in percent (0.01% increments). */ 672 uint16_t usPWMMed; /* The PWM value (in percent) at TMed. */ 673 uint16_t usPWMHigh; /* The PWM value at THigh. */ 674 uint8_t ucTHyst; /* Temperature hysteresis. Integer. */ 675 uint32_t ulCycleDelay; /* The time between two invocations of the fan control routine in microseconds. */ 676 uint16_t usTMax; /* The max temperature */ 677 uint8_t ucFanControlMode; 678 uint16_t usFanPWMMinLimit; 679 uint16_t usFanPWMMaxLimit; 680 uint16_t usFanPWMStep; 681 uint16_t usDefaultMaxFanPWM; 682 uint16_t usFanOutputSensitivity; 683 uint16_t usDefaultFanOutputSensitivity; 684 uint16_t usMaxFanPWM; /* The max Fan PWM value for Fuzzy Fan Control feature */ 685 uint16_t usFanRPMMinLimit; /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */ 686 uint16_t usFanRPMMaxLimit; /* Maximum limit range in percentage, usually set to 100% by default */ 687 uint16_t usFanRPMStep; /* Step increments/decerements, in percent */ 688 uint16_t usDefaultMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */ 689 uint16_t usMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */ 690 uint16_t usFanCurrentLow; /* Low current */ 691 uint16_t usFanCurrentHigh; /* High current */ 692 uint16_t usFanRPMLow; /* Low RPM */ 693 uint16_t usFanRPMHigh; /* High RPM */ 694 uint32_t ulMinFanSCLKAcousticLimit; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */ 695 uint8_t ucTargetTemperature; /* Advanced fan controller target temperature. */ 696 uint8_t ucMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */ 697 uint16_t usFanGainEdge; /* The following is added for Fiji */ 698 uint16_t usFanGainHotspot; 699 uint16_t usFanGainLiquid; 700 uint16_t usFanGainVrVddc; 701 uint16_t usFanGainVrMvdd; 702 uint16_t usFanGainPlx; 703 uint16_t usFanGainHbm; 704 uint8_t ucEnableZeroRPM; 705 uint8_t ucFanStopTemperature; 706 uint8_t ucFanStartTemperature; 707 uint32_t ulMaxFanSCLKAcousticLimit; /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */ 708 uint32_t ulTargetGfxClk; 709 uint16_t usZeroRPMStartTemperature; 710 uint16_t usZeroRPMStopTemperature; 711 uint16_t usMGpuThrottlingRPMLimit; 712}; 713 714struct pp_thermal_controller_info { 715 uint8_t ucType; 716 uint8_t ucI2cLine; 717 uint8_t ucI2cAddress; 718 uint8_t use_hw_fan_control; 719 struct pp_fan_info fanInfo; 720 struct pp_advance_fan_control_parameters advanceFanControlParameters; 721}; 722 723struct phm_microcode_version_info { 724 uint32_t SMC; 725 uint32_t DMCU; 726 uint32_t MC; 727 uint32_t NB; 728}; 729 730enum PP_TABLE_VERSION { 731 PP_TABLE_V0 = 0, 732 PP_TABLE_V1, 733 PP_TABLE_V2, 734 PP_TABLE_MAX 735}; 736 737/** 738 * The main hardware manager structure. 739 */ 740#define Workload_Policy_Max 6 741 742struct pp_hwmgr { 743 void *adev; 744 uint32_t chip_family; 745 uint32_t chip_id; 746 uint32_t smu_version; 747 bool not_vf; 748 bool pm_en; 749 bool pp_one_vf; 750 struct mutex msg_lock; 751 752 uint32_t pp_table_version; 753 void *device; 754 struct pp_smumgr *smumgr; 755 const void *soft_pp_table; 756 uint32_t soft_pp_table_size; 757 void *hardcode_pp_table; 758 bool need_pp_table_upload; 759 760 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS]; 761 uint32_t num_vce_state_tables; 762 763 enum amd_dpm_forced_level dpm_level; 764 enum amd_dpm_forced_level saved_dpm_level; 765 enum amd_dpm_forced_level request_dpm_level; 766 uint32_t usec_timeout; 767 void *pptable; 768 struct phm_platform_descriptor platform_descriptor; 769 void *backend; 770 771 void *smu_backend; 772 const struct pp_smumgr_func *smumgr_funcs; 773 bool is_kicker; 774 775 enum PP_DAL_POWERLEVEL dal_power_level; 776 struct phm_dynamic_state_info dyn_state; 777 const struct pp_hwmgr_func *hwmgr_func; 778 const struct pp_table_func *pptable_func; 779 780 struct pp_power_state *ps; 781 uint32_t num_ps; 782 struct pp_thermal_controller_info thermal_controller; 783 bool fan_ctrl_is_in_default_mode; 784 uint32_t fan_ctrl_default_mode; 785 bool fan_ctrl_enabled; 786 uint32_t tmin; 787 struct phm_microcode_version_info microcode_version_info; 788 uint32_t ps_size; 789 struct pp_power_state *current_ps; 790 struct pp_power_state *request_ps; 791 struct pp_power_state *boot_ps; 792 struct pp_power_state *uvd_ps; 793 const struct amd_pp_display_configuration *display_config; 794 uint32_t feature_mask; 795 bool avfs_supported; 796 /* UMD Pstate */ 797 bool en_umd_pstate; 798 uint32_t power_profile_mode; 799 uint32_t default_power_profile_mode; 800 uint32_t pstate_sclk; 801 uint32_t pstate_mclk; 802 bool od_enabled; 803 uint32_t power_limit; 804 uint32_t default_power_limit; 805 uint32_t workload_mask; 806 uint32_t workload_prority[Workload_Policy_Max]; 807 uint32_t workload_setting[Workload_Policy_Max]; 808 bool gfxoff_state_changed_by_workload; 809 uint32_t pstate_sclk_peak; 810 uint32_t pstate_mclk_peak; 811 812 struct delayed_work swctf_delayed_work; 813}; 814 815int hwmgr_early_init(struct pp_hwmgr *hwmgr); 816int hwmgr_sw_init(struct pp_hwmgr *hwmgr); 817int hwmgr_sw_fini(struct pp_hwmgr *hwmgr); 818int hwmgr_hw_init(struct pp_hwmgr *hwmgr); 819int hwmgr_hw_fini(struct pp_hwmgr *hwmgr); 820int hwmgr_suspend(struct pp_hwmgr *hwmgr); 821int hwmgr_resume(struct pp_hwmgr *hwmgr); 822 823int hwmgr_handle_task(struct pp_hwmgr *hwmgr, 824 enum amd_pp_task task_id, 825 enum amd_pm_state_type *user_state); 826 827 828#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU 829 830int smu7_init_function_pointers(struct pp_hwmgr *hwmgr); 831int smu8_init_function_pointers(struct pp_hwmgr *hwmgr); 832int vega12_hwmgr_init(struct pp_hwmgr *hwmgr); 833int vega20_hwmgr_init(struct pp_hwmgr *hwmgr); 834 835#endif /* _HWMGR_H_ */
~/
Read-only file preview.