amd_powerplay.c

   1/*
   2 * Copyright 2015 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#include <linux/types.h>
  24#include <linux/kernel.h>
  25#include <linux/gfp.h>
  26#include <linux/slab.h>
  27#include <linux/firmware.h>
  28#include <linux/reboot.h>
  29#include "amd_shared.h"
  30#include "power_state.h"
  31#include "amdgpu.h"
  32#include "hwmgr.h"
  33#include "amdgpu_dpm_internal.h"
  34
  35static const struct amd_pm_funcs pp_dpm_funcs;
  36
  37static int amd_powerplay_create(struct amdgpu_device *adev)
  38{
  39	struct pp_hwmgr *hwmgr;
  40
  41	if (adev == NULL)
  42		return -EINVAL;
  43
  44	hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL);
  45	if (hwmgr == NULL)
  46		return -ENOMEM;
  47
  48	hwmgr->adev = adev;
  49	hwmgr->not_vf = !amdgpu_sriov_vf(adev);
  50	hwmgr->device = amdgpu_cgs_create_device(adev);
  51	if (!hwmgr->device) {
  52		kfree(hwmgr);
  53		return -ENOMEM;
  54	}
  55
  56	mutex_init(&hwmgr->msg_lock);
  57	hwmgr->chip_family = adev->family;
  58	hwmgr->chip_id = adev->asic_type;
  59	hwmgr->feature_mask = adev->pm.pp_feature;
  60	hwmgr->display_config = &adev->pm.pm_display_cfg;
  61	adev->powerplay.pp_handle = hwmgr;
  62	adev->powerplay.pp_funcs = &pp_dpm_funcs;
  63	return 0;
  64}
  65
  66
  67static void amd_powerplay_destroy(struct amdgpu_device *adev)
  68{
  69	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
  70
  71	mutex_destroy(&hwmgr->msg_lock);
  72
  73	kfree(hwmgr->hardcode_pp_table);
  74	hwmgr->hardcode_pp_table = NULL;
  75
  76	kfree(hwmgr);
  77	hwmgr = NULL;
  78}
  79
  80static int pp_early_init(struct amdgpu_ip_block *ip_block)
  81{
  82	int ret;
  83	struct amdgpu_device *adev = ip_block->adev;
  84	ret = amd_powerplay_create(adev);
  85
  86	if (ret != 0)
  87		return ret;
  88
  89	ret = hwmgr_early_init(adev->powerplay.pp_handle);
  90	if (ret)
  91		return -EINVAL;
  92
  93	return 0;
  94}
  95
  96static void pp_swctf_delayed_work_handler(struct work_struct *work)
  97{
  98	struct pp_hwmgr *hwmgr =
  99		container_of(work, struct pp_hwmgr, swctf_delayed_work.work);
 100	struct amdgpu_device *adev = hwmgr->adev;
 101	struct amdgpu_dpm_thermal *range =
 102				&adev->pm.dpm.thermal;
 103	uint32_t gpu_temperature, size = sizeof(gpu_temperature);
 104	int ret;
 105
 106	/*
 107	 * If the hotspot/edge temperature is confirmed as below SW CTF setting point
 108	 * after the delay enforced, nothing will be done.
 109	 * Otherwise, a graceful shutdown will be performed to prevent further damage.
 110	 */
 111	if (range->sw_ctf_threshold &&
 112	    hwmgr->hwmgr_func->read_sensor) {
 113		ret = hwmgr->hwmgr_func->read_sensor(hwmgr,
 114						     AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
 115						     &gpu_temperature,
 116						     &size);
 117		/*
 118		 * For some legacy ASICs, hotspot temperature retrieving might be not
 119		 * supported. Check the edge temperature instead then.
 120		 */
 121		if (ret == -EOPNOTSUPP)
 122			ret = hwmgr->hwmgr_func->read_sensor(hwmgr,
 123							     AMDGPU_PP_SENSOR_EDGE_TEMP,
 124							     &gpu_temperature,
 125							     &size);
 126		if (!ret && gpu_temperature / 1000 < range->sw_ctf_threshold)
 127			return;
 128	}
 129
 130	dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
 131	dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
 132	orderly_poweroff(true);
 133}
 134
 135static int pp_sw_init(struct amdgpu_ip_block *ip_block)
 136{
 137	struct amdgpu_device *adev = ip_block->adev;
 138	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
 139	int ret = 0;
 140
 141	ret = hwmgr_sw_init(hwmgr);
 142
 143	pr_debug("powerplay sw init %s\n", ret ? "failed" : "successfully");
 144
 145	if (!ret)
 146		INIT_DELAYED_WORK(&hwmgr->swctf_delayed_work,
 147				  pp_swctf_delayed_work_handler);
 148
 149	return ret;
 150}
 151
 152static int pp_sw_fini(struct amdgpu_ip_block *ip_block)
 153{
 154	struct amdgpu_device *adev = ip_block->adev;
 155	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
 156
 157	hwmgr_sw_fini(hwmgr);
 158
 159	amdgpu_ucode_release(&adev->pm.fw);
 160
 161	return 0;
 162}
 163
 164static int pp_hw_init(struct amdgpu_ip_block *ip_block)
 165{
 166	int ret = 0;
 167	struct amdgpu_device *adev = ip_block->adev;
 168	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
 169
 170	ret = hwmgr_hw_init(hwmgr);
 171
 172	if (ret)
 173		pr_err("powerplay hw init failed\n");
 174
 175	return ret;
 176}
 177
 178static int pp_hw_fini(struct amdgpu_ip_block *ip_block)
 179{
 180	struct pp_hwmgr *hwmgr = ip_block->adev->powerplay.pp_handle;
 181
 182	cancel_delayed_work_sync(&hwmgr->swctf_delayed_work);
 183
 184	hwmgr_hw_fini(hwmgr);
 185
 186	return 0;
 187}
 188
 189static void pp_reserve_vram_for_smu(struct amdgpu_device *adev)
 190{
 191	int r = -EINVAL;
 192	void *cpu_ptr = NULL;
 193	uint64_t gpu_addr;
 194	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
 195
 196	if (amdgpu_bo_create_kernel(adev, adev->pm.smu_prv_buffer_size,
 197						PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 198						&adev->pm.smu_prv_buffer,
 199						&gpu_addr,
 200						&cpu_ptr)) {
 201		DRM_ERROR("amdgpu: failed to create smu prv buffer\n");
 202		return;
 203	}
 204
 205	if (hwmgr->hwmgr_func->notify_cac_buffer_info)
 206		r = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr,
 207					lower_32_bits((unsigned long)cpu_ptr),
 208					upper_32_bits((unsigned long)cpu_ptr),
 209					lower_32_bits(gpu_addr),
 210					upper_32_bits(gpu_addr),
 211					adev->pm.smu_prv_buffer_size);
 212
 213	if (r) {
 214		amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL);
 215		adev->pm.smu_prv_buffer = NULL;
 216		DRM_ERROR("amdgpu: failed to notify SMU buffer address\n");
 217	}
 218}
 219
 220static int pp_late_init(struct amdgpu_ip_block *ip_block)
 221{
 222	struct amdgpu_device *adev = ip_block->adev;
 223	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
 224
 225	if (hwmgr && hwmgr->pm_en)
 226		hwmgr_handle_task(hwmgr,
 227					AMD_PP_TASK_COMPLETE_INIT, NULL);
 228	if (adev->pm.smu_prv_buffer_size != 0)
 229		pp_reserve_vram_for_smu(adev);
 230
 231	return 0;
 232}
 233
 234static void pp_late_fini(struct amdgpu_ip_block *ip_block)
 235{
 236	struct amdgpu_device *adev = ip_block->adev;
 237
 238	if (adev->pm.smu_prv_buffer)
 239		amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL);
 240	amd_powerplay_destroy(adev);
 241}
 242
 243
 244static bool pp_is_idle(struct amdgpu_ip_block *ip_block)
 245{
 246	return false;
 247}
 248
 249static int pp_set_powergating_state(struct amdgpu_ip_block *ip_block,
 250				    enum amd_powergating_state state)
 251{
 252	return 0;
 253}
 254
 255static int pp_suspend(struct amdgpu_ip_block *ip_block)
 256{
 257	struct amdgpu_device *adev = ip_block->adev;
 258	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
 259
 260	cancel_delayed_work_sync(&hwmgr->swctf_delayed_work);
 261
 262	return hwmgr_suspend(hwmgr);
 263}
 264
 265static int pp_resume(struct amdgpu_ip_block *ip_block)
 266{
 267	struct pp_hwmgr *hwmgr = ip_block->adev->powerplay.pp_handle;
 268
 269	return hwmgr_resume(hwmgr);
 270}
 271
 272static int pp_set_clockgating_state(struct amdgpu_ip_block *ip_block,
 273					  enum amd_clockgating_state state)
 274{
 275	return 0;
 276}
 277
 278static const struct amd_ip_funcs pp_ip_funcs = {
 279	.name = "powerplay",
 280	.early_init = pp_early_init,
 281	.late_init = pp_late_init,
 282	.sw_init = pp_sw_init,
 283	.sw_fini = pp_sw_fini,
 284	.hw_init = pp_hw_init,
 285	.hw_fini = pp_hw_fini,
 286	.late_fini = pp_late_fini,
 287	.suspend = pp_suspend,
 288	.resume = pp_resume,
 289	.is_idle = pp_is_idle,
 290	.set_clockgating_state = pp_set_clockgating_state,
 291	.set_powergating_state = pp_set_powergating_state,
 292};
 293
 294const struct amdgpu_ip_block_version pp_smu_ip_block =
 295{
 296	.type = AMD_IP_BLOCK_TYPE_SMC,
 297	.major = 1,
 298	.minor = 0,
 299	.rev = 0,
 300	.funcs = &pp_ip_funcs,
 301};
 302
 303/* This interface only be supported On Vi,
 304 * because only smu7/8 can help to load gfx/sdma fw,
 305 * smu need to be enabled before load other ip's fw.
 306 * so call start smu to load smu7 fw and other ip's fw
 307 */
 308static int pp_dpm_load_fw(void *handle)
 309{
 310	struct pp_hwmgr *hwmgr = handle;
 311
 312	if (!hwmgr || !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->start_smu)
 313		return -EINVAL;
 314
 315	if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
 316		pr_err("fw load failed\n");
 317		return -EINVAL;
 318	}
 319
 320	return 0;
 321}
 322
 323static int pp_dpm_fw_loading_complete(void *handle)
 324{
 325	return 0;
 326}
 327
 328static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
 329{
 330	struct pp_hwmgr *hwmgr = handle;
 331
 332	if (!hwmgr || !hwmgr->pm_en)
 333		return -EINVAL;
 334
 335	if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
 336		pr_info_ratelimited("%s was not implemented.\n", __func__);
 337		return 0;
 338	}
 339
 340	return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 341}
 342
 343static void pp_dpm_en_umd_pstate(struct pp_hwmgr  *hwmgr,
 344						enum amd_dpm_forced_level *level)
 345{
 346	uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 347					AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 348					AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 349					AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 350
 351	if (!(hwmgr->dpm_level & profile_mode_mask)) {
 352		/* enter umd pstate, save current level, disable gfx cg*/
 353		if (*level & profile_mode_mask) {
 354			hwmgr->saved_dpm_level = hwmgr->dpm_level;
 355			hwmgr->en_umd_pstate = true;
 356		}
 357	} else {
 358		/* exit umd pstate, restore level, enable gfx cg*/
 359		if (!(*level & profile_mode_mask)) {
 360			if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
 361				*level = hwmgr->saved_dpm_level;
 362			hwmgr->en_umd_pstate = false;
 363		}
 364	}
 365}
 366
 367static int pp_dpm_force_performance_level(void *handle,
 368					enum amd_dpm_forced_level level)
 369{
 370	struct pp_hwmgr *hwmgr = handle;
 371
 372	if (!hwmgr || !hwmgr->pm_en)
 373		return -EINVAL;
 374
 375	if (level == hwmgr->dpm_level)
 376		return 0;
 377
 378	pp_dpm_en_umd_pstate(hwmgr, &level);
 379	hwmgr->request_dpm_level = level;
 380	hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 381
 382	return 0;
 383}
 384
 385static enum amd_dpm_forced_level pp_dpm_get_performance_level(
 386								void *handle)
 387{
 388	struct pp_hwmgr *hwmgr = handle;
 389
 390	if (!hwmgr || !hwmgr->pm_en)
 391		return -EINVAL;
 392
 393	return hwmgr->dpm_level;
 394}
 395
 396static uint32_t pp_dpm_get_sclk(void *handle, bool low)
 397{
 398	struct pp_hwmgr *hwmgr = handle;
 399
 400	if (!hwmgr || !hwmgr->pm_en)
 401		return 0;
 402
 403	if (hwmgr->hwmgr_func->get_sclk == NULL) {
 404		pr_info_ratelimited("%s was not implemented.\n", __func__);
 405		return 0;
 406	}
 407	return hwmgr->hwmgr_func->get_sclk(hwmgr, low);
 408}
 409
 410static uint32_t pp_dpm_get_mclk(void *handle, bool low)
 411{
 412	struct pp_hwmgr *hwmgr = handle;
 413
 414	if (!hwmgr || !hwmgr->pm_en)
 415		return 0;
 416
 417	if (hwmgr->hwmgr_func->get_mclk == NULL) {
 418		pr_info_ratelimited("%s was not implemented.\n", __func__);
 419		return 0;
 420	}
 421	return hwmgr->hwmgr_func->get_mclk(hwmgr, low);
 422}
 423
 424static void pp_dpm_powergate_vce(void *handle, bool gate)
 425{
 426	struct pp_hwmgr *hwmgr = handle;
 427
 428	if (!hwmgr || !hwmgr->pm_en)
 429		return;
 430
 431	if (hwmgr->hwmgr_func->powergate_vce == NULL) {
 432		pr_info_ratelimited("%s was not implemented.\n", __func__);
 433		return;
 434	}
 435	hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
 436}
 437
 438static void pp_dpm_powergate_uvd(void *handle, bool gate)
 439{
 440	struct pp_hwmgr *hwmgr = handle;
 441
 442	if (!hwmgr || !hwmgr->pm_en)
 443		return;
 444
 445	if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
 446		pr_info_ratelimited("%s was not implemented.\n", __func__);
 447		return;
 448	}
 449	hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
 450}
 451
 452static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
 453		enum amd_pm_state_type *user_state)
 454{
 455	struct pp_hwmgr *hwmgr = handle;
 456
 457	if (!hwmgr || !hwmgr->pm_en)
 458		return -EINVAL;
 459
 460	return hwmgr_handle_task(hwmgr, task_id, user_state);
 461}
 462
 463static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
 464{
 465	struct pp_hwmgr *hwmgr = handle;
 466	struct pp_power_state *state;
 467	enum amd_pm_state_type pm_type;
 468
 469	if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps)
 470		return -EINVAL;
 471
 472	state = hwmgr->current_ps;
 473
 474	switch (state->classification.ui_label) {
 475	case PP_StateUILabel_Battery:
 476		pm_type = POWER_STATE_TYPE_BATTERY;
 477		break;
 478	case PP_StateUILabel_Balanced:
 479		pm_type = POWER_STATE_TYPE_BALANCED;
 480		break;
 481	case PP_StateUILabel_Performance:
 482		pm_type = POWER_STATE_TYPE_PERFORMANCE;
 483		break;
 484	default:
 485		if (state->classification.flags & PP_StateClassificationFlag_Boot)
 486			pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
 487		else
 488			pm_type = POWER_STATE_TYPE_DEFAULT;
 489		break;
 490	}
 491
 492	return pm_type;
 493}
 494
 495static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
 496{
 497	struct pp_hwmgr *hwmgr = handle;
 498
 499	if (!hwmgr || !hwmgr->pm_en)
 500		return -EOPNOTSUPP;
 501
 502	if (hwmgr->hwmgr_func->set_fan_control_mode == NULL)
 503		return -EOPNOTSUPP;
 504
 505	if (mode == U32_MAX)
 506		return -EINVAL;
 507
 508	hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
 509
 510	return 0;
 511}
 512
 513static int pp_dpm_get_fan_control_mode(void *handle, uint32_t *fan_mode)
 514{
 515	struct pp_hwmgr *hwmgr = handle;
 516
 517	if (!hwmgr || !hwmgr->pm_en)
 518		return -EOPNOTSUPP;
 519
 520	if (hwmgr->hwmgr_func->get_fan_control_mode == NULL)
 521		return -EOPNOTSUPP;
 522
 523	if (!fan_mode)
 524		return -EINVAL;
 525
 526	*fan_mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
 527	return 0;
 528}
 529
 530static int pp_dpm_set_fan_speed_pwm(void *handle, uint32_t speed)
 531{
 532	struct pp_hwmgr *hwmgr = handle;
 533
 534	if (!hwmgr || !hwmgr->pm_en)
 535		return -EOPNOTSUPP;
 536
 537	if (hwmgr->hwmgr_func->set_fan_speed_pwm == NULL)
 538		return -EOPNOTSUPP;
 539
 540	if (speed == U32_MAX)
 541		return -EINVAL;
 542
 543	return hwmgr->hwmgr_func->set_fan_speed_pwm(hwmgr, speed);
 544}
 545
 546static int pp_dpm_get_fan_speed_pwm(void *handle, uint32_t *speed)
 547{
 548	struct pp_hwmgr *hwmgr = handle;
 549
 550	if (!hwmgr || !hwmgr->pm_en)
 551		return -EOPNOTSUPP;
 552
 553	if (hwmgr->hwmgr_func->get_fan_speed_pwm == NULL)
 554		return -EOPNOTSUPP;
 555
 556	if (!speed)
 557		return -EINVAL;
 558
 559	return hwmgr->hwmgr_func->get_fan_speed_pwm(hwmgr, speed);
 560}
 561
 562static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
 563{
 564	struct pp_hwmgr *hwmgr = handle;
 565
 566	if (!hwmgr || !hwmgr->pm_en)
 567		return -EOPNOTSUPP;
 568
 569	if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
 570		return -EOPNOTSUPP;
 571
 572	if (!rpm)
 573		return -EINVAL;
 574
 575	return hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm);
 576}
 577
 578static int pp_dpm_set_fan_speed_rpm(void *handle, uint32_t rpm)
 579{
 580	struct pp_hwmgr *hwmgr = handle;
 581
 582	if (!hwmgr || !hwmgr->pm_en)
 583		return -EOPNOTSUPP;
 584
 585	if (hwmgr->hwmgr_func->set_fan_speed_rpm == NULL)
 586		return -EOPNOTSUPP;
 587
 588	if (rpm == U32_MAX)
 589		return -EINVAL;
 590
 591	return hwmgr->hwmgr_func->set_fan_speed_rpm(hwmgr, rpm);
 592}
 593
 594static int pp_dpm_get_pp_num_states(void *handle,
 595		struct pp_states_info *data)
 596{
 597	struct pp_hwmgr *hwmgr = handle;
 598	int i;
 599
 600	memset(data, 0, sizeof(*data));
 601
 602	if (!hwmgr || !hwmgr->pm_en || !hwmgr->ps)
 603		return -EINVAL;
 604
 605	data->nums = hwmgr->num_ps;
 606
 607	for (i = 0; i < hwmgr->num_ps; i++) {
 608		struct pp_power_state *state = (struct pp_power_state *)
 609				((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
 610		switch (state->classification.ui_label) {
 611		case PP_StateUILabel_Battery:
 612			data->states[i] = POWER_STATE_TYPE_BATTERY;
 613			break;
 614		case PP_StateUILabel_Balanced:
 615			data->states[i] = POWER_STATE_TYPE_BALANCED;
 616			break;
 617		case PP_StateUILabel_Performance:
 618			data->states[i] = POWER_STATE_TYPE_PERFORMANCE;
 619			break;
 620		default:
 621			if (state->classification.flags & PP_StateClassificationFlag_Boot)
 622				data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT;
 623			else
 624				data->states[i] = POWER_STATE_TYPE_DEFAULT;
 625		}
 626	}
 627	return 0;
 628}
 629
 630static int pp_dpm_get_pp_table(void *handle, char **table)
 631{
 632	struct pp_hwmgr *hwmgr = handle;
 633
 634	if (!hwmgr || !hwmgr->pm_en || !table)
 635		return -EINVAL;
 636
 637	if (!hwmgr->soft_pp_table)
 638		return -EOPNOTSUPP;
 639
 640	*table = (char *)hwmgr->soft_pp_table;
 641	return hwmgr->soft_pp_table_size;
 642}
 643
 644static int amd_powerplay_reset(void *handle)
 645{
 646	struct pp_hwmgr *hwmgr = handle;
 647	int ret;
 648
 649	ret = hwmgr_hw_fini(hwmgr);
 650	if (ret)
 651		return ret;
 652
 653	ret = hwmgr_hw_init(hwmgr);
 654	if (ret)
 655		return ret;
 656
 657	return hwmgr_handle_task(hwmgr, AMD_PP_TASK_COMPLETE_INIT, NULL);
 658}
 659
 660static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
 661{
 662	struct pp_hwmgr *hwmgr = handle;
 663	int ret = -ENOMEM;
 664
 665	if (!hwmgr || !hwmgr->pm_en)
 666		return -EINVAL;
 667
 668	if (!hwmgr->hardcode_pp_table) {
 669		hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
 670						   hwmgr->soft_pp_table_size,
 671						   GFP_KERNEL);
 672		if (!hwmgr->hardcode_pp_table)
 673			return ret;
 674	}
 675
 676	memcpy(hwmgr->hardcode_pp_table, buf, size);
 677
 678	hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
 679
 680	ret = amd_powerplay_reset(handle);
 681	if (ret)
 682		return ret;
 683
 684	if (hwmgr->hwmgr_func->avfs_control)
 685		ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false);
 686
 687	return ret;
 688}
 689
 690static int pp_dpm_force_clock_level(void *handle,
 691		enum pp_clock_type type, uint32_t mask)
 692{
 693	struct pp_hwmgr *hwmgr = handle;
 694
 695	if (!hwmgr || !hwmgr->pm_en)
 696		return -EINVAL;
 697
 698	if (hwmgr->hwmgr_func->force_clock_level == NULL) {
 699		pr_info_ratelimited("%s was not implemented.\n", __func__);
 700		return 0;
 701	}
 702
 703	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
 704		pr_debug("force clock level is for dpm manual mode only.\n");
 705		return -EINVAL;
 706	}
 707
 708	return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
 709}
 710
 711static int pp_dpm_emit_clock_levels(void *handle,
 712				    enum pp_clock_type type,
 713				    char *buf,
 714				    int *offset)
 715{
 716	struct pp_hwmgr *hwmgr = handle;
 717
 718	if (!hwmgr || !hwmgr->pm_en)
 719		return -EOPNOTSUPP;
 720
 721	if (!hwmgr->hwmgr_func->emit_clock_levels)
 722		return -ENOENT;
 723
 724	return hwmgr->hwmgr_func->emit_clock_levels(hwmgr, type, buf, offset);
 725}
 726
 727static int pp_dpm_print_clock_levels(void *handle,
 728		enum pp_clock_type type, char *buf)
 729{
 730	struct pp_hwmgr *hwmgr = handle;
 731
 732	if (!hwmgr || !hwmgr->pm_en)
 733		return -EINVAL;
 734
 735	if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
 736		pr_info_ratelimited("%s was not implemented.\n", __func__);
 737		return 0;
 738	}
 739	return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
 740}
 741
 742static int pp_dpm_get_sclk_od(void *handle)
 743{
 744	struct pp_hwmgr *hwmgr = handle;
 745
 746	if (!hwmgr || !hwmgr->pm_en)
 747		return -EINVAL;
 748
 749	if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
 750		pr_info_ratelimited("%s was not implemented.\n", __func__);
 751		return 0;
 752	}
 753	return hwmgr->hwmgr_func->get_sclk_od(hwmgr);
 754}
 755
 756static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
 757{
 758	struct pp_hwmgr *hwmgr = handle;
 759
 760	if (!hwmgr || !hwmgr->pm_en)
 761		return -EINVAL;
 762
 763	if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
 764		pr_info_ratelimited("%s was not implemented.\n", __func__);
 765		return 0;
 766	}
 767
 768	return hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
 769}
 770
 771static int pp_dpm_get_mclk_od(void *handle)
 772{
 773	struct pp_hwmgr *hwmgr = handle;
 774
 775	if (!hwmgr || !hwmgr->pm_en)
 776		return -EINVAL;
 777
 778	if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
 779		pr_info_ratelimited("%s was not implemented.\n", __func__);
 780		return 0;
 781	}
 782	return hwmgr->hwmgr_func->get_mclk_od(hwmgr);
 783}
 784
 785static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
 786{
 787	struct pp_hwmgr *hwmgr = handle;
 788
 789	if (!hwmgr || !hwmgr->pm_en)
 790		return -EINVAL;
 791
 792	if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
 793		pr_info_ratelimited("%s was not implemented.\n", __func__);
 794		return 0;
 795	}
 796	return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
 797}
 798
 799static int pp_dpm_read_sensor(void *handle, int idx,
 800			      void *value, int *size)
 801{
 802	struct pp_hwmgr *hwmgr = handle;
 803
 804	if (!hwmgr || !hwmgr->pm_en || !value)
 805		return -EINVAL;
 806
 807	switch (idx) {
 808	case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
 809		*((uint32_t *)value) = hwmgr->pstate_sclk * 100;
 810		return 0;
 811	case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
 812		*((uint32_t *)value) = hwmgr->pstate_mclk * 100;
 813		return 0;
 814	case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK:
 815		*((uint32_t *)value) = hwmgr->pstate_sclk_peak * 100;
 816		return 0;
 817	case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK:
 818		*((uint32_t *)value) = hwmgr->pstate_mclk_peak * 100;
 819		return 0;
 820	case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
 821		*((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMinRPM;
 822		return 0;
 823	case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
 824		*((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMaxRPM;
 825		return 0;
 826	default:
 827		return hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
 828	}
 829}
 830
 831static struct amd_vce_state*
 832pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
 833{
 834	struct pp_hwmgr *hwmgr = handle;
 835
 836	if (!hwmgr || !hwmgr->pm_en)
 837		return NULL;
 838
 839	if (idx < hwmgr->num_vce_state_tables)
 840		return &hwmgr->vce_states[idx];
 841	return NULL;
 842}
 843
 844static int pp_get_power_profile_mode(void *handle, char *buf)
 845{
 846	struct pp_hwmgr *hwmgr = handle;
 847
 848	if (!hwmgr || !hwmgr->pm_en || !hwmgr->hwmgr_func->get_power_profile_mode)
 849		return -EOPNOTSUPP;
 850	if (!buf)
 851		return -EINVAL;
 852
 853	return hwmgr->hwmgr_func->get_power_profile_mode(hwmgr, buf);
 854}
 855
 856static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
 857{
 858	struct pp_hwmgr *hwmgr = handle;
 859
 860	if (!hwmgr || !hwmgr->pm_en || !hwmgr->hwmgr_func->set_power_profile_mode)
 861		return -EOPNOTSUPP;
 862
 863	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
 864		pr_debug("power profile setting is for manual dpm mode only.\n");
 865		return -EINVAL;
 866	}
 867
 868	return hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
 869}
 870
 871static int pp_set_fine_grain_clk_vol(void *handle, uint32_t type, long *input, uint32_t size)
 872{
 873	struct pp_hwmgr *hwmgr = handle;
 874
 875	if (!hwmgr || !hwmgr->pm_en)
 876		return -EINVAL;
 877
 878	if (hwmgr->hwmgr_func->set_fine_grain_clk_vol == NULL)
 879		return 0;
 880
 881	return hwmgr->hwmgr_func->set_fine_grain_clk_vol(hwmgr, type, input, size);
 882}
 883
 884static int pp_odn_edit_dpm_table(void *handle, enum PP_OD_DPM_TABLE_COMMAND type,
 885				 long *input, uint32_t size)
 886{
 887	struct pp_hwmgr *hwmgr = handle;
 888
 889	if (!hwmgr || !hwmgr->pm_en)
 890		return -EINVAL;
 891
 892	if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
 893		pr_info_ratelimited("%s was not implemented.\n", __func__);
 894		return 0;
 895	}
 896
 897	return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size);
 898}
 899
 900static int pp_dpm_set_mp1_state(void *handle, enum pp_mp1_state mp1_state)
 901{
 902	struct pp_hwmgr *hwmgr = handle;
 903
 904	if (!hwmgr)
 905		return -EINVAL;
 906
 907	if (!hwmgr->pm_en)
 908		return 0;
 909
 910	if (hwmgr->hwmgr_func->set_mp1_state)
 911		return hwmgr->hwmgr_func->set_mp1_state(hwmgr, mp1_state);
 912
 913	return 0;
 914}
 915
 916static int pp_dpm_switch_power_profile(void *handle,
 917		enum PP_SMC_POWER_PROFILE type, bool en)
 918{
 919	struct pp_hwmgr *hwmgr = handle;
 920	long workload[1];
 921	uint32_t index;
 922
 923	if (!hwmgr || !hwmgr->pm_en)
 924		return -EINVAL;
 925
 926	if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
 927		pr_info_ratelimited("%s was not implemented.\n", __func__);
 928		return -EINVAL;
 929	}
 930
 931	if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
 932		return -EINVAL;
 933
 934	if (!en) {
 935		hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]);
 936		index = fls(hwmgr->workload_mask);
 937		index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0;
 938		workload[0] = hwmgr->workload_setting[index];
 939	} else {
 940		hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]);
 941		index = fls(hwmgr->workload_mask);
 942		index = index <= Workload_Policy_Max ? index - 1 : 0;
 943		workload[0] = hwmgr->workload_setting[index];
 944	}
 945
 946	if (type == PP_SMC_POWER_PROFILE_COMPUTE &&
 947		hwmgr->hwmgr_func->disable_power_features_for_compute_performance) {
 948			if (hwmgr->hwmgr_func->disable_power_features_for_compute_performance(hwmgr, en))
 949				return -EINVAL;
 950	}
 951
 952	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
 953		hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, workload, 0);
 954
 955	return 0;
 956}
 957
 958static int pp_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit)
 959{
 960	struct pp_hwmgr *hwmgr = handle;
 961	uint32_t max_power_limit;
 962
 963	if (!hwmgr || !hwmgr->pm_en)
 964		return -EINVAL;
 965
 966	if (hwmgr->hwmgr_func->set_power_limit == NULL) {
 967		pr_info_ratelimited("%s was not implemented.\n", __func__);
 968		return -EINVAL;
 969	}
 970
 971	if (limit == 0)
 972		limit = hwmgr->default_power_limit;
 973
 974	max_power_limit = hwmgr->default_power_limit;
 975	if (hwmgr->od_enabled) {
 976		max_power_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
 977		max_power_limit /= 100;
 978	}
 979
 980	if (limit > max_power_limit)
 981		return -EINVAL;
 982
 983	hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
 984	hwmgr->power_limit = limit;
 985	return 0;
 986}
 987
 988static int pp_get_power_limit(void *handle, uint32_t *limit,
 989			      enum pp_power_limit_level pp_limit_level,
 990			      enum pp_power_type power_type)
 991{
 992	struct pp_hwmgr *hwmgr = handle;
 993	int ret = 0;
 994
 995	if (!hwmgr || !hwmgr->pm_en || !limit)
 996		return -EINVAL;
 997
 998	if (power_type != PP_PWR_TYPE_SUSTAINED)
 999		return -EOPNOTSUPP;
1000
1001	switch (pp_limit_level) {
1002		case PP_PWR_LIMIT_CURRENT:
1003			*limit = hwmgr->power_limit;
1004			break;
1005		case PP_PWR_LIMIT_DEFAULT:
1006			*limit = hwmgr->default_power_limit;
1007			break;
1008		case PP_PWR_LIMIT_MAX:
1009			*limit = hwmgr->default_power_limit;
1010			if (hwmgr->od_enabled) {
1011				*limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
1012				*limit /= 100;
1013			}
1014			break;
1015		case PP_PWR_LIMIT_MIN:
1016			*limit = 0;
1017			break;
1018		default:
1019			ret = -EOPNOTSUPP;
1020			break;
1021	}
1022
1023	return ret;
1024}
1025
1026static int pp_display_configuration_change(void *handle,
1027	const struct amd_pp_display_configuration *display_config)
1028{
1029	struct pp_hwmgr *hwmgr = handle;
1030
1031	if (!hwmgr || !hwmgr->pm_en)
1032		return -EINVAL;
1033
1034	phm_store_dal_configuration_data(hwmgr, display_config);
1035	return 0;
1036}
1037
1038static int pp_get_display_power_level(void *handle,
1039		struct amd_pp_simple_clock_info *output)
1040{
1041	struct pp_hwmgr *hwmgr = handle;
1042
1043	if (!hwmgr || !hwmgr->pm_en || !output)
1044		return -EINVAL;
1045
1046	return phm_get_dal_power_level(hwmgr, output);
1047}
1048
1049static int pp_get_current_clocks(void *handle,
1050		struct amd_pp_clock_info *clocks)
1051{
1052	struct amd_pp_simple_clock_info simple_clocks = { 0 };
1053	struct pp_clock_info hw_clocks;
1054	struct pp_hwmgr *hwmgr = handle;
1055	int ret = 0;
1056
1057	if (!hwmgr || !hwmgr->pm_en)
1058		return -EINVAL;
1059
1060	phm_get_dal_power_level(hwmgr, &simple_clocks);
1061
1062	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1063					PHM_PlatformCaps_PowerContainment))
1064		ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1065					&hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment);
1066	else
1067		ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1068					&hw_clocks, PHM_PerformanceLevelDesignation_Activity);
1069
1070	if (ret) {
1071		pr_debug("Error in phm_get_clock_info \n");
1072		return -EINVAL;
1073	}
1074
1075	clocks->min_engine_clock = hw_clocks.min_eng_clk;
1076	clocks->max_engine_clock = hw_clocks.max_eng_clk;
1077	clocks->min_memory_clock = hw_clocks.min_mem_clk;
1078	clocks->max_memory_clock = hw_clocks.max_mem_clk;
1079	clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1080	clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1081
1082	clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1083	clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1084
1085	if (simple_clocks.level == 0)
1086		clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1087	else
1088		clocks->max_clocks_state = simple_clocks.level;
1089
1090	if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
1091		clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1092		clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1093	}
1094	return 0;
1095}
1096
1097static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
1098{
1099	struct pp_hwmgr *hwmgr = handle;
1100
1101	if (!hwmgr || !hwmgr->pm_en)
1102		return -EINVAL;
1103
1104	if (clocks == NULL)
1105		return -EINVAL;
1106
1107	return phm_get_clock_by_type(hwmgr, type, clocks);
1108}
1109
1110static int pp_get_clock_by_type_with_latency(void *handle,
1111		enum amd_pp_clock_type type,
1112		struct pp_clock_levels_with_latency *clocks)
1113{
1114	struct pp_hwmgr *hwmgr = handle;
1115
1116	if (!hwmgr || !hwmgr->pm_en || !clocks)
1117		return -EINVAL;
1118
1119	return phm_get_clock_by_type_with_latency(hwmgr, type, clocks);
1120}
1121
1122static int pp_get_clock_by_type_with_voltage(void *handle,
1123		enum amd_pp_clock_type type,
1124		struct pp_clock_levels_with_voltage *clocks)
1125{
1126	struct pp_hwmgr *hwmgr = handle;
1127
1128	if (!hwmgr || !hwmgr->pm_en || !clocks)
1129		return -EINVAL;
1130
1131	return phm_get_clock_by_type_with_voltage(hwmgr, type, clocks);
1132}
1133
1134static int pp_set_watermarks_for_clocks_ranges(void *handle,
1135		void *clock_ranges)
1136{
1137	struct pp_hwmgr *hwmgr = handle;
1138
1139	if (!hwmgr || !hwmgr->pm_en || !clock_ranges)
1140		return -EINVAL;
1141
1142	return phm_set_watermarks_for_clocks_ranges(hwmgr,
1143						    clock_ranges);
1144}
1145
1146static int pp_display_clock_voltage_request(void *handle,
1147		struct pp_display_clock_request *clock)
1148{
1149	struct pp_hwmgr *hwmgr = handle;
1150
1151	if (!hwmgr || !hwmgr->pm_en || !clock)
1152		return -EINVAL;
1153
1154	return phm_display_clock_voltage_request(hwmgr, clock);
1155}
1156
1157static int pp_get_display_mode_validation_clocks(void *handle,
1158		struct amd_pp_simple_clock_info *clocks)
1159{
1160	struct pp_hwmgr *hwmgr = handle;
1161	int ret = 0;
1162
1163	if (!hwmgr || !hwmgr->pm_en || !clocks)
1164		return -EINVAL;
1165
1166	clocks->level = PP_DAL_POWERLEVEL_7;
1167
1168	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
1169		ret = phm_get_max_high_clocks(hwmgr, clocks);
1170
1171	return ret;
1172}
1173
1174static int pp_dpm_powergate_mmhub(void *handle)
1175{
1176	struct pp_hwmgr *hwmgr = handle;
1177
1178	if (!hwmgr || !hwmgr->pm_en)
1179		return -EINVAL;
1180
1181	if (hwmgr->hwmgr_func->powergate_mmhub == NULL) {
1182		pr_info_ratelimited("%s was not implemented.\n", __func__);
1183		return 0;
1184	}
1185
1186	return hwmgr->hwmgr_func->powergate_mmhub(hwmgr);
1187}
1188
1189static int pp_dpm_powergate_gfx(void *handle, bool gate)
1190{
1191	struct pp_hwmgr *hwmgr = handle;
1192
1193	if (!hwmgr || !hwmgr->pm_en)
1194		return 0;
1195
1196	if (hwmgr->hwmgr_func->powergate_gfx == NULL) {
1197		pr_info_ratelimited("%s was not implemented.\n", __func__);
1198		return 0;
1199	}
1200
1201	return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate);
1202}
1203
1204static void pp_dpm_powergate_acp(void *handle, bool gate)
1205{
1206	struct pp_hwmgr *hwmgr = handle;
1207
1208	if (!hwmgr || !hwmgr->pm_en)
1209		return;
1210
1211	if (hwmgr->hwmgr_func->powergate_acp == NULL) {
1212		pr_info_ratelimited("%s was not implemented.\n", __func__);
1213		return;
1214	}
1215
1216	hwmgr->hwmgr_func->powergate_acp(hwmgr, gate);
1217}
1218
1219static void pp_dpm_powergate_sdma(void *handle, bool gate)
1220{
1221	struct pp_hwmgr *hwmgr = handle;
1222
1223	if (!hwmgr)
1224		return;
1225
1226	if (hwmgr->hwmgr_func->powergate_sdma == NULL) {
1227		pr_info_ratelimited("%s was not implemented.\n", __func__);
1228		return;
1229	}
1230
1231	hwmgr->hwmgr_func->powergate_sdma(hwmgr, gate);
1232}
1233
1234static int pp_set_powergating_by_smu(void *handle,
1235				uint32_t block_type,
1236				bool gate,
1237				int inst)
1238{
1239	int ret = 0;
1240
1241	switch (block_type) {
1242	case AMD_IP_BLOCK_TYPE_UVD:
1243	case AMD_IP_BLOCK_TYPE_VCN:
1244		pp_dpm_powergate_uvd(handle, gate);
1245		break;
1246	case AMD_IP_BLOCK_TYPE_VCE:
1247		pp_dpm_powergate_vce(handle, gate);
1248		break;
1249	case AMD_IP_BLOCK_TYPE_GMC:
1250		/*
1251		 * For now, this is only used on PICASSO.
1252		 * And only "gate" operation is supported.
1253		 */
1254		if (gate)
1255			pp_dpm_powergate_mmhub(handle);
1256		break;
1257	case AMD_IP_BLOCK_TYPE_GFX:
1258		ret = pp_dpm_powergate_gfx(handle, gate);
1259		break;
1260	case AMD_IP_BLOCK_TYPE_ACP:
1261		pp_dpm_powergate_acp(handle, gate);
1262		break;
1263	case AMD_IP_BLOCK_TYPE_SDMA:
1264		pp_dpm_powergate_sdma(handle, gate);
1265		break;
1266	default:
1267		break;
1268	}
1269	return ret;
1270}
1271
1272static int pp_notify_smu_enable_pwe(void *handle)
1273{
1274	struct pp_hwmgr *hwmgr = handle;
1275
1276	if (!hwmgr || !hwmgr->pm_en)
1277		return -EINVAL;
1278
1279	if (hwmgr->hwmgr_func->smus_notify_pwe == NULL) {
1280		pr_info_ratelimited("%s was not implemented.\n", __func__);
1281		return -EINVAL;
1282	}
1283
1284	hwmgr->hwmgr_func->smus_notify_pwe(hwmgr);
1285
1286	return 0;
1287}
1288
1289static int pp_enable_mgpu_fan_boost(void *handle)
1290{
1291	struct pp_hwmgr *hwmgr = handle;
1292
1293	if (!hwmgr)
1294		return -EINVAL;
1295
1296	if (!hwmgr->pm_en ||
1297	     hwmgr->hwmgr_func->enable_mgpu_fan_boost == NULL)
1298		return 0;
1299
1300	hwmgr->hwmgr_func->enable_mgpu_fan_boost(hwmgr);
1301
1302	return 0;
1303}
1304
1305static int pp_set_min_deep_sleep_dcefclk(void *handle, uint32_t clock)
1306{
1307	struct pp_hwmgr *hwmgr = handle;
1308
1309	if (!hwmgr || !hwmgr->pm_en)
1310		return -EINVAL;
1311
1312	if (hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk == NULL) {
1313		pr_debug("%s was not implemented.\n", __func__);
1314		return -EINVAL;
1315	}
1316
1317	hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock);
1318
1319	return 0;
1320}
1321
1322static int pp_set_hard_min_dcefclk_by_freq(void *handle, uint32_t clock)
1323{
1324	struct pp_hwmgr *hwmgr = handle;
1325
1326	if (!hwmgr || !hwmgr->pm_en)
1327		return -EINVAL;
1328
1329	if (hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq == NULL) {
1330		pr_debug("%s was not implemented.\n", __func__);
1331		return -EINVAL;
1332	}
1333
1334	hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock);
1335
1336	return 0;
1337}
1338
1339static int pp_set_hard_min_fclk_by_freq(void *handle, uint32_t clock)
1340{
1341	struct pp_hwmgr *hwmgr = handle;
1342
1343	if (!hwmgr || !hwmgr->pm_en)
1344		return -EINVAL;
1345
1346	if (hwmgr->hwmgr_func->set_hard_min_fclk_by_freq == NULL) {
1347		pr_debug("%s was not implemented.\n", __func__);
1348		return -EINVAL;
1349	}
1350
1351	hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock);
1352
1353	return 0;
1354}
1355
1356static int pp_set_active_display_count(void *handle, uint32_t count)
1357{
1358	struct pp_hwmgr *hwmgr = handle;
1359
1360	if (!hwmgr || !hwmgr->pm_en)
1361		return -EINVAL;
1362
1363	return phm_set_active_display_count(hwmgr, count);
1364}
1365
1366static int pp_get_asic_baco_capability(void *handle)
1367{
1368	struct pp_hwmgr *hwmgr = handle;
1369
1370	if (!hwmgr)
1371		return false;
1372
1373	if (!(hwmgr->not_vf && amdgpu_dpm) ||
1374		!hwmgr->hwmgr_func->get_bamaco_support)
1375		return false;
1376
1377	return hwmgr->hwmgr_func->get_bamaco_support(hwmgr);
1378}
1379
1380static int pp_get_asic_baco_state(void *handle, int *state)
1381{
1382	struct pp_hwmgr *hwmgr = handle;
1383
1384	if (!hwmgr)
1385		return -EINVAL;
1386
1387	if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_state)
1388		return 0;
1389
1390	hwmgr->hwmgr_func->get_asic_baco_state(hwmgr, (enum BACO_STATE *)state);
1391
1392	return 0;
1393}
1394
1395static int pp_set_asic_baco_state(void *handle, int state)
1396{
1397	struct pp_hwmgr *hwmgr = handle;
1398
1399	if (!hwmgr)
1400		return -EINVAL;
1401
1402	if (!(hwmgr->not_vf && amdgpu_dpm) ||
1403		!hwmgr->hwmgr_func->set_asic_baco_state)
1404		return 0;
1405
1406	hwmgr->hwmgr_func->set_asic_baco_state(hwmgr, (enum BACO_STATE)state);
1407
1408	return 0;
1409}
1410
1411static int pp_get_ppfeature_status(void *handle, char *buf)
1412{
1413	struct pp_hwmgr *hwmgr = handle;
1414
1415	if (!hwmgr || !hwmgr->pm_en || !buf)
1416		return -EINVAL;
1417
1418	if (hwmgr->hwmgr_func->get_ppfeature_status == NULL) {
1419		pr_info_ratelimited("%s was not implemented.\n", __func__);
1420		return -EINVAL;
1421	}
1422
1423	return hwmgr->hwmgr_func->get_ppfeature_status(hwmgr, buf);
1424}
1425
1426static int pp_set_ppfeature_status(void *handle, uint64_t ppfeature_masks)
1427{
1428	struct pp_hwmgr *hwmgr = handle;
1429
1430	if (!hwmgr || !hwmgr->pm_en)
1431		return -EINVAL;
1432
1433	if (hwmgr->hwmgr_func->set_ppfeature_status == NULL) {
1434		pr_info_ratelimited("%s was not implemented.\n", __func__);
1435		return -EINVAL;
1436	}
1437
1438	return hwmgr->hwmgr_func->set_ppfeature_status(hwmgr, ppfeature_masks);
1439}
1440
1441static int pp_asic_reset_mode_2(void *handle)
1442{
1443	struct pp_hwmgr *hwmgr = handle;
1444
1445	if (!hwmgr || !hwmgr->pm_en)
1446		return -EINVAL;
1447
1448	if (hwmgr->hwmgr_func->asic_reset == NULL) {
1449		pr_info_ratelimited("%s was not implemented.\n", __func__);
1450		return -EINVAL;
1451	}
1452
1453	return hwmgr->hwmgr_func->asic_reset(hwmgr, SMU_ASIC_RESET_MODE_2);
1454}
1455
1456static int pp_smu_i2c_bus_access(void *handle, bool acquire)
1457{
1458	struct pp_hwmgr *hwmgr = handle;
1459
1460	if (!hwmgr || !hwmgr->pm_en)
1461		return -EINVAL;
1462
1463	if (hwmgr->hwmgr_func->smu_i2c_bus_access == NULL) {
1464		pr_info_ratelimited("%s was not implemented.\n", __func__);
1465		return -EINVAL;
1466	}
1467
1468	return hwmgr->hwmgr_func->smu_i2c_bus_access(hwmgr, acquire);
1469}
1470
1471static int pp_set_df_cstate(void *handle, enum pp_df_cstate state)
1472{
1473	struct pp_hwmgr *hwmgr = handle;
1474
1475	if (!hwmgr)
1476		return -EINVAL;
1477
1478	if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_df_cstate)
1479		return 0;
1480
1481	hwmgr->hwmgr_func->set_df_cstate(hwmgr, state);
1482
1483	return 0;
1484}
1485
1486static int pp_set_xgmi_pstate(void *handle, uint32_t pstate)
1487{
1488	struct pp_hwmgr *hwmgr = handle;
1489
1490	if (!hwmgr)
1491		return -EINVAL;
1492
1493	if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_xgmi_pstate)
1494		return 0;
1495
1496	hwmgr->hwmgr_func->set_xgmi_pstate(hwmgr, pstate);
1497
1498	return 0;
1499}
1500
1501static ssize_t pp_get_gpu_metrics(void *handle, void **table)
1502{
1503	struct pp_hwmgr *hwmgr = handle;
1504
1505	if (!hwmgr)
1506		return -EINVAL;
1507
1508	if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_gpu_metrics)
1509		return -EOPNOTSUPP;
1510
1511	return hwmgr->hwmgr_func->get_gpu_metrics(hwmgr, table);
1512}
1513
1514static int pp_gfx_state_change_set(void *handle, uint32_t state)
1515{
1516	struct pp_hwmgr *hwmgr = handle;
1517
1518	if (!hwmgr || !hwmgr->pm_en)
1519		return -EINVAL;
1520
1521	if (hwmgr->hwmgr_func->gfx_state_change == NULL) {
1522		pr_info_ratelimited("%s was not implemented.\n", __func__);
1523		return -EINVAL;
1524	}
1525
1526	hwmgr->hwmgr_func->gfx_state_change(hwmgr, state);
1527	return 0;
1528}
1529
1530static int pp_get_prv_buffer_details(void *handle, void **addr, size_t *size)
1531{
1532	struct pp_hwmgr *hwmgr = handle;
1533	struct amdgpu_device *adev = hwmgr->adev;
1534	int err;
1535
1536	if (!addr || !size)
1537		return -EINVAL;
1538
1539	*addr = NULL;
1540	*size = 0;
1541	if (adev->pm.smu_prv_buffer) {
1542		err = amdgpu_bo_kmap(adev->pm.smu_prv_buffer, addr);
1543		if (err)
1544			return err;
1545		*size = adev->pm.smu_prv_buffer_size;
1546	}
1547
1548	return 0;
1549}
1550
1551static void pp_pm_compute_clocks(void *handle)
1552{
1553	struct pp_hwmgr *hwmgr = handle;
1554	struct amdgpu_device *adev = hwmgr->adev;
1555
1556	if (!adev->dc_enabled) {
1557		amdgpu_dpm_get_display_cfg(adev);
1558		pp_display_configuration_change(handle,
1559						&adev->pm.pm_display_cfg);
1560	}
1561
1562	pp_dpm_dispatch_tasks(handle,
1563			      AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
1564			      NULL);
1565}
1566
1567static const struct amd_pm_funcs pp_dpm_funcs = {
1568	.load_firmware = pp_dpm_load_fw,
1569	.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
1570	.force_performance_level = pp_dpm_force_performance_level,
1571	.get_performance_level = pp_dpm_get_performance_level,
1572	.get_current_power_state = pp_dpm_get_current_power_state,
1573	.dispatch_tasks = pp_dpm_dispatch_tasks,
1574	.set_fan_control_mode = pp_dpm_set_fan_control_mode,
1575	.get_fan_control_mode = pp_dpm_get_fan_control_mode,
1576	.set_fan_speed_pwm = pp_dpm_set_fan_speed_pwm,
1577	.get_fan_speed_pwm = pp_dpm_get_fan_speed_pwm,
1578	.get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm,
1579	.set_fan_speed_rpm = pp_dpm_set_fan_speed_rpm,
1580	.get_pp_num_states = pp_dpm_get_pp_num_states,
1581	.get_pp_table = pp_dpm_get_pp_table,
1582	.set_pp_table = pp_dpm_set_pp_table,
1583	.force_clock_level = pp_dpm_force_clock_level,
1584	.emit_clock_levels = pp_dpm_emit_clock_levels,
1585	.print_clock_levels = pp_dpm_print_clock_levels,
1586	.get_sclk_od = pp_dpm_get_sclk_od,
1587	.set_sclk_od = pp_dpm_set_sclk_od,
1588	.get_mclk_od = pp_dpm_get_mclk_od,
1589	.set_mclk_od = pp_dpm_set_mclk_od,
1590	.read_sensor = pp_dpm_read_sensor,
1591	.get_vce_clock_state = pp_dpm_get_vce_clock_state,
1592	.switch_power_profile = pp_dpm_switch_power_profile,
1593	.set_clockgating_by_smu = pp_set_clockgating_by_smu,
1594	.set_powergating_by_smu = pp_set_powergating_by_smu,
1595	.get_power_profile_mode = pp_get_power_profile_mode,
1596	.set_power_profile_mode = pp_set_power_profile_mode,
1597	.set_fine_grain_clk_vol = pp_set_fine_grain_clk_vol,
1598	.odn_edit_dpm_table = pp_odn_edit_dpm_table,
1599	.set_mp1_state = pp_dpm_set_mp1_state,
1600	.set_power_limit = pp_set_power_limit,
1601	.get_power_limit = pp_get_power_limit,
1602/* export to DC */
1603	.get_sclk = pp_dpm_get_sclk,
1604	.get_mclk = pp_dpm_get_mclk,
1605	.display_configuration_change = pp_display_configuration_change,
1606	.get_display_power_level = pp_get_display_power_level,
1607	.get_current_clocks = pp_get_current_clocks,
1608	.get_clock_by_type = pp_get_clock_by_type,
1609	.get_clock_by_type_with_latency = pp_get_clock_by_type_with_latency,
1610	.get_clock_by_type_with_voltage = pp_get_clock_by_type_with_voltage,
1611	.set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges,
1612	.display_clock_voltage_request = pp_display_clock_voltage_request,
1613	.get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks,
1614	.notify_smu_enable_pwe = pp_notify_smu_enable_pwe,
1615	.enable_mgpu_fan_boost = pp_enable_mgpu_fan_boost,
1616	.set_active_display_count = pp_set_active_display_count,
1617	.set_min_deep_sleep_dcefclk = pp_set_min_deep_sleep_dcefclk,
1618	.set_hard_min_dcefclk_by_freq = pp_set_hard_min_dcefclk_by_freq,
1619	.set_hard_min_fclk_by_freq = pp_set_hard_min_fclk_by_freq,
1620	.get_asic_baco_capability = pp_get_asic_baco_capability,
1621	.get_asic_baco_state = pp_get_asic_baco_state,
1622	.set_asic_baco_state = pp_set_asic_baco_state,
1623	.get_ppfeature_status = pp_get_ppfeature_status,
1624	.set_ppfeature_status = pp_set_ppfeature_status,
1625	.asic_reset_mode_2 = pp_asic_reset_mode_2,
1626	.smu_i2c_bus_access = pp_smu_i2c_bus_access,
1627	.set_df_cstate = pp_set_df_cstate,
1628	.set_xgmi_pstate = pp_set_xgmi_pstate,
1629	.get_gpu_metrics = pp_get_gpu_metrics,
1630	.gfx_state_change_set = pp_gfx_state_change_set,
1631	.get_smu_prv_buf_details = pp_get_prv_buffer_details,
1632	.pm_compute_clocks = pp_pm_compute_clocks,
1633};