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si_dpm.c
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linux-6.19.14/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
1/* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include <linux/module.h> 25#include <linux/pci.h> 26 27#include "amdgpu.h" 28#include "amdgpu_pm.h" 29#include "amdgpu_dpm.h" 30#include "amdgpu_atombios.h" 31#include "amdgpu_dpm_internal.h" 32#include "amd_pcie.h" 33#include "atom.h" 34#include "gfx_v6_0.h" 35#include "r600_dpm.h" 36#include "sid.h" 37#include "si_dpm.h" 38#include "../include/pptable.h" 39#include <linux/math64.h> 40#include <linux/seq_file.h> 41#include <linux/firmware.h> 42#include <legacy_dpm.h> 43 44#include "bif/bif_3_0_d.h" 45#include "bif/bif_3_0_sh_mask.h" 46 47#include "dce/dce_6_0_d.h" 48#include "dce/dce_6_0_sh_mask.h" 49 50#include "gca/gfx_6_0_d.h" 51#include "gca/gfx_6_0_sh_mask.h" 52 53#include"gmc/gmc_6_0_d.h" 54#include"gmc/gmc_6_0_sh_mask.h" 55 56#include "smu/smu_6_0_d.h" 57#include "smu/smu_6_0_sh_mask.h" 58 59#define MC_CG_ARB_FREQ_F0 0x0a 60#define MC_CG_ARB_FREQ_F1 0x0b 61#define MC_CG_ARB_FREQ_F2 0x0c 62#define MC_CG_ARB_FREQ_F3 0x0d 63 64#define SMC_RAM_END 0x20000 65 66#define SCLK_MIN_DEEPSLEEP_FREQ 1350 67 68 69/* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */ 70#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12 71#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14 72#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16 73#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18 74#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20 75#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22 76 77#define BIOS_SCRATCH_4 0x5cd 78 79MODULE_FIRMWARE("amdgpu/tahiti_smc.bin"); 80MODULE_FIRMWARE("amdgpu/pitcairn_smc.bin"); 81MODULE_FIRMWARE("amdgpu/pitcairn_k_smc.bin"); 82MODULE_FIRMWARE("amdgpu/verde_smc.bin"); 83MODULE_FIRMWARE("amdgpu/verde_k_smc.bin"); 84MODULE_FIRMWARE("amdgpu/oland_smc.bin"); 85MODULE_FIRMWARE("amdgpu/oland_k_smc.bin"); 86MODULE_FIRMWARE("amdgpu/hainan_smc.bin"); 87MODULE_FIRMWARE("amdgpu/hainan_k_smc.bin"); 88MODULE_FIRMWARE("amdgpu/banks_k_2_smc.bin"); 89 90static const struct amd_pm_funcs si_dpm_funcs; 91 92union power_info { 93 struct _ATOM_POWERPLAY_INFO info; 94 struct _ATOM_POWERPLAY_INFO_V2 info_2; 95 struct _ATOM_POWERPLAY_INFO_V3 info_3; 96 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 97 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 98 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 99 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4; 100 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5; 101}; 102 103union fan_info { 104 struct _ATOM_PPLIB_FANTABLE fan; 105 struct _ATOM_PPLIB_FANTABLE2 fan2; 106 struct _ATOM_PPLIB_FANTABLE3 fan3; 107}; 108 109union pplib_clock_info { 110 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 111 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 112 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 113 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 114 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 115}; 116 117enum si_dpm_auto_throttle_src { 118 SI_DPM_AUTO_THROTTLE_SRC_THERMAL, 119 SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL 120}; 121 122enum si_dpm_event_src { 123 SI_DPM_EVENT_SRC_ANALOG = 0, 124 SI_DPM_EVENT_SRC_EXTERNAL = 1, 125 SI_DPM_EVENT_SRC_DIGITAL = 2, 126 SI_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 127 SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 128}; 129 130static const u32 r600_utc[R600_PM_NUMBER_OF_TC] = 131{ 132 R600_UTC_DFLT_00, 133 R600_UTC_DFLT_01, 134 R600_UTC_DFLT_02, 135 R600_UTC_DFLT_03, 136 R600_UTC_DFLT_04, 137 R600_UTC_DFLT_05, 138 R600_UTC_DFLT_06, 139 R600_UTC_DFLT_07, 140 R600_UTC_DFLT_08, 141 R600_UTC_DFLT_09, 142 R600_UTC_DFLT_10, 143 R600_UTC_DFLT_11, 144 R600_UTC_DFLT_12, 145 R600_UTC_DFLT_13, 146 R600_UTC_DFLT_14, 147}; 148 149static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] = 150{ 151 R600_DTC_DFLT_00, 152 R600_DTC_DFLT_01, 153 R600_DTC_DFLT_02, 154 R600_DTC_DFLT_03, 155 R600_DTC_DFLT_04, 156 R600_DTC_DFLT_05, 157 R600_DTC_DFLT_06, 158 R600_DTC_DFLT_07, 159 R600_DTC_DFLT_08, 160 R600_DTC_DFLT_09, 161 R600_DTC_DFLT_10, 162 R600_DTC_DFLT_11, 163 R600_DTC_DFLT_12, 164 R600_DTC_DFLT_13, 165 R600_DTC_DFLT_14, 166}; 167 168static const struct si_cac_config_reg cac_weights_tahiti[] = 169{ 170 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 171 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 172 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 173 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 174 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 175 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 176 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 177 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 178 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 179 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 180 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 181 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 182 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 183 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 185 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 186 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 187 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 188 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 189 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 190 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 191 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 192 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 193 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 194 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 195 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 196 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 197 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 198 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 199 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 200 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 201 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 202 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 203 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 204 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 205 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 206 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 207 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 208 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 209 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 210 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 211 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 212 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 213 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 214 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 215 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 216 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 217 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 218 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 219 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 220 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 221 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 222 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 223 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 224 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 225 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 226 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 227 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 228 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 229 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 230 { 0xFFFFFFFF } 231}; 232 233static const struct si_cac_config_reg lcac_tahiti[] = 234{ 235 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 236 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 237 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 238 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 239 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 240 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 241 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 242 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 243 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 244 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 245 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 246 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 247 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 248 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 249 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 250 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 251 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 252 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 253 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 254 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 255 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 256 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 257 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 258 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 259 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 260 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 261 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 262 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 263 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 264 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 265 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 266 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 267 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 268 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 269 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 270 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 271 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 272 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 273 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 274 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 275 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 276 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 277 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 278 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 279 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 280 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 281 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 282 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 283 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 284 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 285 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 286 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 287 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 288 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 289 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 290 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 291 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 292 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 293 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 294 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 295 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 296 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 297 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 298 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 299 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 300 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 301 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 302 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 303 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 304 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 305 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 306 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 307 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 308 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 309 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 310 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 311 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 312 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 313 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 314 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 315 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 316 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 317 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 318 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 319 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 320 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 321 { 0xFFFFFFFF } 322 323}; 324 325static const struct si_cac_config_reg cac_override_tahiti[] = 326{ 327 { 0xFFFFFFFF } 328}; 329 330static const struct si_powertune_data powertune_data_tahiti = 331{ 332 ((1 << 16) | 27027), 333 6, 334 0, 335 4, 336 95, 337 { 338 0UL, 339 0UL, 340 4521550UL, 341 309631529UL, 342 -1270850L, 343 4513710L, 344 40 345 }, 346 595000000UL, 347 12, 348 { 349 0, 350 0, 351 0, 352 0, 353 0, 354 0, 355 0, 356 0 357 }, 358 true 359}; 360 361static const struct si_dte_data dte_data_tahiti = 362{ 363 { 1159409, 0, 0, 0, 0 }, 364 { 777, 0, 0, 0, 0 }, 365 2, 366 54000, 367 127000, 368 25, 369 2, 370 10, 371 13, 372 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 373 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 374 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 375 85, 376 false 377}; 378 379static const struct si_dte_data dte_data_tahiti_pro = 380{ 381 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 382 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 383 5, 384 45000, 385 100, 386 0xA, 387 1, 388 0, 389 0x10, 390 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 391 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 392 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 393 90, 394 true 395}; 396 397static const struct si_dte_data dte_data_new_zealand = 398{ 399 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 400 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 401 0x5, 402 0xAFC8, 403 0x69, 404 0x32, 405 1, 406 0, 407 0x10, 408 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 409 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 410 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 411 85, 412 true 413}; 414 415static const struct si_dte_data dte_data_aruba_pro = 416{ 417 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 418 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 419 5, 420 45000, 421 100, 422 0xA, 423 1, 424 0, 425 0x10, 426 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 427 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 428 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 429 90, 430 true 431}; 432 433static const struct si_dte_data dte_data_malta = 434{ 435 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 436 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 437 5, 438 45000, 439 100, 440 0xA, 441 1, 442 0, 443 0x10, 444 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 445 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 446 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 447 90, 448 true 449}; 450 451static const struct si_cac_config_reg cac_weights_pitcairn[] = 452{ 453 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 454 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 455 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 456 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 457 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 458 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 459 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 460 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 461 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 462 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 463 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 464 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 465 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 466 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 467 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 468 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 469 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 470 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 471 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 472 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 473 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 474 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 475 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 476 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 477 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 478 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 479 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 480 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 481 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 482 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 483 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 484 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 485 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 486 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 487 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 488 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 489 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 490 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 491 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 492 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 493 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 494 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 495 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 496 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 497 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 498 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 499 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 500 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 501 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 502 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 503 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 504 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 505 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 506 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 507 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 508 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 509 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 510 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 511 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 512 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 513 { 0xFFFFFFFF } 514}; 515 516static const struct si_cac_config_reg lcac_pitcairn[] = 517{ 518 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 519 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 520 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 521 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 522 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 523 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 524 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 525 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 526 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 527 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 528 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 529 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 530 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 531 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 532 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 533 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 534 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 535 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 536 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 537 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 538 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 539 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 540 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 541 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 542 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 543 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 544 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 545 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 546 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 547 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 548 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 549 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 550 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 551 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 552 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 553 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 554 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 555 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 556 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 557 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 558 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 559 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 560 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 561 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 562 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 563 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 564 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 565 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 566 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 567 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 568 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 569 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 570 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 571 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 572 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 573 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 574 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 575 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 576 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 577 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 578 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 579 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 580 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 581 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 582 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 583 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 584 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 585 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 586 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 587 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 588 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 589 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 590 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 591 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 592 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 593 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 594 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 595 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 596 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 597 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 598 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 599 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 600 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 601 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 602 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 603 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 604 { 0xFFFFFFFF } 605}; 606 607static const struct si_cac_config_reg cac_override_pitcairn[] = 608{ 609 { 0xFFFFFFFF } 610}; 611 612static const struct si_powertune_data powertune_data_pitcairn = 613{ 614 ((1 << 16) | 27027), 615 5, 616 0, 617 6, 618 100, 619 { 620 51600000UL, 621 1800000UL, 622 7194395UL, 623 309631529UL, 624 -1270850L, 625 4513710L, 626 100 627 }, 628 117830498UL, 629 12, 630 { 631 0, 632 0, 633 0, 634 0, 635 0, 636 0, 637 0, 638 0 639 }, 640 true 641}; 642 643static const struct si_dte_data dte_data_pitcairn = 644{ 645 { 0, 0, 0, 0, 0 }, 646 { 0, 0, 0, 0, 0 }, 647 0, 648 0, 649 0, 650 0, 651 0, 652 0, 653 0, 654 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 655 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 656 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 657 0, 658 false 659}; 660 661static const struct si_dte_data dte_data_curacao_xt = 662{ 663 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 664 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 665 5, 666 45000, 667 100, 668 0xA, 669 1, 670 0, 671 0x10, 672 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 673 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 674 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 675 90, 676 true 677}; 678 679static const struct si_dte_data dte_data_curacao_pro = 680{ 681 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 682 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 683 5, 684 45000, 685 100, 686 0xA, 687 1, 688 0, 689 0x10, 690 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 691 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 692 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 693 90, 694 true 695}; 696 697static const struct si_dte_data dte_data_neptune_xt = 698{ 699 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 700 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 701 5, 702 45000, 703 100, 704 0xA, 705 1, 706 0, 707 0x10, 708 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 709 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 710 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 711 90, 712 true 713}; 714 715static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 716{ 717 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 718 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 719 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 720 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 721 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 723 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 724 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 725 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 726 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 727 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 728 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 729 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 730 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 731 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 732 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 733 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 734 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 735 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 736 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 737 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 738 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 739 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 740 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 741 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 742 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 743 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 744 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 745 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 746 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 747 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 748 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 749 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 750 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 751 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 752 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 753 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 754 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 755 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 756 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 757 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 758 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 759 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 760 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 761 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 762 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 763 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 764 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 765 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 766 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 767 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 768 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 769 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 770 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 771 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 772 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 773 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 774 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 775 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 776 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 777 { 0xFFFFFFFF } 778}; 779 780static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 781{ 782 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 783 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 784 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 785 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 786 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 788 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 789 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 790 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 791 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 792 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 793 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 794 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 795 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 796 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 797 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 798 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 799 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 800 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 801 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 802 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 803 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 804 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 805 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 806 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 807 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 808 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 809 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 810 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 811 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 812 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 813 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 814 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 815 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 816 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 817 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 818 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 819 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 820 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 821 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 822 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 823 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 824 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 825 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 826 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 827 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 828 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 829 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 830 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 831 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 832 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 833 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 834 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 835 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 836 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 837 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 838 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 839 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 840 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 841 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 842 { 0xFFFFFFFF } 843}; 844 845static const struct si_cac_config_reg cac_weights_heathrow[] = 846{ 847 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 848 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 849 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 850 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 851 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 853 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 854 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 855 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 856 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 857 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 858 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 859 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 860 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 861 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 862 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 863 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 864 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 865 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 866 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 867 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 868 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 869 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 870 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 871 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 872 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 873 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 874 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 875 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 876 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 877 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 878 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 879 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 880 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 881 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 882 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 883 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 884 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 885 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 886 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 887 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 888 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 889 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 890 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 891 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 892 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 893 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 894 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 895 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 896 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 897 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 898 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 899 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 900 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 901 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 902 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 903 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 904 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 905 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 906 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 907 { 0xFFFFFFFF } 908}; 909 910static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 911{ 912 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 913 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 914 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 915 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 916 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 918 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 919 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 920 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 921 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 922 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 923 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 924 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 925 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 926 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 927 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 928 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 929 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 930 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 931 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 932 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 933 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 934 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 935 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 936 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 937 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 938 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 939 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 940 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 942 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 943 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 944 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 945 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 946 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 947 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 948 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 949 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 950 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 951 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 952 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 953 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 954 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 955 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 956 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 957 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 958 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 959 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 960 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 961 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 962 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 963 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 964 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 965 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 966 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 967 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 968 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 969 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 970 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 971 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 972 { 0xFFFFFFFF } 973}; 974 975static const struct si_cac_config_reg cac_weights_cape_verde[] = 976{ 977 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 978 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 979 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 980 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 981 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 982 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 983 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 984 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 985 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 986 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 987 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 988 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 989 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 990 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 991 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 992 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 993 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 994 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 995 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 996 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 997 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 998 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 999 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1000 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1001 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1002 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1003 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1004 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1005 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1006 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1007 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1008 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1009 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1010 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1011 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1012 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1013 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1014 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1015 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1016 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1017 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1018 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1019 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1020 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1021 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1022 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1023 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1024 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1025 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1026 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1027 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1028 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1029 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1030 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1031 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1032 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1033 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1034 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1035 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1036 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1037 { 0xFFFFFFFF } 1038}; 1039 1040static const struct si_cac_config_reg lcac_cape_verde[] = 1041{ 1042 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1043 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1044 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1045 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1046 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1047 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1048 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1049 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1050 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1051 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1052 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1053 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1054 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1055 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1056 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1057 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1058 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1059 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1060 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1061 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1062 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1063 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1064 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1065 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1066 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1067 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1068 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1069 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1070 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1071 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1072 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1073 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1074 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1075 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1076 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1077 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1078 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1079 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1080 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1081 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1082 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1083 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1084 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1085 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1086 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1087 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1088 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1089 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1090 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1091 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1092 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1093 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1094 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1095 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1096 { 0xFFFFFFFF } 1097}; 1098 1099static const struct si_cac_config_reg cac_override_cape_verde[] = 1100{ 1101 { 0xFFFFFFFF } 1102}; 1103 1104static const struct si_powertune_data powertune_data_cape_verde = 1105{ 1106 ((1 << 16) | 0x6993), 1107 5, 1108 0, 1109 7, 1110 105, 1111 { 1112 0UL, 1113 0UL, 1114 7194395UL, 1115 309631529UL, 1116 -1270850L, 1117 4513710L, 1118 100 1119 }, 1120 117830498UL, 1121 12, 1122 { 1123 0, 1124 0, 1125 0, 1126 0, 1127 0, 1128 0, 1129 0, 1130 0 1131 }, 1132 true 1133}; 1134 1135static const struct si_dte_data dte_data_cape_verde = 1136{ 1137 { 0, 0, 0, 0, 0 }, 1138 { 0, 0, 0, 0, 0 }, 1139 0, 1140 0, 1141 0, 1142 0, 1143 0, 1144 0, 1145 0, 1146 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1147 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1148 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1149 0, 1150 false 1151}; 1152 1153static const struct si_dte_data dte_data_venus_xtx = 1154{ 1155 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1156 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1157 5, 1158 55000, 1159 0x69, 1160 0xA, 1161 1, 1162 0, 1163 0x3, 1164 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1165 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1166 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1167 90, 1168 true 1169}; 1170 1171static const struct si_dte_data dte_data_venus_xt = 1172{ 1173 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1174 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1175 5, 1176 55000, 1177 0x69, 1178 0xA, 1179 1, 1180 0, 1181 0x3, 1182 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1183 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1184 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1185 90, 1186 true 1187}; 1188 1189static const struct si_dte_data dte_data_venus_pro = 1190{ 1191 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1192 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1193 5, 1194 55000, 1195 0x69, 1196 0xA, 1197 1, 1198 0, 1199 0x3, 1200 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1201 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1202 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1203 90, 1204 true 1205}; 1206 1207static const struct si_cac_config_reg cac_weights_oland[] = 1208{ 1209 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1228 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1229 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1230 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1231 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1232 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1233 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1234 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1235 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1236 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1252 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1253 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1254 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1255 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1256 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1257 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1258 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1259 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1269 { 0xFFFFFFFF } 1270}; 1271 1272static const struct si_cac_config_reg cac_weights_mars_pro[] = 1273{ 1274 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1293 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1294 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1295 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1296 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1297 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1298 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1299 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1300 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1301 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1317 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1318 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1319 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1320 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1321 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1322 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1323 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1324 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1334 { 0xFFFFFFFF } 1335}; 1336 1337static const struct si_cac_config_reg cac_weights_mars_xt[] = 1338{ 1339 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1358 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1359 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1360 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1361 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1362 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1363 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1364 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1365 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1366 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1382 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1383 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1384 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1385 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1386 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1387 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1388 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1389 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1399 { 0xFFFFFFFF } 1400}; 1401 1402static const struct si_cac_config_reg cac_weights_oland_pro[] = 1403{ 1404 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1423 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1424 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1425 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1426 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1427 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1428 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1429 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1430 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1431 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1464 { 0xFFFFFFFF } 1465}; 1466 1467static const struct si_cac_config_reg cac_weights_oland_xt[] = 1468{ 1469 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1470 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1471 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1472 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1473 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1474 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1475 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1488 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1489 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1490 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1491 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1492 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1493 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1494 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1495 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1496 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1516 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1517 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1518 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1519 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1520 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1521 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1522 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1523 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1524 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1525 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1526 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1527 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1528 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1529 { 0xFFFFFFFF } 1530}; 1531 1532static const struct si_cac_config_reg lcac_oland[] = 1533{ 1534 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1535 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1536 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1537 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1538 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1539 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1540 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1541 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1542 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1543 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1544 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1545 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1546 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1547 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1548 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1549 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1550 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1551 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1552 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1553 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1554 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1555 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1556 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1557 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1558 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1559 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1560 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1561 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1562 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1563 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1564 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1565 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1566 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1567 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1568 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1569 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1570 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1571 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1572 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1573 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1574 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1575 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1576 { 0xFFFFFFFF } 1577}; 1578 1579static const struct si_cac_config_reg lcac_mars_pro[] = 1580{ 1581 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1582 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1583 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1584 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1585 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1586 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1587 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1588 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1589 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1590 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1591 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1592 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1593 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1594 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1595 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1596 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1597 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1598 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1599 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1600 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1601 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1602 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1603 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1604 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1605 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1606 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1607 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1608 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1609 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1610 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1611 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1612 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1613 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1614 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1615 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1616 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1617 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1618 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1619 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1620 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1621 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1622 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1623 { 0xFFFFFFFF } 1624}; 1625 1626static const struct si_cac_config_reg cac_override_oland[] = 1627{ 1628 { 0xFFFFFFFF } 1629}; 1630 1631static const struct si_powertune_data powertune_data_oland = 1632{ 1633 ((1 << 16) | 0x6993), 1634 5, 1635 0, 1636 7, 1637 105, 1638 { 1639 0UL, 1640 0UL, 1641 7194395UL, 1642 309631529UL, 1643 -1270850L, 1644 4513710L, 1645 100 1646 }, 1647 117830498UL, 1648 12, 1649 { 1650 0, 1651 0, 1652 0, 1653 0, 1654 0, 1655 0, 1656 0, 1657 0 1658 }, 1659 true 1660}; 1661 1662static const struct si_powertune_data powertune_data_mars_pro = 1663{ 1664 ((1 << 16) | 0x6993), 1665 5, 1666 0, 1667 7, 1668 105, 1669 { 1670 0UL, 1671 0UL, 1672 7194395UL, 1673 309631529UL, 1674 -1270850L, 1675 4513710L, 1676 100 1677 }, 1678 117830498UL, 1679 12, 1680 { 1681 0, 1682 0, 1683 0, 1684 0, 1685 0, 1686 0, 1687 0, 1688 0 1689 }, 1690 true 1691}; 1692 1693static const struct si_dte_data dte_data_oland = 1694{ 1695 { 0, 0, 0, 0, 0 }, 1696 { 0, 0, 0, 0, 0 }, 1697 0, 1698 0, 1699 0, 1700 0, 1701 0, 1702 0, 1703 0, 1704 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1705 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1706 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1707 0, 1708 false 1709}; 1710 1711static const struct si_dte_data dte_data_mars_pro = 1712{ 1713 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1714 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1715 5, 1716 55000, 1717 105, 1718 0xA, 1719 1, 1720 0, 1721 0x10, 1722 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1723 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1724 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1725 90, 1726 true 1727}; 1728 1729static const struct si_dte_data dte_data_sun_xt = 1730{ 1731 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1732 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1733 5, 1734 55000, 1735 105, 1736 0xA, 1737 1, 1738 0, 1739 0x10, 1740 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1741 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1742 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1743 90, 1744 true 1745}; 1746 1747 1748static const struct si_cac_config_reg cac_weights_hainan[] = 1749{ 1750 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1751 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1752 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1753 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1754 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1755 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1756 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1757 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1758 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1759 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1760 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1761 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1762 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1763 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1764 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1765 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1766 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1767 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1768 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1769 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1770 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1771 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1772 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1773 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1774 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1775 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1776 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1777 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1778 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1779 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1780 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1781 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1782 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1783 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1784 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1785 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1786 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1787 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1788 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1789 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1790 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1791 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1792 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1793 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1794 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1795 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1796 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1797 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1798 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1799 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1800 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1801 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1802 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1803 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1804 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1805 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1806 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1807 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1808 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1809 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1810 { 0xFFFFFFFF } 1811}; 1812 1813static const struct si_powertune_data powertune_data_hainan = 1814{ 1815 ((1 << 16) | 0x6993), 1816 5, 1817 0, 1818 9, 1819 105, 1820 { 1821 0UL, 1822 0UL, 1823 7194395UL, 1824 309631529UL, 1825 -1270850L, 1826 4513710L, 1827 100 1828 }, 1829 117830498UL, 1830 12, 1831 { 1832 0, 1833 0, 1834 0, 1835 0, 1836 0, 1837 0, 1838 0, 1839 0 1840 }, 1841 true 1842}; 1843 1844static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev); 1845static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev); 1846static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev); 1847static struct si_ps *si_get_ps(struct amdgpu_ps *rps); 1848 1849static int si_populate_voltage_value(struct amdgpu_device *adev, 1850 const struct atom_voltage_table *table, 1851 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1852static int si_get_std_voltage_value(struct amdgpu_device *adev, 1853 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1854 u16 *std_voltage); 1855static int si_write_smc_soft_register(struct amdgpu_device *adev, 1856 u16 reg_offset, u32 value); 1857static int si_convert_power_level_to_smc(struct amdgpu_device *adev, 1858 struct rv7xx_pl *pl, 1859 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1860static int si_calculate_sclk_params(struct amdgpu_device *adev, 1861 u32 engine_clock, 1862 SISLANDS_SMC_SCLK_VALUE *sclk); 1863 1864static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev); 1865static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev); 1866static void si_dpm_set_irq_funcs(struct amdgpu_device *adev); 1867 1868static struct si_power_info *si_get_pi(struct amdgpu_device *adev) 1869{ 1870 struct si_power_info *pi = adev->pm.dpm.priv; 1871 return pi; 1872} 1873 1874static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1875 u16 v, s32 t, u32 ileakage, u32 *leakage) 1876{ 1877 s64 kt, kv, leakage_w, i_leakage, vddc; 1878 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1879 s64 tmp; 1880 1881 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1882 vddc = div64_s64(drm_int2fixp(v), 1000); 1883 temperature = div64_s64(drm_int2fixp(t), 1000); 1884 1885 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1886 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1887 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1888 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1889 t_ref = drm_int2fixp(coeff->t_ref); 1890 1891 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1892 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1893 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1894 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1895 1896 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1897 1898 *leakage = drm_fixp2int(leakage_w * 1000); 1899} 1900 1901static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev, 1902 const struct ni_leakage_coeffients *coeff, 1903 u16 v, 1904 s32 t, 1905 u32 i_leakage, 1906 u32 *leakage) 1907{ 1908 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1909} 1910 1911static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1912 const u32 fixed_kt, u16 v, 1913 u32 ileakage, u32 *leakage) 1914{ 1915 s64 kt, kv, leakage_w, i_leakage, vddc; 1916 1917 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1918 vddc = div64_s64(drm_int2fixp(v), 1000); 1919 1920 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1921 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1922 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1923 1924 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1925 1926 *leakage = drm_fixp2int(leakage_w * 1000); 1927} 1928 1929static void si_calculate_leakage_for_v(struct amdgpu_device *adev, 1930 const struct ni_leakage_coeffients *coeff, 1931 const u32 fixed_kt, 1932 u16 v, 1933 u32 i_leakage, 1934 u32 *leakage) 1935{ 1936 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1937} 1938 1939 1940static void si_update_dte_from_pl2(struct amdgpu_device *adev, 1941 struct si_dte_data *dte_data) 1942{ 1943 u32 p_limit1 = adev->pm.dpm.tdp_limit; 1944 u32 p_limit2 = adev->pm.dpm.near_tdp_limit; 1945 u32 k = dte_data->k; 1946 u32 t_max = dte_data->max_t; 1947 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1948 u32 t_0 = dte_data->t0; 1949 u32 i; 1950 1951 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1952 dte_data->tdep_count = 3; 1953 1954 for (i = 0; i < k; i++) { 1955 dte_data->r[i] = 1956 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1957 (p_limit2 * (u32)100); 1958 } 1959 1960 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1961 1962 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1963 dte_data->tdep_r[i] = dte_data->r[4]; 1964 } 1965 } else { 1966 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1967 } 1968} 1969 1970static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev) 1971{ 1972 struct rv7xx_power_info *pi = adev->pm.dpm.priv; 1973 1974 return pi; 1975} 1976 1977static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev) 1978{ 1979 struct ni_power_info *pi = adev->pm.dpm.priv; 1980 1981 return pi; 1982} 1983 1984static struct si_ps *si_get_ps(struct amdgpu_ps *aps) 1985{ 1986 struct si_ps *ps = aps->ps_priv; 1987 1988 return ps; 1989} 1990 1991static void si_initialize_powertune_defaults(struct amdgpu_device *adev) 1992{ 1993 struct ni_power_info *ni_pi = ni_get_pi(adev); 1994 struct si_power_info *si_pi = si_get_pi(adev); 1995 bool update_dte_from_pl2 = false; 1996 1997 if (adev->asic_type == CHIP_TAHITI) { 1998 si_pi->cac_weights = cac_weights_tahiti; 1999 si_pi->lcac_config = lcac_tahiti; 2000 si_pi->cac_override = cac_override_tahiti; 2001 si_pi->powertune_data = &powertune_data_tahiti; 2002 si_pi->dte_data = dte_data_tahiti; 2003 2004 switch (adev->pdev->device) { 2005 case 0x6798: 2006 si_pi->dte_data.enable_dte_by_default = true; 2007 break; 2008 case 0x6799: 2009 si_pi->dte_data = dte_data_new_zealand; 2010 break; 2011 case 0x6790: 2012 case 0x6791: 2013 case 0x6792: 2014 case 0x679E: 2015 si_pi->dte_data = dte_data_aruba_pro; 2016 update_dte_from_pl2 = true; 2017 break; 2018 case 0x679B: 2019 si_pi->dte_data = dte_data_malta; 2020 update_dte_from_pl2 = true; 2021 break; 2022 case 0x679A: 2023 si_pi->dte_data = dte_data_tahiti_pro; 2024 update_dte_from_pl2 = true; 2025 break; 2026 default: 2027 if (si_pi->dte_data.enable_dte_by_default == true) 2028 DRM_ERROR("DTE is not enabled!\n"); 2029 break; 2030 } 2031 } else if (adev->asic_type == CHIP_PITCAIRN) { 2032 si_pi->cac_weights = cac_weights_pitcairn; 2033 si_pi->lcac_config = lcac_pitcairn; 2034 si_pi->cac_override = cac_override_pitcairn; 2035 si_pi->powertune_data = &powertune_data_pitcairn; 2036 2037 switch (adev->pdev->device) { 2038 case 0x6810: 2039 case 0x6818: 2040 si_pi->dte_data = dte_data_curacao_xt; 2041 update_dte_from_pl2 = true; 2042 break; 2043 case 0x6819: 2044 case 0x6811: 2045 si_pi->dte_data = dte_data_curacao_pro; 2046 update_dte_from_pl2 = true; 2047 break; 2048 case 0x6800: 2049 case 0x6806: 2050 si_pi->dte_data = dte_data_neptune_xt; 2051 update_dte_from_pl2 = true; 2052 break; 2053 default: 2054 si_pi->dte_data = dte_data_pitcairn; 2055 break; 2056 } 2057 } else if (adev->asic_type == CHIP_VERDE) { 2058 si_pi->lcac_config = lcac_cape_verde; 2059 si_pi->cac_override = cac_override_cape_verde; 2060 si_pi->powertune_data = &powertune_data_cape_verde; 2061 2062 switch (adev->pdev->device) { 2063 case 0x683B: 2064 case 0x683F: 2065 case 0x6829: 2066 case 0x6835: 2067 si_pi->cac_weights = cac_weights_cape_verde_pro; 2068 si_pi->dte_data = dte_data_cape_verde; 2069 break; 2070 case 0x682C: 2071 si_pi->cac_weights = cac_weights_cape_verde_pro; 2072 si_pi->dte_data = dte_data_sun_xt; 2073 update_dte_from_pl2 = true; 2074 break; 2075 case 0x6825: 2076 case 0x6827: 2077 si_pi->cac_weights = cac_weights_heathrow; 2078 si_pi->dte_data = dte_data_cape_verde; 2079 break; 2080 case 0x6824: 2081 case 0x682D: 2082 si_pi->cac_weights = cac_weights_chelsea_xt; 2083 si_pi->dte_data = dte_data_cape_verde; 2084 break; 2085 case 0x682F: 2086 si_pi->cac_weights = cac_weights_chelsea_pro; 2087 si_pi->dte_data = dte_data_cape_verde; 2088 break; 2089 case 0x6820: 2090 si_pi->cac_weights = cac_weights_heathrow; 2091 si_pi->dte_data = dte_data_venus_xtx; 2092 break; 2093 case 0x6821: 2094 si_pi->cac_weights = cac_weights_heathrow; 2095 si_pi->dte_data = dte_data_venus_xt; 2096 break; 2097 case 0x6823: 2098 case 0x682B: 2099 case 0x6822: 2100 case 0x682A: 2101 si_pi->cac_weights = cac_weights_chelsea_pro; 2102 si_pi->dte_data = dte_data_venus_pro; 2103 break; 2104 default: 2105 si_pi->cac_weights = cac_weights_cape_verde; 2106 si_pi->dte_data = dte_data_cape_verde; 2107 break; 2108 } 2109 } else if (adev->asic_type == CHIP_OLAND) { 2110 si_pi->lcac_config = lcac_mars_pro; 2111 si_pi->cac_override = cac_override_oland; 2112 si_pi->powertune_data = &powertune_data_mars_pro; 2113 si_pi->dte_data = dte_data_mars_pro; 2114 2115 switch (adev->pdev->device) { 2116 case 0x6601: 2117 case 0x6621: 2118 case 0x6603: 2119 case 0x6605: 2120 si_pi->cac_weights = cac_weights_mars_pro; 2121 update_dte_from_pl2 = true; 2122 break; 2123 case 0x6600: 2124 case 0x6606: 2125 case 0x6620: 2126 case 0x6604: 2127 si_pi->cac_weights = cac_weights_mars_xt; 2128 update_dte_from_pl2 = true; 2129 break; 2130 case 0x6611: 2131 case 0x6613: 2132 case 0x6608: 2133 si_pi->cac_weights = cac_weights_oland_pro; 2134 update_dte_from_pl2 = true; 2135 break; 2136 case 0x6610: 2137 si_pi->cac_weights = cac_weights_oland_xt; 2138 update_dte_from_pl2 = true; 2139 break; 2140 default: 2141 si_pi->cac_weights = cac_weights_oland; 2142 si_pi->lcac_config = lcac_oland; 2143 si_pi->cac_override = cac_override_oland; 2144 si_pi->powertune_data = &powertune_data_oland; 2145 si_pi->dte_data = dte_data_oland; 2146 break; 2147 } 2148 } else if (adev->asic_type == CHIP_HAINAN) { 2149 si_pi->cac_weights = cac_weights_hainan; 2150 si_pi->lcac_config = lcac_oland; 2151 si_pi->cac_override = cac_override_oland; 2152 si_pi->powertune_data = &powertune_data_hainan; 2153 si_pi->dte_data = dte_data_sun_xt; 2154 update_dte_from_pl2 = true; 2155 } else { 2156 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2157 return; 2158 } 2159 2160 ni_pi->enable_power_containment = false; 2161 ni_pi->enable_cac = false; 2162 ni_pi->enable_sq_ramping = false; 2163 si_pi->enable_dte = false; 2164 2165 if (si_pi->powertune_data->enable_powertune_by_default) { 2166 ni_pi->enable_power_containment = true; 2167 ni_pi->enable_cac = true; 2168 if (si_pi->dte_data.enable_dte_by_default) { 2169 si_pi->enable_dte = true; 2170 if (update_dte_from_pl2) 2171 si_update_dte_from_pl2(adev, &si_pi->dte_data); 2172 2173 } 2174 ni_pi->enable_sq_ramping = true; 2175 } 2176 2177 ni_pi->driver_calculate_cac_leakage = true; 2178 ni_pi->cac_configuration_required = true; 2179 2180 if (ni_pi->cac_configuration_required) { 2181 ni_pi->support_cac_long_term_average = true; 2182 si_pi->dyn_powertune_data.l2_lta_window_size = 2183 si_pi->powertune_data->l2_lta_window_size_default; 2184 si_pi->dyn_powertune_data.lts_truncate = 2185 si_pi->powertune_data->lts_truncate_default; 2186 } else { 2187 ni_pi->support_cac_long_term_average = false; 2188 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2189 si_pi->dyn_powertune_data.lts_truncate = 0; 2190 } 2191 2192 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2193} 2194 2195static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev) 2196{ 2197 return 1; 2198} 2199 2200static u32 si_calculate_cac_wintime(struct amdgpu_device *adev) 2201{ 2202 u32 xclk; 2203 u32 wintime; 2204 u32 cac_window; 2205 u32 cac_window_size; 2206 2207 xclk = amdgpu_asic_get_xclk(adev); 2208 2209 if (xclk == 0) 2210 return 0; 2211 2212 cac_window = RREG32(mmCG_CAC_CTRL) & CG_CAC_CTRL__CAC_WINDOW_MASK; 2213 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2214 2215 wintime = (cac_window_size * 100) / xclk; 2216 2217 return wintime; 2218} 2219 2220static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2221{ 2222 return power_in_watts; 2223} 2224 2225static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev, 2226 bool adjust_polarity, 2227 u32 tdp_adjustment, 2228 u32 *tdp_limit, 2229 u32 *near_tdp_limit) 2230{ 2231 u32 adjustment_delta, max_tdp_limit; 2232 2233 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit) 2234 return -EINVAL; 2235 2236 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100; 2237 2238 if (adjust_polarity) { 2239 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; 2240 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit); 2241 } else { 2242 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; 2243 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit; 2244 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted) 2245 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2246 else 2247 *near_tdp_limit = 0; 2248 } 2249 2250 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2251 return -EINVAL; 2252 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2253 return -EINVAL; 2254 2255 return 0; 2256} 2257 2258static int si_populate_smc_tdp_limits(struct amdgpu_device *adev, 2259 struct amdgpu_ps *amdgpu_state) 2260{ 2261 struct ni_power_info *ni_pi = ni_get_pi(adev); 2262 struct si_power_info *si_pi = si_get_pi(adev); 2263 2264 if (ni_pi->enable_power_containment) { 2265 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2266 PP_SIslands_PAPMParameters *papm_parm; 2267 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table; 2268 u32 scaling_factor = si_get_smc_power_scaling_factor(adev); 2269 u32 tdp_limit; 2270 u32 near_tdp_limit; 2271 int ret; 2272 2273 if (scaling_factor == 0) 2274 return -EINVAL; 2275 2276 ret = si_calculate_adjusted_tdp_limits(adev, 2277 false, /* ??? */ 2278 adev->pm.dpm.tdp_adjustment, 2279 &tdp_limit, 2280 &near_tdp_limit); 2281 if (ret) 2282 return ret; 2283 2284 if (adev->pdev->device == 0x6611 && adev->pdev->revision == 0x87) { 2285 /* Workaround buggy powertune on Radeon 430 and 520. */ 2286 tdp_limit = 32; 2287 near_tdp_limit = 28; 2288 } 2289 2290 smc_table->dpm2Params.TDPLimit = 2291 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2292 smc_table->dpm2Params.NearTDPLimit = 2293 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2294 smc_table->dpm2Params.SafePowerLimit = 2295 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2296 2297 ret = amdgpu_si_copy_bytes_to_smc(adev, 2298 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2299 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2300 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2301 sizeof(u32) * 3, 2302 si_pi->sram_end); 2303 if (ret) 2304 return ret; 2305 2306 if (si_pi->enable_ppm) { 2307 papm_parm = &si_pi->papm_parm; 2308 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2309 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2310 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2311 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2312 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2313 papm_parm->PlatformPowerLimit = 0xffffffff; 2314 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2315 2316 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start, 2317 (u8 *)papm_parm, 2318 sizeof(PP_SIslands_PAPMParameters), 2319 si_pi->sram_end); 2320 if (ret) 2321 return ret; 2322 } 2323 } 2324 return 0; 2325} 2326 2327static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev, 2328 struct amdgpu_ps *amdgpu_state) 2329{ 2330 struct ni_power_info *ni_pi = ni_get_pi(adev); 2331 struct si_power_info *si_pi = si_get_pi(adev); 2332 2333 if (ni_pi->enable_power_containment) { 2334 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2335 int ret; 2336 2337 ret = amdgpu_si_copy_bytes_to_smc(adev, 2338 (si_pi->state_table_start + 2339 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2340 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2341 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2342 sizeof(u32) * 2, 2343 si_pi->sram_end); 2344 if (ret) 2345 return ret; 2346 } 2347 2348 return 0; 2349} 2350 2351static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev, 2352 const u16 prev_std_vddc, 2353 const u16 curr_std_vddc) 2354{ 2355 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2356 u64 prev_vddc = (u64)prev_std_vddc; 2357 u64 curr_vddc = (u64)curr_std_vddc; 2358 u64 pwr_efficiency_ratio, n, d; 2359 2360 if ((prev_vddc == 0) || (curr_vddc == 0)) 2361 return 0; 2362 2363 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2364 d = prev_vddc * prev_vddc; 2365 pwr_efficiency_ratio = div64_u64(n, d); 2366 2367 if (pwr_efficiency_ratio > (u64)0xFFFF) 2368 return 0; 2369 2370 return (u16)pwr_efficiency_ratio; 2371} 2372 2373static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev, 2374 struct amdgpu_ps *amdgpu_state) 2375{ 2376 struct si_power_info *si_pi = si_get_pi(adev); 2377 2378 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2379 amdgpu_state->vclk && amdgpu_state->dclk) 2380 return true; 2381 2382 return false; 2383} 2384 2385struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev) 2386{ 2387 struct evergreen_power_info *pi = adev->pm.dpm.priv; 2388 2389 return pi; 2390} 2391 2392static int si_populate_power_containment_values(struct amdgpu_device *adev, 2393 struct amdgpu_ps *amdgpu_state, 2394 SISLANDS_SMC_SWSTATE *smc_state) 2395{ 2396 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 2397 struct ni_power_info *ni_pi = ni_get_pi(adev); 2398 struct si_ps *state = si_get_ps(amdgpu_state); 2399 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2400 u32 prev_sclk; 2401 u32 max_sclk; 2402 u32 min_sclk; 2403 u16 prev_std_vddc; 2404 u16 curr_std_vddc; 2405 int i; 2406 u16 pwr_efficiency_ratio; 2407 u8 max_ps_percent; 2408 bool disable_uvd_power_tune; 2409 int ret; 2410 2411 if (ni_pi->enable_power_containment == false) 2412 return 0; 2413 2414 if (state->performance_level_count == 0) 2415 return -EINVAL; 2416 2417 if (smc_state->levelCount != state->performance_level_count) 2418 return -EINVAL; 2419 2420 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state); 2421 2422 smc_state->levels[0].dpm2.MaxPS = 0; 2423 smc_state->levels[0].dpm2.NearTDPDec = 0; 2424 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2425 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2426 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2427 2428 for (i = 1; i < state->performance_level_count; i++) { 2429 prev_sclk = state->performance_levels[i-1].sclk; 2430 max_sclk = state->performance_levels[i].sclk; 2431 if (i == 1) 2432 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2433 else 2434 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2435 2436 if (prev_sclk > max_sclk) 2437 return -EINVAL; 2438 2439 if ((max_ps_percent == 0) || 2440 (prev_sclk == max_sclk) || 2441 disable_uvd_power_tune) 2442 min_sclk = max_sclk; 2443 else if (i == 1) 2444 min_sclk = prev_sclk; 2445 else 2446 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2447 2448 if (min_sclk < state->performance_levels[0].sclk) 2449 min_sclk = state->performance_levels[0].sclk; 2450 2451 if (min_sclk == 0) 2452 return -EINVAL; 2453 2454 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 2455 state->performance_levels[i-1].vddc, &vddc); 2456 if (ret) 2457 return ret; 2458 2459 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc); 2460 if (ret) 2461 return ret; 2462 2463 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 2464 state->performance_levels[i].vddc, &vddc); 2465 if (ret) 2466 return ret; 2467 2468 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc); 2469 if (ret) 2470 return ret; 2471 2472 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev, 2473 prev_std_vddc, curr_std_vddc); 2474 2475 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2476 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2477 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2478 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2479 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2480 } 2481 2482 return 0; 2483} 2484 2485static int si_populate_sq_ramping_values(struct amdgpu_device *adev, 2486 struct amdgpu_ps *amdgpu_state, 2487 SISLANDS_SMC_SWSTATE *smc_state) 2488{ 2489 struct ni_power_info *ni_pi = ni_get_pi(adev); 2490 struct si_ps *state = si_get_ps(amdgpu_state); 2491 u32 sq_power_throttle, sq_power_throttle2; 2492 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2493 int i; 2494 2495 if (state->performance_level_count == 0) 2496 return -EINVAL; 2497 2498 if (smc_state->levelCount != state->performance_level_count) 2499 return -EINVAL; 2500 2501 if (adev->pm.dpm.sq_ramping_threshold == 0) 2502 return -EINVAL; 2503 2504 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (SQ_POWER_THROTTLE__MAX_POWER_MASK >> SQ_POWER_THROTTLE__MAX_POWER__SHIFT)) 2505 enable_sq_ramping = false; 2506 2507 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (SQ_POWER_THROTTLE__MIN_POWER_MASK >> SQ_POWER_THROTTLE__MIN_POWER__SHIFT)) 2508 enable_sq_ramping = false; 2509 2510 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK >> SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT)) 2511 enable_sq_ramping = false; 2512 2513 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK >> SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT)) 2514 enable_sq_ramping = false; 2515 2516 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK >> SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT)) 2517 enable_sq_ramping = false; 2518 2519 for (i = 0; i < state->performance_level_count; i++) { 2520 sq_power_throttle = 0; 2521 sq_power_throttle2 = 0; 2522 2523 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && 2524 enable_sq_ramping) { 2525 sq_power_throttle |= SISLANDS_DPM2_SQ_RAMP_MAX_POWER << SQ_POWER_THROTTLE__MAX_POWER__SHIFT; 2526 sq_power_throttle |= SISLANDS_DPM2_SQ_RAMP_MIN_POWER << SQ_POWER_THROTTLE__MIN_POWER__SHIFT; 2527 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA << SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT; 2528 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_STI_SIZE << SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT; 2529 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_LTI_RATIO << SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT; 2530 } else { 2531 sq_power_throttle |= SQ_POWER_THROTTLE__MAX_POWER_MASK | 2532 SQ_POWER_THROTTLE__MIN_POWER_MASK; 2533 sq_power_throttle2 |= SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK | 2534 SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK | 2535 SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK; 2536 } 2537 2538 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2539 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2540 } 2541 2542 return 0; 2543} 2544 2545static int si_enable_power_containment(struct amdgpu_device *adev, 2546 struct amdgpu_ps *amdgpu_new_state, 2547 bool enable) 2548{ 2549 struct ni_power_info *ni_pi = ni_get_pi(adev); 2550 PPSMC_Result smc_result; 2551 int ret = 0; 2552 2553 if (ni_pi->enable_power_containment) { 2554 if (enable) { 2555 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { 2556 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive); 2557 if (smc_result != PPSMC_Result_OK) 2558 ret = -EINVAL; 2559 } 2560 } else { 2561 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive); 2562 if (smc_result != PPSMC_Result_OK) 2563 ret = -EINVAL; 2564 } 2565 } 2566 2567 return ret; 2568} 2569 2570static int si_initialize_smc_dte_tables(struct amdgpu_device *adev) 2571{ 2572 struct si_power_info *si_pi = si_get_pi(adev); 2573 int ret = 0; 2574 struct si_dte_data *dte_data = &si_pi->dte_data; 2575 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2576 u32 table_size; 2577 u8 tdep_count; 2578 u32 i; 2579 2580 if (dte_data == NULL) 2581 si_pi->enable_dte = false; 2582 2583 if (si_pi->enable_dte == false) 2584 return 0; 2585 2586 if (dte_data->k <= 0) 2587 return -EINVAL; 2588 2589 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2590 if (dte_tables == NULL) { 2591 si_pi->enable_dte = false; 2592 return -ENOMEM; 2593 } 2594 2595 table_size = dte_data->k; 2596 2597 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2598 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2599 2600 tdep_count = dte_data->tdep_count; 2601 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2602 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2603 2604 dte_tables->K = cpu_to_be32(table_size); 2605 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2606 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2607 dte_tables->WindowSize = dte_data->window_size; 2608 dte_tables->temp_select = dte_data->temp_select; 2609 dte_tables->DTE_mode = dte_data->dte_mode; 2610 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2611 2612 if (tdep_count > 0) 2613 table_size--; 2614 2615 for (i = 0; i < table_size; i++) { 2616 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2617 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2618 } 2619 2620 dte_tables->Tdep_count = tdep_count; 2621 2622 for (i = 0; i < (u32)tdep_count; i++) { 2623 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2624 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2625 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2626 } 2627 2628 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start, 2629 (u8 *)dte_tables, 2630 sizeof(Smc_SIslands_DTE_Configuration), 2631 si_pi->sram_end); 2632 kfree(dte_tables); 2633 2634 return ret; 2635} 2636 2637static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev, 2638 u16 *max, u16 *min) 2639{ 2640 struct si_power_info *si_pi = si_get_pi(adev); 2641 struct amdgpu_cac_leakage_table *table = 2642 &adev->pm.dpm.dyn_state.cac_leakage_table; 2643 u32 i; 2644 u32 v0_loadline; 2645 2646 if (table == NULL) 2647 return -EINVAL; 2648 2649 *max = 0; 2650 *min = 0xFFFF; 2651 2652 for (i = 0; i < table->count; i++) { 2653 if (table->entries[i].vddc > *max) 2654 *max = table->entries[i].vddc; 2655 if (table->entries[i].vddc < *min) 2656 *min = table->entries[i].vddc; 2657 } 2658 2659 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2660 return -EINVAL; 2661 2662 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2663 2664 if (v0_loadline > 0xFFFFUL) 2665 return -EINVAL; 2666 2667 *min = (u16)v0_loadline; 2668 2669 if ((*min > *max) || (*max == 0) || (*min == 0)) 2670 return -EINVAL; 2671 2672 return 0; 2673} 2674 2675static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2676{ 2677 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2678 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2679} 2680 2681static int si_init_dte_leakage_table(struct amdgpu_device *adev, 2682 PP_SIslands_CacConfig *cac_tables, 2683 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2684 u16 t0, u16 t_step) 2685{ 2686 struct si_power_info *si_pi = si_get_pi(adev); 2687 u32 leakage; 2688 unsigned int i, j; 2689 s32 t; 2690 u32 smc_leakage; 2691 u32 scaling_factor; 2692 u16 voltage; 2693 2694 scaling_factor = si_get_smc_power_scaling_factor(adev); 2695 2696 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2697 t = (1000 * (i * t_step + t0)); 2698 2699 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2700 voltage = vddc_max - (vddc_step * j); 2701 2702 si_calculate_leakage_for_v_and_t(adev, 2703 &si_pi->powertune_data->leakage_coefficients, 2704 voltage, 2705 t, 2706 si_pi->dyn_powertune_data.cac_leakage, 2707 &leakage); 2708 2709 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2710 2711 if (smc_leakage > 0xFFFF) 2712 smc_leakage = 0xFFFF; 2713 2714 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2715 cpu_to_be16((u16)smc_leakage); 2716 } 2717 } 2718 return 0; 2719} 2720 2721static int si_init_simplified_leakage_table(struct amdgpu_device *adev, 2722 PP_SIslands_CacConfig *cac_tables, 2723 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2724{ 2725 struct si_power_info *si_pi = si_get_pi(adev); 2726 u32 leakage; 2727 unsigned int i, j; 2728 u32 smc_leakage; 2729 u32 scaling_factor; 2730 u16 voltage; 2731 2732 scaling_factor = si_get_smc_power_scaling_factor(adev); 2733 2734 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2735 voltage = vddc_max - (vddc_step * j); 2736 2737 si_calculate_leakage_for_v(adev, 2738 &si_pi->powertune_data->leakage_coefficients, 2739 si_pi->powertune_data->fixed_kt, 2740 voltage, 2741 si_pi->dyn_powertune_data.cac_leakage, 2742 &leakage); 2743 2744 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2745 2746 if (smc_leakage > 0xFFFF) 2747 smc_leakage = 0xFFFF; 2748 2749 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2750 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2751 cpu_to_be16((u16)smc_leakage); 2752 } 2753 return 0; 2754} 2755 2756static int si_initialize_smc_cac_tables(struct amdgpu_device *adev) 2757{ 2758 struct ni_power_info *ni_pi = ni_get_pi(adev); 2759 struct si_power_info *si_pi = si_get_pi(adev); 2760 PP_SIslands_CacConfig *cac_tables = NULL; 2761 u16 vddc_max, vddc_min, vddc_step; 2762 u16 t0, t_step; 2763 u32 load_line_slope, reg; 2764 int ret = 0; 2765 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100; 2766 2767 if (ni_pi->enable_cac == false) 2768 return 0; 2769 2770 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2771 if (!cac_tables) 2772 return -ENOMEM; 2773 2774 reg = RREG32(mmCG_CAC_CTRL) & ~CG_CAC_CTRL__CAC_WINDOW_MASK; 2775 reg |= (si_pi->powertune_data->cac_window << CG_CAC_CTRL__CAC_WINDOW__SHIFT); 2776 WREG32(mmCG_CAC_CTRL, reg); 2777 2778 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage; 2779 si_pi->dyn_powertune_data.dc_pwr_value = 2780 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2781 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev); 2782 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2783 2784 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2785 2786 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min); 2787 if (ret) 2788 goto done_free; 2789 2790 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2791 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2792 t_step = 4; 2793 t0 = 60; 2794 2795 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2796 ret = si_init_dte_leakage_table(adev, cac_tables, 2797 vddc_max, vddc_min, vddc_step, 2798 t0, t_step); 2799 else 2800 ret = si_init_simplified_leakage_table(adev, cac_tables, 2801 vddc_max, vddc_min, vddc_step); 2802 if (ret) 2803 goto done_free; 2804 2805 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2806 2807 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2808 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2809 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2810 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2811 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2812 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2813 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2814 cac_tables->calculation_repeats = cpu_to_be32(2); 2815 cac_tables->dc_cac = cpu_to_be32(0); 2816 cac_tables->log2_PG_LKG_SCALE = 12; 2817 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2818 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2819 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2820 2821 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start, 2822 (u8 *)cac_tables, 2823 sizeof(PP_SIslands_CacConfig), 2824 si_pi->sram_end); 2825 2826 if (ret) 2827 goto done_free; 2828 2829 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2830 2831done_free: 2832 if (ret) { 2833 ni_pi->enable_cac = false; 2834 ni_pi->enable_power_containment = false; 2835 } 2836 2837 kfree(cac_tables); 2838 2839 return ret; 2840} 2841 2842static int si_program_cac_config_registers(struct amdgpu_device *adev, 2843 const struct si_cac_config_reg *cac_config_regs) 2844{ 2845 const struct si_cac_config_reg *config_regs = cac_config_regs; 2846 u32 data = 0, offset; 2847 2848 if (!config_regs) 2849 return -EINVAL; 2850 2851 while (config_regs->offset != 0xFFFFFFFF) { 2852 switch (config_regs->type) { 2853 case SISLANDS_CACCONFIG_CGIND: 2854 offset = SMC_CG_IND_START + config_regs->offset; 2855 if (offset < SMC_CG_IND_END) 2856 data = RREG32_SMC(offset); 2857 break; 2858 default: 2859 data = RREG32(config_regs->offset); 2860 break; 2861 } 2862 2863 data &= ~config_regs->mask; 2864 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2865 2866 switch (config_regs->type) { 2867 case SISLANDS_CACCONFIG_CGIND: 2868 offset = SMC_CG_IND_START + config_regs->offset; 2869 if (offset < SMC_CG_IND_END) 2870 WREG32_SMC(offset, data); 2871 break; 2872 default: 2873 WREG32(config_regs->offset, data); 2874 break; 2875 } 2876 config_regs++; 2877 } 2878 return 0; 2879} 2880 2881static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev) 2882{ 2883 struct ni_power_info *ni_pi = ni_get_pi(adev); 2884 struct si_power_info *si_pi = si_get_pi(adev); 2885 int ret; 2886 2887 if ((ni_pi->enable_cac == false) || 2888 (ni_pi->cac_configuration_required == false)) 2889 return 0; 2890 2891 ret = si_program_cac_config_registers(adev, si_pi->lcac_config); 2892 if (ret) 2893 return ret; 2894 ret = si_program_cac_config_registers(adev, si_pi->cac_override); 2895 if (ret) 2896 return ret; 2897 ret = si_program_cac_config_registers(adev, si_pi->cac_weights); 2898 if (ret) 2899 return ret; 2900 2901 return 0; 2902} 2903 2904static int si_enable_smc_cac(struct amdgpu_device *adev, 2905 struct amdgpu_ps *amdgpu_new_state, 2906 bool enable) 2907{ 2908 struct ni_power_info *ni_pi = ni_get_pi(adev); 2909 struct si_power_info *si_pi = si_get_pi(adev); 2910 PPSMC_Result smc_result; 2911 int ret = 0; 2912 2913 if (ni_pi->enable_cac) { 2914 if (enable) { 2915 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { 2916 if (ni_pi->support_cac_long_term_average) { 2917 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable); 2918 if (smc_result != PPSMC_Result_OK) 2919 ni_pi->support_cac_long_term_average = false; 2920 } 2921 2922 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac); 2923 if (smc_result != PPSMC_Result_OK) { 2924 ret = -EINVAL; 2925 ni_pi->cac_enabled = false; 2926 } else { 2927 ni_pi->cac_enabled = true; 2928 } 2929 2930 if (si_pi->enable_dte) { 2931 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE); 2932 if (smc_result != PPSMC_Result_OK) 2933 ret = -EINVAL; 2934 } 2935 } 2936 } else if (ni_pi->cac_enabled) { 2937 if (si_pi->enable_dte) 2938 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE); 2939 2940 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac); 2941 2942 ni_pi->cac_enabled = false; 2943 2944 if (ni_pi->support_cac_long_term_average) 2945 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable); 2946 } 2947 } 2948 return ret; 2949} 2950 2951static int si_init_smc_spll_table(struct amdgpu_device *adev) 2952{ 2953 struct ni_power_info *ni_pi = ni_get_pi(adev); 2954 struct si_power_info *si_pi = si_get_pi(adev); 2955 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2956 SISLANDS_SMC_SCLK_VALUE sclk_params; 2957 u32 fb_div, p_div; 2958 u32 clk_s, clk_v; 2959 u32 sclk = 0; 2960 int ret = 0; 2961 u32 tmp; 2962 int i; 2963 2964 if (si_pi->spll_table_start == 0) 2965 return -EINVAL; 2966 2967 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2968 if (spll_table == NULL) 2969 return -ENOMEM; 2970 2971 for (i = 0; i < 256; i++) { 2972 ret = si_calculate_sclk_params(adev, sclk, &sclk_params); 2973 if (ret) 2974 break; 2975 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK) >> CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT; 2976 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK) >> CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT; 2977 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CG_SPLL_SPREAD_SPECTRUM__CLK_S_MASK) >> CG_SPLL_SPREAD_SPECTRUM__CLK_S__SHIFT; 2978 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CG_SPLL_SPREAD_SPECTRUM_2__CLK_V_MASK) >> CG_SPLL_SPREAD_SPECTRUM_2__CLK_V__SHIFT; 2979 2980 fb_div &= ~0x00001FFF; 2981 fb_div >>= 1; 2982 clk_v >>= 6; 2983 2984 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2985 ret = -EINVAL; 2986 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2987 ret = -EINVAL; 2988 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2989 ret = -EINVAL; 2990 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2991 ret = -EINVAL; 2992 2993 if (ret) 2994 break; 2995 2996 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2997 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2998 spll_table->freq[i] = cpu_to_be32(tmp); 2999 3000 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 3001 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 3002 spll_table->ss[i] = cpu_to_be32(tmp); 3003 3004 sclk += 512; 3005 } 3006 3007 3008 if (!ret) 3009 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start, 3010 (u8 *)spll_table, 3011 sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 3012 si_pi->sram_end); 3013 3014 if (ret) 3015 ni_pi->enable_power_containment = false; 3016 3017 kfree(spll_table); 3018 3019 return ret; 3020} 3021 3022static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev, 3023 u16 vce_voltage) 3024{ 3025 u16 highest_leakage = 0; 3026 struct si_power_info *si_pi = si_get_pi(adev); 3027 int i; 3028 3029 for (i = 0; i < si_pi->leakage_voltage.count; i++){ 3030 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) 3031 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; 3032 } 3033 3034 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) 3035 return highest_leakage; 3036 3037 return vce_voltage; 3038} 3039 3040static int si_get_vce_clock_voltage(struct amdgpu_device *adev, 3041 u32 evclk, u32 ecclk, u16 *voltage) 3042{ 3043 u32 i; 3044 int ret = -EINVAL; 3045 struct amdgpu_vce_clock_voltage_dependency_table *table = 3046 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 3047 3048 if (((evclk == 0) && (ecclk == 0)) || 3049 (table && (table->count == 0))) { 3050 *voltage = 0; 3051 return 0; 3052 } 3053 3054 for (i = 0; i < table->count; i++) { 3055 if ((evclk <= table->entries[i].evclk) && 3056 (ecclk <= table->entries[i].ecclk)) { 3057 *voltage = table->entries[i].v; 3058 ret = 0; 3059 break; 3060 } 3061 } 3062 3063 /* if no match return the highest voltage */ 3064 if (ret) 3065 *voltage = table->entries[table->count - 1].v; 3066 3067 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage); 3068 3069 return ret; 3070} 3071 3072static bool si_dpm_vblank_too_short(void *handle) 3073{ 3074 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3075 u32 vblank_time = adev->pm.pm_display_cfg.min_vblank_time; 3076 /* we never hit the non-gddr5 limit so disable it */ 3077 u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0; 3078 3079 /* Consider zero vblank time too short and disable MCLK switching. 3080 * Note that the vblank time is set to maximum when no displays are attached, 3081 * so we'll still enable MCLK switching in that case. 3082 */ 3083 if (vblank_time == 0) 3084 return true; 3085 else if (vblank_time < switch_limit) 3086 return true; 3087 else 3088 return false; 3089 3090} 3091 3092static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev, 3093 u32 arb_freq_src, u32 arb_freq_dest) 3094{ 3095 u32 mc_arb_dram_timing; 3096 u32 mc_arb_dram_timing2; 3097 u32 burst_time; 3098 u32 mc_cg_config; 3099 3100 switch (arb_freq_src) { 3101 case MC_CG_ARB_FREQ_F0: 3102 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING); 3103 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 3104 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT; 3105 break; 3106 case MC_CG_ARB_FREQ_F1: 3107 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1); 3108 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1); 3109 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT; 3110 break; 3111 case MC_CG_ARB_FREQ_F2: 3112 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2); 3113 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2); 3114 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT; 3115 break; 3116 case MC_CG_ARB_FREQ_F3: 3117 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3); 3118 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3); 3119 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT; 3120 break; 3121 default: 3122 return -EINVAL; 3123 } 3124 3125 switch (arb_freq_dest) { 3126 case MC_CG_ARB_FREQ_F0: 3127 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing); 3128 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); 3129 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK); 3130 break; 3131 case MC_CG_ARB_FREQ_F1: 3132 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); 3133 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); 3134 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK); 3135 break; 3136 case MC_CG_ARB_FREQ_F2: 3137 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing); 3138 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2); 3139 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK); 3140 break; 3141 case MC_CG_ARB_FREQ_F3: 3142 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing); 3143 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2); 3144 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK); 3145 break; 3146 default: 3147 return -EINVAL; 3148 } 3149 3150 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F; 3151 WREG32(MC_CG_CONFIG, mc_cg_config); 3152 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK); 3153 3154 return 0; 3155} 3156 3157static void ni_update_current_ps(struct amdgpu_device *adev, 3158 struct amdgpu_ps *rps) 3159{ 3160 struct si_ps *new_ps = si_get_ps(rps); 3161 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 3162 struct ni_power_info *ni_pi = ni_get_pi(adev); 3163 3164 eg_pi->current_rps = *rps; 3165 ni_pi->current_ps = *new_ps; 3166 eg_pi->current_rps.ps_priv = &ni_pi->current_ps; 3167 adev->pm.dpm.current_ps = &eg_pi->current_rps; 3168} 3169 3170static void ni_update_requested_ps(struct amdgpu_device *adev, 3171 struct amdgpu_ps *rps) 3172{ 3173 struct si_ps *new_ps = si_get_ps(rps); 3174 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 3175 struct ni_power_info *ni_pi = ni_get_pi(adev); 3176 3177 eg_pi->requested_rps = *rps; 3178 ni_pi->requested_ps = *new_ps; 3179 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps; 3180 adev->pm.dpm.requested_ps = &eg_pi->requested_rps; 3181} 3182 3183static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev, 3184 struct amdgpu_ps *new_ps, 3185 struct amdgpu_ps *old_ps) 3186{ 3187 struct si_ps *new_state = si_get_ps(new_ps); 3188 struct si_ps *current_state = si_get_ps(old_ps); 3189 3190 if ((new_ps->vclk == old_ps->vclk) && 3191 (new_ps->dclk == old_ps->dclk)) 3192 return; 3193 3194 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= 3195 current_state->performance_levels[current_state->performance_level_count - 1].sclk) 3196 return; 3197 3198 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); 3199} 3200 3201static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev, 3202 struct amdgpu_ps *new_ps, 3203 struct amdgpu_ps *old_ps) 3204{ 3205 struct si_ps *new_state = si_get_ps(new_ps); 3206 struct si_ps *current_state = si_get_ps(old_ps); 3207 3208 if ((new_ps->vclk == old_ps->vclk) && 3209 (new_ps->dclk == old_ps->dclk)) 3210 return; 3211 3212 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < 3213 current_state->performance_levels[current_state->performance_level_count - 1].sclk) 3214 return; 3215 3216 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); 3217} 3218 3219static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage) 3220{ 3221 unsigned int i; 3222 3223 for (i = 0; i < table->count; i++) 3224 if (voltage <= table->entries[i].value) 3225 return table->entries[i].value; 3226 3227 return table->entries[table->count - 1].value; 3228} 3229 3230static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks, 3231 u32 max_clock, u32 requested_clock) 3232{ 3233 unsigned int i; 3234 3235 if ((clocks == NULL) || (clocks->count == 0)) 3236 return (requested_clock < max_clock) ? requested_clock : max_clock; 3237 3238 for (i = 0; i < clocks->count; i++) { 3239 if (clocks->values[i] >= requested_clock) 3240 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock; 3241 } 3242 3243 return (clocks->values[clocks->count - 1] < max_clock) ? 3244 clocks->values[clocks->count - 1] : max_clock; 3245} 3246 3247static u32 btc_get_valid_mclk(struct amdgpu_device *adev, 3248 u32 max_mclk, u32 requested_mclk) 3249{ 3250 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values, 3251 max_mclk, requested_mclk); 3252} 3253 3254static u32 btc_get_valid_sclk(struct amdgpu_device *adev, 3255 u32 max_sclk, u32 requested_sclk) 3256{ 3257 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values, 3258 max_sclk, requested_sclk); 3259} 3260 3261static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table, 3262 u32 *max_clock) 3263{ 3264 u32 i, clock = 0; 3265 3266 if ((table == NULL) || (table->count == 0)) { 3267 *max_clock = clock; 3268 return; 3269 } 3270 3271 for (i = 0; i < table->count; i++) { 3272 if (clock < table->entries[i].clk) 3273 clock = table->entries[i].clk; 3274 } 3275 *max_clock = clock; 3276} 3277 3278static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table, 3279 u32 clock, u16 max_voltage, u16 *voltage) 3280{ 3281 u32 i; 3282 3283 if ((table == NULL) || (table->count == 0)) 3284 return; 3285 3286 for (i= 0; i < table->count; i++) { 3287 if (clock <= table->entries[i].clk) { 3288 if (*voltage < table->entries[i].v) 3289 *voltage = (u16)((table->entries[i].v < max_voltage) ? 3290 table->entries[i].v : max_voltage); 3291 return; 3292 } 3293 } 3294 3295 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage; 3296} 3297 3298static void btc_adjust_clock_combinations(struct amdgpu_device *adev, 3299 const struct amdgpu_clock_and_voltage_limits *max_limits, 3300 struct rv7xx_pl *pl) 3301{ 3302 3303 if ((pl->mclk == 0) || (pl->sclk == 0)) 3304 return; 3305 3306 if (pl->mclk == pl->sclk) 3307 return; 3308 3309 if (pl->mclk > pl->sclk) { 3310 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio) 3311 pl->sclk = btc_get_valid_sclk(adev, 3312 max_limits->sclk, 3313 (pl->mclk + 3314 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / 3315 adev->pm.dpm.dyn_state.mclk_sclk_ratio); 3316 } else { 3317 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta) 3318 pl->mclk = btc_get_valid_mclk(adev, 3319 max_limits->mclk, 3320 pl->sclk - 3321 adev->pm.dpm.dyn_state.sclk_mclk_delta); 3322 } 3323} 3324 3325static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev, 3326 u16 max_vddc, u16 max_vddci, 3327 u16 *vddc, u16 *vddci) 3328{ 3329 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 3330 u16 new_voltage; 3331 3332 if ((0 == *vddc) || (0 == *vddci)) 3333 return; 3334 3335 if (*vddc > *vddci) { 3336 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { 3337 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table, 3338 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta)); 3339 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci; 3340 } 3341 } else { 3342 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { 3343 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table, 3344 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta)); 3345 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc; 3346 } 3347 } 3348} 3349 3350static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, 3351 u32 *p, u32 *u) 3352{ 3353 u32 b_c = 0; 3354 u32 i_c; 3355 u32 tmp; 3356 3357 i_c = (i * r_c) / 100; 3358 tmp = i_c >> p_b; 3359 3360 while (tmp) { 3361 b_c++; 3362 tmp >>= 1; 3363 } 3364 3365 *u = (b_c + 1) / 2; 3366 *p = i_c / (1 << (2 * (*u))); 3367} 3368 3369static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th) 3370{ 3371 u32 k, a, ah, al; 3372 u32 t1; 3373 3374 if ((fl == 0) || (fh == 0) || (fl > fh)) 3375 return -EINVAL; 3376 3377 k = (100 * fh) / fl; 3378 t1 = (t * (k - 100)); 3379 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100)); 3380 a = (a + 5) / 10; 3381 ah = ((a * t) + 5000) / 10000; 3382 al = a - ah; 3383 3384 *th = t - ah; 3385 *tl = t + al; 3386 3387 return 0; 3388} 3389 3390static bool r600_is_uvd_state(u32 class, u32 class2) 3391{ 3392 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 3393 return true; 3394 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) 3395 return true; 3396 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) 3397 return true; 3398 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) 3399 return true; 3400 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) 3401 return true; 3402 return false; 3403} 3404 3405static u8 rv770_get_memory_module_index(struct amdgpu_device *adev) 3406{ 3407 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff); 3408} 3409 3410static void rv770_get_max_vddc(struct amdgpu_device *adev) 3411{ 3412 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3413 u16 vddc; 3414 3415 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc)) 3416 pi->max_vddc = 0; 3417 else 3418 pi->max_vddc = vddc; 3419} 3420 3421static void rv770_get_engine_memory_ss(struct amdgpu_device *adev) 3422{ 3423 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3424 struct amdgpu_atom_ss ss; 3425 3426 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss, 3427 ASIC_INTERNAL_ENGINE_SS, 0); 3428 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss, 3429 ASIC_INTERNAL_MEMORY_SS, 0); 3430 3431 if (pi->sclk_ss || pi->mclk_ss) 3432 pi->dynamic_ss = true; 3433 else 3434 pi->dynamic_ss = false; 3435} 3436 3437 3438static void si_apply_state_adjust_rules(struct amdgpu_device *adev, 3439 struct amdgpu_ps *rps) 3440{ 3441 const struct amd_pp_display_configuration *display_cfg = 3442 &adev->pm.pm_display_cfg; 3443 struct si_ps *ps = si_get_ps(rps); 3444 struct amdgpu_clock_and_voltage_limits *max_limits; 3445 bool disable_mclk_switching = false; 3446 bool disable_sclk_switching = false; 3447 u32 mclk, sclk; 3448 u16 vddc, vddci, min_vce_voltage = 0; 3449 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 3450 u32 max_sclk = 0, max_mclk = 0; 3451 u32 high_pixelclock_count = 0; 3452 int i; 3453 3454 if (adev->asic_type == CHIP_HAINAN) { 3455 if ((adev->pdev->revision == 0x81) || 3456 (adev->pdev->revision == 0xC3) || 3457 (adev->pdev->device == 0x6660) || 3458 (adev->pdev->device == 0x6664) || 3459 (adev->pdev->device == 0x6665) || 3460 (adev->pdev->device == 0x6667) || 3461 (adev->pdev->device == 0x666F)) { 3462 max_sclk = 75000; 3463 } 3464 if ((adev->pdev->revision == 0xC3) || 3465 (adev->pdev->device == 0x6665)) { 3466 max_sclk = 60000; 3467 max_mclk = 80000; 3468 } 3469 if ((adev->pdev->device == 0x666f) && 3470 (adev->pdev->revision == 0x00)) { 3471 max_sclk = 80000; 3472 max_mclk = 95000; 3473 } 3474 } else if (adev->asic_type == CHIP_OLAND) { 3475 if ((adev->pdev->revision == 0xC7) || 3476 (adev->pdev->revision == 0x80) || 3477 (adev->pdev->revision == 0x81) || 3478 (adev->pdev->revision == 0x83) || 3479 (adev->pdev->revision == 0x87 && 3480 adev->pdev->device != 0x6611) || 3481 (adev->pdev->device == 0x6604) || 3482 (adev->pdev->device == 0x6605)) { 3483 max_sclk = 75000; 3484 } else if (adev->pdev->revision == 0x87 && 3485 adev->pdev->device == 0x6611) { 3486 /* Radeon 430 and 520 */ 3487 max_sclk = 78000; 3488 } 3489 } 3490 3491 /* We define "high pixelclock" for SI as higher than necessary for 4K 30Hz. 3492 * For example, 4K 60Hz and 1080p 144Hz fall into this category. 3493 * Find number of such displays connected. 3494 */ 3495 for (i = 0; i < display_cfg->num_display; i++) { 3496 /* The array only contains active displays. */ 3497 if (display_cfg->displays[i].pixel_clock > 297000) 3498 high_pixelclock_count++; 3499 } 3500 3501 /* These are some ad-hoc fixes to some issues observed with SI GPUs. 3502 * They are necessary because we don't have something like dce_calcs 3503 * for these GPUs to calculate bandwidth requirements. 3504 */ 3505 if (high_pixelclock_count) { 3506 /* Work around flickering lines at the bottom edge 3507 * of the screen when using a single 4K 60Hz monitor. 3508 */ 3509 disable_mclk_switching = true; 3510 3511 /* On Oland, we observe some flickering when two 4K 60Hz 3512 * displays are connected, possibly because voltage is too low. 3513 * Raise the voltage by requiring a higher SCLK. 3514 * (Voltage cannot be adjusted independently without also SCLK.) 3515 */ 3516 if (high_pixelclock_count > 1 && adev->asic_type == CHIP_OLAND) 3517 disable_sclk_switching = true; 3518 } 3519 3520 if (rps->vce_active) { 3521 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; 3522 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; 3523 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk, 3524 &min_vce_voltage); 3525 } else { 3526 rps->evclk = 0; 3527 rps->ecclk = 0; 3528 } 3529 3530 if ((adev->pm.pm_display_cfg.num_display > 1) || 3531 si_dpm_vblank_too_short(adev)) 3532 disable_mclk_switching = true; 3533 3534 if (rps->vclk || rps->dclk) { 3535 disable_mclk_switching = true; 3536 disable_sclk_switching = true; 3537 } 3538 3539 if (adev->pm.ac_power) 3540 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3541 else 3542 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3543 3544 for (i = ps->performance_level_count - 2; i >= 0; i--) { 3545 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 3546 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 3547 } 3548 if (adev->pm.ac_power == false) { 3549 for (i = 0; i < ps->performance_level_count; i++) { 3550 if (ps->performance_levels[i].mclk > max_limits->mclk) 3551 ps->performance_levels[i].mclk = max_limits->mclk; 3552 if (ps->performance_levels[i].sclk > max_limits->sclk) 3553 ps->performance_levels[i].sclk = max_limits->sclk; 3554 if (ps->performance_levels[i].vddc > max_limits->vddc) 3555 ps->performance_levels[i].vddc = max_limits->vddc; 3556 if (ps->performance_levels[i].vddci > max_limits->vddci) 3557 ps->performance_levels[i].vddci = max_limits->vddci; 3558 } 3559 } 3560 3561 /* limit clocks to max supported clocks based on voltage dependency tables */ 3562 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3563 &max_sclk_vddc); 3564 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3565 &max_mclk_vddci); 3566 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3567 &max_mclk_vddc); 3568 3569 for (i = 0; i < ps->performance_level_count; i++) { 3570 if (max_sclk_vddc) { 3571 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3572 ps->performance_levels[i].sclk = max_sclk_vddc; 3573 } 3574 if (max_mclk_vddci) { 3575 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3576 ps->performance_levels[i].mclk = max_mclk_vddci; 3577 } 3578 if (max_mclk_vddc) { 3579 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3580 ps->performance_levels[i].mclk = max_mclk_vddc; 3581 } 3582 if (max_mclk) { 3583 if (ps->performance_levels[i].mclk > max_mclk) 3584 ps->performance_levels[i].mclk = max_mclk; 3585 } 3586 if (max_sclk) { 3587 if (ps->performance_levels[i].sclk > max_sclk) 3588 ps->performance_levels[i].sclk = max_sclk; 3589 } 3590 } 3591 3592 /* XXX validate the min clocks required for display */ 3593 3594 if (disable_mclk_switching) { 3595 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3596 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3597 } else { 3598 mclk = ps->performance_levels[0].mclk; 3599 vddci = ps->performance_levels[0].vddci; 3600 } 3601 3602 if (disable_sclk_switching) { 3603 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3604 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3605 } else { 3606 sclk = ps->performance_levels[0].sclk; 3607 vddc = ps->performance_levels[0].vddc; 3608 } 3609 3610 if (rps->vce_active) { 3611 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) 3612 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; 3613 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk) 3614 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk; 3615 } 3616 3617 /* adjusted low state */ 3618 ps->performance_levels[0].sclk = sclk; 3619 ps->performance_levels[0].mclk = mclk; 3620 ps->performance_levels[0].vddc = vddc; 3621 ps->performance_levels[0].vddci = vddci; 3622 3623 if (disable_sclk_switching) { 3624 sclk = ps->performance_levels[0].sclk; 3625 for (i = 1; i < ps->performance_level_count; i++) { 3626 if (sclk < ps->performance_levels[i].sclk) 3627 sclk = ps->performance_levels[i].sclk; 3628 } 3629 for (i = 0; i < ps->performance_level_count; i++) { 3630 ps->performance_levels[i].sclk = sclk; 3631 ps->performance_levels[i].vddc = vddc; 3632 } 3633 } else { 3634 for (i = 1; i < ps->performance_level_count; i++) { 3635 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3636 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3637 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3638 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3639 } 3640 } 3641 3642 if (disable_mclk_switching) { 3643 mclk = ps->performance_levels[0].mclk; 3644 for (i = 1; i < ps->performance_level_count; i++) { 3645 if (mclk < ps->performance_levels[i].mclk) 3646 mclk = ps->performance_levels[i].mclk; 3647 } 3648 for (i = 0; i < ps->performance_level_count; i++) { 3649 ps->performance_levels[i].mclk = mclk; 3650 ps->performance_levels[i].vddci = vddci; 3651 } 3652 } else { 3653 for (i = 1; i < ps->performance_level_count; i++) { 3654 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3655 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3656 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3657 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3658 } 3659 } 3660 3661 for (i = 0; i < ps->performance_level_count; i++) 3662 btc_adjust_clock_combinations(adev, max_limits, 3663 &ps->performance_levels[i]); 3664 3665 for (i = 0; i < ps->performance_level_count; i++) { 3666 if (ps->performance_levels[i].vddc < min_vce_voltage) 3667 ps->performance_levels[i].vddc = min_vce_voltage; 3668 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3669 ps->performance_levels[i].sclk, 3670 max_limits->vddc, &ps->performance_levels[i].vddc); 3671 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3672 ps->performance_levels[i].mclk, 3673 max_limits->vddci, &ps->performance_levels[i].vddci); 3674 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3675 ps->performance_levels[i].mclk, 3676 max_limits->vddc, &ps->performance_levels[i].vddc); 3677 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3678 display_cfg->display_clk, 3679 max_limits->vddc, &ps->performance_levels[i].vddc); 3680 } 3681 3682 for (i = 0; i < ps->performance_level_count; i++) { 3683 btc_apply_voltage_delta_rules(adev, 3684 max_limits->vddc, max_limits->vddci, 3685 &ps->performance_levels[i].vddc, 3686 &ps->performance_levels[i].vddci); 3687 } 3688 3689 ps->dc_compatible = true; 3690 for (i = 0; i < ps->performance_level_count; i++) { 3691 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3692 ps->dc_compatible = false; 3693 } 3694} 3695 3696#if 0 3697static int si_read_smc_soft_register(struct amdgpu_device *adev, 3698 u16 reg_offset, u32 *value) 3699{ 3700 struct si_power_info *si_pi = si_get_pi(adev); 3701 3702 return amdgpu_si_read_smc_sram_dword(adev, 3703 si_pi->soft_regs_start + reg_offset, value, 3704 si_pi->sram_end); 3705} 3706#endif 3707 3708static int si_write_smc_soft_register(struct amdgpu_device *adev, 3709 u16 reg_offset, u32 value) 3710{ 3711 struct si_power_info *si_pi = si_get_pi(adev); 3712 3713 return amdgpu_si_write_smc_sram_dword(adev, 3714 si_pi->soft_regs_start + reg_offset, 3715 value, si_pi->sram_end); 3716} 3717 3718static bool si_is_special_1gb_platform(struct amdgpu_device *adev) 3719{ 3720 bool ret = false; 3721 u32 tmp, width, row, column, bank, density; 3722 bool is_memory_gddr5, is_special; 3723 3724 tmp = RREG32(MC_SEQ_MISC0); 3725 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3726 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3727 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3728 3729 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3730 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3731 3732 tmp = RREG32(mmMC_ARB_RAMCFG); 3733 row = ((tmp & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT) + 10; 3734 column = ((tmp & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT) + 8; 3735 bank = ((tmp & MC_ARB_RAMCFG__NOOFBANK_MASK) >> MC_ARB_RAMCFG__NOOFBANK__SHIFT) + 2; 3736 3737 density = (1 << (row + column - 20 + bank)) * width; 3738 3739 if ((adev->pdev->device == 0x6819) && 3740 is_memory_gddr5 && is_special && (density == 0x400)) 3741 ret = true; 3742 3743 return ret; 3744} 3745 3746static void si_get_leakage_vddc(struct amdgpu_device *adev) 3747{ 3748 struct si_power_info *si_pi = si_get_pi(adev); 3749 u16 vddc, count = 0; 3750 int i, ret; 3751 3752 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3753 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3754 3755 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3756 si_pi->leakage_voltage.entries[count].voltage = vddc; 3757 si_pi->leakage_voltage.entries[count].leakage_index = 3758 SISLANDS_LEAKAGE_INDEX0 + i; 3759 count++; 3760 } 3761 } 3762 si_pi->leakage_voltage.count = count; 3763} 3764 3765static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev, 3766 u32 index, u16 *leakage_voltage) 3767{ 3768 struct si_power_info *si_pi = si_get_pi(adev); 3769 int i; 3770 3771 if (leakage_voltage == NULL) 3772 return -EINVAL; 3773 3774 if ((index & 0xff00) != 0xff00) 3775 return -EINVAL; 3776 3777 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3778 return -EINVAL; 3779 3780 if (index < SISLANDS_LEAKAGE_INDEX0) 3781 return -EINVAL; 3782 3783 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3784 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3785 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3786 return 0; 3787 } 3788 } 3789 return -EAGAIN; 3790} 3791 3792static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources) 3793{ 3794 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3795 bool want_thermal_protection; 3796 enum si_dpm_event_src dpm_event_src; 3797 3798 switch (sources) { 3799 case 0: 3800 default: 3801 want_thermal_protection = false; 3802 break; 3803 case (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL): 3804 want_thermal_protection = true; 3805 dpm_event_src = SI_DPM_EVENT_SRC_DIGITAL; 3806 break; 3807 case (1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3808 want_thermal_protection = true; 3809 dpm_event_src = SI_DPM_EVENT_SRC_EXTERNAL; 3810 break; 3811 case ((1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3812 (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3813 want_thermal_protection = true; 3814 dpm_event_src = SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3815 break; 3816 } 3817 3818 if (want_thermal_protection) { 3819 WREG32_P(mmCG_THERMAL_CTRL, dpm_event_src << CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT, ~CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK); 3820 if (pi->thermal_protection) 3821 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK); 3822 } else { 3823 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK); 3824 } 3825} 3826 3827static void si_enable_auto_throttle_source(struct amdgpu_device *adev, 3828 enum si_dpm_auto_throttle_src source, 3829 bool enable) 3830{ 3831 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3832 3833 if (enable) { 3834 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3835 pi->active_auto_throttle_sources |= 1 << source; 3836 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); 3837 } 3838 } else { 3839 if (pi->active_auto_throttle_sources & (1 << source)) { 3840 pi->active_auto_throttle_sources &= ~(1 << source); 3841 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); 3842 } 3843 } 3844} 3845 3846static void si_start_dpm(struct amdgpu_device *adev) 3847{ 3848 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK, ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK); 3849} 3850 3851static void si_stop_dpm(struct amdgpu_device *adev) 3852{ 3853 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK); 3854} 3855 3856static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable) 3857{ 3858 if (enable) 3859 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK); 3860 else 3861 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK, ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK); 3862 3863} 3864 3865#if 0 3866static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev, 3867 u32 thermal_level) 3868{ 3869 PPSMC_Result ret; 3870 3871 if (thermal_level == 0) { 3872 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); 3873 if (ret == PPSMC_Result_OK) 3874 return 0; 3875 else 3876 return -EINVAL; 3877 } 3878 return 0; 3879} 3880 3881static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev) 3882{ 3883 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3884} 3885#endif 3886 3887#if 0 3888static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power) 3889{ 3890 if (ac_power) 3891 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3892 0 : -EINVAL; 3893 3894 return 0; 3895} 3896#endif 3897 3898static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, 3899 PPSMC_Msg msg, u32 parameter) 3900{ 3901 WREG32(mmSMC_SCRATCH0, parameter); 3902 return amdgpu_si_send_msg_to_smc(adev, msg); 3903} 3904 3905static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev) 3906{ 3907 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3908 return -EINVAL; 3909 3910 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3911 0 : -EINVAL; 3912} 3913 3914static int si_dpm_force_performance_level(void *handle, 3915 enum amd_dpm_forced_level level) 3916{ 3917 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3918 struct amdgpu_ps *rps = adev->pm.dpm.current_ps; 3919 struct si_ps *ps = si_get_ps(rps); 3920 u32 levels = ps->performance_level_count; 3921 3922 if (level == AMD_DPM_FORCED_LEVEL_HIGH) { 3923 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3924 return -EINVAL; 3925 3926 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3927 return -EINVAL; 3928 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) { 3929 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3930 return -EINVAL; 3931 3932 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3933 return -EINVAL; 3934 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) { 3935 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3936 return -EINVAL; 3937 3938 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3939 return -EINVAL; 3940 } 3941 3942 adev->pm.dpm.forced_level = level; 3943 3944 return 0; 3945} 3946 3947#if 0 3948static int si_set_boot_state(struct amdgpu_device *adev) 3949{ 3950 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3951 0 : -EINVAL; 3952} 3953#endif 3954 3955static int si_set_sw_state(struct amdgpu_device *adev) 3956{ 3957 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3958 0 : -EINVAL; 3959} 3960 3961static int si_halt_smc(struct amdgpu_device *adev) 3962{ 3963 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3964 return -EINVAL; 3965 3966 return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ? 3967 0 : -EINVAL; 3968} 3969 3970static int si_resume_smc(struct amdgpu_device *adev) 3971{ 3972 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3973 return -EINVAL; 3974 3975 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3976 0 : -EINVAL; 3977} 3978 3979static void si_dpm_start_smc(struct amdgpu_device *adev) 3980{ 3981 amdgpu_si_program_jump_on_start(adev); 3982 amdgpu_si_start_smc(adev); 3983 amdgpu_si_smc_clock(adev, true); 3984} 3985 3986static void si_dpm_stop_smc(struct amdgpu_device *adev) 3987{ 3988 amdgpu_si_reset_smc(adev); 3989 amdgpu_si_smc_clock(adev, false); 3990} 3991 3992static int si_process_firmware_header(struct amdgpu_device *adev) 3993{ 3994 struct si_power_info *si_pi = si_get_pi(adev); 3995 u32 tmp; 3996 int ret; 3997 3998 ret = amdgpu_si_read_smc_sram_dword(adev, 3999 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4000 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 4001 &tmp, si_pi->sram_end); 4002 if (ret) 4003 return ret; 4004 4005 si_pi->state_table_start = tmp; 4006 4007 ret = amdgpu_si_read_smc_sram_dword(adev, 4008 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4009 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 4010 &tmp, si_pi->sram_end); 4011 if (ret) 4012 return ret; 4013 4014 si_pi->soft_regs_start = tmp; 4015 4016 ret = amdgpu_si_read_smc_sram_dword(adev, 4017 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4018 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 4019 &tmp, si_pi->sram_end); 4020 if (ret) 4021 return ret; 4022 4023 si_pi->mc_reg_table_start = tmp; 4024 4025 ret = amdgpu_si_read_smc_sram_dword(adev, 4026 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4027 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 4028 &tmp, si_pi->sram_end); 4029 if (ret) 4030 return ret; 4031 4032 si_pi->fan_table_start = tmp; 4033 4034 ret = amdgpu_si_read_smc_sram_dword(adev, 4035 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4036 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 4037 &tmp, si_pi->sram_end); 4038 if (ret) 4039 return ret; 4040 4041 si_pi->arb_table_start = tmp; 4042 4043 ret = amdgpu_si_read_smc_sram_dword(adev, 4044 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4045 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 4046 &tmp, si_pi->sram_end); 4047 if (ret) 4048 return ret; 4049 4050 si_pi->cac_table_start = tmp; 4051 4052 ret = amdgpu_si_read_smc_sram_dword(adev, 4053 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4054 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 4055 &tmp, si_pi->sram_end); 4056 if (ret) 4057 return ret; 4058 4059 si_pi->dte_table_start = tmp; 4060 4061 ret = amdgpu_si_read_smc_sram_dword(adev, 4062 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4063 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 4064 &tmp, si_pi->sram_end); 4065 if (ret) 4066 return ret; 4067 4068 si_pi->spll_table_start = tmp; 4069 4070 ret = amdgpu_si_read_smc_sram_dword(adev, 4071 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4072 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 4073 &tmp, si_pi->sram_end); 4074 if (ret) 4075 return ret; 4076 4077 si_pi->papm_cfg_table_start = tmp; 4078 4079 return ret; 4080} 4081 4082static void si_read_clock_registers(struct amdgpu_device *adev) 4083{ 4084 struct si_power_info *si_pi = si_get_pi(adev); 4085 4086 si_pi->clock_registers.cg_spll_func_cntl = RREG32(mmCG_SPLL_FUNC_CNTL); 4087 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(mmCG_SPLL_FUNC_CNTL_2); 4088 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(mmCG_SPLL_FUNC_CNTL_3); 4089 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(mmCG_SPLL_FUNC_CNTL_4); 4090 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(mmCG_SPLL_SPREAD_SPECTRUM); 4091 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(mmCG_SPLL_SPREAD_SPECTRUM_2); 4092 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 4093 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 4094 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 4095 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 4096 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 4097 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 4098 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 4099 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 4100 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 4101} 4102 4103static void si_enable_thermal_protection(struct amdgpu_device *adev, 4104 bool enable) 4105{ 4106 if (enable) 4107 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK); 4108 else 4109 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK); 4110} 4111 4112static void si_enable_acpi_power_management(struct amdgpu_device *adev) 4113{ 4114 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__STATIC_PM_EN_MASK, ~GENERAL_PWRMGT__STATIC_PM_EN_MASK); 4115} 4116 4117#if 0 4118static int si_enter_ulp_state(struct amdgpu_device *adev) 4119{ 4120 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 4121 4122 udelay(25000); 4123 4124 return 0; 4125} 4126 4127static int si_exit_ulp_state(struct amdgpu_device *adev) 4128{ 4129 int i; 4130 4131 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 4132 4133 udelay(7000); 4134 4135 for (i = 0; i < adev->usec_timeout; i++) { 4136 if (RREG32(SMC_RESP_0) == 1) 4137 break; 4138 udelay(1000); 4139 } 4140 4141 return 0; 4142} 4143#endif 4144 4145static int si_notify_smc_display_change(struct amdgpu_device *adev, 4146 bool has_display) 4147{ 4148 PPSMC_Msg msg = has_display ? 4149 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 4150 4151 return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ? 4152 0 : -EINVAL; 4153} 4154 4155static void si_program_response_times(struct amdgpu_device *adev) 4156{ 4157 u32 voltage_response_time, acpi_delay_time, vbi_time_out; 4158 u32 vddc_dly, acpi_dly, vbi_dly; 4159 u32 reference_clock; 4160 4161 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 4162 4163 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time; 4164 4165 if (voltage_response_time == 0) 4166 voltage_response_time = 1000; 4167 4168 acpi_delay_time = 15000; 4169 vbi_time_out = 100000; 4170 4171 reference_clock = amdgpu_asic_get_xclk(adev); 4172 4173 vddc_dly = (voltage_response_time * reference_clock) / 100; 4174 acpi_dly = (acpi_delay_time * reference_clock) / 100; 4175 vbi_dly = (vbi_time_out * reference_clock) / 100; 4176 4177 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 4178 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 4179 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 4180 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 4181} 4182 4183static void si_program_ds_registers(struct amdgpu_device *adev) 4184{ 4185 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4186 u32 tmp; 4187 4188 /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */ 4189 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0) 4190 tmp = 0x10; 4191 else 4192 tmp = 0x1; 4193 4194 if (eg_pi->sclk_deep_sleep) { 4195 WREG32_P(mmMISC_CLK_CNTL, (tmp << MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL__SHIFT), ~MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL_MASK); 4196 WREG32_P(mmCG_SPLL_AUTOSCALE_CNTL, CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK, 4197 ~CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK); 4198 } 4199} 4200 4201static void si_program_display_gap(struct amdgpu_device *adev) 4202{ 4203 const struct amd_pp_display_configuration *cfg = &adev->pm.pm_display_cfg; 4204 u32 tmp, pipe; 4205 4206 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL) & ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK); 4207 if (cfg->num_display > 0) 4208 tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT; 4209 else 4210 tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT; 4211 4212 if (cfg->num_display > 1) 4213 tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT; 4214 else 4215 tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT; 4216 4217 WREG32(mmCG_DISPLAY_GAP_CNTL, tmp); 4218 4219 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 4220 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 4221 4222 if (cfg->num_display > 0 && pipe != cfg->crtc_index) { 4223 pipe = cfg->crtc_index; 4224 4225 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 4226 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 4227 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 4228 } 4229 4230 /* Setting this to false forces the performance state to low if the crtcs are disabled. 4231 * This can be a problem on PowerXpress systems or if you want to use the card 4232 * for offscreen rendering or compute if there are no crtcs enabled. 4233 */ 4234 si_notify_smc_display_change(adev, cfg->num_display > 0); 4235} 4236 4237static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable) 4238{ 4239 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4240 4241 if (enable) { 4242 if (pi->sclk_ss) 4243 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK, ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK); 4244 } else { 4245 WREG32_P(mmCG_SPLL_SPREAD_SPECTRUM, 0, ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK); 4246 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK); 4247 } 4248} 4249 4250static void si_setup_bsp(struct amdgpu_device *adev) 4251{ 4252 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4253 u32 xclk = amdgpu_asic_get_xclk(adev); 4254 4255 r600_calculate_u_and_p(pi->asi, 4256 xclk, 4257 16, 4258 &pi->bsp, 4259 &pi->bsu); 4260 4261 r600_calculate_u_and_p(pi->pasi, 4262 xclk, 4263 16, 4264 &pi->pbsp, 4265 &pi->pbsu); 4266 4267 4268 pi->dsp = (pi->bsp << CG_BSP__BSP__SHIFT) | (pi->bsu << CG_BSP__BSU__SHIFT); 4269 pi->psp = (pi->pbsp << CG_BSP__BSP__SHIFT) | (pi->pbsu << CG_BSP__BSU__SHIFT); 4270 4271 WREG32(mmCG_BSP, pi->dsp); 4272} 4273 4274static void si_program_git(struct amdgpu_device *adev) 4275{ 4276 WREG32_P(mmCG_GIT, R600_GICST_DFLT << CG_GIT__CG_GICST__SHIFT, ~CG_GIT__CG_GICST_MASK); 4277} 4278 4279static void si_program_tp(struct amdgpu_device *adev) 4280{ 4281 int i; 4282 enum r600_td td = R600_TD_DFLT; 4283 4284 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 4285 WREG32(mmCG_FFCT_0 + i, (r600_utc[i] << CG_FFCT_0__UTC_0__SHIFT | r600_dtc[i] << CG_FFCT_0__DTC_0__SHIFT)); 4286 4287 if (td == R600_TD_AUTO) 4288 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK); 4289 else 4290 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK, ~SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK); 4291 4292 if (td == R600_TD_UP) 4293 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK); 4294 4295 if (td == R600_TD_DOWN) 4296 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK, ~SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK); 4297} 4298 4299static void si_program_tpp(struct amdgpu_device *adev) 4300{ 4301 WREG32(mmCG_TPC, R600_TPC_DFLT); 4302} 4303 4304static void si_program_sstp(struct amdgpu_device *adev) 4305{ 4306 WREG32(mmCG_SSP, (R600_SSTU_DFLT << CG_SSP__SSTU__SHIFT| R600_SST_DFLT << CG_SSP__SST__SHIFT)); 4307} 4308 4309static void si_enable_display_gap(struct amdgpu_device *adev) 4310{ 4311 u32 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL); 4312 4313 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK); 4314 tmp |= (R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT | 4315 R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT); 4316 4317 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG_MASK); 4318 tmp |= (R600_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG__SHIFT | 4319 R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG__SHIFT); 4320 WREG32(mmCG_DISPLAY_GAP_CNTL, tmp); 4321} 4322 4323static void si_program_vc(struct amdgpu_device *adev) 4324{ 4325 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4326 4327 WREG32(mmCG_FTV, pi->vrc); 4328} 4329 4330static void si_clear_vc(struct amdgpu_device *adev) 4331{ 4332 WREG32(mmCG_FTV, 0); 4333} 4334 4335static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 4336{ 4337 u8 mc_para_index; 4338 4339 if (memory_clock < 10000) 4340 mc_para_index = 0; 4341 else if (memory_clock >= 80000) 4342 mc_para_index = 0x0f; 4343 else 4344 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 4345 return mc_para_index; 4346} 4347 4348static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 4349{ 4350 u8 mc_para_index; 4351 4352 if (strobe_mode) { 4353 if (memory_clock < 12500) 4354 mc_para_index = 0x00; 4355 else if (memory_clock > 47500) 4356 mc_para_index = 0x0f; 4357 else 4358 mc_para_index = (u8)((memory_clock - 10000) / 2500); 4359 } else { 4360 if (memory_clock < 65000) 4361 mc_para_index = 0x00; 4362 else if (memory_clock > 135000) 4363 mc_para_index = 0x0f; 4364 else 4365 mc_para_index = (u8)((memory_clock - 60000) / 5000); 4366 } 4367 return mc_para_index; 4368} 4369 4370static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk) 4371{ 4372 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4373 bool strobe_mode = false; 4374 u8 result = 0; 4375 4376 if (mclk <= pi->mclk_strobe_mode_threshold) 4377 strobe_mode = true; 4378 4379 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 4380 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 4381 else 4382 result = si_get_ddr3_mclk_frequency_ratio(mclk); 4383 4384 if (strobe_mode) 4385 result |= SISLANDS_SMC_STROBE_ENABLE; 4386 4387 return result; 4388} 4389 4390static int si_upload_firmware(struct amdgpu_device *adev) 4391{ 4392 struct si_power_info *si_pi = si_get_pi(adev); 4393 4394 amdgpu_si_reset_smc(adev); 4395 amdgpu_si_smc_clock(adev, false); 4396 4397 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end); 4398} 4399 4400static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev, 4401 const struct atom_voltage_table *table, 4402 const struct amdgpu_phase_shedding_limits_table *limits) 4403{ 4404 u32 data, num_bits, num_levels; 4405 4406 if ((table == NULL) || (limits == NULL)) 4407 return false; 4408 4409 data = table->mask_low; 4410 4411 num_bits = hweight32(data); 4412 4413 if (num_bits == 0) 4414 return false; 4415 4416 num_levels = (1 << num_bits); 4417 4418 if (table->count != num_levels) 4419 return false; 4420 4421 if (limits->count != (num_levels - 1)) 4422 return false; 4423 4424 return true; 4425} 4426 4427static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev, 4428 u32 max_voltage_steps, 4429 struct atom_voltage_table *voltage_table) 4430{ 4431 unsigned int i, diff; 4432 4433 if (voltage_table->count <= max_voltage_steps) 4434 return; 4435 4436 diff = voltage_table->count - max_voltage_steps; 4437 4438 for (i= 0; i < max_voltage_steps; i++) 4439 voltage_table->entries[i] = voltage_table->entries[i + diff]; 4440 4441 voltage_table->count = max_voltage_steps; 4442} 4443 4444static int si_get_svi2_voltage_table(struct amdgpu_device *adev, 4445 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table, 4446 struct atom_voltage_table *voltage_table) 4447{ 4448 u32 i; 4449 4450 if (voltage_dependency_table == NULL) 4451 return -EINVAL; 4452 4453 voltage_table->mask_low = 0; 4454 voltage_table->phase_delay = 0; 4455 4456 voltage_table->count = voltage_dependency_table->count; 4457 for (i = 0; i < voltage_table->count; i++) { 4458 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 4459 voltage_table->entries[i].smio_low = 0; 4460 } 4461 4462 return 0; 4463} 4464 4465static int si_construct_voltage_tables(struct amdgpu_device *adev) 4466{ 4467 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4468 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4469 struct si_power_info *si_pi = si_get_pi(adev); 4470 int ret; 4471 4472 if (pi->voltage_control) { 4473 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC, 4474 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 4475 if (ret) 4476 return ret; 4477 4478 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4479 si_trim_voltage_table_to_fit_state_table(adev, 4480 SISLANDS_MAX_NO_VREG_STEPS, 4481 &eg_pi->vddc_voltage_table); 4482 } else if (si_pi->voltage_control_svi2) { 4483 ret = si_get_svi2_voltage_table(adev, 4484 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 4485 &eg_pi->vddc_voltage_table); 4486 if (ret) 4487 return ret; 4488 } else { 4489 return -EINVAL; 4490 } 4491 4492 if (eg_pi->vddci_control) { 4493 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI, 4494 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 4495 if (ret) 4496 return ret; 4497 4498 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4499 si_trim_voltage_table_to_fit_state_table(adev, 4500 SISLANDS_MAX_NO_VREG_STEPS, 4501 &eg_pi->vddci_voltage_table); 4502 } 4503 if (si_pi->vddci_control_svi2) { 4504 ret = si_get_svi2_voltage_table(adev, 4505 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 4506 &eg_pi->vddci_voltage_table); 4507 if (ret) 4508 return ret; 4509 } 4510 4511 if (pi->mvdd_control) { 4512 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC, 4513 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 4514 4515 if (ret) { 4516 pi->mvdd_control = false; 4517 return ret; 4518 } 4519 4520 if (si_pi->mvdd_voltage_table.count == 0) { 4521 pi->mvdd_control = false; 4522 return -EINVAL; 4523 } 4524 4525 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4526 si_trim_voltage_table_to_fit_state_table(adev, 4527 SISLANDS_MAX_NO_VREG_STEPS, 4528 &si_pi->mvdd_voltage_table); 4529 } 4530 4531 if (si_pi->vddc_phase_shed_control) { 4532 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC, 4533 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 4534 if (ret) 4535 si_pi->vddc_phase_shed_control = false; 4536 4537 if ((si_pi->vddc_phase_shed_table.count == 0) || 4538 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 4539 si_pi->vddc_phase_shed_control = false; 4540 } 4541 4542 return 0; 4543} 4544 4545static void si_populate_smc_voltage_table(struct amdgpu_device *adev, 4546 const struct atom_voltage_table *voltage_table, 4547 SISLANDS_SMC_STATETABLE *table) 4548{ 4549 unsigned int i; 4550 4551 for (i = 0; i < voltage_table->count; i++) 4552 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 4553} 4554 4555static int si_populate_smc_voltage_tables(struct amdgpu_device *adev, 4556 SISLANDS_SMC_STATETABLE *table) 4557{ 4558 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4559 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4560 struct si_power_info *si_pi = si_get_pi(adev); 4561 u8 i; 4562 4563 if (si_pi->voltage_control_svi2) { 4564 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 4565 si_pi->svc_gpio_id); 4566 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 4567 si_pi->svd_gpio_id); 4568 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4569 2); 4570 } else { 4571 if (eg_pi->vddc_voltage_table.count) { 4572 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table); 4573 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4574 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4575 4576 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4577 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4578 table->maxVDDCIndexInPPTable = i; 4579 break; 4580 } 4581 } 4582 } 4583 4584 if (eg_pi->vddci_voltage_table.count) { 4585 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table); 4586 4587 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4588 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4589 } 4590 4591 4592 if (si_pi->mvdd_voltage_table.count) { 4593 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table); 4594 4595 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4596 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4597 } 4598 4599 if (si_pi->vddc_phase_shed_control) { 4600 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table, 4601 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4602 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table); 4603 4604 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = 4605 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4606 4607 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4608 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4609 } else { 4610 si_pi->vddc_phase_shed_control = false; 4611 } 4612 } 4613 } 4614 4615 return 0; 4616} 4617 4618static int si_populate_voltage_value(struct amdgpu_device *adev, 4619 const struct atom_voltage_table *table, 4620 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4621{ 4622 unsigned int i; 4623 4624 for (i = 0; i < table->count; i++) { 4625 if (value <= table->entries[i].value) { 4626 voltage->index = (u8)i; 4627 voltage->value = cpu_to_be16(table->entries[i].value); 4628 break; 4629 } 4630 } 4631 4632 if (i >= table->count) 4633 return -EINVAL; 4634 4635 return 0; 4636} 4637 4638static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk, 4639 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4640{ 4641 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4642 struct si_power_info *si_pi = si_get_pi(adev); 4643 4644 if (pi->mvdd_control) { 4645 if (mclk <= pi->mvdd_split_frequency) 4646 voltage->index = 0; 4647 else 4648 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4649 4650 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4651 } 4652 return 0; 4653} 4654 4655static int si_get_std_voltage_value(struct amdgpu_device *adev, 4656 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4657 u16 *std_voltage) 4658{ 4659 u16 v_index; 4660 bool voltage_found = false; 4661 *std_voltage = be16_to_cpu(voltage->value); 4662 4663 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4664 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4665 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4666 return -EINVAL; 4667 4668 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4669 if (be16_to_cpu(voltage->value) == 4670 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4671 voltage_found = true; 4672 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) 4673 *std_voltage = 4674 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4675 else 4676 *std_voltage = 4677 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4678 break; 4679 } 4680 } 4681 4682 if (!voltage_found) { 4683 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4684 if (be16_to_cpu(voltage->value) <= 4685 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4686 voltage_found = true; 4687 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) 4688 *std_voltage = 4689 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4690 else 4691 *std_voltage = 4692 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4693 break; 4694 } 4695 } 4696 } 4697 } else { 4698 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count) 4699 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4700 } 4701 } 4702 4703 return 0; 4704} 4705 4706static int si_populate_std_voltage_value(struct amdgpu_device *adev, 4707 u16 value, u8 index, 4708 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4709{ 4710 voltage->index = index; 4711 voltage->value = cpu_to_be16(value); 4712 4713 return 0; 4714} 4715 4716static int si_populate_phase_shedding_value(struct amdgpu_device *adev, 4717 const struct amdgpu_phase_shedding_limits_table *limits, 4718 u16 voltage, u32 sclk, u32 mclk, 4719 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4720{ 4721 unsigned int i; 4722 4723 for (i = 0; i < limits->count; i++) { 4724 if ((voltage <= limits->entries[i].voltage) && 4725 (sclk <= limits->entries[i].sclk) && 4726 (mclk <= limits->entries[i].mclk)) 4727 break; 4728 } 4729 4730 smc_voltage->phase_settings = (u8)i; 4731 4732 return 0; 4733} 4734 4735static int si_init_arb_table_index(struct amdgpu_device *adev) 4736{ 4737 struct si_power_info *si_pi = si_get_pi(adev); 4738 u32 tmp; 4739 int ret; 4740 4741 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, 4742 &tmp, si_pi->sram_end); 4743 if (ret) 4744 return ret; 4745 4746 tmp &= 0x00FFFFFF; 4747 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4748 4749 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start, 4750 tmp, si_pi->sram_end); 4751} 4752 4753static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev) 4754{ 4755 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4756} 4757 4758static int si_reset_to_default(struct amdgpu_device *adev) 4759{ 4760 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4761 0 : -EINVAL; 4762} 4763 4764static int si_force_switch_to_arb_f0(struct amdgpu_device *adev) 4765{ 4766 struct si_power_info *si_pi = si_get_pi(adev); 4767 u32 tmp; 4768 int ret; 4769 4770 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, 4771 &tmp, si_pi->sram_end); 4772 if (ret) 4773 return ret; 4774 4775 tmp = (tmp >> 24) & 0xff; 4776 4777 if (tmp == MC_CG_ARB_FREQ_F0) 4778 return 0; 4779 4780 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0); 4781} 4782 4783static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev, 4784 u32 engine_clock) 4785{ 4786 u32 dram_rows; 4787 u32 dram_refresh_rate; 4788 u32 mc_arb_rfsh_rate; 4789 u32 tmp = (RREG32(mmMC_ARB_RAMCFG) & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT; 4790 4791 if (tmp >= 4) 4792 dram_rows = 16384; 4793 else 4794 dram_rows = 1 << (tmp + 10); 4795 4796 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4797 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4798 4799 return mc_arb_rfsh_rate; 4800} 4801 4802static int si_populate_memory_timing_parameters(struct amdgpu_device *adev, 4803 struct rv7xx_pl *pl, 4804 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4805{ 4806 u32 dram_timing; 4807 u32 dram_timing2; 4808 u32 burst_time; 4809 int ret; 4810 4811 arb_regs->mc_arb_rfsh_rate = 4812 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk); 4813 4814 ret = amdgpu_atombios_set_engine_dram_timings(adev, pl->sclk, 4815 pl->mclk); 4816 if (ret) 4817 return ret; 4818 4819 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4820 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4821 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4822 4823 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4824 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4825 arb_regs->mc_arb_burst_time = (u8)burst_time; 4826 4827 return 0; 4828} 4829 4830static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev, 4831 struct amdgpu_ps *amdgpu_state, 4832 unsigned int first_arb_set) 4833{ 4834 struct si_power_info *si_pi = si_get_pi(adev); 4835 struct si_ps *state = si_get_ps(amdgpu_state); 4836 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4837 int i, ret = 0; 4838 4839 for (i = 0; i < state->performance_level_count; i++) { 4840 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs); 4841 if (ret) 4842 break; 4843 ret = amdgpu_si_copy_bytes_to_smc(adev, 4844 si_pi->arb_table_start + 4845 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4846 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4847 (u8 *)&arb_regs, 4848 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4849 si_pi->sram_end); 4850 if (ret) 4851 break; 4852 } 4853 4854 return ret; 4855} 4856 4857static int si_program_memory_timing_parameters(struct amdgpu_device *adev, 4858 struct amdgpu_ps *amdgpu_new_state) 4859{ 4860 return si_do_program_memory_timing_parameters(adev, amdgpu_new_state, 4861 SISLANDS_DRIVER_STATE_ARB_INDEX); 4862} 4863 4864static int si_populate_initial_mvdd_value(struct amdgpu_device *adev, 4865 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4866{ 4867 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4868 struct si_power_info *si_pi = si_get_pi(adev); 4869 4870 if (pi->mvdd_control) 4871 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table, 4872 si_pi->mvdd_bootup_value, voltage); 4873 4874 return 0; 4875} 4876 4877static int si_populate_smc_initial_state(struct amdgpu_device *adev, 4878 struct amdgpu_ps *amdgpu_initial_state, 4879 SISLANDS_SMC_STATETABLE *table) 4880{ 4881 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state); 4882 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4883 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4884 struct si_power_info *si_pi = si_get_pi(adev); 4885 u32 reg; 4886 int ret; 4887 4888 table->initialState.level.mclk.vDLL_CNTL = 4889 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4890 table->initialState.level.mclk.vMCLK_PWRMGT_CNTL = 4891 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4892 table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL = 4893 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4894 table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL = 4895 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4896 table->initialState.level.mclk.vMPLL_FUNC_CNTL = 4897 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4898 table->initialState.level.mclk.vMPLL_FUNC_CNTL_1 = 4899 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4900 table->initialState.level.mclk.vMPLL_FUNC_CNTL_2 = 4901 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4902 table->initialState.level.mclk.vMPLL_SS = 4903 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4904 table->initialState.level.mclk.vMPLL_SS2 = 4905 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4906 4907 table->initialState.level.mclk.mclk_value = 4908 cpu_to_be32(initial_state->performance_levels[0].mclk); 4909 4910 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL = 4911 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4912 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = 4913 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4914 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = 4915 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4916 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = 4917 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4918 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM = 4919 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4920 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4921 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4922 4923 table->initialState.level.sclk.sclk_value = 4924 cpu_to_be32(initial_state->performance_levels[0].sclk); 4925 4926 table->initialState.level.arbRefreshState = 4927 SISLANDS_INITIAL_STATE_ARB_INDEX; 4928 4929 table->initialState.level.ACIndex = 0; 4930 4931 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 4932 initial_state->performance_levels[0].vddc, 4933 &table->initialState.level.vddc); 4934 4935 if (!ret) { 4936 u16 std_vddc; 4937 4938 ret = si_get_std_voltage_value(adev, 4939 &table->initialState.level.vddc, 4940 &std_vddc); 4941 if (!ret) 4942 si_populate_std_voltage_value(adev, std_vddc, 4943 table->initialState.level.vddc.index, 4944 &table->initialState.level.std_vddc); 4945 } 4946 4947 if (eg_pi->vddci_control) 4948 si_populate_voltage_value(adev, 4949 &eg_pi->vddci_voltage_table, 4950 initial_state->performance_levels[0].vddci, 4951 &table->initialState.level.vddci); 4952 4953 if (si_pi->vddc_phase_shed_control) 4954 si_populate_phase_shedding_value(adev, 4955 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 4956 initial_state->performance_levels[0].vddc, 4957 initial_state->performance_levels[0].sclk, 4958 initial_state->performance_levels[0].mclk, 4959 &table->initialState.level.vddc); 4960 4961 si_populate_initial_mvdd_value(adev, &table->initialState.level.mvdd); 4962 4963 reg = 0xffff << CG_AT__CG_R__SHIFT | 0 << CG_AT__CG_L__SHIFT; 4964 table->initialState.level.aT = cpu_to_be32(reg); 4965 table->initialState.level.bSP = cpu_to_be32(pi->dsp); 4966 table->initialState.level.gen2PCIE = (u8)si_pi->boot_pcie_gen; 4967 4968 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 4969 table->initialState.level.strobeMode = 4970 si_get_strobe_mode_settings(adev, 4971 initial_state->performance_levels[0].mclk); 4972 4973 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4974 table->initialState.level.mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4975 else 4976 table->initialState.level.mcFlags = 0; 4977 } 4978 4979 table->initialState.levelCount = 1; 4980 4981 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4982 4983 table->initialState.level.dpm2.MaxPS = 0; 4984 table->initialState.level.dpm2.NearTDPDec = 0; 4985 table->initialState.level.dpm2.AboveSafeInc = 0; 4986 table->initialState.level.dpm2.BelowSafeInc = 0; 4987 table->initialState.level.dpm2.PwrEfficiencyRatio = 0; 4988 4989 reg = SQ_POWER_THROTTLE__MIN_POWER_MASK | 4990 SQ_POWER_THROTTLE__MAX_POWER_MASK; 4991 table->initialState.level.SQPowerThrottle = cpu_to_be32(reg); 4992 4993 reg = SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK | 4994 SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK | 4995 SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK; 4996 table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg); 4997 4998 return 0; 4999} 5000 5001static enum si_pcie_gen si_gen_pcie_gen_support(struct amdgpu_device *adev, 5002 u32 sys_mask, 5003 enum si_pcie_gen asic_gen, 5004 enum si_pcie_gen default_gen) 5005{ 5006 switch (asic_gen) { 5007 case SI_PCIE_GEN1: 5008 return SI_PCIE_GEN1; 5009 case SI_PCIE_GEN2: 5010 return SI_PCIE_GEN2; 5011 case SI_PCIE_GEN3: 5012 return SI_PCIE_GEN3; 5013 default: 5014 if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) && 5015 (default_gen == SI_PCIE_GEN3)) 5016 return SI_PCIE_GEN3; 5017 else if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) && 5018 (default_gen == SI_PCIE_GEN2)) 5019 return SI_PCIE_GEN2; 5020 else 5021 return SI_PCIE_GEN1; 5022 } 5023 return SI_PCIE_GEN1; 5024} 5025 5026static int si_populate_smc_acpi_state(struct amdgpu_device *adev, 5027 SISLANDS_SMC_STATETABLE *table) 5028{ 5029 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5030 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5031 struct si_power_info *si_pi = si_get_pi(adev); 5032 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 5033 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 5034 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 5035 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 5036 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 5037 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 5038 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 5039 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 5040 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 5041 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 5042 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 5043 u32 reg; 5044 int ret; 5045 5046 table->ACPIState = table->initialState; 5047 5048 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 5049 5050 if (pi->acpi_vddc) { 5051 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 5052 pi->acpi_vddc, &table->ACPIState.level.vddc); 5053 if (!ret) { 5054 u16 std_vddc; 5055 5056 ret = si_get_std_voltage_value(adev, 5057 &table->ACPIState.level.vddc, &std_vddc); 5058 if (!ret) 5059 si_populate_std_voltage_value(adev, std_vddc, 5060 table->ACPIState.level.vddc.index, 5061 &table->ACPIState.level.std_vddc); 5062 } 5063 table->ACPIState.level.gen2PCIE = si_pi->acpi_pcie_gen; 5064 5065 if (si_pi->vddc_phase_shed_control) { 5066 si_populate_phase_shedding_value(adev, 5067 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 5068 pi->acpi_vddc, 5069 0, 5070 0, 5071 &table->ACPIState.level.vddc); 5072 } 5073 } else { 5074 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 5075 pi->min_vddc_in_table, &table->ACPIState.level.vddc); 5076 if (!ret) { 5077 u16 std_vddc; 5078 5079 ret = si_get_std_voltage_value(adev, 5080 &table->ACPIState.level.vddc, &std_vddc); 5081 5082 if (!ret) 5083 si_populate_std_voltage_value(adev, std_vddc, 5084 table->ACPIState.level.vddc.index, 5085 &table->ACPIState.level.std_vddc); 5086 } 5087 table->ACPIState.level.gen2PCIE = 5088 (u8)si_gen_pcie_gen_support(adev, 5089 si_pi->sys_pcie_mask, 5090 si_pi->boot_pcie_gen, 5091 SI_PCIE_GEN1); 5092 5093 if (si_pi->vddc_phase_shed_control) 5094 si_populate_phase_shedding_value(adev, 5095 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 5096 pi->min_vddc_in_table, 5097 0, 5098 0, 5099 &table->ACPIState.level.vddc); 5100 } 5101 5102 if (pi->acpi_vddc) { 5103 if (eg_pi->acpi_vddci) 5104 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table, 5105 eg_pi->acpi_vddci, 5106 &table->ACPIState.level.vddci); 5107 } 5108 5109 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 5110 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 5111 5112 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 5113 5114 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK; 5115 spll_func_cntl_2 |= 4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT; 5116 5117 table->ACPIState.level.mclk.vDLL_CNTL = 5118 cpu_to_be32(dll_cntl); 5119 table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL = 5120 cpu_to_be32(mclk_pwrmgt_cntl); 5121 table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL = 5122 cpu_to_be32(mpll_ad_func_cntl); 5123 table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL = 5124 cpu_to_be32(mpll_dq_func_cntl); 5125 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL = 5126 cpu_to_be32(mpll_func_cntl); 5127 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_1 = 5128 cpu_to_be32(mpll_func_cntl_1); 5129 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_2 = 5130 cpu_to_be32(mpll_func_cntl_2); 5131 table->ACPIState.level.mclk.vMPLL_SS = 5132 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 5133 table->ACPIState.level.mclk.vMPLL_SS2 = 5134 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 5135 5136 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL = 5137 cpu_to_be32(spll_func_cntl); 5138 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = 5139 cpu_to_be32(spll_func_cntl_2); 5140 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = 5141 cpu_to_be32(spll_func_cntl_3); 5142 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = 5143 cpu_to_be32(spll_func_cntl_4); 5144 5145 table->ACPIState.level.mclk.mclk_value = 0; 5146 table->ACPIState.level.sclk.sclk_value = 0; 5147 5148 si_populate_mvdd_value(adev, 0, &table->ACPIState.level.mvdd); 5149 5150 if (eg_pi->dynamic_ac_timing) 5151 table->ACPIState.level.ACIndex = 0; 5152 5153 table->ACPIState.level.dpm2.MaxPS = 0; 5154 table->ACPIState.level.dpm2.NearTDPDec = 0; 5155 table->ACPIState.level.dpm2.AboveSafeInc = 0; 5156 table->ACPIState.level.dpm2.BelowSafeInc = 0; 5157 table->ACPIState.level.dpm2.PwrEfficiencyRatio = 0; 5158 5159 reg = SQ_POWER_THROTTLE__MIN_POWER_MASK | SQ_POWER_THROTTLE__MAX_POWER_MASK; 5160 table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg); 5161 5162 reg = SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK | SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK | SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK; 5163 table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg); 5164 5165 return 0; 5166} 5167 5168static int si_populate_ulv_state(struct amdgpu_device *adev, 5169 struct SISLANDS_SMC_SWSTATE_SINGLE *state) 5170{ 5171 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5172 struct si_power_info *si_pi = si_get_pi(adev); 5173 struct si_ulv_param *ulv = &si_pi->ulv; 5174 u32 sclk_in_sr = 1350; /* ??? */ 5175 int ret; 5176 5177 ret = si_convert_power_level_to_smc(adev, &ulv->pl, 5178 &state->level); 5179 if (!ret) { 5180 if (eg_pi->sclk_deep_sleep) { 5181 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5182 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5183 else 5184 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5185 } 5186 if (ulv->one_pcie_lane_in_ulv) 5187 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 5188 state->level.arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 5189 state->level.ACIndex = 1; 5190 state->level.std_vddc = state->level.vddc; 5191 state->levelCount = 1; 5192 5193 state->flags |= PPSMC_SWSTATE_FLAG_DC; 5194 } 5195 5196 return ret; 5197} 5198 5199static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev) 5200{ 5201 struct si_power_info *si_pi = si_get_pi(adev); 5202 struct si_ulv_param *ulv = &si_pi->ulv; 5203 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 5204 int ret; 5205 5206 ret = si_populate_memory_timing_parameters(adev, &ulv->pl, 5207 &arb_regs); 5208 if (ret) 5209 return ret; 5210 5211 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 5212 ulv->volt_change_delay); 5213 5214 ret = amdgpu_si_copy_bytes_to_smc(adev, 5215 si_pi->arb_table_start + 5216 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 5217 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 5218 (u8 *)&arb_regs, 5219 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 5220 si_pi->sram_end); 5221 5222 return ret; 5223} 5224 5225static void si_get_mvdd_configuration(struct amdgpu_device *adev) 5226{ 5227 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5228 5229 pi->mvdd_split_frequency = 30000; 5230} 5231 5232static int si_init_smc_table(struct amdgpu_device *adev) 5233{ 5234 struct si_power_info *si_pi = si_get_pi(adev); 5235 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps; 5236 const struct si_ulv_param *ulv = &si_pi->ulv; 5237 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 5238 int ret; 5239 u32 lane_width; 5240 u32 vr_hot_gpio; 5241 5242 si_populate_smc_voltage_tables(adev, table); 5243 5244 switch (adev->pm.int_thermal_type) { 5245 case THERMAL_TYPE_SI: 5246 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 5247 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 5248 break; 5249 case THERMAL_TYPE_NONE: 5250 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 5251 break; 5252 default: 5253 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 5254 break; 5255 } 5256 5257 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 5258 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 5259 5260 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 5261 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819)) 5262 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 5263 } 5264 5265 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 5266 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 5267 5268 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 5269 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 5270 5271 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 5272 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 5273 5274 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 5275 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 5276 vr_hot_gpio = adev->pm.dpm.backbias_response_time; 5277 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 5278 vr_hot_gpio); 5279 } 5280 5281 ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table); 5282 if (ret) 5283 return ret; 5284 5285 ret = si_populate_smc_acpi_state(adev, table); 5286 if (ret) 5287 return ret; 5288 5289 table->driverState.flags = table->initialState.flags; 5290 table->driverState.levelCount = table->initialState.levelCount; 5291 table->driverState.levels[0] = table->initialState.level; 5292 5293 ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state, 5294 SISLANDS_INITIAL_STATE_ARB_INDEX); 5295 if (ret) 5296 return ret; 5297 5298 if (ulv->supported && ulv->pl.vddc) { 5299 ret = si_populate_ulv_state(adev, &table->ULVState); 5300 if (ret) 5301 return ret; 5302 5303 ret = si_program_ulv_memory_timing_parameters(adev); 5304 if (ret) 5305 return ret; 5306 5307 WREG32(mmCG_ULV_CONTROL, ulv->cg_ulv_control); 5308 WREG32(mmCG_ULV_PARAMETER, ulv->cg_ulv_parameter); 5309 5310 lane_width = amdgpu_get_pcie_lanes(adev); 5311 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5312 } else { 5313 table->ULVState = table->initialState; 5314 } 5315 5316 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start, 5317 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 5318 si_pi->sram_end); 5319} 5320 5321static int si_calculate_sclk_params(struct amdgpu_device *adev, 5322 u32 engine_clock, 5323 SISLANDS_SMC_SCLK_VALUE *sclk) 5324{ 5325 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5326 struct si_power_info *si_pi = si_get_pi(adev); 5327 struct atom_clock_dividers dividers; 5328 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 5329 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 5330 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 5331 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 5332 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 5333 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 5334 u64 tmp; 5335 u32 reference_clock = adev->clock.spll.reference_freq; 5336 u32 reference_divider; 5337 u32 fbdiv; 5338 int ret; 5339 5340 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 5341 engine_clock, false, ÷rs); 5342 if (ret) 5343 return ret; 5344 5345 reference_divider = 1 + dividers.ref_div; 5346 5347 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 5348 do_div(tmp, reference_clock); 5349 fbdiv = (u32) tmp; 5350 5351 spll_func_cntl &= ~(CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK | CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK); 5352 spll_func_cntl |= dividers.ref_div << CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT; 5353 spll_func_cntl |= dividers.post_div << CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT; 5354 5355 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK; 5356 spll_func_cntl_2 |= 2 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT; 5357 5358 spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK; 5359 spll_func_cntl_3 |= fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT; 5360 spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK; 5361 5362 if (pi->sclk_ss) { 5363 struct amdgpu_atom_ss ss; 5364 u32 vco_freq = engine_clock * dividers.post_div; 5365 5366 if (amdgpu_atombios_get_asic_ss_info(adev, &ss, 5367 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 5368 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 5369 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 5370 5371 cg_spll_spread_spectrum &= ~CG_SPLL_SPREAD_SPECTRUM__CLK_S_MASK; 5372 cg_spll_spread_spectrum |= clk_s << CG_SPLL_SPREAD_SPECTRUM__CLK_S__SHIFT; 5373 cg_spll_spread_spectrum |= CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK; 5374 5375 cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLK_V_MASK; 5376 cg_spll_spread_spectrum_2 |= clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLK_V__SHIFT; 5377 } 5378 } 5379 5380 sclk->sclk_value = engine_clock; 5381 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 5382 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 5383 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 5384 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 5385 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 5386 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 5387 5388 return 0; 5389} 5390 5391static int si_populate_sclk_value(struct amdgpu_device *adev, 5392 u32 engine_clock, 5393 SISLANDS_SMC_SCLK_VALUE *sclk) 5394{ 5395 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 5396 int ret; 5397 5398 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp); 5399 if (!ret) { 5400 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 5401 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 5402 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 5403 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 5404 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 5405 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 5406 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 5407 } 5408 5409 return ret; 5410} 5411 5412static int si_populate_mclk_value(struct amdgpu_device *adev, 5413 u32 engine_clock, 5414 u32 memory_clock, 5415 SISLANDS_SMC_MCLK_VALUE *mclk, 5416 bool strobe_mode, 5417 bool dll_state_on) 5418{ 5419 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5420 struct si_power_info *si_pi = si_get_pi(adev); 5421 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 5422 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 5423 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 5424 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 5425 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 5426 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 5427 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 5428 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 5429 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 5430 struct atom_mpll_param mpll_param; 5431 int ret; 5432 5433 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param); 5434 if (ret) 5435 return ret; 5436 5437 mpll_func_cntl &= ~BWCTRL_MASK; 5438 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 5439 5440 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 5441 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 5442 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 5443 5444 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 5445 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 5446 5447 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 5448 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 5449 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 5450 YCLK_POST_DIV(mpll_param.post_div); 5451 } 5452 5453 if (pi->mclk_ss) { 5454 struct amdgpu_atom_ss ss; 5455 u32 freq_nom; 5456 u32 tmp; 5457 u32 reference_clock = adev->clock.mpll.reference_freq; 5458 5459 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 5460 freq_nom = memory_clock * 4; 5461 else 5462 freq_nom = memory_clock * 2; 5463 5464 tmp = freq_nom / reference_clock; 5465 tmp = tmp * tmp; 5466 if (amdgpu_atombios_get_asic_ss_info(adev, &ss, 5467 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 5468 u32 clks = reference_clock * 5 / ss.rate; 5469 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 5470 5471 mpll_ss1 &= ~CLKV_MASK; 5472 mpll_ss1 |= CLKV(clkv); 5473 5474 mpll_ss2 &= ~CLKS_MASK; 5475 mpll_ss2 |= CLKS(clks); 5476 } 5477 } 5478 5479 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 5480 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 5481 5482 if (dll_state_on) 5483 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 5484 else 5485 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 5486 5487 mclk->mclk_value = cpu_to_be32(memory_clock); 5488 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 5489 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 5490 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 5491 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 5492 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 5493 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 5494 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 5495 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 5496 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 5497 5498 return 0; 5499} 5500 5501static void si_populate_smc_sp(struct amdgpu_device *adev, 5502 struct amdgpu_ps *amdgpu_state, 5503 SISLANDS_SMC_SWSTATE *smc_state) 5504{ 5505 struct si_ps *ps = si_get_ps(amdgpu_state); 5506 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5507 int i; 5508 5509 for (i = 0; i < ps->performance_level_count - 1; i++) 5510 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 5511 5512 smc_state->levels[ps->performance_level_count - 1].bSP = 5513 cpu_to_be32(pi->psp); 5514} 5515 5516static int si_convert_power_level_to_smc(struct amdgpu_device *adev, 5517 struct rv7xx_pl *pl, 5518 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 5519{ 5520 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5521 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5522 struct si_power_info *si_pi = si_get_pi(adev); 5523 int ret; 5524 bool dll_state_on; 5525 u16 std_vddc; 5526 5527 if (eg_pi->pcie_performance_request && 5528 (si_pi->force_pcie_gen != SI_PCIE_GEN_INVALID)) 5529 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 5530 else 5531 level->gen2PCIE = (u8)pl->pcie_gen; 5532 5533 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk); 5534 if (ret) 5535 return ret; 5536 5537 level->mcFlags = 0; 5538 5539 if (pi->mclk_stutter_mode_threshold && 5540 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 5541 !eg_pi->uvd_enabled && 5542 (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) && 5543 (adev->pm.pm_display_cfg.num_display <= 2)) { 5544 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 5545 } 5546 5547 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 5548 if (pl->mclk > pi->mclk_edc_enable_threshold) 5549 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 5550 5551 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 5552 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 5553 5554 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk); 5555 5556 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 5557 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 5558 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 5559 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5560 else 5561 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 5562 } else { 5563 dll_state_on = false; 5564 } 5565 } else { 5566 level->strobeMode = si_get_strobe_mode_settings(adev, 5567 pl->mclk); 5568 5569 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5570 } 5571 5572 ret = si_populate_mclk_value(adev, 5573 pl->sclk, 5574 pl->mclk, 5575 &level->mclk, 5576 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 5577 if (ret) 5578 return ret; 5579 5580 ret = si_populate_voltage_value(adev, 5581 &eg_pi->vddc_voltage_table, 5582 pl->vddc, &level->vddc); 5583 if (ret) 5584 return ret; 5585 5586 5587 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc); 5588 if (ret) 5589 return ret; 5590 5591 ret = si_populate_std_voltage_value(adev, std_vddc, 5592 level->vddc.index, &level->std_vddc); 5593 if (ret) 5594 return ret; 5595 5596 if (eg_pi->vddci_control) { 5597 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table, 5598 pl->vddci, &level->vddci); 5599 if (ret) 5600 return ret; 5601 } 5602 5603 if (si_pi->vddc_phase_shed_control) { 5604 ret = si_populate_phase_shedding_value(adev, 5605 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 5606 pl->vddc, 5607 pl->sclk, 5608 pl->mclk, 5609 &level->vddc); 5610 if (ret) 5611 return ret; 5612 } 5613 5614 level->MaxPoweredUpCU = si_pi->max_cu; 5615 5616 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd); 5617 5618 return ret; 5619} 5620 5621static int si_populate_smc_t(struct amdgpu_device *adev, 5622 struct amdgpu_ps *amdgpu_state, 5623 SISLANDS_SMC_SWSTATE *smc_state) 5624{ 5625 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5626 struct si_ps *state = si_get_ps(amdgpu_state); 5627 u32 a_t; 5628 u32 t_l, t_h; 5629 u32 high_bsp; 5630 int i, ret; 5631 5632 if (state->performance_level_count >= 9) 5633 return -EINVAL; 5634 5635 if (state->performance_level_count < 2) { 5636 a_t = 0xffff << CG_AT__CG_R__SHIFT | 0 << CG_AT__CG_L__SHIFT; 5637 smc_state->levels[0].aT = cpu_to_be32(a_t); 5638 return 0; 5639 } 5640 5641 smc_state->levels[0].aT = cpu_to_be32(0); 5642 5643 for (i = 0; i <= state->performance_level_count - 2; i++) { 5644 ret = r600_calculate_at( 5645 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5646 100 * R600_AH_DFLT, 5647 state->performance_levels[i + 1].sclk, 5648 state->performance_levels[i].sclk, 5649 &t_l, 5650 &t_h); 5651 5652 if (ret) { 5653 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5654 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5655 } 5656 5657 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_AT__CG_R_MASK; 5658 a_t |= (t_l * pi->bsp / 20000) << CG_AT__CG_R__SHIFT; 5659 smc_state->levels[i].aT = cpu_to_be32(a_t); 5660 5661 high_bsp = (i == state->performance_level_count - 2) ? 5662 pi->pbsp : pi->bsp; 5663 a_t = (0xffff) << CG_AT__CG_R__SHIFT | (t_h * high_bsp / 20000) << CG_AT__CG_L__SHIFT; 5664 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5665 } 5666 5667 return 0; 5668} 5669 5670static int si_disable_ulv(struct amdgpu_device *adev) 5671{ 5672 PPSMC_Result r; 5673 5674 r = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV); 5675 return (r == PPSMC_Result_OK) ? 0 : -EINVAL; 5676} 5677 5678static bool si_is_state_ulv_compatible(struct amdgpu_device *adev, 5679 struct amdgpu_ps *amdgpu_state) 5680{ 5681 const struct si_power_info *si_pi = si_get_pi(adev); 5682 const struct si_ulv_param *ulv = &si_pi->ulv; 5683 const struct si_ps *state = si_get_ps(amdgpu_state); 5684 int i; 5685 5686 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5687 return false; 5688 5689 /* XXX validate against display requirements! */ 5690 5691 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5692 if (adev->pm.pm_display_cfg.display_clk <= 5693 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5694 if (ulv->pl.vddc < 5695 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5696 return false; 5697 } 5698 } 5699 5700 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0)) 5701 return false; 5702 5703 return true; 5704} 5705 5706static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev, 5707 struct amdgpu_ps *amdgpu_new_state) 5708{ 5709 const struct si_power_info *si_pi = si_get_pi(adev); 5710 const struct si_ulv_param *ulv = &si_pi->ulv; 5711 5712 if (ulv->supported) { 5713 if (si_is_state_ulv_compatible(adev, amdgpu_new_state)) 5714 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5715 0 : -EINVAL; 5716 } 5717 return 0; 5718} 5719 5720static int si_convert_power_state_to_smc(struct amdgpu_device *adev, 5721 struct amdgpu_ps *amdgpu_state, 5722 SISLANDS_SMC_SWSTATE *smc_state) 5723{ 5724 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5725 struct ni_power_info *ni_pi = ni_get_pi(adev); 5726 struct si_power_info *si_pi = si_get_pi(adev); 5727 struct si_ps *state = si_get_ps(amdgpu_state); 5728 int i, ret; 5729 u32 threshold; 5730 u32 sclk_in_sr = 1350; /* ??? */ 5731 5732 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5733 return -EINVAL; 5734 5735 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5736 5737 if (amdgpu_state->vclk && amdgpu_state->dclk) { 5738 eg_pi->uvd_enabled = true; 5739 if (eg_pi->smu_uvd_hs) 5740 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5741 } else { 5742 eg_pi->uvd_enabled = false; 5743 } 5744 5745 if (state->dc_compatible) 5746 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5747 5748 smc_state->levelCount = 0; 5749 for (i = 0; i < state->performance_level_count; i++) { 5750 if (eg_pi->sclk_deep_sleep) { 5751 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5752 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5753 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5754 else 5755 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5756 } 5757 } 5758 5759 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i], 5760 &smc_state->levels[i]); 5761 smc_state->levels[i].arbRefreshState = 5762 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5763 5764 if (ret) 5765 return ret; 5766 5767 if (ni_pi->enable_power_containment) 5768 smc_state->levels[i].displayWatermark = 5769 (state->performance_levels[i].sclk < threshold) ? 5770 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5771 else 5772 smc_state->levels[i].displayWatermark = (i < 2) ? 5773 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5774 5775 if (eg_pi->dynamic_ac_timing) 5776 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5777 else 5778 smc_state->levels[i].ACIndex = 0; 5779 5780 smc_state->levelCount++; 5781 } 5782 5783 si_write_smc_soft_register(adev, 5784 SI_SMC_SOFT_REGISTER_watermark_threshold, 5785 threshold / 512); 5786 5787 si_populate_smc_sp(adev, amdgpu_state, smc_state); 5788 5789 ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state); 5790 if (ret) 5791 ni_pi->enable_power_containment = false; 5792 5793 ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state); 5794 if (ret) 5795 ni_pi->enable_sq_ramping = false; 5796 5797 return si_populate_smc_t(adev, amdgpu_state, smc_state); 5798} 5799 5800static int si_upload_sw_state(struct amdgpu_device *adev, 5801 struct amdgpu_ps *amdgpu_new_state) 5802{ 5803 struct si_power_info *si_pi = si_get_pi(adev); 5804 struct si_ps *new_state = si_get_ps(amdgpu_new_state); 5805 int ret; 5806 u32 address = si_pi->state_table_start + 5807 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5808 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5809 size_t state_size = struct_size(smc_state, levels, 5810 new_state->performance_level_count); 5811 memset(smc_state, 0, state_size); 5812 5813 ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state); 5814 if (ret) 5815 return ret; 5816 5817 return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, 5818 state_size, si_pi->sram_end); 5819} 5820 5821static int si_upload_ulv_state(struct amdgpu_device *adev) 5822{ 5823 struct si_power_info *si_pi = si_get_pi(adev); 5824 struct si_ulv_param *ulv = &si_pi->ulv; 5825 int ret = 0; 5826 5827 if (ulv->supported && ulv->pl.vddc) { 5828 u32 address = si_pi->state_table_start + 5829 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5830 struct SISLANDS_SMC_SWSTATE_SINGLE *smc_state = &si_pi->smc_statetable.ULVState; 5831 u32 state_size = sizeof(struct SISLANDS_SMC_SWSTATE_SINGLE); 5832 5833 memset(smc_state, 0, state_size); 5834 5835 ret = si_populate_ulv_state(adev, smc_state); 5836 if (!ret) 5837 ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, 5838 state_size, si_pi->sram_end); 5839 } 5840 5841 return ret; 5842} 5843 5844static int si_upload_smc_data(struct amdgpu_device *adev) 5845{ 5846 const struct amd_pp_display_configuration *cfg = &adev->pm.pm_display_cfg; 5847 u32 crtc_index = 0; 5848 u32 mclk_change_block_cp_min = 0; 5849 u32 mclk_change_block_cp_max = 0; 5850 5851 /* When a display is plugged in, program these so that the SMC 5852 * performs MCLK switching when it doesn't cause flickering. 5853 * When no display is plugged in, there is no need to restrict 5854 * MCLK switching, so program them to zero. 5855 */ 5856 if (cfg->num_display) { 5857 crtc_index = cfg->crtc_index; 5858 5859 if (cfg->line_time_in_us) { 5860 mclk_change_block_cp_min = 200 / cfg->line_time_in_us; 5861 mclk_change_block_cp_max = 100 / cfg->line_time_in_us; 5862 } 5863 } 5864 5865 si_write_smc_soft_register(adev, 5866 SI_SMC_SOFT_REGISTER_crtc_index, 5867 crtc_index); 5868 5869 si_write_smc_soft_register(adev, 5870 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5871 mclk_change_block_cp_min); 5872 5873 si_write_smc_soft_register(adev, 5874 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5875 mclk_change_block_cp_max); 5876 5877 return 0; 5878} 5879 5880static int si_set_mc_special_registers(struct amdgpu_device *adev, 5881 struct si_mc_reg_table *table) 5882{ 5883 u8 i, j, k; 5884 u32 temp_reg; 5885 5886 for (i = 0, j = table->last; i < table->last; i++) { 5887 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5888 return -EINVAL; 5889 switch (table->mc_reg_address[i].s1) { 5890 case MC_SEQ_MISC1: 5891 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5892 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS; 5893 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP; 5894 for (k = 0; k < table->num_entries; k++) 5895 table->mc_reg_table_entry[k].mc_data[j] = 5896 ((temp_reg & 0xffff0000)) | 5897 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5898 j++; 5899 5900 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5901 return -EINVAL; 5902 temp_reg = RREG32(MC_PMG_CMD_MRS); 5903 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS; 5904 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP; 5905 for (k = 0; k < table->num_entries; k++) { 5906 table->mc_reg_table_entry[k].mc_data[j] = 5907 (temp_reg & 0xffff0000) | 5908 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5909 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) 5910 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5911 } 5912 j++; 5913 5914 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { 5915 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5916 return -EINVAL; 5917 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD; 5918 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD; 5919 for (k = 0; k < table->num_entries; k++) 5920 table->mc_reg_table_entry[k].mc_data[j] = 5921 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5922 j++; 5923 } 5924 break; 5925 case MC_SEQ_RESERVE_M: 5926 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5927 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1; 5928 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP; 5929 for(k = 0; k < table->num_entries; k++) 5930 table->mc_reg_table_entry[k].mc_data[j] = 5931 (temp_reg & 0xffff0000) | 5932 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5933 j++; 5934 break; 5935 default: 5936 break; 5937 } 5938 } 5939 5940 table->last = j; 5941 5942 return 0; 5943} 5944 5945static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5946{ 5947 bool result = true; 5948 switch (in_reg) { 5949 case MC_SEQ_RAS_TIMING: 5950 *out_reg = MC_SEQ_RAS_TIMING_LP; 5951 break; 5952 case MC_SEQ_CAS_TIMING: 5953 *out_reg = MC_SEQ_CAS_TIMING_LP; 5954 break; 5955 case MC_SEQ_MISC_TIMING: 5956 *out_reg = MC_SEQ_MISC_TIMING_LP; 5957 break; 5958 case MC_SEQ_MISC_TIMING2: 5959 *out_reg = MC_SEQ_MISC_TIMING2_LP; 5960 break; 5961 case MC_SEQ_RD_CTL_D0: 5962 *out_reg = MC_SEQ_RD_CTL_D0_LP; 5963 break; 5964 case MC_SEQ_RD_CTL_D1: 5965 *out_reg = MC_SEQ_RD_CTL_D1_LP; 5966 break; 5967 case MC_SEQ_WR_CTL_D0: 5968 *out_reg = MC_SEQ_WR_CTL_D0_LP; 5969 break; 5970 case MC_SEQ_WR_CTL_D1: 5971 *out_reg = MC_SEQ_WR_CTL_D1_LP; 5972 break; 5973 case MC_PMG_CMD_EMRS: 5974 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP; 5975 break; 5976 case MC_PMG_CMD_MRS: 5977 *out_reg = MC_SEQ_PMG_CMD_MRS_LP; 5978 break; 5979 case MC_PMG_CMD_MRS1: 5980 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP; 5981 break; 5982 case MC_SEQ_PMG_TIMING: 5983 *out_reg = MC_SEQ_PMG_TIMING_LP; 5984 break; 5985 case MC_PMG_CMD_MRS2: 5986 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP; 5987 break; 5988 case MC_SEQ_WR_CTL_2: 5989 *out_reg = MC_SEQ_WR_CTL_2_LP; 5990 break; 5991 default: 5992 result = false; 5993 break; 5994 } 5995 5996 return result; 5997} 5998 5999static void si_set_valid_flag(struct si_mc_reg_table *table) 6000{ 6001 u8 i, j; 6002 6003 for (i = 0; i < table->last; i++) { 6004 for (j = 1; j < table->num_entries; j++) { 6005 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 6006 table->valid_flag |= 1 << i; 6007 break; 6008 } 6009 } 6010 } 6011} 6012 6013static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 6014{ 6015 u32 i; 6016 u16 address; 6017 6018 for (i = 0; i < table->last; i++) 6019 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 6020 address : table->mc_reg_address[i].s1; 6021 6022} 6023 6024static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 6025 struct si_mc_reg_table *si_table) 6026{ 6027 u8 i, j; 6028 6029 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 6030 return -EINVAL; 6031 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 6032 return -EINVAL; 6033 6034 for (i = 0; i < table->last; i++) 6035 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 6036 si_table->last = table->last; 6037 6038 for (i = 0; i < table->num_entries; i++) { 6039 si_table->mc_reg_table_entry[i].mclk_max = 6040 table->mc_reg_table_entry[i].mclk_max; 6041 for (j = 0; j < table->last; j++) { 6042 si_table->mc_reg_table_entry[i].mc_data[j] = 6043 table->mc_reg_table_entry[i].mc_data[j]; 6044 } 6045 } 6046 si_table->num_entries = table->num_entries; 6047 6048 return 0; 6049} 6050 6051static int si_initialize_mc_reg_table(struct amdgpu_device *adev) 6052{ 6053 struct si_power_info *si_pi = si_get_pi(adev); 6054 struct atom_mc_reg_table *table; 6055 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 6056 u8 module_index = rv770_get_memory_module_index(adev); 6057 int ret; 6058 6059 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 6060 if (!table) 6061 return -ENOMEM; 6062 6063 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 6064 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 6065 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 6066 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 6067 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 6068 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 6069 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 6070 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 6071 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 6072 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 6073 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 6074 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 6075 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 6076 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 6077 6078 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table); 6079 if (ret) 6080 goto init_mc_done; 6081 6082 ret = si_copy_vbios_mc_reg_table(table, si_table); 6083 if (ret) 6084 goto init_mc_done; 6085 6086 si_set_s0_mc_reg_index(si_table); 6087 6088 ret = si_set_mc_special_registers(adev, si_table); 6089 if (ret) 6090 goto init_mc_done; 6091 6092 si_set_valid_flag(si_table); 6093 6094init_mc_done: 6095 kfree(table); 6096 6097 return ret; 6098 6099} 6100 6101static void si_populate_mc_reg_addresses(struct amdgpu_device *adev, 6102 SMC_SIslands_MCRegisters *mc_reg_table) 6103{ 6104 struct si_power_info *si_pi = si_get_pi(adev); 6105 u32 i, j; 6106 6107 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 6108 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 6109 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 6110 break; 6111 mc_reg_table->address[i].s0 = 6112 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 6113 mc_reg_table->address[i].s1 = 6114 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 6115 i++; 6116 } 6117 } 6118 mc_reg_table->last = (u8)i; 6119} 6120 6121static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 6122 SMC_SIslands_MCRegisterSet *data, 6123 u32 num_entries, u32 valid_flag) 6124{ 6125 u32 i, j; 6126 6127 for(i = 0, j = 0; j < num_entries; j++) { 6128 if (valid_flag & (1 << j)) { 6129 data->value[i] = cpu_to_be32(entry->mc_data[j]); 6130 i++; 6131 } 6132 } 6133} 6134 6135static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev, 6136 struct rv7xx_pl *pl, 6137 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 6138{ 6139 struct si_power_info *si_pi = si_get_pi(adev); 6140 u32 i = 0; 6141 6142 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 6143 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 6144 break; 6145 } 6146 6147 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 6148 --i; 6149 6150 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 6151 mc_reg_table_data, si_pi->mc_reg_table.last, 6152 si_pi->mc_reg_table.valid_flag); 6153} 6154 6155static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev, 6156 struct amdgpu_ps *amdgpu_state, 6157 SMC_SIslands_MCRegisters *mc_reg_table) 6158{ 6159 struct si_ps *state = si_get_ps(amdgpu_state); 6160 int i; 6161 6162 for (i = 0; i < state->performance_level_count; i++) { 6163 si_convert_mc_reg_table_entry_to_smc(adev, 6164 &state->performance_levels[i], 6165 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 6166 } 6167} 6168 6169static int si_populate_mc_reg_table(struct amdgpu_device *adev, 6170 struct amdgpu_ps *amdgpu_boot_state) 6171{ 6172 struct si_ps *boot_state = si_get_ps(amdgpu_boot_state); 6173 struct si_power_info *si_pi = si_get_pi(adev); 6174 struct si_ulv_param *ulv = &si_pi->ulv; 6175 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 6176 6177 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 6178 6179 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1); 6180 6181 si_populate_mc_reg_addresses(adev, smc_mc_reg_table); 6182 6183 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0], 6184 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 6185 6186 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 6187 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 6188 si_pi->mc_reg_table.last, 6189 si_pi->mc_reg_table.valid_flag); 6190 6191 if (ulv->supported && ulv->pl.vddc != 0) 6192 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl, 6193 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 6194 else 6195 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 6196 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 6197 si_pi->mc_reg_table.last, 6198 si_pi->mc_reg_table.valid_flag); 6199 6200 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table); 6201 6202 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start, 6203 (u8 *)smc_mc_reg_table, 6204 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 6205} 6206 6207static int si_upload_mc_reg_table(struct amdgpu_device *adev, 6208 struct amdgpu_ps *amdgpu_new_state) 6209{ 6210 struct si_ps *new_state = si_get_ps(amdgpu_new_state); 6211 struct si_power_info *si_pi = si_get_pi(adev); 6212 u32 address = si_pi->mc_reg_table_start + 6213 offsetof(SMC_SIslands_MCRegisters, 6214 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 6215 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 6216 6217 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 6218 6219 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table); 6220 6221 return amdgpu_si_copy_bytes_to_smc(adev, address, 6222 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 6223 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 6224 si_pi->sram_end); 6225} 6226 6227static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable) 6228{ 6229 if (enable) 6230 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK, ~GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK); 6231 else 6232 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK); 6233} 6234 6235static enum si_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev, 6236 struct amdgpu_ps *amdgpu_state) 6237{ 6238 struct si_ps *state = si_get_ps(amdgpu_state); 6239 int i; 6240 u16 pcie_speed, max_speed = 0; 6241 6242 for (i = 0; i < state->performance_level_count; i++) { 6243 pcie_speed = state->performance_levels[i].pcie_gen; 6244 if (max_speed < pcie_speed) 6245 max_speed = pcie_speed; 6246 } 6247 return max_speed; 6248} 6249 6250static u16 si_get_current_pcie_speed(struct amdgpu_device *adev) 6251{ 6252 u32 speed_cntl; 6253 6254 speed_cntl = RREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL) & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK; 6255 speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 6256 6257 return (u16)speed_cntl; 6258} 6259 6260static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev, 6261 struct amdgpu_ps *amdgpu_new_state, 6262 struct amdgpu_ps *amdgpu_current_state) 6263{ 6264 struct si_power_info *si_pi = si_get_pi(adev); 6265 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state); 6266 enum si_pcie_gen current_link_speed; 6267 6268 if (si_pi->force_pcie_gen == SI_PCIE_GEN_INVALID) 6269 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state); 6270 else 6271 current_link_speed = si_pi->force_pcie_gen; 6272 6273 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID; 6274 si_pi->pspp_notify_required = false; 6275 if (target_link_speed > current_link_speed) { 6276 switch (target_link_speed) { 6277#if defined(CONFIG_ACPI) 6278 case SI_PCIE_GEN3: 6279 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 6280 break; 6281 si_pi->force_pcie_gen = SI_PCIE_GEN2; 6282 if (current_link_speed == SI_PCIE_GEN2) 6283 break; 6284 fallthrough; 6285 case SI_PCIE_GEN2: 6286 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 6287 break; 6288 fallthrough; 6289#endif 6290 default: 6291 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev); 6292 break; 6293 } 6294 } else { 6295 if (target_link_speed < current_link_speed) 6296 si_pi->pspp_notify_required = true; 6297 } 6298} 6299 6300static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev, 6301 struct amdgpu_ps *amdgpu_new_state, 6302 struct amdgpu_ps *amdgpu_current_state) 6303{ 6304 struct si_power_info *si_pi = si_get_pi(adev); 6305 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state); 6306 u8 request; 6307 6308 if (si_pi->pspp_notify_required) { 6309 if (target_link_speed == SI_PCIE_GEN3) 6310 request = PCIE_PERF_REQ_PECI_GEN3; 6311 else if (target_link_speed == SI_PCIE_GEN2) 6312 request = PCIE_PERF_REQ_PECI_GEN2; 6313 else 6314 request = PCIE_PERF_REQ_PECI_GEN1; 6315 6316 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 6317 (si_get_current_pcie_speed(adev) > 0)) 6318 return; 6319 6320#if defined(CONFIG_ACPI) 6321 amdgpu_acpi_pcie_performance_request(adev, request, false); 6322#endif 6323 } 6324} 6325 6326#if 0 6327static int si_ds_request(struct amdgpu_device *adev, 6328 bool ds_status_on, u32 count_write) 6329{ 6330 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 6331 6332 if (eg_pi->sclk_deep_sleep) { 6333 if (ds_status_on) 6334 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 6335 PPSMC_Result_OK) ? 6336 0 : -EINVAL; 6337 else 6338 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 6339 PPSMC_Result_OK) ? 0 : -EINVAL; 6340 } 6341 return 0; 6342} 6343#endif 6344 6345static void si_set_max_cu_value(struct amdgpu_device *adev) 6346{ 6347 struct si_power_info *si_pi = si_get_pi(adev); 6348 6349 if (adev->asic_type == CHIP_VERDE) { 6350 switch (adev->pdev->device) { 6351 case 0x6820: 6352 case 0x6825: 6353 case 0x6821: 6354 case 0x6823: 6355 case 0x6827: 6356 si_pi->max_cu = 10; 6357 break; 6358 case 0x682D: 6359 case 0x6824: 6360 case 0x682F: 6361 case 0x6826: 6362 si_pi->max_cu = 8; 6363 break; 6364 case 0x6828: 6365 case 0x6830: 6366 case 0x6831: 6367 case 0x6838: 6368 case 0x6839: 6369 case 0x683D: 6370 si_pi->max_cu = 10; 6371 break; 6372 case 0x683B: 6373 case 0x683F: 6374 case 0x6829: 6375 si_pi->max_cu = 8; 6376 break; 6377 default: 6378 si_pi->max_cu = 0; 6379 break; 6380 } 6381 } else { 6382 si_pi->max_cu = 0; 6383 } 6384} 6385 6386static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev, 6387 struct amdgpu_clock_voltage_dependency_table *table) 6388{ 6389 u32 i; 6390 int j; 6391 u16 leakage_voltage; 6392 6393 if (table) { 6394 for (i = 0; i < table->count; i++) { 6395 switch (si_get_leakage_voltage_from_leakage_index(adev, 6396 table->entries[i].v, 6397 &leakage_voltage)) { 6398 case 0: 6399 table->entries[i].v = leakage_voltage; 6400 break; 6401 case -EAGAIN: 6402 return -EINVAL; 6403 case -EINVAL: 6404 default: 6405 break; 6406 } 6407 } 6408 6409 for (j = (table->count - 2); j >= 0; j--) { 6410 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 6411 table->entries[j].v : table->entries[j + 1].v; 6412 } 6413 } 6414 return 0; 6415} 6416 6417static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev) 6418{ 6419 int ret = 0; 6420 6421 ret = si_patch_single_dependency_table_based_on_leakage(adev, 6422 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 6423 if (ret) 6424 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n"); 6425 ret = si_patch_single_dependency_table_based_on_leakage(adev, 6426 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 6427 if (ret) 6428 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n"); 6429 ret = si_patch_single_dependency_table_based_on_leakage(adev, 6430 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 6431 if (ret) 6432 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n"); 6433 return ret; 6434} 6435 6436static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev, 6437 struct amdgpu_ps *amdgpu_new_state, 6438 struct amdgpu_ps *amdgpu_current_state) 6439{ 6440 u32 lane_width; 6441 u32 new_lane_width = 6442 ((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 6443 u32 current_lane_width = 6444 ((amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 6445 6446 if (new_lane_width != current_lane_width) { 6447 amdgpu_set_pcie_lanes(adev, new_lane_width); 6448 lane_width = amdgpu_get_pcie_lanes(adev); 6449 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 6450 } 6451} 6452 6453static void si_dpm_setup_asic(struct amdgpu_device *adev) 6454{ 6455 si_read_clock_registers(adev); 6456 si_enable_acpi_power_management(adev); 6457} 6458 6459static int si_thermal_enable_alert(struct amdgpu_device *adev, 6460 bool enable) 6461{ 6462 u32 thermal_int = RREG32(mmCG_THERMAL_INT); 6463 6464 if (enable) { 6465 PPSMC_Result result; 6466 6467 thermal_int &= ~(CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK | CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK); 6468 WREG32(mmCG_THERMAL_INT, thermal_int); 6469 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); 6470 if (result != PPSMC_Result_OK) { 6471 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 6472 return -EINVAL; 6473 } 6474 } else { 6475 thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK | CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK; 6476 WREG32(mmCG_THERMAL_INT, thermal_int); 6477 } 6478 6479 return 0; 6480} 6481 6482static int si_thermal_set_temperature_range(struct amdgpu_device *adev, 6483 int min_temp, int max_temp) 6484{ 6485 int low_temp = 0 * 1000; 6486 int high_temp = 255 * 1000; 6487 6488 if (low_temp < min_temp) 6489 low_temp = min_temp; 6490 if (high_temp > max_temp) 6491 high_temp = max_temp; 6492 if (high_temp < low_temp) { 6493 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 6494 return -EINVAL; 6495 } 6496 6497 WREG32_P(mmCG_THERMAL_INT, (high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT, ~CG_THERMAL_INT__DIG_THERM_INTH_MASK); 6498 WREG32_P(mmCG_THERMAL_INT, (low_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT, ~CG_THERMAL_INT__DIG_THERM_INTL_MASK); 6499 WREG32_P(mmCG_THERMAL_CTRL, (high_temp / 1000) << CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT, ~CG_THERMAL_CTRL__DIG_THERM_DPM_MASK); 6500 6501 adev->pm.dpm.thermal.min_temp = low_temp; 6502 adev->pm.dpm.thermal.max_temp = high_temp; 6503 6504 return 0; 6505} 6506 6507static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode) 6508{ 6509 struct si_power_info *si_pi = si_get_pi(adev); 6510 u32 tmp; 6511 6512 if (si_pi->fan_ctrl_is_in_default_mode) { 6513 tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT; 6514 si_pi->fan_ctrl_default_mode = tmp; 6515 tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK) >> CG_FDO_CTRL2__TMIN__SHIFT; 6516 si_pi->t_min = tmp; 6517 si_pi->fan_ctrl_is_in_default_mode = false; 6518 } 6519 6520 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK; 6521 tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT; 6522 WREG32(mmCG_FDO_CTRL2, tmp); 6523 6524 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK; 6525 tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT; 6526 WREG32(mmCG_FDO_CTRL2, tmp); 6527} 6528 6529static int si_thermal_setup_fan_table(struct amdgpu_device *adev) 6530{ 6531 struct si_power_info *si_pi = si_get_pi(adev); 6532 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 6533 u32 duty100; 6534 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 6535 u16 fdo_min, slope1, slope2; 6536 u32 reference_clock, tmp; 6537 int ret; 6538 u64 tmp64; 6539 6540 if (!si_pi->fan_table_start) { 6541 adev->pm.dpm.fan.ucode_fan_control = false; 6542 return 0; 6543 } 6544 6545 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT; 6546 6547 if (duty100 == 0) { 6548 adev->pm.dpm.fan.ucode_fan_control = false; 6549 return 0; 6550 } 6551 6552 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100; 6553 do_div(tmp64, 10000); 6554 fdo_min = (u16)tmp64; 6555 6556 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min; 6557 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med; 6558 6559 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min; 6560 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med; 6561 6562 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 6563 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 6564 6565 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100); 6566 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100); 6567 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100); 6568 fan_table.slope1 = cpu_to_be16(slope1); 6569 fan_table.slope2 = cpu_to_be16(slope2); 6570 fan_table.fdo_min = cpu_to_be16(fdo_min); 6571 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst); 6572 fan_table.hys_up = cpu_to_be16(1); 6573 fan_table.hys_slope = cpu_to_be16(1); 6574 fan_table.temp_resp_lim = cpu_to_be16(5); 6575 reference_clock = amdgpu_asic_get_xclk(adev); 6576 6577 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay * 6578 reference_clock) / 1600); 6579 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6580 6581 tmp = (RREG32(mmCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK) >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT; 6582 fan_table.temp_src = (uint8_t)tmp; 6583 6584 ret = amdgpu_si_copy_bytes_to_smc(adev, 6585 si_pi->fan_table_start, 6586 (u8 *)(&fan_table), 6587 sizeof(fan_table), 6588 si_pi->sram_end); 6589 6590 if (ret) { 6591 DRM_ERROR("Failed to load fan table to the SMC."); 6592 adev->pm.dpm.fan.ucode_fan_control = false; 6593 } 6594 6595 return ret; 6596} 6597 6598static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev) 6599{ 6600 struct si_power_info *si_pi = si_get_pi(adev); 6601 PPSMC_Result ret; 6602 6603 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl); 6604 if (ret == PPSMC_Result_OK) { 6605 si_pi->fan_is_controlled_by_smc = true; 6606 return 0; 6607 } else { 6608 return -EINVAL; 6609 } 6610} 6611 6612static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev) 6613{ 6614 struct si_power_info *si_pi = si_get_pi(adev); 6615 PPSMC_Result ret; 6616 6617 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl); 6618 6619 if (ret == PPSMC_Result_OK) { 6620 si_pi->fan_is_controlled_by_smc = false; 6621 return 0; 6622 } else { 6623 return -EINVAL; 6624 } 6625} 6626 6627static int si_dpm_get_fan_speed_pwm(void *handle, 6628 u32 *speed) 6629{ 6630 u32 duty, duty100; 6631 u64 tmp64; 6632 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6633 6634 if (!speed) 6635 return -EINVAL; 6636 6637 if (adev->pm.no_fan) 6638 return -ENOENT; 6639 6640 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT; 6641 duty = (RREG32(mmCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK) >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT; 6642 6643 if (duty100 == 0) 6644 return -EINVAL; 6645 6646 tmp64 = (u64)duty * 255; 6647 do_div(tmp64, duty100); 6648 *speed = min_t(u32, tmp64, 255); 6649 6650 return 0; 6651} 6652 6653static int si_dpm_set_fan_speed_pwm(void *handle, 6654 u32 speed) 6655{ 6656 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6657 struct si_power_info *si_pi = si_get_pi(adev); 6658 u32 tmp; 6659 u32 duty, duty100; 6660 u64 tmp64; 6661 6662 if (adev->pm.no_fan) 6663 return -ENOENT; 6664 6665 if (si_pi->fan_is_controlled_by_smc) 6666 return -EINVAL; 6667 6668 if (speed > 255) 6669 return -EINVAL; 6670 6671 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT; 6672 6673 if (duty100 == 0) 6674 return -EINVAL; 6675 6676 tmp64 = (u64)speed * duty100; 6677 do_div(tmp64, 255); 6678 duty = (u32)tmp64; 6679 6680 tmp = RREG32(mmCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK; 6681 tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT; 6682 WREG32(mmCG_FDO_CTRL0, tmp); 6683 6684 return 0; 6685} 6686 6687static int si_dpm_set_fan_control_mode(void *handle, u32 mode) 6688{ 6689 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6690 6691 if (mode == U32_MAX) 6692 return -EINVAL; 6693 6694 if (mode) { 6695 /* stop auto-manage */ 6696 if (adev->pm.dpm.fan.ucode_fan_control) 6697 si_fan_ctrl_stop_smc_fan_control(adev); 6698 si_fan_ctrl_set_static_mode(adev, mode); 6699 } else { 6700 /* restart auto-manage */ 6701 if (adev->pm.dpm.fan.ucode_fan_control) 6702 si_thermal_start_smc_fan_control(adev); 6703 else 6704 si_fan_ctrl_set_default_mode(adev); 6705 } 6706 6707 return 0; 6708} 6709 6710static int si_dpm_get_fan_control_mode(void *handle, u32 *fan_mode) 6711{ 6712 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6713 struct si_power_info *si_pi = si_get_pi(adev); 6714 u32 tmp; 6715 6716 if (!fan_mode) 6717 return -EINVAL; 6718 6719 if (si_pi->fan_is_controlled_by_smc) 6720 return 0; 6721 6722 tmp = RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK; 6723 *fan_mode = (tmp >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT); 6724 6725 return 0; 6726} 6727 6728#if 0 6729static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev, 6730 u32 *speed) 6731{ 6732 u32 tach_period; 6733 u32 xclk = amdgpu_asic_get_xclk(adev); 6734 6735 if (adev->pm.no_fan) 6736 return -ENOENT; 6737 6738 if (adev->pm.fan_pulses_per_revolution == 0) 6739 return -ENOENT; 6740 6741 tach_period = (RREG32(mmCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK) >> CG_TACH_STATUS__TACH_PERIOD__SHIFT; 6742 if (tach_period == 0) 6743 return -ENOENT; 6744 6745 *speed = 60 * xclk * 10000 / tach_period; 6746 6747 return 0; 6748} 6749 6750static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev, 6751 u32 speed) 6752{ 6753 u32 tach_period, tmp; 6754 u32 xclk = amdgpu_asic_get_xclk(adev); 6755 6756 if (adev->pm.no_fan) 6757 return -ENOENT; 6758 6759 if (adev->pm.fan_pulses_per_revolution == 0) 6760 return -ENOENT; 6761 6762 if ((speed < adev->pm.fan_min_rpm) || 6763 (speed > adev->pm.fan_max_rpm)) 6764 return -EINVAL; 6765 6766 if (adev->pm.dpm.fan.ucode_fan_control) 6767 si_fan_ctrl_stop_smc_fan_control(adev); 6768 6769 tach_period = 60 * xclk * 10000 / (8 * speed); 6770 tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK; 6771 tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT; 6772 WREG32(mmCG_TACH_CTRL, tmp); 6773 6774 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM); 6775 6776 return 0; 6777} 6778#endif 6779 6780static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev) 6781{ 6782 struct si_power_info *si_pi = si_get_pi(adev); 6783 u32 tmp; 6784 6785 if (!si_pi->fan_ctrl_is_in_default_mode) { 6786 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK; 6787 tmp |= si_pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT; 6788 WREG32(mmCG_FDO_CTRL2, tmp); 6789 6790 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK; 6791 tmp |= si_pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT; 6792 WREG32(mmCG_FDO_CTRL2, tmp); 6793 si_pi->fan_ctrl_is_in_default_mode = true; 6794 } 6795} 6796 6797static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev) 6798{ 6799 if (adev->pm.dpm.fan.ucode_fan_control) { 6800 si_fan_ctrl_start_smc_fan_control(adev); 6801 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC); 6802 } 6803} 6804 6805static void si_thermal_initialize(struct amdgpu_device *adev) 6806{ 6807 u32 tmp; 6808 6809 if (adev->pm.fan_pulses_per_revolution) { 6810 tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK; 6811 tmp |= (adev->pm.fan_pulses_per_revolution -1) << CG_TACH_CTRL__EDGE_PER_REV__SHIFT; 6812 WREG32(mmCG_TACH_CTRL, tmp); 6813 } 6814 6815 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK; 6816 tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT; 6817 WREG32(mmCG_FDO_CTRL2, tmp); 6818} 6819 6820static int si_thermal_start_thermal_controller(struct amdgpu_device *adev) 6821{ 6822 int ret; 6823 6824 si_thermal_initialize(adev); 6825 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6826 if (ret) 6827 return ret; 6828 ret = si_thermal_enable_alert(adev, true); 6829 if (ret) 6830 return ret; 6831 if (adev->pm.dpm.fan.ucode_fan_control) { 6832 ret = si_halt_smc(adev); 6833 if (ret) 6834 return ret; 6835 ret = si_thermal_setup_fan_table(adev); 6836 if (ret) 6837 return ret; 6838 ret = si_resume_smc(adev); 6839 if (ret) 6840 return ret; 6841 si_thermal_start_smc_fan_control(adev); 6842 } 6843 6844 return 0; 6845} 6846 6847static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev) 6848{ 6849 if (!adev->pm.no_fan) { 6850 si_fan_ctrl_set_default_mode(adev); 6851 si_fan_ctrl_stop_smc_fan_control(adev); 6852 } 6853} 6854 6855static int si_dpm_enable(struct amdgpu_device *adev) 6856{ 6857 struct rv7xx_power_info *pi = rv770_get_pi(adev); 6858 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 6859 struct si_power_info *si_pi = si_get_pi(adev); 6860 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; 6861 int ret; 6862 6863 if (amdgpu_si_is_smc_running(adev)) 6864 return -EINVAL; 6865 if (pi->voltage_control || si_pi->voltage_control_svi2) 6866 si_enable_voltage_control(adev, true); 6867 if (pi->mvdd_control) 6868 si_get_mvdd_configuration(adev); 6869 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6870 ret = si_construct_voltage_tables(adev); 6871 if (ret) { 6872 DRM_ERROR("si_construct_voltage_tables failed\n"); 6873 return ret; 6874 } 6875 } 6876 if (eg_pi->dynamic_ac_timing) { 6877 ret = si_initialize_mc_reg_table(adev); 6878 if (ret) 6879 eg_pi->dynamic_ac_timing = false; 6880 } 6881 if (pi->dynamic_ss) 6882 si_enable_spread_spectrum(adev, true); 6883 if (pi->thermal_protection) 6884 si_enable_thermal_protection(adev, true); 6885 si_setup_bsp(adev); 6886 si_program_git(adev); 6887 si_program_tp(adev); 6888 si_program_tpp(adev); 6889 si_program_sstp(adev); 6890 si_enable_display_gap(adev); 6891 si_program_vc(adev); 6892 ret = si_upload_firmware(adev); 6893 if (ret) { 6894 DRM_ERROR("si_upload_firmware failed\n"); 6895 return ret; 6896 } 6897 ret = si_process_firmware_header(adev); 6898 if (ret) { 6899 DRM_ERROR("si_process_firmware_header failed\n"); 6900 return ret; 6901 } 6902 ret = si_initial_switch_from_arb_f0_to_f1(adev); 6903 if (ret) { 6904 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6905 return ret; 6906 } 6907 ret = si_init_smc_table(adev); 6908 if (ret) { 6909 DRM_ERROR("si_init_smc_table failed\n"); 6910 return ret; 6911 } 6912 ret = si_init_smc_spll_table(adev); 6913 if (ret) { 6914 DRM_ERROR("si_init_smc_spll_table failed\n"); 6915 return ret; 6916 } 6917 ret = si_init_arb_table_index(adev); 6918 if (ret) { 6919 DRM_ERROR("si_init_arb_table_index failed\n"); 6920 return ret; 6921 } 6922 if (eg_pi->dynamic_ac_timing) { 6923 ret = si_populate_mc_reg_table(adev, boot_ps); 6924 if (ret) { 6925 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6926 return ret; 6927 } 6928 } 6929 ret = si_initialize_smc_cac_tables(adev); 6930 if (ret) { 6931 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6932 return ret; 6933 } 6934 ret = si_initialize_hardware_cac_manager(adev); 6935 if (ret) { 6936 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6937 return ret; 6938 } 6939 ret = si_initialize_smc_dte_tables(adev); 6940 if (ret) { 6941 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6942 return ret; 6943 } 6944 ret = si_populate_smc_tdp_limits(adev, boot_ps); 6945 if (ret) { 6946 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6947 return ret; 6948 } 6949 ret = si_populate_smc_tdp_limits_2(adev, boot_ps); 6950 if (ret) { 6951 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6952 return ret; 6953 } 6954 si_program_response_times(adev); 6955 si_program_ds_registers(adev); 6956 si_dpm_start_smc(adev); 6957 ret = si_notify_smc_display_change(adev, false); 6958 if (ret) { 6959 DRM_ERROR("si_notify_smc_display_change failed\n"); 6960 return ret; 6961 } 6962 si_enable_sclk_control(adev, true); 6963 si_start_dpm(adev); 6964 6965 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6966 si_thermal_start_thermal_controller(adev); 6967 6968 ni_update_current_ps(adev, boot_ps); 6969 6970 return 0; 6971} 6972 6973static int si_set_temperature_range(struct amdgpu_device *adev) 6974{ 6975 int ret; 6976 6977 ret = si_thermal_enable_alert(adev, false); 6978 if (ret) 6979 return ret; 6980 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6981 if (ret) 6982 return ret; 6983 ret = si_thermal_enable_alert(adev, true); 6984 if (ret) 6985 return ret; 6986 6987 return ret; 6988} 6989 6990static void si_dpm_disable(struct amdgpu_device *adev) 6991{ 6992 struct rv7xx_power_info *pi = rv770_get_pi(adev); 6993 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; 6994 6995 if (!amdgpu_si_is_smc_running(adev)) 6996 return; 6997 si_thermal_stop_thermal_controller(adev); 6998 si_disable_ulv(adev); 6999 si_clear_vc(adev); 7000 if (pi->thermal_protection) 7001 si_enable_thermal_protection(adev, false); 7002 si_enable_power_containment(adev, boot_ps, false); 7003 si_enable_smc_cac(adev, boot_ps, false); 7004 si_enable_spread_spectrum(adev, false); 7005 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 7006 si_stop_dpm(adev); 7007 si_reset_to_default(adev); 7008 si_dpm_stop_smc(adev); 7009 si_force_switch_to_arb_f0(adev); 7010 7011 ni_update_current_ps(adev, boot_ps); 7012} 7013 7014static int si_dpm_pre_set_power_state(void *handle) 7015{ 7016 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7017 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7018 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; 7019 struct amdgpu_ps *new_ps = &requested_ps; 7020 7021 ni_update_requested_ps(adev, new_ps); 7022 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps); 7023 7024 return 0; 7025} 7026 7027static int si_power_control_set_level(struct amdgpu_device *adev) 7028{ 7029 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps; 7030 int ret; 7031 7032 ret = si_restrict_performance_levels_before_switch(adev); 7033 if (ret) 7034 return ret; 7035 ret = si_halt_smc(adev); 7036 if (ret) 7037 return ret; 7038 ret = si_populate_smc_tdp_limits(adev, new_ps); 7039 if (ret) 7040 return ret; 7041 ret = si_populate_smc_tdp_limits_2(adev, new_ps); 7042 if (ret) 7043 return ret; 7044 ret = si_resume_smc(adev); 7045 if (ret) 7046 return ret; 7047 return si_set_sw_state(adev); 7048} 7049 7050static void si_set_vce_clock(struct amdgpu_device *adev, 7051 struct amdgpu_ps *new_rps, 7052 struct amdgpu_ps *old_rps) 7053{ 7054 if ((old_rps->evclk != new_rps->evclk) || 7055 (old_rps->ecclk != new_rps->ecclk)) { 7056 /* Turn the clocks on when encoding, off otherwise */ 7057 dev_dbg(adev->dev, "set VCE clocks: %u, %u\n", new_rps->evclk, new_rps->ecclk); 7058 7059 if (new_rps->evclk || new_rps->ecclk) { 7060 amdgpu_asic_set_vce_clocks(adev, new_rps->evclk, new_rps->ecclk); 7061 amdgpu_device_ip_set_clockgating_state( 7062 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_UNGATE); 7063 amdgpu_device_ip_set_powergating_state( 7064 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_PG_STATE_UNGATE); 7065 } else { 7066 amdgpu_device_ip_set_powergating_state( 7067 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_PG_STATE_GATE); 7068 amdgpu_device_ip_set_clockgating_state( 7069 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_GATE); 7070 amdgpu_asic_set_vce_clocks(adev, 0, 0); 7071 } 7072 } 7073} 7074 7075static int si_dpm_set_power_state(void *handle) 7076{ 7077 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7078 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7079 struct amdgpu_ps *new_ps = &eg_pi->requested_rps; 7080 struct amdgpu_ps *old_ps = &eg_pi->current_rps; 7081 int ret; 7082 7083 ret = si_disable_ulv(adev); 7084 if (ret) { 7085 DRM_ERROR("si_disable_ulv failed\n"); 7086 return ret; 7087 } 7088 ret = si_restrict_performance_levels_before_switch(adev); 7089 if (ret) { 7090 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 7091 return ret; 7092 } 7093 if (eg_pi->pcie_performance_request) 7094 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps); 7095 ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps); 7096 ret = si_enable_power_containment(adev, new_ps, false); 7097 if (ret) { 7098 DRM_ERROR("si_enable_power_containment failed\n"); 7099 return ret; 7100 } 7101 ret = si_enable_smc_cac(adev, new_ps, false); 7102 if (ret) { 7103 DRM_ERROR("si_enable_smc_cac failed\n"); 7104 return ret; 7105 } 7106 ret = si_halt_smc(adev); 7107 if (ret) { 7108 DRM_ERROR("si_halt_smc failed\n"); 7109 return ret; 7110 } 7111 ret = si_upload_sw_state(adev, new_ps); 7112 if (ret) { 7113 DRM_ERROR("si_upload_sw_state failed\n"); 7114 return ret; 7115 } 7116 ret = si_upload_smc_data(adev); 7117 if (ret) { 7118 DRM_ERROR("si_upload_smc_data failed\n"); 7119 return ret; 7120 } 7121 ret = si_upload_ulv_state(adev); 7122 if (ret) { 7123 DRM_ERROR("si_upload_ulv_state failed\n"); 7124 return ret; 7125 } 7126 if (eg_pi->dynamic_ac_timing) { 7127 ret = si_upload_mc_reg_table(adev, new_ps); 7128 if (ret) { 7129 DRM_ERROR("si_upload_mc_reg_table failed\n"); 7130 return ret; 7131 } 7132 } 7133 ret = si_program_memory_timing_parameters(adev, new_ps); 7134 if (ret) { 7135 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 7136 return ret; 7137 } 7138 si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps); 7139 7140 ret = si_resume_smc(adev); 7141 if (ret) { 7142 DRM_ERROR("si_resume_smc failed\n"); 7143 return ret; 7144 } 7145 ret = si_set_sw_state(adev); 7146 if (ret) { 7147 DRM_ERROR("si_set_sw_state failed\n"); 7148 return ret; 7149 } 7150 ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps); 7151 si_set_vce_clock(adev, new_ps, old_ps); 7152 if (eg_pi->pcie_performance_request) 7153 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps); 7154 ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps); 7155 if (ret) { 7156 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 7157 return ret; 7158 } 7159 ret = si_enable_smc_cac(adev, new_ps, true); 7160 if (ret) { 7161 DRM_ERROR("si_enable_smc_cac failed\n"); 7162 return ret; 7163 } 7164 ret = si_enable_power_containment(adev, new_ps, true); 7165 if (ret) { 7166 DRM_ERROR("si_enable_power_containment failed\n"); 7167 return ret; 7168 } 7169 7170 ret = si_power_control_set_level(adev); 7171 if (ret) { 7172 DRM_ERROR("si_power_control_set_level failed\n"); 7173 return ret; 7174 } 7175 7176 return 0; 7177} 7178 7179static void si_dpm_post_set_power_state(void *handle) 7180{ 7181 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7182 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7183 struct amdgpu_ps *new_ps = &eg_pi->requested_rps; 7184 7185 ni_update_current_ps(adev, new_ps); 7186} 7187 7188#if 0 7189void si_dpm_reset_asic(struct amdgpu_device *adev) 7190{ 7191 si_restrict_performance_levels_before_switch(adev); 7192 si_disable_ulv(adev); 7193 si_set_boot_state(adev); 7194} 7195#endif 7196 7197static void si_dpm_display_configuration_changed(void *handle) 7198{ 7199 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7200 7201 si_program_display_gap(adev); 7202} 7203 7204 7205static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev, 7206 struct amdgpu_ps *rps, 7207 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 7208 u8 table_rev) 7209{ 7210 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 7211 rps->class = le16_to_cpu(non_clock_info->usClassification); 7212 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 7213 7214 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 7215 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 7216 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 7217 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 7218 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 7219 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 7220 } else { 7221 rps->vclk = 0; 7222 rps->dclk = 0; 7223 } 7224 7225 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 7226 adev->pm.dpm.boot_ps = rps; 7227 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 7228 adev->pm.dpm.uvd_ps = rps; 7229} 7230 7231static void si_parse_pplib_clock_info(struct amdgpu_device *adev, 7232 struct amdgpu_ps *rps, int index, 7233 union pplib_clock_info *clock_info) 7234{ 7235 struct rv7xx_power_info *pi = rv770_get_pi(adev); 7236 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7237 struct si_power_info *si_pi = si_get_pi(adev); 7238 struct si_ps *ps = si_get_ps(rps); 7239 u16 leakage_voltage; 7240 struct rv7xx_pl *pl = &ps->performance_levels[index]; 7241 int ret; 7242 7243 ps->performance_level_count = index + 1; 7244 7245 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 7246 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 7247 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 7248 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 7249 7250 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 7251 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 7252 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 7253 pl->pcie_gen = si_gen_pcie_gen_support(adev, 7254 si_pi->sys_pcie_mask, 7255 si_pi->boot_pcie_gen, 7256 clock_info->si.ucPCIEGen); 7257 7258 /* patch up vddc if necessary */ 7259 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc, 7260 &leakage_voltage); 7261 if (ret == 0) 7262 pl->vddc = leakage_voltage; 7263 7264 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 7265 pi->acpi_vddc = pl->vddc; 7266 eg_pi->acpi_vddci = pl->vddci; 7267 si_pi->acpi_pcie_gen = pl->pcie_gen; 7268 } 7269 7270 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 7271 index == 0) { 7272 /* XXX disable for A0 tahiti */ 7273 si_pi->ulv.supported = false; 7274 si_pi->ulv.pl = *pl; 7275 si_pi->ulv.one_pcie_lane_in_ulv = false; 7276 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 7277 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 7278 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 7279 } 7280 7281 if (pi->min_vddc_in_table > pl->vddc) 7282 pi->min_vddc_in_table = pl->vddc; 7283 7284 if (pi->max_vddc_in_table < pl->vddc) 7285 pi->max_vddc_in_table = pl->vddc; 7286 7287 /* patch up boot state */ 7288 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 7289 u16 vddc, vddci, mvdd; 7290 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd); 7291 pl->mclk = adev->clock.default_mclk; 7292 pl->sclk = adev->clock.default_sclk; 7293 pl->vddc = vddc; 7294 pl->vddci = vddci; 7295 si_pi->mvdd_bootup_value = mvdd; 7296 } 7297 7298 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 7299 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 7300 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 7301 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 7302 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 7303 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 7304 } 7305} 7306 7307union pplib_power_state { 7308 struct _ATOM_PPLIB_STATE v1; 7309 struct _ATOM_PPLIB_STATE_V2 v2; 7310}; 7311 7312static int si_parse_power_table(struct amdgpu_device *adev) 7313{ 7314 struct amdgpu_mode_info *mode_info = &adev->mode_info; 7315 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 7316 union pplib_power_state *power_state; 7317 int i, j, k, non_clock_array_index, clock_array_index; 7318 union pplib_clock_info *clock_info; 7319 struct _StateArray *state_array; 7320 struct _ClockInfoArray *clock_info_array; 7321 struct _NonClockInfoArray *non_clock_info_array; 7322 union power_info *power_info; 7323 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 7324 u16 data_offset; 7325 u8 frev, crev; 7326 u8 *power_state_offset; 7327 struct si_ps *ps; 7328 7329 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 7330 &frev, &crev, &data_offset)) 7331 return -EINVAL; 7332 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 7333 7334 amdgpu_add_thermal_controller(adev); 7335 7336 state_array = (struct _StateArray *) 7337 (mode_info->atom_context->bios + data_offset + 7338 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 7339 clock_info_array = (struct _ClockInfoArray *) 7340 (mode_info->atom_context->bios + data_offset + 7341 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 7342 non_clock_info_array = (struct _NonClockInfoArray *) 7343 (mode_info->atom_context->bios + data_offset + 7344 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 7345 7346 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, 7347 sizeof(struct amdgpu_ps), 7348 GFP_KERNEL); 7349 if (!adev->pm.dpm.ps) 7350 return -ENOMEM; 7351 power_state_offset = (u8 *)state_array->states; 7352 for (adev->pm.dpm.num_ps = 0, i = 0; i < state_array->ucNumEntries; i++) { 7353 u8 *idx; 7354 power_state = (union pplib_power_state *)power_state_offset; 7355 non_clock_array_index = power_state->v2.nonClockInfoIndex; 7356 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 7357 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 7358 ps = kzalloc(sizeof(struct si_ps), GFP_KERNEL); 7359 if (ps == NULL) 7360 return -ENOMEM; 7361 adev->pm.dpm.ps[i].ps_priv = ps; 7362 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], 7363 non_clock_info, 7364 non_clock_info_array->ucEntrySize); 7365 k = 0; 7366 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 7367 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 7368 clock_array_index = idx[j]; 7369 if (clock_array_index >= clock_info_array->ucNumEntries) 7370 continue; 7371 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 7372 break; 7373 clock_info = (union pplib_clock_info *) 7374 ((u8 *)&clock_info_array->clockInfo[0] + 7375 (clock_array_index * clock_info_array->ucEntrySize)); 7376 si_parse_pplib_clock_info(adev, 7377 &adev->pm.dpm.ps[i], k, 7378 clock_info); 7379 k++; 7380 } 7381 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 7382 adev->pm.dpm.num_ps++; 7383 } 7384 7385 /* fill in the vce power states */ 7386 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { 7387 u32 sclk, mclk; 7388 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; 7389 clock_info = (union pplib_clock_info *) 7390 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 7391 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 7392 sclk |= clock_info->si.ucEngineClockHigh << 16; 7393 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 7394 mclk |= clock_info->si.ucMemoryClockHigh << 16; 7395 adev->pm.dpm.vce_states[i].sclk = sclk; 7396 adev->pm.dpm.vce_states[i].mclk = mclk; 7397 } 7398 7399 return 0; 7400} 7401 7402static int si_dpm_init(struct amdgpu_device *adev) 7403{ 7404 struct rv7xx_power_info *pi; 7405 struct evergreen_power_info *eg_pi; 7406 struct ni_power_info *ni_pi; 7407 struct si_power_info *si_pi; 7408 struct atom_clock_dividers dividers; 7409 int ret; 7410 7411 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 7412 if (si_pi == NULL) 7413 return -ENOMEM; 7414 adev->pm.dpm.priv = si_pi; 7415 ni_pi = &si_pi->ni; 7416 eg_pi = &ni_pi->eg; 7417 pi = &eg_pi->rv7xx; 7418 7419 si_pi->sys_pcie_mask = 7420 adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK; 7421 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID; 7422 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev); 7423 7424 si_set_max_cu_value(adev); 7425 7426 rv770_get_max_vddc(adev); 7427 si_get_leakage_vddc(adev); 7428 si_patch_dependency_tables_based_on_leakage(adev); 7429 7430 pi->acpi_vddc = 0; 7431 eg_pi->acpi_vddci = 0; 7432 pi->min_vddc_in_table = 0; 7433 pi->max_vddc_in_table = 0; 7434 7435 ret = amdgpu_get_platform_caps(adev); 7436 if (ret) 7437 return ret; 7438 7439 ret = amdgpu_parse_extended_power_table(adev); 7440 if (ret) 7441 return ret; 7442 7443 ret = si_parse_power_table(adev); 7444 if (ret) 7445 return ret; 7446 7447 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 7448 kcalloc(4, 7449 sizeof(struct amdgpu_clock_voltage_dependency_entry), 7450 GFP_KERNEL); 7451 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) 7452 return -ENOMEM; 7453 7454 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 7455 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 7456 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 7457 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 7458 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 7459 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 7460 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 7461 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 7462 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 7463 7464 if (adev->pm.dpm.voltage_response_time == 0) 7465 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 7466 if (adev->pm.dpm.backbias_response_time == 0) 7467 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 7468 7469 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 7470 0, false, ÷rs); 7471 if (ret) 7472 pi->ref_div = dividers.ref_div + 1; 7473 else 7474 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 7475 7476 eg_pi->smu_uvd_hs = false; 7477 7478 pi->mclk_strobe_mode_threshold = 40000; 7479 if (si_is_special_1gb_platform(adev)) 7480 pi->mclk_stutter_mode_threshold = 0; 7481 else 7482 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 7483 pi->mclk_edc_enable_threshold = 40000; 7484 eg_pi->mclk_edc_wr_enable_threshold = 40000; 7485 7486 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 7487 7488 pi->voltage_control = 7489 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7490 VOLTAGE_OBJ_GPIO_LUT); 7491 if (!pi->voltage_control) { 7492 si_pi->voltage_control_svi2 = 7493 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7494 VOLTAGE_OBJ_SVID2); 7495 if (si_pi->voltage_control_svi2) 7496 amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7497 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 7498 } 7499 7500 pi->mvdd_control = 7501 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 7502 VOLTAGE_OBJ_GPIO_LUT); 7503 7504 eg_pi->vddci_control = 7505 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7506 VOLTAGE_OBJ_GPIO_LUT); 7507 if (!eg_pi->vddci_control) 7508 si_pi->vddci_control_svi2 = 7509 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7510 VOLTAGE_OBJ_SVID2); 7511 7512 si_pi->vddc_phase_shed_control = 7513 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7514 VOLTAGE_OBJ_PHASE_LUT); 7515 7516 rv770_get_engine_memory_ss(adev); 7517 7518 pi->asi = RV770_ASI_DFLT; 7519 pi->pasi = CYPRESS_HASI_DFLT; 7520 pi->vrc = SISLANDS_VRC_DFLT; 7521 7522 eg_pi->sclk_deep_sleep = true; 7523 si_pi->sclk_deep_sleep_above_low = false; 7524 7525 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE) 7526 pi->thermal_protection = true; 7527 else 7528 pi->thermal_protection = false; 7529 7530 eg_pi->dynamic_ac_timing = true; 7531 7532#if defined(CONFIG_ACPI) 7533 eg_pi->pcie_performance_request = 7534 amdgpu_acpi_is_pcie_performance_request_supported(adev); 7535#else 7536 eg_pi->pcie_performance_request = false; 7537#endif 7538 7539 si_pi->sram_end = SMC_RAM_END; 7540 7541 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 7542 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 7543 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 7544 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 7545 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 7546 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 7547 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 7548 7549 si_initialize_powertune_defaults(adev); 7550 7551 /* make sure dc limits are valid */ 7552 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 7553 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 7554 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 7555 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 7556 7557 si_pi->fan_ctrl_is_in_default_mode = true; 7558 7559 return 0; 7560} 7561 7562static void si_dpm_fini(struct amdgpu_device *adev) 7563{ 7564 int i; 7565 7566 if (adev->pm.dpm.ps) 7567 for (i = 0; i < adev->pm.dpm.num_ps; i++) 7568 kfree(adev->pm.dpm.ps[i].ps_priv); 7569 kfree(adev->pm.dpm.ps); 7570 kfree(adev->pm.dpm.priv); 7571 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 7572 amdgpu_free_extended_power_table(adev); 7573} 7574 7575static void si_dpm_debugfs_print_current_performance_level(void *handle, 7576 struct seq_file *m) 7577{ 7578 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7579 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7580 struct amdgpu_ps *rps = &eg_pi->current_rps; 7581 struct si_ps *ps = si_get_ps(rps); 7582 struct rv7xx_pl *pl; 7583 u32 current_index = 7584 (RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >> 7585 TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX__SHIFT; 7586 7587 if (current_index >= ps->performance_level_count) { 7588 seq_printf(m, "invalid dpm profile %d\n", current_index); 7589 } else { 7590 pl = &ps->performance_levels[current_index]; 7591 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7592 seq_printf(m, "vce evclk: %d ecclk: %d\n", rps->evclk, rps->ecclk); 7593 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7594 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7595 } 7596} 7597 7598static int si_dpm_set_interrupt_state(struct amdgpu_device *adev, 7599 struct amdgpu_irq_src *source, 7600 unsigned type, 7601 enum amdgpu_interrupt_state state) 7602{ 7603 u32 cg_thermal_int; 7604 7605 switch (type) { 7606 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH: 7607 switch (state) { 7608 case AMDGPU_IRQ_STATE_DISABLE: 7609 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); 7610 cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK; 7611 WREG32(mmCG_THERMAL_INT, cg_thermal_int); 7612 break; 7613 case AMDGPU_IRQ_STATE_ENABLE: 7614 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); 7615 cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK; 7616 WREG32(mmCG_THERMAL_INT, cg_thermal_int); 7617 break; 7618 default: 7619 break; 7620 } 7621 break; 7622 7623 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW: 7624 switch (state) { 7625 case AMDGPU_IRQ_STATE_DISABLE: 7626 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); 7627 cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK; 7628 WREG32(mmCG_THERMAL_INT, cg_thermal_int); 7629 break; 7630 case AMDGPU_IRQ_STATE_ENABLE: 7631 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); 7632 cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK; 7633 WREG32(mmCG_THERMAL_INT, cg_thermal_int); 7634 break; 7635 default: 7636 break; 7637 } 7638 break; 7639 7640 default: 7641 break; 7642 } 7643 return 0; 7644} 7645 7646static int si_dpm_process_interrupt(struct amdgpu_device *adev, 7647 struct amdgpu_irq_src *source, 7648 struct amdgpu_iv_entry *entry) 7649{ 7650 bool queue_thermal = false; 7651 7652 if (entry == NULL) 7653 return -EINVAL; 7654 7655 switch (entry->src_id) { 7656 case 230: /* thermal low to high */ 7657 DRM_DEBUG("IH: thermal low to high\n"); 7658 adev->pm.dpm.thermal.high_to_low = false; 7659 queue_thermal = true; 7660 break; 7661 case 231: /* thermal high to low */ 7662 DRM_DEBUG("IH: thermal high to low\n"); 7663 adev->pm.dpm.thermal.high_to_low = true; 7664 queue_thermal = true; 7665 break; 7666 default: 7667 break; 7668 } 7669 7670 if (queue_thermal) 7671 schedule_work(&adev->pm.dpm.thermal.work); 7672 7673 return 0; 7674} 7675 7676static int si_dpm_late_init(struct amdgpu_ip_block *ip_block) 7677{ 7678 int ret; 7679 struct amdgpu_device *adev = ip_block->adev; 7680 7681 if (!adev->pm.dpm_enabled) 7682 return 0; 7683 7684 ret = si_set_temperature_range(adev); 7685 if (ret) 7686 return ret; 7687#if 0 //TODO ? 7688 si_dpm_powergate_uvd(adev, true); 7689#endif 7690 return 0; 7691} 7692 7693/** 7694 * si_dpm_init_microcode - load ucode images from disk 7695 * 7696 * @adev: amdgpu_device pointer 7697 * 7698 * Use the firmware interface to load the ucode images into 7699 * the driver (not loaded into hw). 7700 * Returns 0 on success, error on failure. 7701 */ 7702static int si_dpm_init_microcode(struct amdgpu_device *adev) 7703{ 7704 const char *chip_name; 7705 int err; 7706 7707 DRM_DEBUG("\n"); 7708 switch (adev->asic_type) { 7709 case CHIP_TAHITI: 7710 chip_name = "tahiti"; 7711 break; 7712 case CHIP_PITCAIRN: 7713 if ((adev->pdev->revision == 0x81) && 7714 ((adev->pdev->device == 0x6810) || 7715 (adev->pdev->device == 0x6811))) 7716 chip_name = "pitcairn_k"; 7717 else 7718 chip_name = "pitcairn"; 7719 break; 7720 case CHIP_VERDE: 7721 if (((adev->pdev->device == 0x6820) && 7722 ((adev->pdev->revision == 0x81) || 7723 (adev->pdev->revision == 0x83))) || 7724 ((adev->pdev->device == 0x6821) && 7725 ((adev->pdev->revision == 0x83) || 7726 (adev->pdev->revision == 0x87))) || 7727 ((adev->pdev->revision == 0x87) && 7728 ((adev->pdev->device == 0x6823) || 7729 (adev->pdev->device == 0x682b)))) 7730 chip_name = "verde_k"; 7731 else 7732 chip_name = "verde"; 7733 break; 7734 case CHIP_OLAND: 7735 if (((adev->pdev->revision == 0x81) && 7736 ((adev->pdev->device == 0x6600) || 7737 (adev->pdev->device == 0x6604) || 7738 (adev->pdev->device == 0x6605) || 7739 (adev->pdev->device == 0x6610))) || 7740 ((adev->pdev->revision == 0x83) && 7741 (adev->pdev->device == 0x6610))) 7742 chip_name = "oland_k"; 7743 else 7744 chip_name = "oland"; 7745 break; 7746 case CHIP_HAINAN: 7747 if (((adev->pdev->revision == 0x81) && 7748 (adev->pdev->device == 0x6660)) || 7749 ((adev->pdev->revision == 0x83) && 7750 ((adev->pdev->device == 0x6660) || 7751 (adev->pdev->device == 0x6663) || 7752 (adev->pdev->device == 0x6665) || 7753 (adev->pdev->device == 0x6667)))) 7754 chip_name = "hainan_k"; 7755 else if ((adev->pdev->revision == 0xc3) && 7756 (adev->pdev->device == 0x6665)) 7757 chip_name = "banks_k_2"; 7758 else 7759 chip_name = "hainan"; 7760 break; 7761 default: BUG(); 7762 } 7763 7764 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED, 7765 "amdgpu/%s_smc.bin", chip_name); 7766 if (err) { 7767 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s_smc.bin\"\n", 7768 err, chip_name); 7769 amdgpu_ucode_release(&adev->pm.fw); 7770 } 7771 return err; 7772} 7773 7774static int si_dpm_sw_init(struct amdgpu_ip_block *ip_block) 7775{ 7776 int ret; 7777 struct amdgpu_device *adev = ip_block->adev; 7778 7779 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq); 7780 if (ret) 7781 return ret; 7782 7783 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq); 7784 if (ret) 7785 return ret; 7786 7787 /* default to balanced state */ 7788 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; 7789 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 7790 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO; 7791 adev->pm.default_sclk = adev->clock.default_sclk; 7792 adev->pm.default_mclk = adev->clock.default_mclk; 7793 adev->pm.current_sclk = adev->clock.default_sclk; 7794 adev->pm.current_mclk = adev->clock.default_mclk; 7795 adev->pm.int_thermal_type = THERMAL_TYPE_NONE; 7796 7797 if (amdgpu_dpm == 0) 7798 return 0; 7799 7800 ret = si_dpm_init_microcode(adev); 7801 if (ret) 7802 return ret; 7803 7804 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); 7805 ret = si_dpm_init(adev); 7806 if (ret) 7807 goto dpm_failed; 7808 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 7809 if (amdgpu_dpm == 1) 7810 amdgpu_pm_print_power_states(adev); 7811 DRM_INFO("amdgpu: dpm initialized\n"); 7812 7813 return 0; 7814 7815dpm_failed: 7816 si_dpm_fini(adev); 7817 DRM_ERROR("amdgpu: dpm initialization failed\n"); 7818 return ret; 7819} 7820 7821static int si_dpm_sw_fini(struct amdgpu_ip_block *ip_block) 7822{ 7823 struct amdgpu_device *adev = ip_block->adev; 7824 7825 flush_work(&adev->pm.dpm.thermal.work); 7826 7827 si_dpm_fini(adev); 7828 7829 return 0; 7830} 7831 7832static int si_dpm_hw_init(struct amdgpu_ip_block *ip_block) 7833{ 7834 int ret; 7835 7836 struct amdgpu_device *adev = ip_block->adev; 7837 7838 if (!amdgpu_dpm) 7839 return 0; 7840 7841 mutex_lock(&adev->pm.mutex); 7842 si_dpm_setup_asic(adev); 7843 ret = si_dpm_enable(adev); 7844 if (ret) 7845 adev->pm.dpm_enabled = false; 7846 else 7847 adev->pm.dpm_enabled = true; 7848 amdgpu_legacy_dpm_compute_clocks(adev); 7849 mutex_unlock(&adev->pm.mutex); 7850 return ret; 7851} 7852 7853static int si_dpm_hw_fini(struct amdgpu_ip_block *ip_block) 7854{ 7855 struct amdgpu_device *adev = ip_block->adev; 7856 7857 if (adev->pm.dpm_enabled) 7858 si_dpm_disable(adev); 7859 7860 return 0; 7861} 7862 7863static int si_dpm_suspend(struct amdgpu_ip_block *ip_block) 7864{ 7865 struct amdgpu_device *adev = ip_block->adev; 7866 7867 cancel_work_sync(&adev->pm.dpm.thermal.work); 7868 7869 if (adev->pm.dpm_enabled) { 7870 mutex_lock(&adev->pm.mutex); 7871 adev->pm.dpm_enabled = false; 7872 /* disable dpm */ 7873 si_dpm_disable(adev); 7874 /* reset the power state */ 7875 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 7876 mutex_unlock(&adev->pm.mutex); 7877 } 7878 7879 return 0; 7880} 7881 7882static int si_dpm_resume(struct amdgpu_ip_block *ip_block) 7883{ 7884 int ret = 0; 7885 struct amdgpu_device *adev = ip_block->adev; 7886 7887 if (!amdgpu_dpm) 7888 return 0; 7889 7890 if (!adev->pm.dpm_enabled) { 7891 /* asic init will reset to the boot state */ 7892 mutex_lock(&adev->pm.mutex); 7893 si_dpm_setup_asic(adev); 7894 ret = si_dpm_enable(adev); 7895 if (ret) { 7896 adev->pm.dpm_enabled = false; 7897 } else { 7898 adev->pm.dpm_enabled = true; 7899 amdgpu_legacy_dpm_compute_clocks(adev); 7900 } 7901 mutex_unlock(&adev->pm.mutex); 7902 } 7903 7904 return ret; 7905} 7906 7907static bool si_dpm_is_idle(struct amdgpu_ip_block *ip_block) 7908{ 7909 /* XXX */ 7910 return true; 7911} 7912 7913static int si_dpm_wait_for_idle(struct amdgpu_ip_block *ip_block) 7914{ 7915 /* XXX */ 7916 return 0; 7917} 7918 7919static int si_dpm_set_clockgating_state(struct amdgpu_ip_block *ip_block, 7920 enum amd_clockgating_state state) 7921{ 7922 return 0; 7923} 7924 7925static int si_dpm_set_powergating_state(struct amdgpu_ip_block *ip_block, 7926 enum amd_powergating_state state) 7927{ 7928 return 0; 7929} 7930 7931/* get temperature in millidegrees */ 7932static int si_dpm_get_temp(void *handle) 7933{ 7934 u32 temp; 7935 int actual_temp = 0; 7936 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7937 7938 temp = (RREG32(mmCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >> 7939 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT; 7940 7941 if (temp & 0x200) 7942 actual_temp = 255; 7943 else 7944 actual_temp = temp & 0x1ff; 7945 7946 actual_temp = (actual_temp * 1000); 7947 7948 return actual_temp; 7949} 7950 7951static u32 si_dpm_get_sclk(void *handle, bool low) 7952{ 7953 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7954 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7955 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); 7956 7957 if (low) 7958 return requested_state->performance_levels[0].sclk; 7959 else 7960 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; 7961} 7962 7963static u32 si_dpm_get_mclk(void *handle, bool low) 7964{ 7965 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7966 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7967 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); 7968 7969 if (low) 7970 return requested_state->performance_levels[0].mclk; 7971 else 7972 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; 7973} 7974 7975static void si_dpm_print_power_state(void *handle, 7976 void *current_ps) 7977{ 7978 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7979 struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps; 7980 struct si_ps *ps = si_get_ps(rps); 7981 struct rv7xx_pl *pl; 7982 int i; 7983 7984 amdgpu_dpm_dbg_print_class_info(adev, rps->class, rps->class2); 7985 amdgpu_dpm_dbg_print_cap_info(adev, rps->caps); 7986 drm_dbg(adev_to_drm(adev), "\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7987 drm_dbg(adev_to_drm(adev), "\tvce evclk: %d ecclk: %d\n", rps->evclk, rps->ecclk); 7988 for (i = 0; i < ps->performance_level_count; i++) { 7989 pl = &ps->performance_levels[i]; 7990 drm_dbg(adev_to_drm(adev), "\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7991 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7992 } 7993 amdgpu_dpm_dbg_print_ps_status(adev, rps); 7994} 7995 7996static int si_dpm_early_init(struct amdgpu_ip_block *ip_block) 7997{ 7998 7999 struct amdgpu_device *adev = ip_block->adev; 8000 8001 adev->powerplay.pp_funcs = &si_dpm_funcs; 8002 adev->powerplay.pp_handle = adev; 8003 si_dpm_set_irq_funcs(adev); 8004 return 0; 8005} 8006 8007static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1, 8008 const struct rv7xx_pl *si_cpl2) 8009{ 8010 return ((si_cpl1->mclk == si_cpl2->mclk) && 8011 (si_cpl1->sclk == si_cpl2->sclk) && 8012 (si_cpl1->pcie_gen == si_cpl2->pcie_gen) && 8013 (si_cpl1->vddc == si_cpl2->vddc) && 8014 (si_cpl1->vddci == si_cpl2->vddci)); 8015} 8016 8017static int si_check_state_equal(void *handle, 8018 void *current_ps, 8019 void *request_ps, 8020 bool *equal) 8021{ 8022 struct si_ps *si_cps; 8023 struct si_ps *si_rps; 8024 int i; 8025 struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps; 8026 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; 8027 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8028 8029 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) 8030 return -EINVAL; 8031 8032 si_cps = si_get_ps((struct amdgpu_ps *)cps); 8033 si_rps = si_get_ps((struct amdgpu_ps *)rps); 8034 8035 if (si_cps == NULL) { 8036 printk("si_cps is NULL\n"); 8037 *equal = false; 8038 return 0; 8039 } 8040 8041 if (si_cps->performance_level_count != si_rps->performance_level_count) { 8042 *equal = false; 8043 return 0; 8044 } 8045 8046 for (i = 0; i < si_cps->performance_level_count; i++) { 8047 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]), 8048 &(si_rps->performance_levels[i]))) { 8049 *equal = false; 8050 return 0; 8051 } 8052 } 8053 8054 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ 8055 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); 8056 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); 8057 8058 return 0; 8059} 8060 8061static int si_dpm_read_sensor(void *handle, int idx, 8062 void *value, int *size) 8063{ 8064 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8065 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 8066 struct amdgpu_ps *rps = &eg_pi->current_rps; 8067 struct si_ps *ps = si_get_ps(rps); 8068 uint32_t sclk, mclk; 8069 u32 pl_index = 8070 (RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >> 8071 TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX__SHIFT; 8072 8073 /* size must be at least 4 bytes for all sensors */ 8074 if (*size < 4) 8075 return -EINVAL; 8076 8077 switch (idx) { 8078 case AMDGPU_PP_SENSOR_GFX_SCLK: 8079 if (pl_index < ps->performance_level_count) { 8080 sclk = ps->performance_levels[pl_index].sclk; 8081 *((uint32_t *)value) = sclk; 8082 *size = 4; 8083 return 0; 8084 } 8085 return -EINVAL; 8086 case AMDGPU_PP_SENSOR_GFX_MCLK: 8087 if (pl_index < ps->performance_level_count) { 8088 mclk = ps->performance_levels[pl_index].mclk; 8089 *((uint32_t *)value) = mclk; 8090 *size = 4; 8091 return 0; 8092 } 8093 return -EINVAL; 8094 case AMDGPU_PP_SENSOR_GPU_TEMP: 8095 *((uint32_t *)value) = si_dpm_get_temp(adev); 8096 *size = 4; 8097 return 0; 8098 default: 8099 return -EOPNOTSUPP; 8100 } 8101} 8102 8103static const struct amd_ip_funcs si_dpm_ip_funcs = { 8104 .name = "si_dpm", 8105 .early_init = si_dpm_early_init, 8106 .late_init = si_dpm_late_init, 8107 .sw_init = si_dpm_sw_init, 8108 .sw_fini = si_dpm_sw_fini, 8109 .hw_init = si_dpm_hw_init, 8110 .hw_fini = si_dpm_hw_fini, 8111 .suspend = si_dpm_suspend, 8112 .resume = si_dpm_resume, 8113 .is_idle = si_dpm_is_idle, 8114 .wait_for_idle = si_dpm_wait_for_idle, 8115 .set_clockgating_state = si_dpm_set_clockgating_state, 8116 .set_powergating_state = si_dpm_set_powergating_state, 8117}; 8118 8119const struct amdgpu_ip_block_version si_smu_ip_block = 8120{ 8121 .type = AMD_IP_BLOCK_TYPE_SMC, 8122 .major = 6, 8123 .minor = 0, 8124 .rev = 0, 8125 .funcs = &si_dpm_ip_funcs, 8126}; 8127 8128static const struct amd_pm_funcs si_dpm_funcs = { 8129 .pre_set_power_state = &si_dpm_pre_set_power_state, 8130 .set_power_state = &si_dpm_set_power_state, 8131 .post_set_power_state = &si_dpm_post_set_power_state, 8132 .display_configuration_changed = &si_dpm_display_configuration_changed, 8133 .get_sclk = &si_dpm_get_sclk, 8134 .get_mclk = &si_dpm_get_mclk, 8135 .print_power_state = &si_dpm_print_power_state, 8136 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 8137 .force_performance_level = &si_dpm_force_performance_level, 8138 .vblank_too_short = &si_dpm_vblank_too_short, 8139 .set_fan_control_mode = &si_dpm_set_fan_control_mode, 8140 .get_fan_control_mode = &si_dpm_get_fan_control_mode, 8141 .set_fan_speed_pwm = &si_dpm_set_fan_speed_pwm, 8142 .get_fan_speed_pwm = &si_dpm_get_fan_speed_pwm, 8143 .check_state_equal = &si_check_state_equal, 8144 .get_vce_clock_state = amdgpu_get_vce_clock_state, 8145 .read_sensor = &si_dpm_read_sensor, 8146 .pm_compute_clocks = amdgpu_legacy_dpm_compute_clocks, 8147}; 8148 8149static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = { 8150 .set = si_dpm_set_interrupt_state, 8151 .process = si_dpm_process_interrupt, 8152}; 8153 8154static void si_dpm_set_irq_funcs(struct amdgpu_device *adev) 8155{ 8156 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; 8157 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs; 8158} 8159
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