amdgpu_dpm_internal.c

 1/*
 2 * Copyright 2021 Advanced Micro Devices, Inc.
 3 *
 4 * Permission is hereby granted, free of charge, to any person obtaining a
 5 * copy of this software and associated documentation files (the "Software"),
 6 * to deal in the Software without restriction, including without limitation
 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 8 * and/or sell copies of the Software, and to permit persons to whom the
 9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "amdgpu.h"
25#include "amdgpu_display.h"
26#include "hwmgr.h"
27#include "amdgpu_smu.h"
28#include "amdgpu_dpm_internal.h"
29
30void amdgpu_dpm_get_display_cfg(struct amdgpu_device *adev)
31{
32	struct drm_device *ddev = adev_to_drm(adev);
33	struct amd_pp_display_configuration *cfg = &adev->pm.pm_display_cfg;
34	struct single_display_configuration *display_cfg;
35	struct drm_crtc *crtc;
36	struct amdgpu_crtc *amdgpu_crtc;
37	struct amdgpu_connector *conn;
38	int num_crtcs = 0;
39	int vrefresh;
40	u32 vblank_in_pixels, vblank_time_us;
41
42	cfg->min_vblank_time = 0xffffffff; /* if the displays are off, vblank time is max */
43
44	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
45		list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
46			amdgpu_crtc = to_amdgpu_crtc(crtc);
47
48			/* The array should only contain active displays. */
49			if (!amdgpu_crtc->enabled)
50				continue;
51
52			conn = to_amdgpu_connector(amdgpu_crtc->connector);
53			display_cfg = &adev->pm.pm_display_cfg.displays[num_crtcs++];
54
55			if (amdgpu_crtc->hw_mode.clock) {
56				vrefresh = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
57
58				vblank_in_pixels =
59					amdgpu_crtc->hw_mode.crtc_htotal *
60					(amdgpu_crtc->hw_mode.crtc_vblank_end -
61					amdgpu_crtc->hw_mode.crtc_vdisplay +
62					(amdgpu_crtc->v_border * 2));
63
64				vblank_time_us =
65					vblank_in_pixels * 1000 / amdgpu_crtc->hw_mode.clock;
66
67				/* The legacy (non-DC) code has issues with mclk switching
68				 * with refresh rates over 120 Hz. Disable mclk switching.
69				 */
70				if (vrefresh > 120)
71					vblank_time_us = 0;
72
73				/* Find minimum vblank time. */
74				if (vblank_time_us < cfg->min_vblank_time)
75					cfg->min_vblank_time = vblank_time_us;
76
77				/* Find vertical refresh rate of first active display. */
78				if (!cfg->vrefresh)
79					cfg->vrefresh = vrefresh;
80			}
81
82			if (amdgpu_crtc->crtc_id < cfg->crtc_index) {
83				/* Find first active CRTC and its line time. */
84				cfg->crtc_index = amdgpu_crtc->crtc_id;
85				cfg->line_time_in_us = amdgpu_crtc->line_time;
86			}
87
88			display_cfg->controller_id = amdgpu_crtc->crtc_id;
89			display_cfg->pixel_clock = conn->pixelclock_for_modeset;
90		}
91	}
92
93	cfg->display_clk = adev->clock.default_dispclk;
94	cfg->num_display = num_crtcs;
95}