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mes_v11_api_def.h
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linux-6.19.14/drivers/gpu/drm/amd/include/mes_v11_api_def.h
1/* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef __MES_API_DEF_H__ 25#define __MES_API_DEF_H__ 26 27#pragma pack(push, 4) 28 29#define MES_API_VERSION 1 30 31/* Maximum log buffer size for MES. Needs to be updated if MES expands MES_EVT_INTR_HIST_LOG */ 32#define AMDGPU_MES_LOG_BUFFER_SIZE 0x4000 33 34/* Driver submits one API(cmd) as a single Frame and this command size is same 35 * for all API to ease the debugging and parsing of ring buffer. 36 */ 37enum { API_FRAME_SIZE_IN_DWORDS = 64 }; 38 39/* To avoid command in scheduler context to be overwritten whenenver mutilple 40 * interrupts come in, this creates another queue. 41 */ 42enum { API_NUMBER_OF_COMMAND_MAX = 32 }; 43 44enum MES_API_TYPE { 45 MES_API_TYPE_SCHEDULER = 1, 46 MES_API_TYPE_MAX 47}; 48 49enum MES_SCH_API_OPCODE { 50 MES_SCH_API_SET_HW_RSRC = 0, 51 MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */ 52 MES_SCH_API_ADD_QUEUE = 2, 53 MES_SCH_API_REMOVE_QUEUE = 3, 54 MES_SCH_API_PERFORM_YIELD = 4, 55 MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5, 56 MES_SCH_API_SUSPEND = 6, 57 MES_SCH_API_RESUME = 7, 58 MES_SCH_API_RESET = 8, 59 MES_SCH_API_SET_LOG_BUFFER = 9, 60 MES_SCH_API_CHANGE_GANG_PRORITY = 10, 61 MES_SCH_API_QUERY_SCHEDULER_STATUS = 11, 62 MES_SCH_API_PROGRAM_GDS = 12, 63 MES_SCH_API_SET_DEBUG_VMID = 13, 64 MES_SCH_API_MISC = 14, 65 MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15, 66 MES_SCH_API_AMD_LOG = 16, 67 MES_SCH_API_SET_HW_RSRC_1 = 19, 68 MES_SCH_API_MAX = 0xFF 69}; 70 71union MES_API_HEADER { 72 struct { 73 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */ 74 uint32_t opcode : 8; 75 uint32_t dwsize : 8; /* including header */ 76 uint32_t reserved : 12; 77 }; 78 79 uint32_t u32All; 80}; 81 82enum MES_AMD_PRIORITY_LEVEL { 83 AMD_PRIORITY_LEVEL_LOW = 0, 84 AMD_PRIORITY_LEVEL_NORMAL = 1, 85 AMD_PRIORITY_LEVEL_MEDIUM = 2, 86 AMD_PRIORITY_LEVEL_HIGH = 3, 87 AMD_PRIORITY_LEVEL_REALTIME = 4, 88 AMD_PRIORITY_NUM_LEVELS 89}; 90 91enum MES_QUEUE_TYPE { 92 MES_QUEUE_TYPE_GFX, 93 MES_QUEUE_TYPE_COMPUTE, 94 MES_QUEUE_TYPE_SDMA, 95 MES_QUEUE_TYPE_MAX, 96}; 97 98struct MES_API_STATUS { 99 uint64_t api_completion_fence_addr; 100 uint64_t api_completion_fence_value; 101}; 102 103enum { MAX_COMPUTE_PIPES = 8 }; 104enum { MAX_GFX_PIPES = 2 }; 105enum { MAX_SDMA_PIPES = 2 }; 106 107enum { MAX_COMPUTE_HQD_PER_PIPE = 8 }; 108enum { MAX_GFX_HQD_PER_PIPE = 8 }; 109enum { MAX_SDMA_HQD_PER_PIPE = 10 }; 110enum { MAX_SDMA_HQD_PER_PIPE_11_0 = 8 }; 111 112enum { MAX_QUEUES_IN_A_GANG = 8 }; 113 114enum VM_HUB_TYPE { 115 VM_HUB_TYPE_GC = 0, 116 VM_HUB_TYPE_MM = 1, 117 VM_HUB_TYPE_MAX, 118}; 119 120enum { VMID_INVALID = 0xffff }; 121 122enum { MAX_VMID_GCHUB = 16 }; 123enum { MAX_VMID_MMHUB = 16 }; 124 125enum SET_DEBUG_VMID_OPERATIONS { 126 DEBUG_VMID_OP_PROGRAM = 0, 127 DEBUG_VMID_OP_ALLOCATE = 1, 128 DEBUG_VMID_OP_RELEASE = 2 129}; 130 131enum MES_LOG_OPERATION { 132 MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0, 133 MES_LOG_OPERATION_QUEUE_NEW_WORK = 1, 134 MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2, 135 MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3, 136 MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4, 137 MES_LOG_OPERATION_QUEUE_INVALID = 0xF, 138}; 139 140enum MES_LOG_CONTEXT_STATE { 141 MES_LOG_CONTEXT_STATE_IDLE = 0, 142 MES_LOG_CONTEXT_STATE_RUNNING = 1, 143 MES_LOG_CONTEXT_STATE_READY = 2, 144 MES_LOG_CONTEXT_STATE_READY_STANDBY = 3, 145 MES_LOG_CONTEXT_STATE_INVALID = 0xF, 146}; 147 148struct MES_LOG_CONTEXT_STATE_CHANGE { 149 void *h_context; 150 enum MES_LOG_CONTEXT_STATE new_context_state; 151}; 152 153struct MES_LOG_QUEUE_NEW_WORK { 154 uint64_t h_queue; 155 uint64_t reserved; 156}; 157 158struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT { 159 uint64_t h_queue; 160 uint64_t h_sync_object; 161}; 162 163struct MES_LOG_QUEUE_NO_MORE_WORK { 164 uint64_t h_queue; 165 uint64_t reserved; 166}; 167 168struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT { 169 uint64_t h_queue; 170 uint64_t h_sync_object; 171}; 172 173struct MES_LOG_ENTRY_HEADER { 174 uint32_t first_free_entry_index; 175 uint32_t wraparound_count; 176 uint64_t number_of_entries; 177 uint64_t reserved[2]; 178}; 179 180struct MES_LOG_ENTRY_DATA { 181 uint64_t gpu_time_stamp; 182 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */ 183 uint32_t reserved_operation_type_bits; 184 union { 185 struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change; 186 struct MES_LOG_QUEUE_NEW_WORK queue_new_work; 187 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object; 188 struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work; 189 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object; 190 uint64_t all[2]; 191 }; 192}; 193 194struct MES_LOG_BUFFER { 195 struct MES_LOG_ENTRY_HEADER header; 196 struct MES_LOG_ENTRY_DATA entries[1]; 197}; 198 199enum MES_SWIP_TO_HWIP_DEF { 200 MES_MAX_HWIP_SEGMENT = 8, 201}; 202 203union MESAPI_SET_HW_RESOURCES { 204 struct { 205 union MES_API_HEADER header; 206 uint32_t vmid_mask_mmhub; 207 uint32_t vmid_mask_gfxhub; 208 uint32_t gds_size; 209 uint32_t paging_vmid; 210 uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES]; 211 uint32_t gfx_hqd_mask[MAX_GFX_PIPES]; 212 uint32_t sdma_hqd_mask[MAX_SDMA_PIPES]; 213 uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS]; 214 uint64_t g_sch_ctx_gpu_mc_ptr; 215 uint64_t query_status_fence_gpu_mc_ptr; 216 uint32_t gc_base[MES_MAX_HWIP_SEGMENT]; 217 uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT]; 218 uint32_t osssys_base[MES_MAX_HWIP_SEGMENT]; 219 struct MES_API_STATUS api_status; 220 union { 221 struct { 222 uint32_t disable_reset : 1; 223 uint32_t use_different_vmid_compute : 1; 224 uint32_t disable_mes_log : 1; 225 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1; 226 uint32_t apply_grbm_remote_register_dummy_read_wa : 1; 227 uint32_t second_gfx_pipe_enabled : 1; 228 uint32_t enable_level_process_quantum_check : 1; 229 uint32_t legacy_sch_mode : 1; 230 uint32_t disable_add_queue_wptr_mc_addr : 1; 231 uint32_t enable_mes_event_int_logging : 1; 232 uint32_t enable_reg_active_poll : 1; 233 uint32_t use_disable_queue_in_legacy_uq_preemption : 1; 234 uint32_t send_write_data : 1; 235 uint32_t os_tdr_timeout_override : 1; 236 uint32_t use_rs64mem_for_proc_gang_ctx : 1; 237 uint32_t use_add_queue_unmap_flag_addr : 1; 238 uint32_t enable_mes_sch_stb_log : 1; 239 uint32_t limit_single_process : 1; 240 uint32_t is_strix_tmz_wa_enabled :1; 241 uint32_t enable_lr_compute_wa : 1; 242 uint32_t reserved : 12; 243 }; 244 uint32_t uint32_t_all; 245 }; 246 uint32_t oversubscription_timer; 247 uint64_t doorbell_info; 248 uint64_t event_intr_history_gpu_mc_ptr; 249 uint64_t timestamp; 250 uint32_t os_tdr_timeout_in_sec; 251 }; 252 253 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 254}; 255 256union MESAPI_SET_HW_RESOURCES_1 { 257 struct { 258 union MES_API_HEADER header; 259 struct MES_API_STATUS api_status; 260 uint64_t timestamp; 261 union { 262 struct { 263 uint32_t enable_mes_info_ctx : 1; 264 uint32_t reserved : 31; 265 }; 266 uint32_t uint32_all; 267 }; 268 uint64_t mes_info_ctx_mc_addr; 269 uint32_t mes_info_ctx_size; 270 uint64_t reserved1; 271 uint64_t cleaner_shader_fence_mc_addr; 272 }; 273 274 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 275}; 276 277union MESAPI__ADD_QUEUE { 278 struct { 279 union MES_API_HEADER header; 280 uint32_t process_id; 281 uint64_t page_table_base_addr; 282 uint64_t process_va_start; 283 uint64_t process_va_end; 284 uint64_t process_quantum; 285 uint64_t process_context_addr; 286 uint64_t gang_quantum; 287 uint64_t gang_context_addr; 288 uint32_t inprocess_gang_priority; 289 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 290 uint32_t doorbell_offset; 291 uint64_t mqd_addr; 292 uint64_t wptr_addr; 293 uint64_t h_context; 294 uint64_t h_queue; 295 enum MES_QUEUE_TYPE queue_type; 296 uint32_t gds_base; 297 uint32_t gds_size; 298 uint32_t gws_base; 299 uint32_t gws_size; 300 uint32_t oa_mask; 301 uint64_t trap_handler_addr; 302 uint32_t vm_context_cntl; 303 304 struct { 305 uint32_t paging : 1; 306 uint32_t debug_vmid : 4; 307 uint32_t program_gds : 1; 308 uint32_t is_gang_suspended : 1; 309 uint32_t is_tmz_queue : 1; 310 uint32_t map_kiq_utility_queue : 1; 311 uint32_t is_kfd_process : 1; 312 uint32_t trap_en : 1; 313 uint32_t is_aql_queue : 1; 314 uint32_t skip_process_ctx_clear : 1; 315 uint32_t map_legacy_kq : 1; 316 uint32_t exclusively_scheduled : 1; 317 uint32_t is_long_running : 1; 318 uint32_t is_dwm_queue : 1; 319 uint32_t is_video_blit_queue : 1; 320 uint32_t reserved : 14; 321 }; 322 struct MES_API_STATUS api_status; 323 uint64_t tma_addr; 324 uint32_t sch_id; 325 uint64_t timestamp; 326 uint32_t process_context_array_index; 327 uint32_t gang_context_array_index; 328 uint32_t pipe_id; 329 uint32_t queue_id; 330 uint32_t alignment_mode_setting; 331 uint64_t unmap_flag_addr; 332 }; 333 334 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 335}; 336 337union MESAPI__REMOVE_QUEUE { 338 struct { 339 union MES_API_HEADER header; 340 uint32_t doorbell_offset; 341 uint64_t gang_context_addr; 342 343 struct { 344 uint32_t unmap_legacy_gfx_queue : 1; 345 uint32_t unmap_kiq_utility_queue : 1; 346 uint32_t preempt_legacy_gfx_queue : 1; 347 uint32_t unmap_legacy_queue : 1; 348 uint32_t remove_queue_after_reset : 1; 349 uint32_t reserved : 27; 350 }; 351 struct MES_API_STATUS api_status; 352 353 uint32_t pipe_id; 354 uint32_t queue_id; 355 356 uint64_t tf_addr; 357 uint32_t tf_data; 358 359 enum MES_QUEUE_TYPE queue_type; 360 }; 361 362 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 363}; 364 365union MESAPI__SET_SCHEDULING_CONFIG { 366 struct { 367 union MES_API_HEADER header; 368 /* Grace period when preempting another priority band for this 369 * priority band. The value for idle priority band is ignored, 370 * as it never preempts other bands. 371 */ 372 uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS]; 373 /* Default quantum for scheduling across processes within 374 * a priority band. 375 */ 376 uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS]; 377 /* Default grace period for processes that preempt each other 378 * within a priority band. 379 */ 380 uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS]; 381 /* For normal level this field specifies the target GPU 382 * percentage in situations when it's starved by the high level. 383 * Valid values are between 0 and 50, with the default being 10. 384 */ 385 uint32_t normal_yield_percent; 386 struct MES_API_STATUS api_status; 387 }; 388 389 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 390}; 391 392union MESAPI__PERFORM_YIELD { 393 struct { 394 union MES_API_HEADER header; 395 uint32_t dummy; 396 struct MES_API_STATUS api_status; 397 }; 398 399 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 400}; 401 402union MESAPI__CHANGE_GANG_PRIORITY_LEVEL { 403 struct { 404 union MES_API_HEADER header; 405 uint32_t inprocess_gang_priority; 406 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level; 407 uint64_t gang_quantum; 408 uint64_t gang_context_addr; 409 struct MES_API_STATUS api_status; 410 }; 411 412 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 413}; 414 415union MESAPI__SUSPEND { 416 struct { 417 union MES_API_HEADER header; 418 /* false - suspend all gangs; true - specific gang */ 419 struct { 420 uint32_t suspend_all_gangs : 1; 421 uint32_t reserved : 31; 422 }; 423 /* gang_context_addr is valid only if suspend_all = false */ 424 uint64_t gang_context_addr; 425 426 uint64_t suspend_fence_addr; 427 uint32_t suspend_fence_value; 428 429 struct MES_API_STATUS api_status; 430 }; 431 432 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 433}; 434 435union MESAPI__RESUME { 436 struct { 437 union MES_API_HEADER header; 438 /* false - resume all gangs; true - specified gang */ 439 struct { 440 uint32_t resume_all_gangs : 1; 441 uint32_t reserved : 31; 442 }; 443 /* valid only if resume_all_gangs = false */ 444 uint64_t gang_context_addr; 445 446 struct MES_API_STATUS api_status; 447 }; 448 449 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 450}; 451 452union MESAPI__RESET { 453 struct { 454 union MES_API_HEADER header; 455 456 struct { 457 /* Only reset the queue given by doorbell_offset (not entire gang) */ 458 uint32_t reset_queue_only : 1; 459 /* Hang detection first then reset any queues that are hung */ 460 uint32_t hang_detect_then_reset : 1; 461 /* Only do hang detection (no reset) */ 462 uint32_t hang_detect_only : 1; 463 /* Rest HP and LP kernel queues not managed by MES */ 464 uint32_t reset_legacy_gfx : 1; 465 uint32_t reserved : 28; 466 }; 467 468 uint64_t gang_context_addr; 469 470 /* valid only if reset_queue_only = true */ 471 uint32_t doorbell_offset; 472 473 /* valid only if hang_detect_then_reset = true */ 474 uint64_t doorbell_offset_addr; 475 enum MES_QUEUE_TYPE queue_type; 476 477 /* valid only if reset_legacy_gfx = true */ 478 uint32_t pipe_id_lp; 479 uint32_t queue_id_lp; 480 uint32_t vmid_id_lp; 481 uint64_t mqd_mc_addr_lp; 482 uint32_t doorbell_offset_lp; 483 uint64_t wptr_addr_lp; 484 485 uint32_t pipe_id_hp; 486 uint32_t queue_id_hp; 487 uint32_t vmid_id_hp; 488 uint64_t mqd_mc_addr_hp; 489 uint32_t doorbell_offset_hp; 490 uint64_t wptr_addr_hp; 491 492 struct MES_API_STATUS api_status; 493 }; 494 495 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 496}; 497 498union MESAPI__SET_LOGGING_BUFFER { 499 struct { 500 union MES_API_HEADER header; 501 /* There are separate log buffers for each queue type */ 502 enum MES_QUEUE_TYPE log_type; 503 /* Log buffer GPU Address */ 504 uint64_t logging_buffer_addr; 505 /* number of entries in the log buffer */ 506 uint32_t number_of_entries; 507 /* Entry index at which CPU interrupt needs to be signalled */ 508 uint32_t interrupt_entry; 509 510 struct MES_API_STATUS api_status; 511 }; 512 513 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 514}; 515 516union MESAPI__QUERY_MES_STATUS { 517 struct { 518 union MES_API_HEADER header; 519 bool mes_healthy; /* 0 - not healthy, 1 - healthy */ 520 struct MES_API_STATUS api_status; 521 }; 522 523 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 524}; 525 526union MESAPI__PROGRAM_GDS { 527 struct { 528 union MES_API_HEADER header; 529 uint64_t process_context_addr; 530 uint32_t gds_base; 531 uint32_t gds_size; 532 uint32_t gws_base; 533 uint32_t gws_size; 534 uint32_t oa_mask; 535 struct MES_API_STATUS api_status; 536 }; 537 538 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 539}; 540 541union MESAPI__SET_DEBUG_VMID { 542 struct { 543 union MES_API_HEADER header; 544 struct MES_API_STATUS api_status; 545 union { 546 struct { 547 uint32_t use_gds : 1; 548 uint32_t operation : 2; 549 uint32_t reserved : 29; 550 } flags; 551 uint32_t u32All; 552 }; 553 uint32_t reserved; 554 uint32_t debug_vmid; 555 uint64_t process_context_addr; 556 uint64_t page_table_base_addr; 557 uint64_t process_va_start; 558 uint64_t process_va_end; 559 uint32_t gds_base; 560 uint32_t gds_size; 561 uint32_t gws_base; 562 uint32_t gws_size; 563 uint32_t oa_mask; 564 565 /* output addr of the acquired vmid value */ 566 uint64_t output_addr; 567 }; 568 569 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 570}; 571 572enum MESAPI_MISC_OPCODE { 573 MESAPI_MISC__WRITE_REG, 574 MESAPI_MISC__INV_GART, 575 MESAPI_MISC__QUERY_STATUS, 576 MESAPI_MISC__READ_REG, 577 MESAPI_MISC__WAIT_REG_MEM, 578 MESAPI_MISC__SET_SHADER_DEBUGGER, 579 MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE, 580 MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES, 581 MESAPI_MISC__CHANGE_CONFIG, 582 MESAPI_MISC__LAUNCH_CLEANER_SHADER, 583 584 MESAPI_MISC__MAX, 585}; 586 587enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 }; 588 589struct WRITE_REG { 590 uint32_t reg_offset; 591 uint32_t reg_value; 592}; 593 594struct READ_REG { 595 uint32_t reg_offset; 596 uint64_t buffer_addr; 597}; 598 599enum WRM_OPERATION { 600 WRM_OPERATION__WAIT_REG_MEM, 601 WRM_OPERATION__WR_WAIT_WR_REG, 602 WRM_OPERATION__MAX, 603}; 604 605struct WAIT_REG_MEM { 606 enum WRM_OPERATION op; 607 uint32_t reference; 608 uint32_t mask; 609 uint32_t reg_offset1; 610 uint32_t reg_offset2; 611}; 612 613struct INV_GART { 614 uint64_t inv_range_va_start; 615 uint64_t inv_range_size; 616}; 617 618struct QUERY_STATUS { 619 uint32_t context_id; 620}; 621 622struct SET_SHADER_DEBUGGER { 623 uint64_t process_context_addr; 624 union { 625 struct { 626 uint32_t single_memop : 1; /* SQ_DEBUG.single_memop */ 627 uint32_t single_alu_op : 1; /* SQ_DEBUG.single_alu_op */ 628 uint32_t reserved : 29; 629 uint32_t process_ctx_flush : 1; 630 }; 631 uint32_t u32all; 632 } flags; 633 uint32_t spi_gdbg_per_vmid_cntl; 634 uint32_t tcp_watch_cntl[4]; /* TCP_WATCHx_CNTL */ 635 uint32_t trap_en; 636}; 637 638enum MESAPI_MISC__CHANGE_CONFIG_OPTION { 639 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS = 0, 640 MESAPI_MISC__CHANGE_CONFIG_OPTION_ENABLE_HWS_LOGGING_BUFFER = 1, 641 MESAPI_MISC__CHANGE_CONFIG_OPTION_CHANGE_TDR_CONFIG = 2, 642 643 MESAPI_MISC__CHANGE_CONFIG_OPTION_MAX = 0x1F 644}; 645 646struct CHANGE_CONFIG { 647 enum MESAPI_MISC__CHANGE_CONFIG_OPTION opcode; 648 union { 649 struct { 650 uint32_t limit_single_process : 1; 651 uint32_t enable_hws_logging_buffer : 1; 652 uint32_t reserved : 31; 653 } bits; 654 uint32_t all; 655 } option; 656 657 struct { 658 uint32_t tdr_level; 659 uint32_t tdr_delay; 660 } tdr_config; 661}; 662 663union MESAPI__MISC { 664 struct { 665 union MES_API_HEADER header; 666 enum MESAPI_MISC_OPCODE opcode; 667 struct MES_API_STATUS api_status; 668 669 union { 670 struct WRITE_REG write_reg; 671 struct INV_GART inv_gart; 672 struct QUERY_STATUS query_status; 673 struct READ_REG read_reg; 674 struct WAIT_REG_MEM wait_reg_mem; 675 struct SET_SHADER_DEBUGGER set_shader_debugger; 676 enum MES_AMD_PRIORITY_LEVEL queue_sch_level; 677 struct CHANGE_CONFIG change_config; 678 679 uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS]; 680 }; 681 }; 682 683 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 684}; 685 686union MESAPI__UPDATE_ROOT_PAGE_TABLE { 687 struct { 688 union MES_API_HEADER header; 689 uint64_t page_table_base_addr; 690 uint64_t process_context_addr; 691 struct MES_API_STATUS api_status; 692 }; 693 694 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 695}; 696 697union MESAPI_AMD_LOG { 698 struct { 699 union MES_API_HEADER header; 700 uint64_t p_buffer_memory; 701 uint64_t p_buffer_size_used; 702 struct MES_API_STATUS api_status; 703 }; 704 705 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; 706}; 707 708#pragma pack(pop) 709#endif
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