FILE
vcn_4_0_5_offset.h
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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_offset.h
1/* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef _vcn_4_0_5_OFFSET_HEADER 25#define _vcn_4_0_5_OFFSET_HEADER 26 27 28 29// addressBlock: uvd_uvddec 30// base address: 0x1fb00 31#define regUVD_CGC_GATE 0x00c1 32#define regUVD_CGC_GATE_BASE_IDX 1 33#define regUVD_CGC_CTRL 0x00c2 34#define regUVD_CGC_CTRL_BASE_IDX 1 35#define regAVM_SUVD_CGC_GATE 0x00c4 36#define regAVM_SUVD_CGC_GATE_BASE_IDX 1 37#define regCDEFE_SUVD_CGC_GATE 0x00c4 38#define regCDEFE_SUVD_CGC_GATE_BASE_IDX 1 39#define regEFC_SUVD_CGC_GATE 0x00c4 40#define regEFC_SUVD_CGC_GATE_BASE_IDX 1 41#define regENT_SUVD_CGC_GATE 0x00c4 42#define regENT_SUVD_CGC_GATE_BASE_IDX 1 43#define regIME_SUVD_CGC_GATE 0x00c4 44#define regIME_SUVD_CGC_GATE_BASE_IDX 1 45#define regPPU_SUVD_CGC_GATE 0x00c4 46#define regPPU_SUVD_CGC_GATE_BASE_IDX 1 47#define regSAOE_SUVD_CGC_GATE 0x00c4 48#define regSAOE_SUVD_CGC_GATE_BASE_IDX 1 49#define regSCM_SUVD_CGC_GATE 0x00c4 50#define regSCM_SUVD_CGC_GATE_BASE_IDX 1 51#define regSDB_SUVD_CGC_GATE 0x00c4 52#define regSDB_SUVD_CGC_GATE_BASE_IDX 1 53#define regSIT0_NXT_SUVD_CGC_GATE 0x00c4 54#define regSIT0_NXT_SUVD_CGC_GATE_BASE_IDX 1 55#define regSIT1_NXT_SUVD_CGC_GATE 0x00c4 56#define regSIT1_NXT_SUVD_CGC_GATE_BASE_IDX 1 57#define regSIT2_NXT_SUVD_CGC_GATE 0x00c4 58#define regSIT2_NXT_SUVD_CGC_GATE_BASE_IDX 1 59#define regSIT_SUVD_CGC_GATE 0x00c4 60#define regSIT_SUVD_CGC_GATE_BASE_IDX 1 61#define regSMPA_SUVD_CGC_GATE 0x00c4 62#define regSMPA_SUVD_CGC_GATE_BASE_IDX 1 63#define regSMP_SUVD_CGC_GATE 0x00c4 64#define regSMP_SUVD_CGC_GATE_BASE_IDX 1 65#define regSRE_SUVD_CGC_GATE 0x00c4 66#define regSRE_SUVD_CGC_GATE_BASE_IDX 1 67#define regUVD_MPBE0_SUVD_CGC_GATE 0x00c4 68#define regUVD_MPBE0_SUVD_CGC_GATE_BASE_IDX 1 69#define regUVD_MPBE1_SUVD_CGC_GATE 0x00c4 70#define regUVD_MPBE1_SUVD_CGC_GATE_BASE_IDX 1 71#define regUVD_SUVD_CGC_GATE 0x00c4 72#define regUVD_SUVD_CGC_GATE_BASE_IDX 1 73#define regAVM_SUVD_CGC_GATE2 0x00c5 74#define regAVM_SUVD_CGC_GATE2_BASE_IDX 1 75#define regCDEFE_SUVD_CGC_GATE2 0x00c5 76#define regCDEFE_SUVD_CGC_GATE2_BASE_IDX 1 77#define regDBR_SUVD_CGC_GATE2 0x00c5 78#define regDBR_SUVD_CGC_GATE2_BASE_IDX 1 79#define regENT_SUVD_CGC_GATE2 0x00c5 80#define regENT_SUVD_CGC_GATE2_BASE_IDX 1 81#define regIME_SUVD_CGC_GATE2 0x00c5 82#define regIME_SUVD_CGC_GATE2_BASE_IDX 1 83#define regMPC1_SUVD_CGC_GATE2 0x00c5 84#define regMPC1_SUVD_CGC_GATE2_BASE_IDX 1 85#define regSAOE_SUVD_CGC_GATE2 0x00c5 86#define regSAOE_SUVD_CGC_GATE2_BASE_IDX 1 87#define regSDB_SUVD_CGC_GATE2 0x00c5 88#define regSDB_SUVD_CGC_GATE2_BASE_IDX 1 89#define regSIT0_NXT_SUVD_CGC_GATE2 0x00c5 90#define regSIT0_NXT_SUVD_CGC_GATE2_BASE_IDX 1 91#define regSIT1_NXT_SUVD_CGC_GATE2 0x00c5 92#define regSIT1_NXT_SUVD_CGC_GATE2_BASE_IDX 1 93#define regSIT2_NXT_SUVD_CGC_GATE2 0x00c5 94#define regSIT2_NXT_SUVD_CGC_GATE2_BASE_IDX 1 95#define regSIT_SUVD_CGC_GATE2 0x00c5 96#define regSIT_SUVD_CGC_GATE2_BASE_IDX 1 97#define regSMPA_SUVD_CGC_GATE2 0x00c5 98#define regSMPA_SUVD_CGC_GATE2_BASE_IDX 1 99#define regSMP_SUVD_CGC_GATE2 0x00c5 100#define regSMP_SUVD_CGC_GATE2_BASE_IDX 1 101#define regSRE_SUVD_CGC_GATE2 0x00c5 102#define regSRE_SUVD_CGC_GATE2_BASE_IDX 1 103#define regUVD_MPBE0_SUVD_CGC_GATE2 0x00c5 104#define regUVD_MPBE0_SUVD_CGC_GATE2_BASE_IDX 1 105#define regUVD_MPBE1_SUVD_CGC_GATE2 0x00c5 106#define regUVD_MPBE1_SUVD_CGC_GATE2_BASE_IDX 1 107#define regUVD_SUVD_CGC_GATE2 0x00c5 108#define regUVD_SUVD_CGC_GATE2_BASE_IDX 1 109#define regAVM_SUVD_CGC_CTRL 0x00c6 110#define regAVM_SUVD_CGC_CTRL_BASE_IDX 1 111#define regCDEFE_SUVD_CGC_CTRL 0x00c6 112#define regCDEFE_SUVD_CGC_CTRL_BASE_IDX 1 113#define regDBR_SUVD_CGC_CTRL 0x00c6 114#define regDBR_SUVD_CGC_CTRL_BASE_IDX 1 115#define regEFC_SUVD_CGC_CTRL 0x00c6 116#define regEFC_SUVD_CGC_CTRL_BASE_IDX 1 117#define regENT_SUVD_CGC_CTRL 0x00c6 118#define regENT_SUVD_CGC_CTRL_BASE_IDX 1 119#define regIME_SUVD_CGC_CTRL 0x00c6 120#define regIME_SUVD_CGC_CTRL_BASE_IDX 1 121#define regMPC1_SUVD_CGC_CTRL 0x00c6 122#define regMPC1_SUVD_CGC_CTRL_BASE_IDX 1 123#define regPPU_SUVD_CGC_CTRL 0x00c6 124#define regPPU_SUVD_CGC_CTRL_BASE_IDX 1 125#define regSAOE_SUVD_CGC_CTRL 0x00c6 126#define regSAOE_SUVD_CGC_CTRL_BASE_IDX 1 127#define regSCM_SUVD_CGC_CTRL 0x00c6 128#define regSCM_SUVD_CGC_CTRL_BASE_IDX 1 129#define regSDB_SUVD_CGC_CTRL 0x00c6 130#define regSDB_SUVD_CGC_CTRL_BASE_IDX 1 131#define regSIT0_NXT_SUVD_CGC_CTRL 0x00c6 132#define regSIT0_NXT_SUVD_CGC_CTRL_BASE_IDX 1 133#define regSIT1_NXT_SUVD_CGC_CTRL 0x00c6 134#define regSIT1_NXT_SUVD_CGC_CTRL_BASE_IDX 1 135#define regSIT2_NXT_SUVD_CGC_CTRL 0x00c6 136#define regSIT2_NXT_SUVD_CGC_CTRL_BASE_IDX 1 137#define regSIT_SUVD_CGC_CTRL 0x00c6 138#define regSIT_SUVD_CGC_CTRL_BASE_IDX 1 139#define regSMPA_SUVD_CGC_CTRL 0x00c6 140#define regSMPA_SUVD_CGC_CTRL_BASE_IDX 1 141#define regSMP_SUVD_CGC_CTRL 0x00c6 142#define regSMP_SUVD_CGC_CTRL_BASE_IDX 1 143#define regSRE_SUVD_CGC_CTRL 0x00c6 144#define regSRE_SUVD_CGC_CTRL_BASE_IDX 1 145#define regUVD_MPBE0_SUVD_CGC_CTRL 0x00c6 146#define regUVD_MPBE0_SUVD_CGC_CTRL_BASE_IDX 1 147#define regUVD_MPBE1_SUVD_CGC_CTRL 0x00c6 148#define regUVD_MPBE1_SUVD_CGC_CTRL_BASE_IDX 1 149#define regUVD_SUVD_CGC_CTRL 0x00c6 150#define regUVD_SUVD_CGC_CTRL_BASE_IDX 1 151#define regUVD_CGC_CTRL3 0x00ca 152#define regUVD_CGC_CTRL3_BASE_IDX 1 153#define regUVD_GPCOM_VCPU_DATA0 0x00d0 154#define regUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 155#define regUVD_GPCOM_VCPU_DATA1 0x00d1 156#define regUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 157#define regUVD_GPCOM_SYS_CMD 0x00d2 158#define regUVD_GPCOM_SYS_CMD_BASE_IDX 1 159#define regUVD_GPCOM_SYS_DATA0 0x00d3 160#define regUVD_GPCOM_SYS_DATA0_BASE_IDX 1 161#define regUVD_GPCOM_SYS_DATA1 0x00d4 162#define regUVD_GPCOM_SYS_DATA1_BASE_IDX 1 163#define regUVD_VCPU_INT_EN 0x00d5 164#define regUVD_VCPU_INT_EN_BASE_IDX 1 165#define regUVD_VCPU_INT_ACK 0x00d7 166#define regUVD_VCPU_INT_ACK_BASE_IDX 1 167#define regUVD_VCPU_INT_ROUTE 0x00d8 168#define regUVD_VCPU_INT_ROUTE_BASE_IDX 1 169#define regUVD_SUVD_INT_EN 0x00db 170#define regUVD_SUVD_INT_EN_BASE_IDX 1 171#define regUVD_SUVD_INT_STATUS 0x00dc 172#define regUVD_SUVD_INT_STATUS_BASE_IDX 1 173#define regUVD_SUVD_INT_ACK 0x00dd 174#define regUVD_SUVD_INT_ACK_BASE_IDX 1 175#define regUVD_MASTINT_EN 0x00e1 176#define regUVD_MASTINT_EN_BASE_IDX 1 177#define regUVD_SYS_INT_EN 0x00e2 178#define regUVD_SYS_INT_EN_BASE_IDX 1 179#define regUVD_SYS_INT_STATUS 0x00e3 180#define regUVD_SYS_INT_STATUS_BASE_IDX 1 181#define regUVD_SYS_INT_ACK 0x00e4 182#define regUVD_SYS_INT_ACK_BASE_IDX 1 183#define regUVD_JOB_DONE 0x00e5 184#define regUVD_JOB_DONE_BASE_IDX 1 185#define regUVD_CBUF_ID 0x00e6 186#define regUVD_CBUF_ID_BASE_IDX 1 187#define regUVD_CONTEXT_ID 0x00e7 188#define regUVD_CONTEXT_ID_BASE_IDX 1 189#define regUVD_CONTEXT_ID2 0x00e8 190#define regUVD_CONTEXT_ID2_BASE_IDX 1 191#define regUVD_NO_OP 0x00e9 192#define regUVD_NO_OP_BASE_IDX 1 193#define regUVD_RB_BASE_LO 0x00ea 194#define regUVD_RB_BASE_LO_BASE_IDX 1 195#define regUVD_RB_BASE_HI 0x00eb 196#define regUVD_RB_BASE_HI_BASE_IDX 1 197#define regUVD_RB_SIZE 0x00ec 198#define regUVD_RB_SIZE_BASE_IDX 1 199#define regUVD_RB_BASE_LO2 0x00ef 200#define regUVD_RB_BASE_LO2_BASE_IDX 1 201#define regUVD_RB_BASE_HI2 0x00f0 202#define regUVD_RB_BASE_HI2_BASE_IDX 1 203#define regUVD_RB_SIZE2 0x00f1 204#define regUVD_RB_SIZE2_BASE_IDX 1 205#define regUVD_RB_BASE_LO3 0x00f4 206#define regUVD_RB_BASE_LO3_BASE_IDX 1 207#define regUVD_RB_BASE_HI3 0x00f5 208#define regUVD_RB_BASE_HI3_BASE_IDX 1 209#define regUVD_RB_SIZE3 0x00f6 210#define regUVD_RB_SIZE3_BASE_IDX 1 211#define regUVD_RB_BASE_LO4 0x00f9 212#define regUVD_RB_BASE_LO4_BASE_IDX 1 213#define regUVD_RB_BASE_HI4 0x00fa 214#define regUVD_RB_BASE_HI4_BASE_IDX 1 215#define regUVD_RB_SIZE4 0x00fb 216#define regUVD_RB_SIZE4_BASE_IDX 1 217#define regUVD_OUT_RB_BASE_LO 0x00fe 218#define regUVD_OUT_RB_BASE_LO_BASE_IDX 1 219#define regUVD_OUT_RB_BASE_HI 0x00ff 220#define regUVD_OUT_RB_BASE_HI_BASE_IDX 1 221#define regUVD_OUT_RB_SIZE 0x0100 222#define regUVD_OUT_RB_SIZE_BASE_IDX 1 223#define regUVD_IOV_ACTIVE_FCN_ID 0x0103 224#define regUVD_IOV_ACTIVE_FCN_ID_BASE_IDX 1 225#define regUVD_IOV_MAILBOX 0x0104 226#define regUVD_IOV_MAILBOX_BASE_IDX 1 227#define regUVD_IOV_MAILBOX_RESP 0x0105 228#define regUVD_IOV_MAILBOX_RESP_BASE_IDX 1 229#define regUVD_RB_ARB_CTRL 0x0106 230#define regUVD_RB_ARB_CTRL_BASE_IDX 1 231#define regUVD_CTX_INDEX 0x0107 232#define regUVD_CTX_INDEX_BASE_IDX 1 233#define regUVD_CTX_DATA 0x0108 234#define regUVD_CTX_DATA_BASE_IDX 1 235#define regUVD_CXW_WR 0x0109 236#define regUVD_CXW_WR_BASE_IDX 1 237#define regUVD_CXW_WR_INT_ID 0x010a 238#define regUVD_CXW_WR_INT_ID_BASE_IDX 1 239#define regUVD_CXW_WR_INT_CTX_ID 0x010b 240#define regUVD_CXW_WR_INT_CTX_ID_BASE_IDX 1 241#define regUVD_CXW_INT_ID 0x010c 242#define regUVD_CXW_INT_ID_BASE_IDX 1 243#define regUVD_MPEG2_ERROR 0x010d 244#define regUVD_MPEG2_ERROR_BASE_IDX 1 245#define regUVD_YBASE 0x0110 246#define regUVD_YBASE_BASE_IDX 1 247#define regUVD_UVBASE 0x0111 248#define regUVD_UVBASE_BASE_IDX 1 249#define regUVD_PITCH 0x0112 250#define regUVD_PITCH_BASE_IDX 1 251#define regUVD_WIDTH 0x0113 252#define regUVD_WIDTH_BASE_IDX 1 253#define regUVD_HEIGHT 0x0114 254#define regUVD_HEIGHT_BASE_IDX 1 255#define regUVD_PICCOUNT 0x0115 256#define regUVD_PICCOUNT_BASE_IDX 1 257#define regUVD_MPRD_INITIAL_XY 0x0116 258#define regUVD_MPRD_INITIAL_XY_BASE_IDX 1 259#define regUVD_MPEG2_CTRL 0x0117 260#define regUVD_MPEG2_CTRL_BASE_IDX 1 261#define regUVD_MB_CTL_BUF_BASE 0x0118 262#define regUVD_MB_CTL_BUF_BASE_BASE_IDX 1 263#define regUVD_PIC_CTL_BUF_BASE 0x0119 264#define regUVD_PIC_CTL_BUF_BASE_BASE_IDX 1 265#define regUVD_DXVA_BUF_SIZE 0x011a 266#define regUVD_DXVA_BUF_SIZE_BASE_IDX 1 267#define regUVD_SCRATCH_NP 0x011b 268#define regUVD_SCRATCH_NP_BASE_IDX 1 269#define regUVD_CLK_SWT_HANDSHAKE 0x011c 270#define regUVD_CLK_SWT_HANDSHAKE_BASE_IDX 1 271#define regUVD_GP_SCRATCH0 0x011e 272#define regUVD_GP_SCRATCH0_BASE_IDX 1 273#define regUVD_GP_SCRATCH1 0x011f 274#define regUVD_GP_SCRATCH1_BASE_IDX 1 275#define regUVD_GP_SCRATCH2 0x0120 276#define regUVD_GP_SCRATCH2_BASE_IDX 1 277#define regUVD_GP_SCRATCH3 0x0121 278#define regUVD_GP_SCRATCH3_BASE_IDX 1 279#define regUVD_GP_SCRATCH4 0x0122 280#define regUVD_GP_SCRATCH4_BASE_IDX 1 281#define regUVD_GP_SCRATCH5 0x0123 282#define regUVD_GP_SCRATCH5_BASE_IDX 1 283#define regUVD_GP_SCRATCH6 0x0124 284#define regUVD_GP_SCRATCH6_BASE_IDX 1 285#define regUVD_GP_SCRATCH7 0x0125 286#define regUVD_GP_SCRATCH7_BASE_IDX 1 287#define regUVD_GP_SCRATCH8 0x0126 288#define regUVD_GP_SCRATCH8_BASE_IDX 1 289#define regUVD_GP_SCRATCH9 0x0127 290#define regUVD_GP_SCRATCH9_BASE_IDX 1 291#define regUVD_GP_SCRATCH10 0x0128 292#define regUVD_GP_SCRATCH10_BASE_IDX 1 293#define regUVD_GP_SCRATCH11 0x0129 294#define regUVD_GP_SCRATCH11_BASE_IDX 1 295#define regUVD_GP_SCRATCH12 0x012a 296#define regUVD_GP_SCRATCH12_BASE_IDX 1 297#define regUVD_GP_SCRATCH13 0x012b 298#define regUVD_GP_SCRATCH13_BASE_IDX 1 299#define regUVD_GP_SCRATCH14 0x012c 300#define regUVD_GP_SCRATCH14_BASE_IDX 1 301#define regUVD_GP_SCRATCH15 0x012d 302#define regUVD_GP_SCRATCH15_BASE_IDX 1 303#define regUVD_GP_SCRATCH16 0x012e 304#define regUVD_GP_SCRATCH16_BASE_IDX 1 305#define regUVD_GP_SCRATCH17 0x012f 306#define regUVD_GP_SCRATCH17_BASE_IDX 1 307#define regUVD_GP_SCRATCH18 0x0130 308#define regUVD_GP_SCRATCH18_BASE_IDX 1 309#define regUVD_GP_SCRATCH19 0x0131 310#define regUVD_GP_SCRATCH19_BASE_IDX 1 311#define regUVD_GP_SCRATCH20 0x0132 312#define regUVD_GP_SCRATCH20_BASE_IDX 1 313#define regUVD_GP_SCRATCH21 0x0133 314#define regUVD_GP_SCRATCH21_BASE_IDX 1 315#define regUVD_GP_SCRATCH22 0x0134 316#define regUVD_GP_SCRATCH22_BASE_IDX 1 317#define regUVD_GP_SCRATCH23 0x0135 318#define regUVD_GP_SCRATCH23_BASE_IDX 1 319#define regUVD_AUDIO_RB_BASE_LO 0x0136 320#define regUVD_AUDIO_RB_BASE_LO_BASE_IDX 1 321#define regUVD_AUDIO_RB_BASE_HI 0x0137 322#define regUVD_AUDIO_RB_BASE_HI_BASE_IDX 1 323#define regUVD_AUDIO_RB_SIZE 0x0138 324#define regUVD_AUDIO_RB_SIZE_BASE_IDX 1 325#define regUVD_VCPU_INT_ACK2 0x013c 326#define regUVD_VCPU_INT_ACK2_BASE_IDX 1 327#define regUVD_VCPU_INT_EN2 0x013d 328#define regUVD_VCPU_INT_EN2_BASE_IDX 1 329#define regUVD_SUVD_CGC_STATUS2 0x013e 330#define regUVD_SUVD_CGC_STATUS2_BASE_IDX 1 331#define regUVD_SUVD_INT_STATUS2 0x0140 332#define regUVD_SUVD_INT_STATUS2_BASE_IDX 1 333#define regUVD_SUVD_INT_EN2 0x0141 334#define regUVD_SUVD_INT_EN2_BASE_IDX 1 335#define regUVD_SUVD_INT_ACK2 0x0142 336#define regUVD_SUVD_INT_ACK2_BASE_IDX 1 337#define regUVD_STATUS 0x0143 338#define regUVD_STATUS_BASE_IDX 1 339#define regUVD_CNTL 0x0146 340#define regUVD_CNTL_BASE_IDX 1 341#define regUVD_SOFT_RESET 0x0147 342#define regUVD_SOFT_RESET_BASE_IDX 1 343#define regUVD_SOFT_RESET2 0x0148 344#define regUVD_SOFT_RESET2_BASE_IDX 1 345#define regUVD_MMSCH_SOFT_RESET 0x0149 346#define regUVD_MMSCH_SOFT_RESET_BASE_IDX 1 347#define regUVD_WIG_CTRL 0x014a 348#define regUVD_WIG_CTRL_BASE_IDX 1 349#define regUVD_CGC_STATUS 0x014c 350#define regUVD_CGC_STATUS_BASE_IDX 1 351#define regUVD_CGC_UDEC_STATUS 0x014e 352#define regUVD_CGC_UDEC_STATUS_BASE_IDX 1 353#define regUVD_SUVD_CGC_STATUS 0x0150 354#define regUVD_SUVD_CGC_STATUS_BASE_IDX 1 355#define regUVD_GPCOM_VCPU_CMD 0x0152 356#define regUVD_GPCOM_VCPU_CMD_BASE_IDX 1 357 358 359// addressBlock: uvd_ecpudec 360// base address: 0x1fe00 361#define regUVD_VCPU_CACHE_OFFSET0 0x0180 362#define regUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1 363#define regUVD_VCPU_CACHE_SIZE0 0x0181 364#define regUVD_VCPU_CACHE_SIZE0_BASE_IDX 1 365#define regUVD_VCPU_CACHE_OFFSET1 0x0182 366#define regUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1 367#define regUVD_VCPU_CACHE_SIZE1 0x0183 368#define regUVD_VCPU_CACHE_SIZE1_BASE_IDX 1 369#define regUVD_VCPU_CACHE_OFFSET2 0x0184 370#define regUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1 371#define regUVD_VCPU_CACHE_SIZE2 0x0185 372#define regUVD_VCPU_CACHE_SIZE2_BASE_IDX 1 373#define regUVD_VCPU_CACHE_OFFSET3 0x0186 374#define regUVD_VCPU_CACHE_OFFSET3_BASE_IDX 1 375#define regUVD_VCPU_CACHE_SIZE3 0x0187 376#define regUVD_VCPU_CACHE_SIZE3_BASE_IDX 1 377#define regUVD_VCPU_CACHE_OFFSET4 0x0188 378#define regUVD_VCPU_CACHE_OFFSET4_BASE_IDX 1 379#define regUVD_VCPU_CACHE_SIZE4 0x0189 380#define regUVD_VCPU_CACHE_SIZE4_BASE_IDX 1 381#define regUVD_VCPU_CACHE_OFFSET5 0x018a 382#define regUVD_VCPU_CACHE_OFFSET5_BASE_IDX 1 383#define regUVD_VCPU_CACHE_SIZE5 0x018b 384#define regUVD_VCPU_CACHE_SIZE5_BASE_IDX 1 385#define regUVD_VCPU_CACHE_OFFSET6 0x018c 386#define regUVD_VCPU_CACHE_OFFSET6_BASE_IDX 1 387#define regUVD_VCPU_CACHE_SIZE6 0x018d 388#define regUVD_VCPU_CACHE_SIZE6_BASE_IDX 1 389#define regUVD_VCPU_CACHE_OFFSET7 0x018e 390#define regUVD_VCPU_CACHE_OFFSET7_BASE_IDX 1 391#define regUVD_VCPU_CACHE_SIZE7 0x018f 392#define regUVD_VCPU_CACHE_SIZE7_BASE_IDX 1 393#define regUVD_VCPU_CACHE_OFFSET8 0x0190 394#define regUVD_VCPU_CACHE_OFFSET8_BASE_IDX 1 395#define regUVD_VCPU_CACHE_SIZE8 0x0191 396#define regUVD_VCPU_CACHE_SIZE8_BASE_IDX 1 397#define regUVD_VCPU_NONCACHE_OFFSET0 0x0192 398#define regUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX 1 399#define regUVD_VCPU_NONCACHE_SIZE0 0x0193 400#define regUVD_VCPU_NONCACHE_SIZE0_BASE_IDX 1 401#define regUVD_VCPU_NONCACHE_OFFSET1 0x0194 402#define regUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX 1 403#define regUVD_VCPU_NONCACHE_SIZE1 0x0195 404#define regUVD_VCPU_NONCACHE_SIZE1_BASE_IDX 1 405#define regUVD_VCPU_CNTL 0x0196 406#define regUVD_VCPU_CNTL_BASE_IDX 1 407#define regUVD_VCPU_PRID 0x0197 408#define regUVD_VCPU_PRID_BASE_IDX 1 409#define regUVD_VCPU_TRCE 0x0198 410#define regUVD_VCPU_TRCE_BASE_IDX 1 411#define regUVD_VCPU_TRCE_RD 0x0199 412#define regUVD_VCPU_TRCE_RD_BASE_IDX 1 413#define regUVD_VCPU_IND_INDEX 0x019b 414#define regUVD_VCPU_IND_INDEX_BASE_IDX 1 415#define regUVD_VCPU_IND_DATA 0x019c 416#define regUVD_VCPU_IND_DATA_BASE_IDX 1 417 418 419// addressBlock: uvd_uvd_mpcdec 420// base address: 0x1ff30 421#define regUVD_MP_SWAP_CNTL 0x01cc 422#define regUVD_MP_SWAP_CNTL_BASE_IDX 1 423#define regUVD_MP_SWAP_CNTL2 0x01cd 424#define regUVD_MP_SWAP_CNTL2_BASE_IDX 1 425#define regUVD_MPC_LUMA_SRCH 0x01ce 426#define regUVD_MPC_LUMA_SRCH_BASE_IDX 1 427#define regUVD_MPC_LUMA_HIT 0x01cf 428#define regUVD_MPC_LUMA_HIT_BASE_IDX 1 429#define regUVD_MPC_LUMA_HITPEND 0x01d0 430#define regUVD_MPC_LUMA_HITPEND_BASE_IDX 1 431#define regUVD_MPC_CHROMA_SRCH 0x01d1 432#define regUVD_MPC_CHROMA_SRCH_BASE_IDX 1 433#define regUVD_MPC_CHROMA_HIT 0x01d2 434#define regUVD_MPC_CHROMA_HIT_BASE_IDX 1 435#define regUVD_MPC_CHROMA_HITPEND 0x01d3 436#define regUVD_MPC_CHROMA_HITPEND_BASE_IDX 1 437#define regUVD_MPC_CNTL 0x01d4 438#define regUVD_MPC_CNTL_BASE_IDX 1 439#define regUVD_MPC_PITCH 0x01d5 440#define regUVD_MPC_PITCH_BASE_IDX 1 441#define regUVD_MPC_SET_MUXA0 0x01d6 442#define regUVD_MPC_SET_MUXA0_BASE_IDX 1 443#define regUVD_MPC_SET_MUXA1 0x01d7 444#define regUVD_MPC_SET_MUXA1_BASE_IDX 1 445#define regUVD_MPC_SET_MUXB0 0x01d8 446#define regUVD_MPC_SET_MUXB0_BASE_IDX 1 447#define regUVD_MPC_SET_MUXB1 0x01d9 448#define regUVD_MPC_SET_MUXB1_BASE_IDX 1 449#define regUVD_MPC_SET_MUX 0x01da 450#define regUVD_MPC_SET_MUX_BASE_IDX 1 451#define regUVD_MPC_SET_ALU 0x01db 452#define regUVD_MPC_SET_ALU_BASE_IDX 1 453#define regUVD_MPC_PERF0 0x01dc 454#define regUVD_MPC_PERF0_BASE_IDX 1 455#define regUVD_MPC_PERF1 0x01dd 456#define regUVD_MPC_PERF1_BASE_IDX 1 457#define regUVD_MPC_IND_INDEX 0x01df 458#define regUVD_MPC_IND_INDEX_BASE_IDX 1 459#define regUVD_MPC_IND_DATA 0x01e0 460#define regUVD_MPC_IND_DATA_BASE_IDX 1 461 462 463// addressBlock: uvd_uvd_rbcdec 464// base address: 0x1ff90 465#define regUVD_RBC_IB_SIZE 0x01e4 466#define regUVD_RBC_IB_SIZE_BASE_IDX 1 467#define regUVD_RBC_IB_SIZE_UPDATE 0x01e5 468#define regUVD_RBC_IB_SIZE_UPDATE_BASE_IDX 1 469#define regUVD_RBC_RB_CNTL 0x01e6 470#define regUVD_RBC_RB_CNTL_BASE_IDX 1 471#define regUVD_RBC_RB_RPTR_ADDR 0x01e7 472#define regUVD_RBC_RB_RPTR_ADDR_BASE_IDX 1 473#define regUVD_RBC_VCPU_ACCESS 0x01ea 474#define regUVD_RBC_VCPU_ACCESS_BASE_IDX 1 475#define regUVD_RBC_READ_REQ_URGENT_CNTL 0x01ed 476#define regUVD_RBC_READ_REQ_URGENT_CNTL_BASE_IDX 1 477#define regUVD_RBC_RB_WPTR_CNTL 0x01ee 478#define regUVD_RBC_RB_WPTR_CNTL_BASE_IDX 1 479#define regUVD_RBC_WPTR_STATUS 0x01ef 480#define regUVD_RBC_WPTR_STATUS_BASE_IDX 1 481#define regUVD_RBC_WPTR_POLL_CNTL 0x01f0 482#define regUVD_RBC_WPTR_POLL_CNTL_BASE_IDX 1 483#define regUVD_RBC_WPTR_POLL_ADDR 0x01f1 484#define regUVD_RBC_WPTR_POLL_ADDR_BASE_IDX 1 485#define regUVD_SEMA_CMD 0x01f2 486#define regUVD_SEMA_CMD_BASE_IDX 1 487#define regUVD_SEMA_ADDR_LOW 0x01f3 488#define regUVD_SEMA_ADDR_LOW_BASE_IDX 1 489#define regUVD_SEMA_ADDR_HIGH 0x01f4 490#define regUVD_SEMA_ADDR_HIGH_BASE_IDX 1 491#define regUVD_ENGINE_CNTL 0x01f5 492#define regUVD_ENGINE_CNTL_BASE_IDX 1 493#define regUVD_SEMA_TIMEOUT_STATUS 0x01f6 494#define regUVD_SEMA_TIMEOUT_STATUS_BASE_IDX 1 495#define regUVD_SEMA_CNTL 0x01f7 496#define regUVD_SEMA_CNTL_BASE_IDX 1 497#define regUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x01f8 498#define regUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 499#define regUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x01f9 500#define regUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX 1 501#define regUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x01fa 502#define regUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 503#define regUVD_JOB_START 0x01fb 504#define regUVD_JOB_START_BASE_IDX 1 505#define regUVD_RBC_BUF_STATUS 0x01fc 506#define regUVD_RBC_BUF_STATUS_BASE_IDX 1 507#define regUVD_RBC_SWAP_CNTL 0x01fd 508#define regUVD_RBC_SWAP_CNTL_BASE_IDX 1 509 510 511// addressBlock: uvd_lmi_adpdec 512// base address: 0x20090 513#define regUVD_LMI_RE_64BIT_BAR_LOW 0x0224 514#define regUVD_LMI_RE_64BIT_BAR_LOW_BASE_IDX 1 515#define regUVD_LMI_RE_64BIT_BAR_HIGH 0x0225 516#define regUVD_LMI_RE_64BIT_BAR_HIGH_BASE_IDX 1 517#define regUVD_LMI_IT_64BIT_BAR_LOW 0x0226 518#define regUVD_LMI_IT_64BIT_BAR_LOW_BASE_IDX 1 519#define regUVD_LMI_IT_64BIT_BAR_HIGH 0x0227 520#define regUVD_LMI_IT_64BIT_BAR_HIGH_BASE_IDX 1 521#define regUVD_LMI_MP_64BIT_BAR_LOW 0x0228 522#define regUVD_LMI_MP_64BIT_BAR_LOW_BASE_IDX 1 523#define regUVD_LMI_MP_64BIT_BAR_HIGH 0x0229 524#define regUVD_LMI_MP_64BIT_BAR_HIGH_BASE_IDX 1 525#define regUVD_LMI_CM_64BIT_BAR_LOW 0x022a 526#define regUVD_LMI_CM_64BIT_BAR_LOW_BASE_IDX 1 527#define regUVD_LMI_CM_64BIT_BAR_HIGH 0x022b 528#define regUVD_LMI_CM_64BIT_BAR_HIGH_BASE_IDX 1 529#define regUVD_LMI_DB_64BIT_BAR_LOW 0x022c 530#define regUVD_LMI_DB_64BIT_BAR_LOW_BASE_IDX 1 531#define regUVD_LMI_DB_64BIT_BAR_HIGH 0x022d 532#define regUVD_LMI_DB_64BIT_BAR_HIGH_BASE_IDX 1 533#define regUVD_LMI_DBW_64BIT_BAR_LOW 0x022e 534#define regUVD_LMI_DBW_64BIT_BAR_LOW_BASE_IDX 1 535#define regUVD_LMI_DBW_64BIT_BAR_HIGH 0x022f 536#define regUVD_LMI_DBW_64BIT_BAR_HIGH_BASE_IDX 1 537#define regUVD_LMI_IDCT_64BIT_BAR_LOW 0x0230 538#define regUVD_LMI_IDCT_64BIT_BAR_LOW_BASE_IDX 1 539#define regUVD_LMI_IDCT_64BIT_BAR_HIGH 0x0231 540#define regUVD_LMI_IDCT_64BIT_BAR_HIGH_BASE_IDX 1 541#define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW 0x0232 542#define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW_BASE_IDX 1 543#define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH 0x0233 544#define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH_BASE_IDX 1 545#define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW 0x0234 546#define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW_BASE_IDX 1 547#define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH 0x0235 548#define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH_BASE_IDX 1 549#define regUVD_LMI_MPC_64BIT_BAR_LOW 0x0238 550#define regUVD_LMI_MPC_64BIT_BAR_LOW_BASE_IDX 1 551#define regUVD_LMI_MPC_64BIT_BAR_HIGH 0x0239 552#define regUVD_LMI_MPC_64BIT_BAR_HIGH_BASE_IDX 1 553#define regUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x023a 554#define regUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1 555#define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x023b 556#define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 557#define regUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x023c 558#define regUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1 559#define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x023d 560#define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 561#define regUVD_LMI_LBSI_64BIT_BAR_LOW 0x023e 562#define regUVD_LMI_LBSI_64BIT_BAR_LOW_BASE_IDX 1 563#define regUVD_LMI_LBSI_64BIT_BAR_HIGH 0x023f 564#define regUVD_LMI_LBSI_64BIT_BAR_HIGH_BASE_IDX 1 565#define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW 0x0240 566#define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX 1 567#define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 0x0241 568#define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX 1 569#define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW 0x0242 570#define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX 1 571#define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 0x0243 572#define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX 1 573#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x0244 574#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 575#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x0245 576#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 577#define regUVD_LMI_CENC_64BIT_BAR_LOW 0x0246 578#define regUVD_LMI_CENC_64BIT_BAR_LOW_BASE_IDX 1 579#define regUVD_LMI_CENC_64BIT_BAR_HIGH 0x0247 580#define regUVD_LMI_CENC_64BIT_BAR_HIGH_BASE_IDX 1 581#define regUVD_LMI_SRE_64BIT_BAR_LOW 0x0248 582#define regUVD_LMI_SRE_64BIT_BAR_LOW_BASE_IDX 1 583#define regUVD_LMI_SRE_64BIT_BAR_HIGH 0x0249 584#define regUVD_LMI_SRE_64BIT_BAR_HIGH_BASE_IDX 1 585#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW 0x024a 586#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW_BASE_IDX 1 587#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH 0x024b 588#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH_BASE_IDX 1 589#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW 0x024c 590#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW_BASE_IDX 1 591#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH 0x024d 592#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 593#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW 0x024e 594#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 595#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH 0x024f 596#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 597#define regUVD_LMI_MIF_REF_64BIT_BAR_LOW 0x0250 598#define regUVD_LMI_MIF_REF_64BIT_BAR_LOW_BASE_IDX 1 599#define regUVD_LMI_MIF_REF_64BIT_BAR_HIGH 0x0251 600#define regUVD_LMI_MIF_REF_64BIT_BAR_HIGH_BASE_IDX 1 601#define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW 0x0252 602#define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW_BASE_IDX 1 603#define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH 0x0253 604#define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH_BASE_IDX 1 605#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW 0x0254 606#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW_BASE_IDX 1 607#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH 0x0255 608#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH_BASE_IDX 1 609#define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW 0x0256 610#define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW_BASE_IDX 1 611#define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH 0x0257 612#define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH_BASE_IDX 1 613#define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW 0x0258 614#define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW_BASE_IDX 1 615#define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH 0x0259 616#define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH_BASE_IDX 1 617#define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW 0x025a 618#define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW_BASE_IDX 1 619#define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH 0x025b 620#define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH_BASE_IDX 1 621#define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW 0x025c 622#define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW_BASE_IDX 1 623#define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH 0x025d 624#define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH_BASE_IDX 1 625#define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW 0x025e 626#define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW_BASE_IDX 1 627#define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH 0x025f 628#define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH_BASE_IDX 1 629#define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW 0x0260 630#define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW_BASE_IDX 1 631#define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH 0x0261 632#define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH_BASE_IDX 1 633#define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW 0x0262 634#define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW_BASE_IDX 1 635#define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH 0x0263 636#define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH_BASE_IDX 1 637#define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW 0x0264 638#define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW_BASE_IDX 1 639#define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH 0x0265 640#define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH_BASE_IDX 1 641#define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW 0x0266 642#define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW_BASE_IDX 1 643#define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH 0x0267 644#define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH_BASE_IDX 1 645#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x0270 646#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1 647#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x0271 648#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1 649#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 0x0272 650#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX 1 651#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 0x0273 652#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX 1 653#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x0274 654#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1 655#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x0275 656#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1 657#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 0x0276 658#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX 1 659#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 0x0277 660#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX 1 661#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 0x0278 662#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX 1 663#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 0x0279 664#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX 1 665#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 0x027a 666#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX 1 667#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 0x027b 668#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX 1 669#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 0x027c 670#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX 1 671#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 0x027d 672#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX 1 673#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 0x027e 674#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX 1 675#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 0x027f 676#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX 1 677#define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW 0x0280 678#define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW_BASE_IDX 1 679#define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH 0x0281 680#define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH_BASE_IDX 1 681#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW 0x0282 682#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW_BASE_IDX 1 683#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH 0x0283 684#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH_BASE_IDX 1 685#define regUVD_LMI_SPH_64BIT_BAR_HIGH 0x0284 686#define regUVD_LMI_SPH_64BIT_BAR_HIGH_BASE_IDX 1 687#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW 0x0298 688#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW_BASE_IDX 1 689#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH 0x0299 690#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 691#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW 0x029a 692#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 693#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH 0x029b 694#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 695#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW 0x029c 696#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW_BASE_IDX 1 697#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH 0x029d 698#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 699#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW 0x029e 700#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 701#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH 0x029f 702#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 703#define regUVD_LMI_ARB_CTRL2 0x02a2 704#define regUVD_LMI_ARB_CTRL2_BASE_IDX 1 705#define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI 0x02a7 706#define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX 1 707#define regUVD_LMI_VCPU_NC_VMIDS_MULTI 0x02a8 708#define regUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX 1 709#define regUVD_LMI_LAT_CTRL 0x02a9 710#define regUVD_LMI_LAT_CTRL_BASE_IDX 1 711#define regUVD_LMI_LAT_CNTR 0x02aa 712#define regUVD_LMI_LAT_CNTR_BASE_IDX 1 713#define regUVD_LMI_AVG_LAT_CNTR 0x02ab 714#define regUVD_LMI_AVG_LAT_CNTR_BASE_IDX 1 715#define regUVD_LMI_SPH 0x02ac 716#define regUVD_LMI_SPH_BASE_IDX 1 717#define regUVD_LMI_VCPU_CACHE_VMID 0x02ad 718#define regUVD_LMI_VCPU_CACHE_VMID_BASE_IDX 1 719#define regUVD_LMI_CTRL2 0x02ae 720#define regUVD_LMI_CTRL2_BASE_IDX 1 721#define regUVD_LMI_URGENT_CTRL 0x02af 722#define regUVD_LMI_URGENT_CTRL_BASE_IDX 1 723#define regUVD_LMI_CTRL 0x02b0 724#define regUVD_LMI_CTRL_BASE_IDX 1 725#define regUVD_LMI_STATUS 0x02b1 726#define regUVD_LMI_STATUS_BASE_IDX 1 727#define regUVD_LMI_PERFMON_CTRL 0x02b4 728#define regUVD_LMI_PERFMON_CTRL_BASE_IDX 1 729#define regUVD_LMI_PERFMON_COUNT_LO 0x02b5 730#define regUVD_LMI_PERFMON_COUNT_LO_BASE_IDX 1 731#define regUVD_LMI_PERFMON_COUNT_HI 0x02b6 732#define regUVD_LMI_PERFMON_COUNT_HI_BASE_IDX 1 733#define regUVD_LMI_ADP_SWAP_CNTL 0x02b7 734#define regUVD_LMI_ADP_SWAP_CNTL_BASE_IDX 1 735#define regUVD_LMI_RBC_RB_VMID 0x02b8 736#define regUVD_LMI_RBC_RB_VMID_BASE_IDX 1 737#define regUVD_LMI_RBC_IB_VMID 0x02b9 738#define regUVD_LMI_RBC_IB_VMID_BASE_IDX 1 739#define regUVD_LMI_MC_CREDITS 0x02ba 740#define regUVD_LMI_MC_CREDITS_BASE_IDX 1 741#define regUVD_LMI_ADP_IND_INDEX 0x02be 742#define regUVD_LMI_ADP_IND_INDEX_BASE_IDX 1 743#define regUVD_LMI_ADP_IND_DATA 0x02bf 744#define regUVD_LMI_ADP_IND_DATA_BASE_IDX 1 745#define regUVD_LMI_ADP_PF_EN 0x02c0 746#define regUVD_LMI_ADP_PF_EN_BASE_IDX 1 747#define regUVD_LMI_PREF_CTRL 0x02c2 748#define regUVD_LMI_PREF_CTRL_BASE_IDX 1 749#define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW 0x02dd 750#define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW_BASE_IDX 1 751#define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH 0x02de 752#define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 753 754 755// addressBlock: uvd_jpegnpdec 756// base address: 0x20f00 757#define regUVD_JPEG_CNTL 0x05c0 758#define regUVD_JPEG_CNTL_BASE_IDX 1 759#define regUVD_JPEG_RB_BASE 0x05c1 760#define regUVD_JPEG_RB_BASE_BASE_IDX 1 761#define regUVD_JPEG_RB_WPTR 0x05c2 762#define regUVD_JPEG_RB_WPTR_BASE_IDX 1 763#define regUVD_JPEG_RB_RPTR 0x05c3 764#define regUVD_JPEG_RB_RPTR_BASE_IDX 1 765#define regUVD_JPEG_RB_SIZE 0x05c4 766#define regUVD_JPEG_RB_SIZE_BASE_IDX 1 767#define regUVD_JPEG_SPS_INFO 0x05c6 768#define regUVD_JPEG_SPS_INFO_BASE_IDX 1 769#define regUVD_JPEG_SPS1_INFO 0x05c7 770#define regUVD_JPEG_SPS1_INFO_BASE_IDX 1 771#define regUVD_JPEG_RE_TIMER 0x05c8 772#define regUVD_JPEG_RE_TIMER_BASE_IDX 1 773#define regUVD_JPEG_INT_EN 0x05ca 774#define regUVD_JPEG_INT_EN_BASE_IDX 1 775#define regUVD_JPEG_INT_STAT 0x05cb 776#define regUVD_JPEG_INT_STAT_BASE_IDX 1 777#define regUVD_JPEG_TIER_CNTL0 0x05cd 778#define regUVD_JPEG_TIER_CNTL0_BASE_IDX 1 779#define regUVD_JPEG_TIER_CNTL1 0x05ce 780#define regUVD_JPEG_TIER_CNTL1_BASE_IDX 1 781#define regUVD_JPEG_TIER_CNTL2 0x05cf 782#define regUVD_JPEG_TIER_CNTL2_BASE_IDX 1 783#define regUVD_JPEG_TIER_STATUS 0x05d0 784#define regUVD_JPEG_TIER_STATUS_BASE_IDX 1 785#define regUVD_JPEG_OUTBUF_CNTL 0x05dc 786#define regUVD_JPEG_OUTBUF_CNTL_BASE_IDX 1 787#define regUVD_JPEG_OUTBUF_WPTR 0x05dd 788#define regUVD_JPEG_OUTBUF_WPTR_BASE_IDX 1 789#define regUVD_JPEG_OUTBUF_RPTR 0x05de 790#define regUVD_JPEG_OUTBUF_RPTR_BASE_IDX 1 791#define regUVD_JPEG_PITCH 0x05df 792#define regUVD_JPEG_PITCH_BASE_IDX 1 793#define regUVD_JPEG_UV_PITCH 0x05e0 794#define regUVD_JPEG_UV_PITCH_BASE_IDX 1 795#define regJPEG_DEC_Y_GFX8_TILING_SURFACE 0x05e1 796#define regJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX 1 797#define regJPEG_DEC_UV_GFX8_TILING_SURFACE 0x05e2 798#define regJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX 1 799#define regJPEG_DEC_GFX8_ADDR_CONFIG 0x05e3 800#define regJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX 1 801#define regJPEG_DEC_Y_GFX10_TILING_SURFACE 0x05e4 802#define regJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX 1 803#define regJPEG_DEC_UV_GFX10_TILING_SURFACE 0x05e5 804#define regJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX 1 805#define regJPEG_DEC_GFX10_ADDR_CONFIG 0x05e6 806#define regJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX 1 807#define regJPEG_DEC_ADDR_MODE 0x05e7 808#define regJPEG_DEC_ADDR_MODE_BASE_IDX 1 809#define regUVD_JPEG_OUTPUT_XY 0x05e8 810#define regUVD_JPEG_OUTPUT_XY_BASE_IDX 1 811#define regUVD_JPEG_GPCOM_CMD 0x05e9 812#define regUVD_JPEG_GPCOM_CMD_BASE_IDX 1 813#define regUVD_JPEG_GPCOM_DATA0 0x05ea 814#define regUVD_JPEG_GPCOM_DATA0_BASE_IDX 1 815#define regUVD_JPEG_GPCOM_DATA1 0x05eb 816#define regUVD_JPEG_GPCOM_DATA1_BASE_IDX 1 817#define regUVD_JPEG_INDEX 0x05ec 818#define regUVD_JPEG_INDEX_BASE_IDX 1 819#define regUVD_JPEG_DATA 0x05ed 820#define regUVD_JPEG_DATA_BASE_IDX 1 821#define regUVD_JPEG_SCRATCH1 0x05ee 822#define regUVD_JPEG_SCRATCH1_BASE_IDX 1 823 824 825// addressBlock: uvd_uvd_jrbc_dec 826// base address: 0x21100 827#define regUVD_JRBC_RB_WPTR 0x0640 828#define regUVD_JRBC_RB_WPTR_BASE_IDX 1 829#define regUVD_JRBC_RB_CNTL 0x0641 830#define regUVD_JRBC_RB_CNTL_BASE_IDX 1 831#define regUVD_JRBC_IB_SIZE 0x0642 832#define regUVD_JRBC_IB_SIZE_BASE_IDX 1 833#define regUVD_JRBC_URGENT_CNTL 0x0643 834#define regUVD_JRBC_URGENT_CNTL_BASE_IDX 1 835#define regUVD_JRBC_RB_REF_DATA 0x0644 836#define regUVD_JRBC_RB_REF_DATA_BASE_IDX 1 837#define regUVD_JRBC_RB_COND_RD_TIMER 0x0645 838#define regUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 1 839#define regUVD_JRBC_SOFT_RESET 0x0648 840#define regUVD_JRBC_SOFT_RESET_BASE_IDX 1 841#define regUVD_JRBC_STATUS 0x0649 842#define regUVD_JRBC_STATUS_BASE_IDX 1 843#define regUVD_JRBC_RB_RPTR 0x064a 844#define regUVD_JRBC_RB_RPTR_BASE_IDX 1 845#define regUVD_JRBC_RB_BUF_STATUS 0x064b 846#define regUVD_JRBC_RB_BUF_STATUS_BASE_IDX 1 847#define regUVD_JRBC_IB_BUF_STATUS 0x064c 848#define regUVD_JRBC_IB_BUF_STATUS_BASE_IDX 1 849#define regUVD_JRBC_IB_SIZE_UPDATE 0x064d 850#define regUVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 1 851#define regUVD_JRBC_IB_COND_RD_TIMER 0x064e 852#define regUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 1 853#define regUVD_JRBC_IB_REF_DATA 0x064f 854#define regUVD_JRBC_IB_REF_DATA_BASE_IDX 1 855#define regUVD_JPEG_PREEMPT_CMD 0x0650 856#define regUVD_JPEG_PREEMPT_CMD_BASE_IDX 1 857#define regUVD_JPEG_PREEMPT_FENCE_DATA0 0x0651 858#define regUVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 1 859#define regUVD_JPEG_PREEMPT_FENCE_DATA1 0x0652 860#define regUVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 1 861#define regUVD_JRBC_RB_SIZE 0x0653 862#define regUVD_JRBC_RB_SIZE_BASE_IDX 1 863#define regUVD_JRBC_SCRATCH0 0x0654 864#define regUVD_JRBC_SCRATCH0_BASE_IDX 1 865 866 867// addressBlock: uvd_uvd_jmi_dec 868// base address: 0x21200 869#define regUVD_JADP_MCIF_URGENT_CTRL 0x0681 870#define regUVD_JADP_MCIF_URGENT_CTRL_BASE_IDX 1 871#define regUVD_JMI_URGENT_CTRL 0x0682 872#define regUVD_JMI_URGENT_CTRL_BASE_IDX 1 873#define regUVD_JPEG_ENC_PF_CTRL 0x0684 874#define regUVD_JPEG_ENC_PF_CTRL_BASE_IDX 1 875#define regUVD_JMI_CTRL 0x0685 876#define regUVD_JMI_CTRL_BASE_IDX 1 877#define regUVD_LMI_JRBC_CTRL 0x0686 878#define regUVD_LMI_JRBC_CTRL_BASE_IDX 1 879#define regUVD_LMI_JPEG_CTRL 0x0687 880#define regUVD_LMI_JPEG_CTRL_BASE_IDX 1 881#define regUVD_JMI_EJRBC_CTRL 0x0688 882#define regUVD_JMI_EJRBC_CTRL_BASE_IDX 1 883#define regUVD_LMI_EJPEG_CTRL 0x0689 884#define regUVD_LMI_EJPEG_CTRL_BASE_IDX 1 885#define regUVD_JMI_SCALER_CTRL 0x068a 886#define regUVD_JMI_SCALER_CTRL_BASE_IDX 1 887#define regJPEG_LMI_DROP 0x068b 888#define regJPEG_LMI_DROP_BASE_IDX 1 889#define regUVD_JMI_EJPEG_DROP 0x068c 890#define regUVD_JMI_EJPEG_DROP_BASE_IDX 1 891#define regJPEG_MEMCHECK_CLAMPING 0x068d 892#define regJPEG_MEMCHECK_CLAMPING_BASE_IDX 1 893#define regUVD_JMI_EJPEG_MEMCHECK_CLAMPING 0x068e 894#define regUVD_JMI_EJPEG_MEMCHECK_CLAMPING_BASE_IDX 1 895#define regUVD_LMI_JRBC_IB_VMID 0x068f 896#define regUVD_LMI_JRBC_IB_VMID_BASE_IDX 1 897#define regUVD_LMI_JRBC_RB_VMID 0x0690 898#define regUVD_LMI_JRBC_RB_VMID_BASE_IDX 1 899#define regUVD_LMI_JPEG_VMID 0x0691 900#define regUVD_LMI_JPEG_VMID_BASE_IDX 1 901#define regUVD_JMI_ENC_JRBC_IB_VMID 0x0692 902#define regUVD_JMI_ENC_JRBC_IB_VMID_BASE_IDX 1 903#define regUVD_JMI_ENC_JRBC_RB_VMID 0x0693 904#define regUVD_JMI_ENC_JRBC_RB_VMID_BASE_IDX 1 905#define regUVD_JMI_ENC_JPEG_VMID 0x0694 906#define regUVD_JMI_ENC_JPEG_VMID_BASE_IDX 1 907#define regJPEG_MEMCHECK_SAFE_ADDR 0x0697 908#define regJPEG_MEMCHECK_SAFE_ADDR_BASE_IDX 1 909#define regJPEG_MEMCHECK_SAFE_ADDR_64BIT 0x0698 910#define regJPEG_MEMCHECK_SAFE_ADDR_64BIT_BASE_IDX 1 911#define regUVD_JMI_LAT_CTRL 0x0699 912#define regUVD_JMI_LAT_CTRL_BASE_IDX 1 913#define regUVD_JMI_LAT_CNTR 0x069a 914#define regUVD_JMI_LAT_CNTR_BASE_IDX 1 915#define regUVD_JMI_AVG_LAT_CNTR 0x069b 916#define regUVD_JMI_AVG_LAT_CNTR_BASE_IDX 1 917#define regUVD_JMI_PERFMON_CTRL 0x069c 918#define regUVD_JMI_PERFMON_CTRL_BASE_IDX 1 919#define regUVD_JMI_PERFMON_COUNT_LO 0x069d 920#define regUVD_JMI_PERFMON_COUNT_LO_BASE_IDX 1 921#define regUVD_JMI_PERFMON_COUNT_HI 0x069e 922#define regUVD_JMI_PERFMON_COUNT_HI_BASE_IDX 1 923#define regUVD_JMI_CLEAN_STATUS 0x069f 924#define regUVD_JMI_CLEAN_STATUS_BASE_IDX 1 925#define regUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x06a0 926#define regUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 1 927#define regUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x06a1 928#define regUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 1 929#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x06a2 930#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 1 931#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x06a3 932#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 1 933#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x06a4 934#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 1 935#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x06a5 936#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 1 937#define regUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x06a6 938#define regUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 1 939#define regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x06a7 940#define regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 941#define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x06a8 942#define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 1 943#define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x06a9 944#define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 945#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x06aa 946#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 1 947#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x06ab 948#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 1 949#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 0x06ac 950#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 1 951#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x06ad 952#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 1 953#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x06ae 954#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 1 955#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x06af 956#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 1 957#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 0x06b0 958#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 1 959#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x06b1 960#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 1 961#define regUVD_JMI_PEL_RD_64BIT_BAR_LOW 0x06b2 962#define regUVD_JMI_PEL_RD_64BIT_BAR_LOW_BASE_IDX 1 963#define regUVD_JMI_PEL_RD_64BIT_BAR_HIGH 0x06b3 964#define regUVD_JMI_PEL_RD_64BIT_BAR_HIGH_BASE_IDX 1 965#define regUVD_JMI_BS_WR_64BIT_BAR_LOW 0x06b4 966#define regUVD_JMI_BS_WR_64BIT_BAR_LOW_BASE_IDX 1 967#define regUVD_JMI_BS_WR_64BIT_BAR_HIGH 0x06b5 968#define regUVD_JMI_BS_WR_64BIT_BAR_HIGH_BASE_IDX 1 969#define regUVD_JMI_SCALAR_RD_64BIT_BAR_LOW 0x06b6 970#define regUVD_JMI_SCALAR_RD_64BIT_BAR_LOW_BASE_IDX 1 971#define regUVD_JMI_SCALAR_RD_64BIT_BAR_HIGH 0x06b7 972#define regUVD_JMI_SCALAR_RD_64BIT_BAR_HIGH_BASE_IDX 1 973#define regUVD_JMI_SCALAR_WR_64BIT_BAR_LOW 0x06b8 974#define regUVD_JMI_SCALAR_WR_64BIT_BAR_LOW_BASE_IDX 1 975#define regUVD_JMI_SCALAR_WR_64BIT_BAR_HIGH 0x06b9 976#define regUVD_JMI_SCALAR_WR_64BIT_BAR_HIGH_BASE_IDX 1 977#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x06ba 978#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 1 979#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x06bb 980#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 1 981#define regUVD_LMI_EJRBC_RB_64BIT_BAR_LOW 0x06bc 982#define regUVD_LMI_EJRBC_RB_64BIT_BAR_LOW_BASE_IDX 1 983#define regUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 0x06bd 984#define regUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 985#define regUVD_LMI_EJRBC_IB_64BIT_BAR_LOW 0x06be 986#define regUVD_LMI_EJRBC_IB_64BIT_BAR_LOW_BASE_IDX 1 987#define regUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 0x06bf 988#define regUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 989#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 0x06c0 990#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 1 991#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x06c1 992#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 1 993#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 0x06c2 994#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 1 995#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x06c3 996#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 1 997#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 0x06c4 998#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 1 999#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x06c5 1000#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 1 1001#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 0x06c6 1002#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 1 1003#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x06c7 1004#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 1 1005#define regUVD_LMI_JPEG_PREEMPT_VMID 0x06c8 1006#define regUVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 1 1007#define regUVD_LMI_ENC_JPEG_PREEMPT_VMID 0x06c9 1008#define regUVD_LMI_ENC_JPEG_PREEMPT_VMID_BASE_IDX 1 1009#define regUVD_LMI_JPEG2_VMID 0x06ca 1010#define regUVD_LMI_JPEG2_VMID_BASE_IDX 1 1011#define regUVD_LMI_JPEG2_READ_64BIT_BAR_LOW 0x06cb 1012#define regUVD_LMI_JPEG2_READ_64BIT_BAR_LOW_BASE_IDX 1 1013#define regUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 0x06cc 1014#define regUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH_BASE_IDX 1 1015#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 0x06cd 1016#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW_BASE_IDX 1 1017#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 0x06ce 1018#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH_BASE_IDX 1 1019#define regUVD_LMI_JPEG_CTRL2 0x06cf 1020#define regUVD_LMI_JPEG_CTRL2_BASE_IDX 1 1021#define regUVD_JMI_DEC_SWAP_CNTL 0x06d0 1022#define regUVD_JMI_DEC_SWAP_CNTL_BASE_IDX 1 1023#define regUVD_JMI_ENC_SWAP_CNTL 0x06d1 1024#define regUVD_JMI_ENC_SWAP_CNTL_BASE_IDX 1 1025#define regUVD_JMI_CNTL 0x06d2 1026#define regUVD_JMI_CNTL_BASE_IDX 1 1027#define regUVD_JMI_ATOMIC_CNTL 0x06d3 1028#define regUVD_JMI_ATOMIC_CNTL_BASE_IDX 1 1029#define regUVD_JMI_ATOMIC_CNTL2 0x06d4 1030#define regUVD_JMI_ATOMIC_CNTL2_BASE_IDX 1 1031#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 0x06d5 1032#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX 1 1033#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 0x06d6 1034#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX 1 1035#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW 0x06d7 1036#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW_BASE_IDX 1 1037#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH 0x06d8 1038#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH_BASE_IDX 1 1039#define regJPEG2_LMI_DROP 0x06d9 1040#define regJPEG2_LMI_DROP_BASE_IDX 1 1041#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 0x06da 1042#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW_BASE_IDX 1 1043#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 0x06db 1044#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH_BASE_IDX 1 1045#define regUVD_JMI_DEC_SWAP_CNTL2 0x06dc 1046#define regUVD_JMI_DEC_SWAP_CNTL2_BASE_IDX 1 1047#define regUVD_JMI_DJPEG_RAS_CNTL 0x06dd 1048#define regUVD_JMI_DJPEG_RAS_CNTL_BASE_IDX 1 1049#define regUVD_JMI_EJPEG_RAS_CNTL 0x06de 1050#define regUVD_JMI_EJPEG_RAS_CNTL_BASE_IDX 1 1051#define regUVD_JPEG_DEC2_PF_CTRL 0x06df 1052#define regUVD_JPEG_DEC2_PF_CTRL_BASE_IDX 1 1053 1054 1055// addressBlock: uvd_uvd_jpeg_common_dec 1056// base address: 0x21400 1057#define regJPEG_SOFT_RESET_STATUS 0x0700 1058#define regJPEG_SOFT_RESET_STATUS_BASE_IDX 1 1059#define regJPEG_SYS_INT_EN 0x0701 1060#define regJPEG_SYS_INT_EN_BASE_IDX 1 1061#define regJPEG_SYS_INT_STATUS 0x0702 1062#define regJPEG_SYS_INT_STATUS_BASE_IDX 1 1063#define regJPEG_SYS_INT_ACK 0x0703 1064#define regJPEG_SYS_INT_ACK_BASE_IDX 1 1065#define regJPEG_MEMCHECK_SYS_INT_EN 0x0704 1066#define regJPEG_MEMCHECK_SYS_INT_EN_BASE_IDX 1 1067#define regJPEG_MEMCHECK_SYS_INT_STAT 0x0705 1068#define regJPEG_MEMCHECK_SYS_INT_STAT_BASE_IDX 1 1069#define regJPEG_MEMCHECK_SYS_INT_ACK 0x0706 1070#define regJPEG_MEMCHECK_SYS_INT_ACK_BASE_IDX 1 1071#define regUVD_JPEG_IOV_ACTIVE_FCN_ID 0x0707 1072#define regUVD_JPEG_IOV_ACTIVE_FCN_ID_BASE_IDX 1 1073#define regJPEG_MASTINT_EN 0x0708 1074#define regJPEG_MASTINT_EN_BASE_IDX 1 1075#define regJPEG_IH_CTRL 0x0709 1076#define regJPEG_IH_CTRL_BASE_IDX 1 1077#define regJRBBM_ARB_CTRL 0x070b 1078#define regJRBBM_ARB_CTRL_BASE_IDX 1 1079 1080 1081// addressBlock: uvd_uvd_jpeg_common_sclk_dec 1082// base address: 0x21480 1083#define regJPEG_CGC_GATE 0x0720 1084#define regJPEG_CGC_GATE_BASE_IDX 1 1085#define regJPEG_CGC_CTRL 0x0721 1086#define regJPEG_CGC_CTRL_BASE_IDX 1 1087#define regJPEG_CGC_STATUS 0x0722 1088#define regJPEG_CGC_STATUS_BASE_IDX 1 1089#define regJPEG_COMN_CGC_MEM_CTRL 0x0723 1090#define regJPEG_COMN_CGC_MEM_CTRL_BASE_IDX 1 1091#define regJPEG_DEC_CGC_MEM_CTRL 0x0724 1092#define regJPEG_DEC_CGC_MEM_CTRL_BASE_IDX 1 1093#define regJPEG2_DEC_CGC_MEM_CTRL 0x0725 1094#define regJPEG2_DEC_CGC_MEM_CTRL_BASE_IDX 1 1095#define regJPEG_ENC_CGC_MEM_CTRL 0x0726 1096#define regJPEG_ENC_CGC_MEM_CTRL_BASE_IDX 1 1097#define regJPEG_SOFT_RESET2 0x0727 1098#define regJPEG_SOFT_RESET2_BASE_IDX 1 1099#define regJPEG_PERF_BANK_CONF 0x0728 1100#define regJPEG_PERF_BANK_CONF_BASE_IDX 1 1101#define regJPEG_PERF_BANK_EVENT_SEL 0x0729 1102#define regJPEG_PERF_BANK_EVENT_SEL_BASE_IDX 1 1103#define regJPEG_PERF_BANK_COUNT0 0x072a 1104#define regJPEG_PERF_BANK_COUNT0_BASE_IDX 1 1105#define regJPEG_PERF_BANK_COUNT1 0x072b 1106#define regJPEG_PERF_BANK_COUNT1_BASE_IDX 1 1107#define regJPEG_PERF_BANK_COUNT2 0x072c 1108#define regJPEG_PERF_BANK_COUNT2_BASE_IDX 1 1109#define regJPEG_PERF_BANK_COUNT3 0x072d 1110#define regJPEG_PERF_BANK_COUNT3_BASE_IDX 1 1111 1112 1113// addressBlock: uvd_uvd_pg_dec 1114// base address: 0x1f800 1115#define regUVD_PGFSM_CONFIG 0x0000 1116#define regUVD_PGFSM_CONFIG_BASE_IDX 1 1117#define regUVD_PGFSM_STATUS 0x0001 1118#define regUVD_PGFSM_STATUS_BASE_IDX 1 1119#define regUVD_POWER_STATUS 0x0002 1120#define regUVD_POWER_STATUS_BASE_IDX 1 1121#define regUVD_JPEG_POWER_STATUS 0x0003 1122#define regUVD_JPEG_POWER_STATUS_BASE_IDX 1 1123#define regUVD_MC_DJPEG_RD_SPACE 0x0006 1124#define regUVD_MC_DJPEG_RD_SPACE_BASE_IDX 1 1125#define regUVD_MC_DJPEG_WR_SPACE 0x0007 1126#define regUVD_MC_DJPEG_WR_SPACE_BASE_IDX 1 1127#define regUVD_PG_IND_INDEX 0x000c 1128#define regUVD_PG_IND_INDEX_BASE_IDX 1 1129#define regUVD_PG_IND_DATA 0x000e 1130#define regUVD_PG_IND_DATA_BASE_IDX 1 1131#define regCC_UVD_HARVESTING 0x000f 1132#define regCC_UVD_HARVESTING_BASE_IDX 1 1133#define regUVD_DPG_LMA_CTL 0x0011 1134#define regUVD_DPG_LMA_CTL_BASE_IDX 1 1135#define regUVD_DPG_LMA_DATA 0x0012 1136#define regUVD_DPG_LMA_DATA_BASE_IDX 1 1137#define regUVD_DPG_LMA_MASK 0x0013 1138#define regUVD_DPG_LMA_MASK_BASE_IDX 1 1139#define regUVD_DPG_PAUSE 0x0014 1140#define regUVD_DPG_PAUSE_BASE_IDX 1 1141#define regUVD_SCRATCH1 0x0015 1142#define regUVD_SCRATCH1_BASE_IDX 1 1143#define regUVD_SCRATCH2 0x0016 1144#define regUVD_SCRATCH2_BASE_IDX 1 1145#define regUVD_SCRATCH3 0x0017 1146#define regUVD_SCRATCH3_BASE_IDX 1 1147#define regUVD_SCRATCH4 0x0018 1148#define regUVD_SCRATCH4_BASE_IDX 1 1149#define regUVD_SCRATCH5 0x0019 1150#define regUVD_SCRATCH5_BASE_IDX 1 1151#define regUVD_SCRATCH6 0x001a 1152#define regUVD_SCRATCH6_BASE_IDX 1 1153#define regUVD_SCRATCH7 0x001b 1154#define regUVD_SCRATCH7_BASE_IDX 1 1155#define regUVD_SCRATCH8 0x001c 1156#define regUVD_SCRATCH8_BASE_IDX 1 1157#define regUVD_SCRATCH9 0x001d 1158#define regUVD_SCRATCH9_BASE_IDX 1 1159#define regUVD_SCRATCH10 0x001e 1160#define regUVD_SCRATCH10_BASE_IDX 1 1161#define regUVD_SCRATCH11 0x001f 1162#define regUVD_SCRATCH11_BASE_IDX 1 1163#define regUVD_SCRATCH12 0x0020 1164#define regUVD_SCRATCH12_BASE_IDX 1 1165#define regUVD_SCRATCH13 0x0021 1166#define regUVD_SCRATCH13_BASE_IDX 1 1167#define regUVD_SCRATCH14 0x0022 1168#define regUVD_SCRATCH14_BASE_IDX 1 1169#define regUVD_FREE_COUNTER_REG 0x0023 1170#define regUVD_FREE_COUNTER_REG_BASE_IDX 1 1171#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x0024 1172#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 1173#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x0025 1174#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 1175#define regUVD_DPG_VCPU_CACHE_OFFSET0 0x0026 1176#define regUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1 1177#define regUVD_DPG_LMI_VCPU_CACHE_VMID 0x0027 1178#define regUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX 1 1179#define regUVD_REG_FILTER_EN 0x0028 1180#define regUVD_REG_FILTER_EN_BASE_IDX 1 1181#define regUVD_PF_STATUS 0x002c 1182#define regUVD_PF_STATUS_BASE_IDX 1 1183#define regUVD_DPG_CLK_EN_VCPU_REPORT 0x002e 1184#define regUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX 1 1185#define regCC_UVD_VCPU_ERR_DETECT_BOT_LO 0x002f 1186#define regCC_UVD_VCPU_ERR_DETECT_BOT_LO_BASE_IDX 1 1187#define regCC_UVD_VCPU_ERR_DETECT_BOT_HI 0x0030 1188#define regCC_UVD_VCPU_ERR_DETECT_BOT_HI_BASE_IDX 1 1189#define regCC_UVD_VCPU_ERR_DETECT_TOP_LO 0x0031 1190#define regCC_UVD_VCPU_ERR_DETECT_TOP_LO_BASE_IDX 1 1191#define regCC_UVD_VCPU_ERR_DETECT_TOP_HI 0x0032 1192#define regCC_UVD_VCPU_ERR_DETECT_TOP_HI_BASE_IDX 1 1193#define regCC_UVD_VCPU_ERR 0x0033 1194#define regCC_UVD_VCPU_ERR_BASE_IDX 1 1195#define regCC_UVD_VCPU_ERR_INST_ADDR_LO 0x0034 1196#define regCC_UVD_VCPU_ERR_INST_ADDR_LO_BASE_IDX 1 1197#define regCC_UVD_VCPU_ERR_INST_ADDR_HI 0x0035 1198#define regCC_UVD_VCPU_ERR_INST_ADDR_HI_BASE_IDX 1 1199#define regUVD_LMI_MMSCH_NC_SPACE 0x003d 1200#define regUVD_LMI_MMSCH_NC_SPACE_BASE_IDX 1 1201#define regUVD_LMI_ATOMIC_SPACE 0x003e 1202#define regUVD_LMI_ATOMIC_SPACE_BASE_IDX 1 1203#define regUVD_GFX8_ADDR_CONFIG 0x0041 1204#define regUVD_GFX8_ADDR_CONFIG_BASE_IDX 1 1205#define regUVD_GFX10_ADDR_CONFIG 0x0042 1206#define regUVD_GFX10_ADDR_CONFIG_BASE_IDX 1 1207#define regUVD_GPCNT2_CNTL 0x0043 1208#define regUVD_GPCNT2_CNTL_BASE_IDX 1 1209#define regUVD_GPCNT2_TARGET_LOWER 0x0044 1210#define regUVD_GPCNT2_TARGET_LOWER_BASE_IDX 1 1211#define regUVD_GPCNT2_STATUS_LOWER 0x0045 1212#define regUVD_GPCNT2_STATUS_LOWER_BASE_IDX 1 1213#define regUVD_GPCNT2_TARGET_UPPER 0x0046 1214#define regUVD_GPCNT2_TARGET_UPPER_BASE_IDX 1 1215#define regUVD_GPCNT2_STATUS_UPPER 0x0047 1216#define regUVD_GPCNT2_STATUS_UPPER_BASE_IDX 1 1217#define regUVD_GPCNT3_CNTL 0x0048 1218#define regUVD_GPCNT3_CNTL_BASE_IDX 1 1219#define regUVD_GPCNT3_TARGET_LOWER 0x0049 1220#define regUVD_GPCNT3_TARGET_LOWER_BASE_IDX 1 1221#define regUVD_GPCNT3_STATUS_LOWER 0x004a 1222#define regUVD_GPCNT3_STATUS_LOWER_BASE_IDX 1 1223#define regUVD_GPCNT3_TARGET_UPPER 0x004b 1224#define regUVD_GPCNT3_TARGET_UPPER_BASE_IDX 1 1225#define regUVD_GPCNT3_STATUS_UPPER 0x004c 1226#define regUVD_GPCNT3_STATUS_UPPER_BASE_IDX 1 1227#define regUVD_VCLK_DS_CNTL 0x004d 1228#define regUVD_VCLK_DS_CNTL_BASE_IDX 1 1229#define regUVD_DCLK_DS_CNTL 0x004e 1230#define regUVD_DCLK_DS_CNTL_BASE_IDX 1 1231#define regUVD_TSC_LOWER 0x004f 1232#define regUVD_TSC_LOWER_BASE_IDX 1 1233#define regUVD_TSC_UPPER 0x0050 1234#define regUVD_TSC_UPPER_BASE_IDX 1 1235#define regVCN_FEATURES 0x0051 1236#define regVCN_FEATURES_BASE_IDX 1 1237#define regUVD_GPUIOV_STATUS 0x0055 1238#define regUVD_GPUIOV_STATUS_BASE_IDX 1 1239#define regUVD_SCRATCH15 0x005c 1240#define regUVD_SCRATCH15_BASE_IDX 1 1241#define regUVD_IPX_DLDO_CONFIG 0x0064 1242#define regUVD_IPX_DLDO_CONFIG_BASE_IDX 1 1243#define regUVD_IPX_DLDO_STATUS 0x0065 1244#define regUVD_IPX_DLDO_STATUS_BASE_IDX 1 1245#define regUVD_SCRATCH32 0x006d 1246#define regUVD_SCRATCH32_BASE_IDX 1 1247#define regUVD_VERSION 0x006e 1248#define regUVD_VERSION_BASE_IDX 1 1249#define regVCN_UMSCH_CNTL 0x006f 1250#define regVCN_UMSCH_CNTL_BASE_IDX 1 1251#define regVCN_RB_DB_CTRL 0x0070 1252#define regVCN_RB_DB_CTRL_BASE_IDX 1 1253#define regVCN_JPEG_DB_CTRL 0x0071 1254#define regVCN_JPEG_DB_CTRL_BASE_IDX 1 1255#define regVCN_RB1_DB_CTRL 0x0072 1256#define regVCN_RB1_DB_CTRL_BASE_IDX 1 1257#define regVCN_RB2_DB_CTRL 0x0073 1258#define regVCN_RB2_DB_CTRL_BASE_IDX 1 1259#define regVCN_RB3_DB_CTRL 0x0074 1260#define regVCN_RB3_DB_CTRL_BASE_IDX 1 1261#define regVCN_RB4_DB_CTRL 0x0075 1262#define regVCN_RB4_DB_CTRL_BASE_IDX 1 1263#define regVCN_UMSCH_RB_DB_CTRL 0x0076 1264#define regVCN_UMSCH_RB_DB_CTRL_BASE_IDX 1 1265#define regVCN_AGDB_CTRL0 0x0079 1266#define regVCN_AGDB_CTRL0_BASE_IDX 1 1267#define regVCN_AGDB_CTRL1 0x007a 1268#define regVCN_AGDB_CTRL1_BASE_IDX 1 1269#define regVCN_AGDB_CTRL2 0x007b 1270#define regVCN_AGDB_CTRL2_BASE_IDX 1 1271#define regVCN_AGDB_CTRL3 0x007c 1272#define regVCN_AGDB_CTRL3_BASE_IDX 1 1273#define regVCN_AGDB_CTRL4 0x007d 1274#define regVCN_AGDB_CTRL4_BASE_IDX 1 1275#define regVCN_AGDB_CTRL5 0x007e 1276#define regVCN_AGDB_CTRL5_BASE_IDX 1 1277#define regVCN_AGDB_MASK0 0x007f 1278#define regVCN_AGDB_MASK0_BASE_IDX 1 1279#define regVCN_AGDB_MASK1 0x0080 1280#define regVCN_AGDB_MASK1_BASE_IDX 1 1281#define regVCN_AGDB_MASK2 0x0081 1282#define regVCN_AGDB_MASK2_BASE_IDX 1 1283#define regVCN_AGDB_MASK3 0x0082 1284#define regVCN_AGDB_MASK3_BASE_IDX 1 1285#define regVCN_AGDB_MASK4 0x0083 1286#define regVCN_AGDB_MASK4_BASE_IDX 1 1287#define regVCN_AGDB_MASK5 0x0084 1288#define regVCN_AGDB_MASK5_BASE_IDX 1 1289#define regVCN_RB_ENABLE 0x0085 1290#define regVCN_RB_ENABLE_BASE_IDX 1 1291#define regVCN_RB_WPTR_CTRL 0x0086 1292#define regVCN_RB_WPTR_CTRL_BASE_IDX 1 1293#define regUVD_RB_RPTR 0x00ac 1294#define regUVD_RB_RPTR_BASE_IDX 1 1295#define regUVD_RB_WPTR 0x00ad 1296#define regUVD_RB_WPTR_BASE_IDX 1 1297#define regUVD_RB_RPTR2 0x00ae 1298#define regUVD_RB_RPTR2_BASE_IDX 1 1299#define regUVD_RB_WPTR2 0x00af 1300#define regUVD_RB_WPTR2_BASE_IDX 1 1301#define regUVD_RB_RPTR3 0x00b0 1302#define regUVD_RB_RPTR3_BASE_IDX 1 1303#define regUVD_RB_WPTR3 0x00b1 1304#define regUVD_RB_WPTR3_BASE_IDX 1 1305#define regUVD_RB_RPTR4 0x00b2 1306#define regUVD_RB_RPTR4_BASE_IDX 1 1307#define regUVD_RB_WPTR4 0x00b3 1308#define regUVD_RB_WPTR4_BASE_IDX 1 1309#define regUVD_OUT_RB_RPTR 0x00b4 1310#define regUVD_OUT_RB_RPTR_BASE_IDX 1 1311#define regUVD_OUT_RB_WPTR 0x00b5 1312#define regUVD_OUT_RB_WPTR_BASE_IDX 1 1313#define regUVD_AUDIO_RB_RPTR 0x00b6 1314#define regUVD_AUDIO_RB_RPTR_BASE_IDX 1 1315#define regUVD_AUDIO_RB_WPTR 0x00b7 1316#define regUVD_AUDIO_RB_WPTR_BASE_IDX 1 1317#define regUVD_RBC_RB_RPTR 0x00b8 1318#define regUVD_RBC_RB_RPTR_BASE_IDX 1 1319#define regUVD_RBC_RB_WPTR 0x00b9 1320#define regUVD_RBC_RB_WPTR_BASE_IDX 1 1321#define regUVD_DPG_LMA_CTL2 0x00bb 1322#define regUVD_DPG_LMA_CTL2_BASE_IDX 1 1323 1324 1325// addressBlock: uvd_vcn_umsch_dec 1326// base address: 0x21500 1327#define regVCN_UMSCH_MES_CNTL 0x0740 1328#define regVCN_UMSCH_MES_CNTL_BASE_IDX 1 1329#define regUMSCH_CTL 0x0741 1330#define regUMSCH_CTL_BASE_IDX 1 1331#define regUMSCH_CTL2 0x0742 1332#define regUMSCH_CTL2_BASE_IDX 1 1333#define regVCN_UMSCH_AGDB_WPTR0 0x0743 1334#define regVCN_UMSCH_AGDB_WPTR0_BASE_IDX 1 1335#define regVCN_UMSCH_AGDB_WPTR1 0x0744 1336#define regVCN_UMSCH_AGDB_WPTR1_BASE_IDX 1 1337#define regVCN_UMSCH_AGDB_WPTR2 0x0745 1338#define regVCN_UMSCH_AGDB_WPTR2_BASE_IDX 1 1339#define regVCN_UMSCH_AGDB_WPTR3 0x0746 1340#define regVCN_UMSCH_AGDB_WPTR3_BASE_IDX 1 1341#define regVCN_UMSCH_AGDB_WPTR4 0x0747 1342#define regVCN_UMSCH_AGDB_WPTR4_BASE_IDX 1 1343#define regVCN_UMSCH_AGDB_WPTR5 0x0748 1344#define regVCN_UMSCH_AGDB_WPTR5_BASE_IDX 1 1345#define regVCN_UMSCH_MAILBOX0 0x0749 1346#define regVCN_UMSCH_MAILBOX0_BASE_IDX 1 1347#define regVCN_UMSCH_MAILBOX_RESP0 0x074a 1348#define regVCN_UMSCH_MAILBOX_RESP0_BASE_IDX 1 1349#define regVCN_UMSCH_MAILBOX1 0x074b 1350#define regVCN_UMSCH_MAILBOX1_BASE_IDX 1 1351#define regVCN_UMSCH_MAILBOX_RESP1 0x074c 1352#define regVCN_UMSCH_MAILBOX_RESP1_BASE_IDX 1 1353#define regVCN_UMSCH_MAILBOX2 0x074d 1354#define regVCN_UMSCH_MAILBOX2_BASE_IDX 1 1355#define regVCN_UMSCH_MAILBOX_RESP2 0x074e 1356#define regVCN_UMSCH_MAILBOX_RESP2_BASE_IDX 1 1357#define regVCN_UMSCH_MAILBOX3 0x074f 1358#define regVCN_UMSCH_MAILBOX3_BASE_IDX 1 1359#define regVCN_UMSCH_MAILBOX_RESP3 0x0750 1360#define regVCN_UMSCH_MAILBOX_RESP3_BASE_IDX 1 1361#define regVCN_UMSCH_SPARE_REGISTER0 0x0751 1362#define regVCN_UMSCH_SPARE_REGISTER0_BASE_IDX 1 1363#define regVCN_UMSCH_SPARE_REGISTER1 0x0752 1364#define regVCN_UMSCH_SPARE_REGISTER1_BASE_IDX 1 1365#define regVCN_UMSCH_SPARE_REGISTER2 0x0753 1366#define regVCN_UMSCH_SPARE_REGISTER2_BASE_IDX 1 1367#define regVCN_UMSCH_SPARE_REGISTER3 0x0754 1368#define regVCN_UMSCH_SPARE_REGISTER3_BASE_IDX 1 1369#define regVCN_UMSCH_SPARE_REGISTER4 0x0755 1370#define regVCN_UMSCH_SPARE_REGISTER4_BASE_IDX 1 1371#define regVCN_UMSCH_SPARE_REGISTER5 0x0756 1372#define regVCN_UMSCH_SPARE_REGISTER5_BASE_IDX 1 1373#define regVCN_UMSCH_SPARE_REGISTER6 0x0757 1374#define regVCN_UMSCH_SPARE_REGISTER6_BASE_IDX 1 1375#define regVCN_UMSCH_SPARE_REGISTER7 0x0758 1376#define regVCN_UMSCH_SPARE_REGISTER7_BASE_IDX 1 1377#define regVCN_UMSCH_MES_UTCL1_CNTL 0x0759 1378#define regVCN_UMSCH_MES_UTCL1_CNTL_BASE_IDX 1 1379#define regVCN_UMSCH_MES_BUSY 0x075a 1380#define regVCN_UMSCH_MES_BUSY_BASE_IDX 1 1381#define regVCN_UMSCH_RB_BASE_LO 0x075b 1382#define regVCN_UMSCH_RB_BASE_LO_BASE_IDX 1 1383#define regVCN_UMSCH_RB_BASE_HI 0x075c 1384#define regVCN_UMSCH_RB_BASE_HI_BASE_IDX 1 1385#define regVCN_UMSCH_RB_SIZE 0x075d 1386#define regVCN_UMSCH_RB_SIZE_BASE_IDX 1 1387#define regVCN_UMSCH_RB_RPTR 0x075e 1388#define regVCN_UMSCH_RB_RPTR_BASE_IDX 1 1389#define regVCN_UMSCH_RB_WPTR 0x075f 1390#define regVCN_UMSCH_RB_WPTR_BASE_IDX 1 1391#define regVCN_UMSCH_MASTINT_EN 0x0760 1392#define regVCN_UMSCH_MASTINT_EN_BASE_IDX 1 1393#define regVCN_UMSCH_IH_CTRL 0x0761 1394#define regVCN_UMSCH_IH_CTRL_BASE_IDX 1 1395#define regVCN_UMSCH_SYS_INT_EN 0x0762 1396#define regVCN_UMSCH_SYS_INT_EN_BASE_IDX 1 1397#define regVCN_UMSCH_SYS_INT_STATUS 0x0763 1398#define regVCN_UMSCH_SYS_INT_STATUS_BASE_IDX 1 1399#define regVCN_UMSCH_SYS_INT_ACK 0x0764 1400#define regVCN_UMSCH_SYS_INT_ACK_BASE_IDX 1 1401#define regVCN_UMSCH_SYS_INT_SRC 0x0765 1402#define regVCN_UMSCH_SYS_INT_SRC_BASE_IDX 1 1403#define regVCN_UMSCH_IH_CTX_CTRL 0x0766 1404#define regVCN_UMSCH_IH_CTX_CTRL_BASE_IDX 1 1405#define regUVD_UMSCH_FORCE 0x076b 1406#define regUVD_UMSCH_FORCE_BASE_IDX 1 1407#define regUMSCH_MES_RESET_CTRL 0x0770 1408#define regUMSCH_MES_RESET_CTRL_BASE_IDX 1 1409 1410 1411// addressBlock: uvd_vcn_cprs64dec 1412// base address: 0x21600 1413#define regVCN_MES_PRGRM_CNTR_START 0x0780 1414#define regVCN_MES_PRGRM_CNTR_START_BASE_IDX 1 1415#define regVCN_MES_INTR_ROUTINE_START 0x0781 1416#define regVCN_MES_INTR_ROUTINE_START_BASE_IDX 1 1417#define regVCN_MES_MTVEC_LO 0x0781 1418#define regVCN_MES_MTVEC_LO_BASE_IDX 1 1419#define regVCN_MES_INTR_ROUTINE_START_HI 0x0782 1420#define regVCN_MES_INTR_ROUTINE_START_HI_BASE_IDX 1 1421#define regVCN_MES_MTVEC_HI 0x0782 1422#define regVCN_MES_MTVEC_HI_BASE_IDX 1 1423#define regVCN_MES_CNTL 0x0787 1424#define regVCN_MES_CNTL_BASE_IDX 1 1425#define regVCN_MES_PIPE_PRIORITY_CNTS 0x0788 1426#define regVCN_MES_PIPE_PRIORITY_CNTS_BASE_IDX 1 1427#define regVCN_MES_PIPE0_PRIORITY 0x0789 1428#define regVCN_MES_PIPE0_PRIORITY_BASE_IDX 1 1429#define regVCN_MES_PIPE1_PRIORITY 0x078a 1430#define regVCN_MES_PIPE1_PRIORITY_BASE_IDX 1 1431#define regVCN_MES_PIPE2_PRIORITY 0x078b 1432#define regVCN_MES_PIPE2_PRIORITY_BASE_IDX 1 1433#define regVCN_MES_PIPE3_PRIORITY 0x078c 1434#define regVCN_MES_PIPE3_PRIORITY_BASE_IDX 1 1435#define regVCN_MES_HEADER_DUMP 0x078d 1436#define regVCN_MES_HEADER_DUMP_BASE_IDX 1 1437#define regVCN_MES_MIE_LO 0x078e 1438#define regVCN_MES_MIE_LO_BASE_IDX 1 1439#define regVCN_MES_MIE_HI 0x078f 1440#define regVCN_MES_MIE_HI_BASE_IDX 1 1441#define regVCN_MES_INTERRUPT 0x0790 1442#define regVCN_MES_INTERRUPT_BASE_IDX 1 1443#define regVCN_MES_SCRATCH_INDEX 0x0791 1444#define regVCN_MES_SCRATCH_INDEX_BASE_IDX 1 1445#define regVCN_MES_SCRATCH_DATA 0x0792 1446#define regVCN_MES_SCRATCH_DATA_BASE_IDX 1 1447#define regVCN_MES_INSTR_PNTR 0x0793 1448#define regVCN_MES_INSTR_PNTR_BASE_IDX 1 1449#define regVCN_MES_MSCRATCH_HI 0x0794 1450#define regVCN_MES_MSCRATCH_HI_BASE_IDX 1 1451#define regVCN_MES_MSCRATCH_LO 0x0795 1452#define regVCN_MES_MSCRATCH_LO_BASE_IDX 1 1453#define regVCN_MES_MSTATUS_LO 0x0796 1454#define regVCN_MES_MSTATUS_LO_BASE_IDX 1 1455#define regVCN_MES_MSTATUS_HI 0x0797 1456#define regVCN_MES_MSTATUS_HI_BASE_IDX 1 1457#define regVCN_MES_MEPC_LO 0x0798 1458#define regVCN_MES_MEPC_LO_BASE_IDX 1 1459#define regVCN_MES_MEPC_HI 0x0799 1460#define regVCN_MES_MEPC_HI_BASE_IDX 1 1461#define regVCN_MES_MCAUSE_LO 0x079a 1462#define regVCN_MES_MCAUSE_LO_BASE_IDX 1 1463#define regVCN_MES_MCAUSE_HI 0x079b 1464#define regVCN_MES_MCAUSE_HI_BASE_IDX 1 1465#define regVCN_MES_MBADADDR_LO 0x079c 1466#define regVCN_MES_MBADADDR_LO_BASE_IDX 1 1467#define regVCN_MES_MBADADDR_HI 0x079d 1468#define regVCN_MES_MBADADDR_HI_BASE_IDX 1 1469#define regVCN_MES_MIP_LO 0x079e 1470#define regVCN_MES_MIP_LO_BASE_IDX 1 1471#define regVCN_MES_MIP_HI 0x079f 1472#define regVCN_MES_MIP_HI_BASE_IDX 1 1473#define regVCN_MES_IC_OP_CNTL 0x07a0 1474#define regVCN_MES_IC_OP_CNTL_BASE_IDX 1 1475#define regVCN_MES_MCYCLE_LO 0x07a6 1476#define regVCN_MES_MCYCLE_LO_BASE_IDX 1 1477#define regVCN_MES_MCYCLE_HI 0x07a7 1478#define regVCN_MES_MCYCLE_HI_BASE_IDX 1 1479#define regVCN_MES_MTIME_LO 0x07a8 1480#define regVCN_MES_MTIME_LO_BASE_IDX 1 1481#define regVCN_MES_MTIME_HI 0x07a9 1482#define regVCN_MES_MTIME_HI_BASE_IDX 1 1483#define regVCN_MES_MINSTRET_LO 0x07aa 1484#define regVCN_MES_MINSTRET_LO_BASE_IDX 1 1485#define regVCN_MES_MINSTRET_HI 0x07ab 1486#define regVCN_MES_MINSTRET_HI_BASE_IDX 1 1487#define regVCN_MES_MISA_LO 0x07ac 1488#define regVCN_MES_MISA_LO_BASE_IDX 1 1489#define regVCN_MES_MISA_HI 0x07ad 1490#define regVCN_MES_MISA_HI_BASE_IDX 1 1491#define regVCN_MES_MVENDORID_LO 0x07ae 1492#define regVCN_MES_MVENDORID_LO_BASE_IDX 1 1493#define regVCN_MES_MVENDORID_HI 0x07af 1494#define regVCN_MES_MVENDORID_HI_BASE_IDX 1 1495#define regVCN_MES_MARCHID_LO 0x07b0 1496#define regVCN_MES_MARCHID_LO_BASE_IDX 1 1497#define regVCN_MES_MARCHID_HI 0x07b1 1498#define regVCN_MES_MARCHID_HI_BASE_IDX 1 1499#define regVCN_MES_MIMPID_LO 0x07b2 1500#define regVCN_MES_MIMPID_LO_BASE_IDX 1 1501#define regVCN_MES_MIMPID_HI 0x07b3 1502#define regVCN_MES_MIMPID_HI_BASE_IDX 1 1503#define regVCN_MES_MHARTID_LO 0x07b4 1504#define regVCN_MES_MHARTID_LO_BASE_IDX 1 1505#define regVCN_MES_MHARTID_HI 0x07b5 1506#define regVCN_MES_MHARTID_HI_BASE_IDX 1 1507#define regVCN_MES_DC_BASE_CNTL 0x07b6 1508#define regVCN_MES_DC_BASE_CNTL_BASE_IDX 1 1509#define regVCN_MES_DC_OP_CNTL 0x07b7 1510#define regVCN_MES_DC_OP_CNTL_BASE_IDX 1 1511#define regVCN_MES_MTIMECMP_LO 0x07b8 1512#define regVCN_MES_MTIMECMP_LO_BASE_IDX 1 1513#define regVCN_MES_MTIMECMP_HI 0x07b9 1514#define regVCN_MES_MTIMECMP_HI_BASE_IDX 1 1515#define regVCN_MES_GP0_LO 0x07c3 1516#define regVCN_MES_GP0_LO_BASE_IDX 1 1517#define regVCN_MES_GP0_HI 0x07c4 1518#define regVCN_MES_GP0_HI_BASE_IDX 1 1519#define regVCN_MES_GP1_LO 0x07c5 1520#define regVCN_MES_GP1_LO_BASE_IDX 1 1521#define regVCN_MES_GP1_HI 0x07c6 1522#define regVCN_MES_GP1_HI_BASE_IDX 1 1523#define regVCN_MES_GP2_LO 0x07c7 1524#define regVCN_MES_GP2_LO_BASE_IDX 1 1525#define regVCN_MES_GP2_HI 0x07c8 1526#define regVCN_MES_GP2_HI_BASE_IDX 1 1527#define regVCN_MES_GP3_LO 0x07c9 1528#define regVCN_MES_GP3_LO_BASE_IDX 1 1529#define regVCN_MES_GP3_HI 0x07ca 1530#define regVCN_MES_GP3_HI_BASE_IDX 1 1531#define regVCN_MES_GP4_LO 0x07cb 1532#define regVCN_MES_GP4_LO_BASE_IDX 1 1533#define regVCN_MES_GP4_HI 0x07cc 1534#define regVCN_MES_GP4_HI_BASE_IDX 1 1535#define regVCN_MES_GP5_LO 0x07cd 1536#define regVCN_MES_GP5_LO_BASE_IDX 1 1537#define regVCN_MES_GP5_HI 0x07ce 1538#define regVCN_MES_GP5_HI_BASE_IDX 1 1539#define regVCN_MES_GP6_LO 0x07cf 1540#define regVCN_MES_GP6_LO_BASE_IDX 1 1541#define regVCN_MES_GP6_HI 0x07d0 1542#define regVCN_MES_GP6_HI_BASE_IDX 1 1543#define regVCN_MES_GP7_LO 0x07d1 1544#define regVCN_MES_GP7_LO_BASE_IDX 1 1545#define regVCN_MES_GP7_HI 0x07d2 1546#define regVCN_MES_GP7_HI_BASE_IDX 1 1547#define regVCN_MES_GP8_LO 0x07d3 1548#define regVCN_MES_GP8_LO_BASE_IDX 1 1549#define regVCN_MES_GP8_HI 0x07d4 1550#define regVCN_MES_GP8_HI_BASE_IDX 1 1551#define regVCN_MES_GP9_LO 0x07d5 1552#define regVCN_MES_GP9_LO_BASE_IDX 1 1553#define regVCN_MES_GP9_HI 0x07d6 1554#define regVCN_MES_GP9_HI_BASE_IDX 1 1555#define regVCN_MES_DM_INDEX_ADDR 0x0800 1556#define regVCN_MES_DM_INDEX_ADDR_BASE_IDX 1 1557#define regVCN_MES_DM_INDEX_DATA 0x0801 1558#define regVCN_MES_DM_INDEX_DATA_BASE_IDX 1 1559#define regVCN_MES_LOCAL_BASE0_LO 0x0803 1560#define regVCN_MES_LOCAL_BASE0_LO_BASE_IDX 1 1561#define regVCN_MES_LOCAL_BASE0_HI 0x0804 1562#define regVCN_MES_LOCAL_BASE0_HI_BASE_IDX 1 1563#define regVCN_MES_LOCAL_MASK0_LO 0x0805 1564#define regVCN_MES_LOCAL_MASK0_LO_BASE_IDX 1 1565#define regVCN_MES_LOCAL_MASK0_HI 0x0806 1566#define regVCN_MES_LOCAL_MASK0_HI_BASE_IDX 1 1567#define regVCN_MES_LOCAL_APERTURE 0x0807 1568#define regVCN_MES_LOCAL_APERTURE_BASE_IDX 1 1569#define regVCN_MES_LOCAL_INSTR_BASE_LO 0x0808 1570#define regVCN_MES_LOCAL_INSTR_BASE_LO_BASE_IDX 1 1571#define regVCN_MES_LOCAL_INSTR_BASE_HI 0x0809 1572#define regVCN_MES_LOCAL_INSTR_BASE_HI_BASE_IDX 1 1573#define regVCN_MES_LOCAL_INSTR_MASK_LO 0x080a 1574#define regVCN_MES_LOCAL_INSTR_MASK_LO_BASE_IDX 1 1575#define regVCN_MES_LOCAL_INSTR_MASK_HI 0x080b 1576#define regVCN_MES_LOCAL_INSTR_MASK_HI_BASE_IDX 1 1577#define regVCN_MES_LOCAL_INSTR_APERTURE 0x080c 1578#define regVCN_MES_LOCAL_INSTR_APERTURE_BASE_IDX 1 1579#define regVCN_MES_LOCAL_SCRATCH_APERTURE 0x080d 1580#define regVCN_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 1581#define regVCN_MES_LOCAL_SCRATCH_BASE_LO 0x080e 1582#define regVCN_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 1583#define regVCN_MES_LOCAL_SCRATCH_BASE_HI 0x080f 1584#define regVCN_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 1585#define regVCN_MES_PERFCOUNT_CNTL 0x0819 1586#define regVCN_MES_PERFCOUNT_CNTL_BASE_IDX 1 1587#define regVCN_MES_PENDING_INTERRUPT 0x081a 1588#define regVCN_MES_PENDING_INTERRUPT_BASE_IDX 1 1589#define regVCN_MES_PRGRM_CNTR_START_HI 0x081d 1590#define regVCN_MES_PRGRM_CNTR_START_HI_BASE_IDX 1 1591#define regVCN_MES_INTERRUPT_DATA_16 0x081f 1592#define regVCN_MES_INTERRUPT_DATA_16_BASE_IDX 1 1593#define regVCN_MES_INTERRUPT_DATA_17 0x0820 1594#define regVCN_MES_INTERRUPT_DATA_17_BASE_IDX 1 1595#define regVCN_MES_INTERRUPT_DATA_18 0x0821 1596#define regVCN_MES_INTERRUPT_DATA_18_BASE_IDX 1 1597#define regVCN_MES_INTERRUPT_DATA_19 0x0822 1598#define regVCN_MES_INTERRUPT_DATA_19_BASE_IDX 1 1599#define regVCN_MES_INTERRUPT_DATA_20 0x0823 1600#define regVCN_MES_INTERRUPT_DATA_20_BASE_IDX 1 1601#define regVCN_MES_INTERRUPT_DATA_21 0x0824 1602#define regVCN_MES_INTERRUPT_DATA_21_BASE_IDX 1 1603#define regVCN_MES_INTERRUPT_DATA_22 0x0825 1604#define regVCN_MES_INTERRUPT_DATA_22_BASE_IDX 1 1605#define regVCN_MES_INTERRUPT_DATA_23 0x0826 1606#define regVCN_MES_INTERRUPT_DATA_23_BASE_IDX 1 1607#define regVCN_MES_INTERRUPT_DATA_24 0x0827 1608#define regVCN_MES_INTERRUPT_DATA_24_BASE_IDX 1 1609#define regVCN_MES_INTERRUPT_DATA_25 0x0828 1610#define regVCN_MES_INTERRUPT_DATA_25_BASE_IDX 1 1611#define regVCN_MES_INTERRUPT_DATA_26 0x0829 1612#define regVCN_MES_INTERRUPT_DATA_26_BASE_IDX 1 1613#define regVCN_MES_INTERRUPT_DATA_27 0x082a 1614#define regVCN_MES_INTERRUPT_DATA_27_BASE_IDX 1 1615#define regVCN_MES_INTERRUPT_DATA_28 0x082b 1616#define regVCN_MES_INTERRUPT_DATA_28_BASE_IDX 1 1617#define regVCN_MES_INTERRUPT_DATA_29 0x082c 1618#define regVCN_MES_INTERRUPT_DATA_29_BASE_IDX 1 1619#define regVCN_MES_INTERRUPT_DATA_30 0x082d 1620#define regVCN_MES_INTERRUPT_DATA_30_BASE_IDX 1 1621#define regVCN_MES_INTERRUPT_DATA_31 0x082e 1622#define regVCN_MES_INTERRUPT_DATA_31_BASE_IDX 1 1623#define regVCN_MES_DC_APERTURE0_BASE 0x082f 1624#define regVCN_MES_DC_APERTURE0_BASE_BASE_IDX 1 1625#define regVCN_MES_DC_APERTURE0_MASK 0x0830 1626#define regVCN_MES_DC_APERTURE0_MASK_BASE_IDX 1 1627#define regVCN_MES_DC_APERTURE0_CNTL 0x0831 1628#define regVCN_MES_DC_APERTURE0_CNTL_BASE_IDX 1 1629#define regVCN_MES_DC_APERTURE1_BASE 0x0832 1630#define regVCN_MES_DC_APERTURE1_BASE_BASE_IDX 1 1631#define regVCN_MES_DC_APERTURE1_MASK 0x0833 1632#define regVCN_MES_DC_APERTURE1_MASK_BASE_IDX 1 1633#define regVCN_MES_DC_APERTURE1_CNTL 0x0834 1634#define regVCN_MES_DC_APERTURE1_CNTL_BASE_IDX 1 1635#define regVCN_MES_DC_APERTURE2_BASE 0x0835 1636#define regVCN_MES_DC_APERTURE2_BASE_BASE_IDX 1 1637#define regVCN_MES_DC_APERTURE2_MASK 0x0836 1638#define regVCN_MES_DC_APERTURE2_MASK_BASE_IDX 1 1639#define regVCN_MES_DC_APERTURE2_CNTL 0x0837 1640#define regVCN_MES_DC_APERTURE2_CNTL_BASE_IDX 1 1641#define regVCN_MES_DC_APERTURE3_BASE 0x0838 1642#define regVCN_MES_DC_APERTURE3_BASE_BASE_IDX 1 1643#define regVCN_MES_DC_APERTURE3_MASK 0x0839 1644#define regVCN_MES_DC_APERTURE3_MASK_BASE_IDX 1 1645#define regVCN_MES_DC_APERTURE3_CNTL 0x083a 1646#define regVCN_MES_DC_APERTURE3_CNTL_BASE_IDX 1 1647#define regVCN_MES_DC_APERTURE4_BASE 0x083b 1648#define regVCN_MES_DC_APERTURE4_BASE_BASE_IDX 1 1649#define regVCN_MES_DC_APERTURE4_MASK 0x083c 1650#define regVCN_MES_DC_APERTURE4_MASK_BASE_IDX 1 1651#define regVCN_MES_DC_APERTURE4_CNTL 0x083d 1652#define regVCN_MES_DC_APERTURE4_CNTL_BASE_IDX 1 1653#define regVCN_MES_DC_APERTURE5_BASE 0x083e 1654#define regVCN_MES_DC_APERTURE5_BASE_BASE_IDX 1 1655#define regVCN_MES_DC_APERTURE5_MASK 0x083f 1656#define regVCN_MES_DC_APERTURE5_MASK_BASE_IDX 1 1657#define regVCN_MES_DC_APERTURE5_CNTL 0x0840 1658#define regVCN_MES_DC_APERTURE5_CNTL_BASE_IDX 1 1659#define regVCN_MES_DC_APERTURE6_BASE 0x0841 1660#define regVCN_MES_DC_APERTURE6_BASE_BASE_IDX 1 1661#define regVCN_MES_DC_APERTURE6_MASK 0x0842 1662#define regVCN_MES_DC_APERTURE6_MASK_BASE_IDX 1 1663#define regVCN_MES_DC_APERTURE6_CNTL 0x0843 1664#define regVCN_MES_DC_APERTURE6_CNTL_BASE_IDX 1 1665#define regVCN_MES_DC_APERTURE7_BASE 0x0844 1666#define regVCN_MES_DC_APERTURE7_BASE_BASE_IDX 1 1667#define regVCN_MES_DC_APERTURE7_MASK 0x0845 1668#define regVCN_MES_DC_APERTURE7_MASK_BASE_IDX 1 1669#define regVCN_MES_DC_APERTURE7_CNTL 0x0846 1670#define regVCN_MES_DC_APERTURE7_CNTL_BASE_IDX 1 1671#define regVCN_MES_DC_APERTURE8_BASE 0x0847 1672#define regVCN_MES_DC_APERTURE8_BASE_BASE_IDX 1 1673#define regVCN_MES_DC_APERTURE8_MASK 0x0848 1674#define regVCN_MES_DC_APERTURE8_MASK_BASE_IDX 1 1675#define regVCN_MES_DC_APERTURE8_CNTL 0x0849 1676#define regVCN_MES_DC_APERTURE8_CNTL_BASE_IDX 1 1677#define regVCN_MES_DC_APERTURE9_BASE 0x084a 1678#define regVCN_MES_DC_APERTURE9_BASE_BASE_IDX 1 1679#define regVCN_MES_DC_APERTURE9_MASK 0x084b 1680#define regVCN_MES_DC_APERTURE9_MASK_BASE_IDX 1 1681#define regVCN_MES_DC_APERTURE9_CNTL 0x084c 1682#define regVCN_MES_DC_APERTURE9_CNTL_BASE_IDX 1 1683#define regVCN_MES_DC_APERTURE10_BASE 0x084d 1684#define regVCN_MES_DC_APERTURE10_BASE_BASE_IDX 1 1685#define regVCN_MES_DC_APERTURE10_MASK 0x084e 1686#define regVCN_MES_DC_APERTURE10_MASK_BASE_IDX 1 1687#define regVCN_MES_DC_APERTURE10_CNTL 0x084f 1688#define regVCN_MES_DC_APERTURE10_CNTL_BASE_IDX 1 1689#define regVCN_MES_DC_APERTURE11_BASE 0x0850 1690#define regVCN_MES_DC_APERTURE11_BASE_BASE_IDX 1 1691#define regVCN_MES_DC_APERTURE11_MASK 0x0851 1692#define regVCN_MES_DC_APERTURE11_MASK_BASE_IDX 1 1693#define regVCN_MES_DC_APERTURE11_CNTL 0x0852 1694#define regVCN_MES_DC_APERTURE11_CNTL_BASE_IDX 1 1695#define regVCN_MES_DC_APERTURE12_BASE 0x0853 1696#define regVCN_MES_DC_APERTURE12_BASE_BASE_IDX 1 1697#define regVCN_MES_DC_APERTURE12_MASK 0x0854 1698#define regVCN_MES_DC_APERTURE12_MASK_BASE_IDX 1 1699#define regVCN_MES_DC_APERTURE12_CNTL 0x0855 1700#define regVCN_MES_DC_APERTURE12_CNTL_BASE_IDX 1 1701#define regVCN_MES_DC_APERTURE13_BASE 0x0856 1702#define regVCN_MES_DC_APERTURE13_BASE_BASE_IDX 1 1703#define regVCN_MES_DC_APERTURE13_MASK 0x0857 1704#define regVCN_MES_DC_APERTURE13_MASK_BASE_IDX 1 1705#define regVCN_MES_DC_APERTURE13_CNTL 0x0858 1706#define regVCN_MES_DC_APERTURE13_CNTL_BASE_IDX 1 1707#define regVCN_MES_DC_APERTURE14_BASE 0x0859 1708#define regVCN_MES_DC_APERTURE14_BASE_BASE_IDX 1 1709#define regVCN_MES_DC_APERTURE14_MASK 0x085a 1710#define regVCN_MES_DC_APERTURE14_MASK_BASE_IDX 1 1711#define regVCN_MES_DC_APERTURE14_CNTL 0x085b 1712#define regVCN_MES_DC_APERTURE14_CNTL_BASE_IDX 1 1713#define regVCN_MES_DC_APERTURE15_BASE 0x085c 1714#define regVCN_MES_DC_APERTURE15_BASE_BASE_IDX 1 1715#define regVCN_MES_DC_APERTURE15_MASK 0x085d 1716#define regVCN_MES_DC_APERTURE15_MASK_BASE_IDX 1 1717#define regVCN_MES_DC_APERTURE15_CNTL 0x085e 1718#define regVCN_MES_DC_APERTURE15_CNTL_BASE_IDX 1 1719 1720 1721// addressBlock: uvd_vcn_hypdec 1722// base address: 0x21a00 1723#define regVCN_MES_IC_BASE_LO 0x08d0 1724#define regVCN_MES_IC_BASE_LO_BASE_IDX 1 1725#define regVCN_MES_MIBASE_LO 0x08d0 1726#define regVCN_MES_MIBASE_LO_BASE_IDX 1 1727#define regVCN_MES_IC_BASE_HI 0x08d1 1728#define regVCN_MES_IC_BASE_HI_BASE_IDX 1 1729#define regVCN_MES_MIBASE_HI 0x08d1 1730#define regVCN_MES_MIBASE_HI_BASE_IDX 1 1731#define regVCN_MES_IC_BASE_CNTL 0x08d2 1732#define regVCN_MES_IC_BASE_CNTL_BASE_IDX 1 1733#define regVCN_MES_DC_BASE_LO 0x08d4 1734#define regVCN_MES_DC_BASE_LO_BASE_IDX 1 1735#define regVCN_MES_MDBASE_LO 0x08d4 1736#define regVCN_MES_MDBASE_LO_BASE_IDX 1 1737#define regVCN_MES_DC_BASE_HI 0x08d5 1738#define regVCN_MES_DC_BASE_HI_BASE_IDX 1 1739#define regVCN_MES_MDBASE_HI 0x08d5 1740#define regVCN_MES_MDBASE_HI_BASE_IDX 1 1741#define regVCN_MES_MIBOUND_LO 0x08db 1742#define regVCN_MES_MIBOUND_LO_BASE_IDX 1 1743#define regVCN_MES_MIBOUND_HI 0x08dc 1744#define regVCN_MES_MIBOUND_HI_BASE_IDX 1 1745#define regVCN_MES_MDBOUND_LO 0x08dd 1746#define regVCN_MES_MDBOUND_LO_BASE_IDX 1 1747#define regVCN_MES_MDBOUND_HI 0x08de 1748#define regVCN_MES_MDBOUND_HI_BASE_IDX 1 1749 1750 1751// addressBlock: uvd_slmi_adpdec 1752// base address: 0x21c00 1753#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 0x0900 1754#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX 1 1755#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 0x0901 1756#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX 1 1757#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 0x0902 1758#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX 1 1759#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 0x0903 1760#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX 1 1761#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 0x0904 1762#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX 1 1763#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 0x0905 1764#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX 1 1765#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 0x0906 1766#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX 1 1767#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 0x0907 1768#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX 1 1769#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 0x0908 1770#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX 1 1771#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 0x0909 1772#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX 1 1773#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 0x090a 1774#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX 1 1775#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 0x090b 1776#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX 1 1777#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 0x090c 1778#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX 1 1779#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 0x090d 1780#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX 1 1781#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 0x090e 1782#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX 1 1783#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 0x090f 1784#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX 1 1785#define regUVD_LMI_MMSCH_NC_VMID 0x0910 1786#define regUVD_LMI_MMSCH_NC_VMID_BASE_IDX 1 1787#define regUVD_LMI_MMSCH_CTRL 0x0911 1788#define regUVD_LMI_MMSCH_CTRL_BASE_IDX 1 1789#define regUVD_MMSCH_LMI_STATUS 0x0912 1790#define regUVD_MMSCH_LMI_STATUS_BASE_IDX 1 1791#define regUMSCH_IOV_ACTIVE_FCN_ID 0x0920 1792#define regUMSCH_IOV_ACTIVE_FCN_ID_BASE_IDX 1 1793#define regUVD_UMSCH_LMI_STATUS 0x0923 1794#define regUVD_UMSCH_LMI_STATUS_BASE_IDX 1 1795 1796 1797#endif
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