FILE
vcn_4_0_3_offset.h
File preview with syntax highlighting.
linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h
1/* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef _vcn_4_0_3_OFFSET_HEADER 24#define _vcn_4_0_3_OFFSET_HEADER 25 26 27 28// addressBlock: aid_uvd0_uvddec 29// base address: 0x1fb00 30#define regUVD_TOP_CTRL 0x00c0 31#define regUVD_TOP_CTRL_BASE_IDX 1 32#define regUVD_CGC_GATE 0x00c1 33#define regUVD_CGC_GATE_BASE_IDX 1 34#define regUVD_CGC_CTRL 0x00c2 35#define regUVD_CGC_CTRL_BASE_IDX 1 36#define regAVM_SUVD_CGC_GATE 0x00c4 37#define regAVM_SUVD_CGC_GATE_BASE_IDX 1 38#define regCDEFE_SUVD_CGC_GATE 0x00c4 39#define regCDEFE_SUVD_CGC_GATE_BASE_IDX 1 40#define regEFC_SUVD_CGC_GATE 0x00c4 41#define regEFC_SUVD_CGC_GATE_BASE_IDX 1 42#define regENT_SUVD_CGC_GATE 0x00c4 43#define regENT_SUVD_CGC_GATE_BASE_IDX 1 44#define regIME_SUVD_CGC_GATE 0x00c4 45#define regIME_SUVD_CGC_GATE_BASE_IDX 1 46#define regPPU_SUVD_CGC_GATE 0x00c4 47#define regPPU_SUVD_CGC_GATE_BASE_IDX 1 48#define regSAOE_SUVD_CGC_GATE 0x00c4 49#define regSAOE_SUVD_CGC_GATE_BASE_IDX 1 50#define regSCM_SUVD_CGC_GATE 0x00c4 51#define regSCM_SUVD_CGC_GATE_BASE_IDX 1 52#define regSDB_SUVD_CGC_GATE 0x00c4 53#define regSDB_SUVD_CGC_GATE_BASE_IDX 1 54#define regSIT0_NXT_SUVD_CGC_GATE 0x00c4 55#define regSIT0_NXT_SUVD_CGC_GATE_BASE_IDX 1 56#define regSIT1_NXT_SUVD_CGC_GATE 0x00c4 57#define regSIT1_NXT_SUVD_CGC_GATE_BASE_IDX 1 58#define regSIT2_NXT_SUVD_CGC_GATE 0x00c4 59#define regSIT2_NXT_SUVD_CGC_GATE_BASE_IDX 1 60#define regSIT_SUVD_CGC_GATE 0x00c4 61#define regSIT_SUVD_CGC_GATE_BASE_IDX 1 62#define regSMPA_SUVD_CGC_GATE 0x00c4 63#define regSMPA_SUVD_CGC_GATE_BASE_IDX 1 64#define regSMP_SUVD_CGC_GATE 0x00c4 65#define regSMP_SUVD_CGC_GATE_BASE_IDX 1 66#define regSRE_SUVD_CGC_GATE 0x00c4 67#define regSRE_SUVD_CGC_GATE_BASE_IDX 1 68#define regUVD_MPBE0_SUVD_CGC_GATE 0x00c4 69#define regUVD_MPBE0_SUVD_CGC_GATE_BASE_IDX 1 70#define regUVD_MPBE1_SUVD_CGC_GATE 0x00c4 71#define regUVD_MPBE1_SUVD_CGC_GATE_BASE_IDX 1 72#define regUVD_SUVD_CGC_GATE 0x00c4 73#define regUVD_SUVD_CGC_GATE_BASE_IDX 1 74#define regAVM_SUVD_CGC_GATE2 0x00c5 75#define regAVM_SUVD_CGC_GATE2_BASE_IDX 1 76#define regCDEFE_SUVD_CGC_GATE2 0x00c5 77#define regCDEFE_SUVD_CGC_GATE2_BASE_IDX 1 78#define regDBR_SUVD_CGC_GATE2 0x00c5 79#define regDBR_SUVD_CGC_GATE2_BASE_IDX 1 80#define regENT_SUVD_CGC_GATE2 0x00c5 81#define regENT_SUVD_CGC_GATE2_BASE_IDX 1 82#define regIME_SUVD_CGC_GATE2 0x00c5 83#define regIME_SUVD_CGC_GATE2_BASE_IDX 1 84#define regMPC1_SUVD_CGC_GATE2 0x00c5 85#define regMPC1_SUVD_CGC_GATE2_BASE_IDX 1 86#define regSAOE_SUVD_CGC_GATE2 0x00c5 87#define regSAOE_SUVD_CGC_GATE2_BASE_IDX 1 88#define regSDB_SUVD_CGC_GATE2 0x00c5 89#define regSDB_SUVD_CGC_GATE2_BASE_IDX 1 90#define regSIT0_NXT_SUVD_CGC_GATE2 0x00c5 91#define regSIT0_NXT_SUVD_CGC_GATE2_BASE_IDX 1 92#define regSIT1_NXT_SUVD_CGC_GATE2 0x00c5 93#define regSIT1_NXT_SUVD_CGC_GATE2_BASE_IDX 1 94#define regSIT2_NXT_SUVD_CGC_GATE2 0x00c5 95#define regSIT2_NXT_SUVD_CGC_GATE2_BASE_IDX 1 96#define regSIT_SUVD_CGC_GATE2 0x00c5 97#define regSIT_SUVD_CGC_GATE2_BASE_IDX 1 98#define regSMPA_SUVD_CGC_GATE2 0x00c5 99#define regSMPA_SUVD_CGC_GATE2_BASE_IDX 1 100#define regSMP_SUVD_CGC_GATE2 0x00c5 101#define regSMP_SUVD_CGC_GATE2_BASE_IDX 1 102#define regSRE_SUVD_CGC_GATE2 0x00c5 103#define regSRE_SUVD_CGC_GATE2_BASE_IDX 1 104#define regUVD_MPBE0_SUVD_CGC_GATE2 0x00c5 105#define regUVD_MPBE0_SUVD_CGC_GATE2_BASE_IDX 1 106#define regUVD_MPBE1_SUVD_CGC_GATE2 0x00c5 107#define regUVD_MPBE1_SUVD_CGC_GATE2_BASE_IDX 1 108#define regUVD_SUVD_CGC_GATE2 0x00c5 109#define regUVD_SUVD_CGC_GATE2_BASE_IDX 1 110#define regAVM_SUVD_CGC_CTRL 0x00c6 111#define regAVM_SUVD_CGC_CTRL_BASE_IDX 1 112#define regCDEFE_SUVD_CGC_CTRL 0x00c6 113#define regCDEFE_SUVD_CGC_CTRL_BASE_IDX 1 114#define regDBR_SUVD_CGC_CTRL 0x00c6 115#define regDBR_SUVD_CGC_CTRL_BASE_IDX 1 116#define regEFC_SUVD_CGC_CTRL 0x00c6 117#define regEFC_SUVD_CGC_CTRL_BASE_IDX 1 118#define regENT_SUVD_CGC_CTRL 0x00c6 119#define regENT_SUVD_CGC_CTRL_BASE_IDX 1 120#define regIME_SUVD_CGC_CTRL 0x00c6 121#define regIME_SUVD_CGC_CTRL_BASE_IDX 1 122#define regMPC1_SUVD_CGC_CTRL 0x00c6 123#define regMPC1_SUVD_CGC_CTRL_BASE_IDX 1 124#define regPPU_SUVD_CGC_CTRL 0x00c6 125#define regPPU_SUVD_CGC_CTRL_BASE_IDX 1 126#define regSAOE_SUVD_CGC_CTRL 0x00c6 127#define regSAOE_SUVD_CGC_CTRL_BASE_IDX 1 128#define regSCM_SUVD_CGC_CTRL 0x00c6 129#define regSCM_SUVD_CGC_CTRL_BASE_IDX 1 130#define regSDB_SUVD_CGC_CTRL 0x00c6 131#define regSDB_SUVD_CGC_CTRL_BASE_IDX 1 132#define regSIT0_NXT_SUVD_CGC_CTRL 0x00c6 133#define regSIT0_NXT_SUVD_CGC_CTRL_BASE_IDX 1 134#define regSIT1_NXT_SUVD_CGC_CTRL 0x00c6 135#define regSIT1_NXT_SUVD_CGC_CTRL_BASE_IDX 1 136#define regSIT2_NXT_SUVD_CGC_CTRL 0x00c6 137#define regSIT2_NXT_SUVD_CGC_CTRL_BASE_IDX 1 138#define regSIT_SUVD_CGC_CTRL 0x00c6 139#define regSIT_SUVD_CGC_CTRL_BASE_IDX 1 140#define regSMPA_SUVD_CGC_CTRL 0x00c6 141#define regSMPA_SUVD_CGC_CTRL_BASE_IDX 1 142#define regSMP_SUVD_CGC_CTRL 0x00c6 143#define regSMP_SUVD_CGC_CTRL_BASE_IDX 1 144#define regSRE_SUVD_CGC_CTRL 0x00c6 145#define regSRE_SUVD_CGC_CTRL_BASE_IDX 1 146#define regUVD_MPBE0_SUVD_CGC_CTRL 0x00c6 147#define regUVD_MPBE0_SUVD_CGC_CTRL_BASE_IDX 1 148#define regUVD_MPBE1_SUVD_CGC_CTRL 0x00c6 149#define regUVD_MPBE1_SUVD_CGC_CTRL_BASE_IDX 1 150#define regUVD_SUVD_CGC_CTRL 0x00c6 151#define regUVD_SUVD_CGC_CTRL_BASE_IDX 1 152#define regUVD_CGC_CTRL3 0x00ca 153#define regUVD_CGC_CTRL3_BASE_IDX 1 154#define regUVD_GPCOM_VCPU_DATA0 0x00d0 155#define regUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 156#define regUVD_GPCOM_VCPU_DATA1 0x00d1 157#define regUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 158#define regUVD_GPCOM_SYS_CMD 0x00d2 159#define regUVD_GPCOM_SYS_CMD_BASE_IDX 1 160#define regUVD_GPCOM_SYS_DATA0 0x00d3 161#define regUVD_GPCOM_SYS_DATA0_BASE_IDX 1 162#define regUVD_GPCOM_SYS_DATA1 0x00d4 163#define regUVD_GPCOM_SYS_DATA1_BASE_IDX 1 164#define regUVD_VCPU_INT_EN 0x00d5 165#define regUVD_VCPU_INT_EN_BASE_IDX 1 166#define regUVD_VCPU_INT_STATUS 0x00d6 167#define regUVD_VCPU_INT_STATUS_BASE_IDX 1 168#define regUVD_VCPU_INT_ACK 0x00d7 169#define regUVD_VCPU_INT_ACK_BASE_IDX 1 170#define regUVD_VCPU_INT_ROUTE 0x00d8 171#define regUVD_VCPU_INT_ROUTE_BASE_IDX 1 172#define regUVD_DRV_FW_MSG 0x00d9 173#define regUVD_DRV_FW_MSG_BASE_IDX 1 174#define regUVD_FW_DRV_MSG_ACK 0x00da 175#define regUVD_FW_DRV_MSG_ACK_BASE_IDX 1 176#define regUVD_SUVD_INT_EN 0x00db 177#define regUVD_SUVD_INT_EN_BASE_IDX 1 178#define regUVD_SUVD_INT_STATUS 0x00dc 179#define regUVD_SUVD_INT_STATUS_BASE_IDX 1 180#define regUVD_SUVD_INT_ACK 0x00dd 181#define regUVD_SUVD_INT_ACK_BASE_IDX 1 182#define regUVD_ENC_VCPU_INT_EN 0x00de 183#define regUVD_ENC_VCPU_INT_EN_BASE_IDX 1 184#define regUVD_ENC_VCPU_INT_STATUS 0x00df 185#define regUVD_ENC_VCPU_INT_STATUS_BASE_IDX 1 186#define regUVD_ENC_VCPU_INT_ACK 0x00e0 187#define regUVD_ENC_VCPU_INT_ACK_BASE_IDX 1 188#define regUVD_MASTINT_EN 0x00e1 189#define regUVD_MASTINT_EN_BASE_IDX 1 190#define regUVD_SYS_INT_EN 0x00e2 191#define regUVD_SYS_INT_EN_BASE_IDX 1 192#define regUVD_SYS_INT_STATUS 0x00e3 193#define regUVD_SYS_INT_STATUS_BASE_IDX 1 194#define regUVD_SYS_INT_ACK 0x00e4 195#define regUVD_SYS_INT_ACK_BASE_IDX 1 196#define regUVD_JOB_DONE 0x00e5 197#define regUVD_JOB_DONE_BASE_IDX 1 198#define regUVD_CBUF_ID 0x00e6 199#define regUVD_CBUF_ID_BASE_IDX 1 200#define regUVD_CONTEXT_ID 0x00e7 201#define regUVD_CONTEXT_ID_BASE_IDX 1 202#define regUVD_CONTEXT_ID2 0x00e8 203#define regUVD_CONTEXT_ID2_BASE_IDX 1 204#define regUVD_NO_OP 0x00e9 205#define regUVD_NO_OP_BASE_IDX 1 206#define regUVD_RB_BASE_LO 0x00ea 207#define regUVD_RB_BASE_LO_BASE_IDX 1 208#define regUVD_RB_BASE_HI 0x00eb 209#define regUVD_RB_BASE_HI_BASE_IDX 1 210#define regUVD_RB_SIZE 0x00ec 211#define regUVD_RB_SIZE_BASE_IDX 1 212#define regUVD_RB_BASE_LO2 0x00ef 213#define regUVD_RB_BASE_LO2_BASE_IDX 1 214#define regUVD_RB_BASE_HI2 0x00f0 215#define regUVD_RB_BASE_HI2_BASE_IDX 1 216#define regUVD_RB_SIZE2 0x00f1 217#define regUVD_RB_SIZE2_BASE_IDX 1 218#define regUVD_RB_BASE_LO3 0x00f4 219#define regUVD_RB_BASE_LO3_BASE_IDX 1 220#define regUVD_RB_BASE_HI3 0x00f5 221#define regUVD_RB_BASE_HI3_BASE_IDX 1 222#define regUVD_RB_SIZE3 0x00f6 223#define regUVD_RB_SIZE3_BASE_IDX 1 224#define regUVD_RB_BASE_LO4 0x00f9 225#define regUVD_RB_BASE_LO4_BASE_IDX 1 226#define regUVD_RB_BASE_HI4 0x00fa 227#define regUVD_RB_BASE_HI4_BASE_IDX 1 228#define regUVD_RB_SIZE4 0x00fb 229#define regUVD_RB_SIZE4_BASE_IDX 1 230#define regUVD_OUT_RB_BASE_LO 0x00fe 231#define regUVD_OUT_RB_BASE_LO_BASE_IDX 1 232#define regUVD_OUT_RB_BASE_HI 0x00ff 233#define regUVD_OUT_RB_BASE_HI_BASE_IDX 1 234#define regUVD_OUT_RB_SIZE 0x0100 235#define regUVD_OUT_RB_SIZE_BASE_IDX 1 236#define regUVD_IOV_ACTIVE_FCN_ID 0x0103 237#define regUVD_IOV_ACTIVE_FCN_ID_BASE_IDX 1 238#define regUVD_IOV_MAILBOX 0x0104 239#define regUVD_IOV_MAILBOX_BASE_IDX 1 240#define regUVD_IOV_MAILBOX_RESP 0x0105 241#define regUVD_IOV_MAILBOX_RESP_BASE_IDX 1 242#define regUVD_RB_ARB_CTRL 0x0106 243#define regUVD_RB_ARB_CTRL_BASE_IDX 1 244#define regUVD_CTX_INDEX 0x0107 245#define regUVD_CTX_INDEX_BASE_IDX 1 246#define regUVD_CTX_DATA 0x0108 247#define regUVD_CTX_DATA_BASE_IDX 1 248#define regUVD_CXW_WR 0x0109 249#define regUVD_CXW_WR_BASE_IDX 1 250#define regUVD_CXW_WR_INT_ID 0x010a 251#define regUVD_CXW_WR_INT_ID_BASE_IDX 1 252#define regUVD_CXW_WR_INT_CTX_ID 0x010b 253#define regUVD_CXW_WR_INT_CTX_ID_BASE_IDX 1 254#define regUVD_CXW_INT_ID 0x010c 255#define regUVD_CXW_INT_ID_BASE_IDX 1 256#define regUVD_MPEG2_ERROR 0x010d 257#define regUVD_MPEG2_ERROR_BASE_IDX 1 258#define regUVD_YBASE 0x0110 259#define regUVD_YBASE_BASE_IDX 1 260#define regUVD_UVBASE 0x0111 261#define regUVD_UVBASE_BASE_IDX 1 262#define regUVD_PITCH 0x0112 263#define regUVD_PITCH_BASE_IDX 1 264#define regUVD_WIDTH 0x0113 265#define regUVD_WIDTH_BASE_IDX 1 266#define regUVD_HEIGHT 0x0114 267#define regUVD_HEIGHT_BASE_IDX 1 268#define regUVD_PICCOUNT 0x0115 269#define regUVD_PICCOUNT_BASE_IDX 1 270#define regUVD_MPRD_INITIAL_XY 0x0116 271#define regUVD_MPRD_INITIAL_XY_BASE_IDX 1 272#define regUVD_MPEG2_CTRL 0x0117 273#define regUVD_MPEG2_CTRL_BASE_IDX 1 274#define regUVD_MB_CTL_BUF_BASE 0x0118 275#define regUVD_MB_CTL_BUF_BASE_BASE_IDX 1 276#define regUVD_PIC_CTL_BUF_BASE 0x0119 277#define regUVD_PIC_CTL_BUF_BASE_BASE_IDX 1 278#define regUVD_DXVA_BUF_SIZE 0x011a 279#define regUVD_DXVA_BUF_SIZE_BASE_IDX 1 280#define regUVD_SCRATCH_NP 0x011b 281#define regUVD_SCRATCH_NP_BASE_IDX 1 282#define regUVD_CLK_SWT_HANDSHAKE 0x011c 283#define regUVD_CLK_SWT_HANDSHAKE_BASE_IDX 1 284#define regUVD_GP_SCRATCH0 0x011e 285#define regUVD_GP_SCRATCH0_BASE_IDX 1 286#define regUVD_GP_SCRATCH1 0x011f 287#define regUVD_GP_SCRATCH1_BASE_IDX 1 288#define regUVD_GP_SCRATCH2 0x0120 289#define regUVD_GP_SCRATCH2_BASE_IDX 1 290#define regUVD_GP_SCRATCH3 0x0121 291#define regUVD_GP_SCRATCH3_BASE_IDX 1 292#define regUVD_GP_SCRATCH4 0x0122 293#define regUVD_GP_SCRATCH4_BASE_IDX 1 294#define regUVD_GP_SCRATCH5 0x0123 295#define regUVD_GP_SCRATCH5_BASE_IDX 1 296#define regUVD_GP_SCRATCH6 0x0124 297#define regUVD_GP_SCRATCH6_BASE_IDX 1 298#define regUVD_GP_SCRATCH7 0x0125 299#define regUVD_GP_SCRATCH7_BASE_IDX 1 300#define regUVD_GP_SCRATCH8 0x0126 301#define regUVD_GP_SCRATCH8_BASE_IDX 1 302#define regUVD_GP_SCRATCH9 0x0127 303#define regUVD_GP_SCRATCH9_BASE_IDX 1 304#define regUVD_GP_SCRATCH10 0x0128 305#define regUVD_GP_SCRATCH10_BASE_IDX 1 306#define regUVD_GP_SCRATCH11 0x0129 307#define regUVD_GP_SCRATCH11_BASE_IDX 1 308#define regUVD_GP_SCRATCH12 0x012a 309#define regUVD_GP_SCRATCH12_BASE_IDX 1 310#define regUVD_GP_SCRATCH13 0x012b 311#define regUVD_GP_SCRATCH13_BASE_IDX 1 312#define regUVD_GP_SCRATCH14 0x012c 313#define regUVD_GP_SCRATCH14_BASE_IDX 1 314#define regUVD_GP_SCRATCH15 0x012d 315#define regUVD_GP_SCRATCH15_BASE_IDX 1 316#define regUVD_GP_SCRATCH16 0x012e 317#define regUVD_GP_SCRATCH16_BASE_IDX 1 318#define regUVD_GP_SCRATCH17 0x012f 319#define regUVD_GP_SCRATCH17_BASE_IDX 1 320#define regUVD_GP_SCRATCH18 0x0130 321#define regUVD_GP_SCRATCH18_BASE_IDX 1 322#define regUVD_GP_SCRATCH19 0x0131 323#define regUVD_GP_SCRATCH19_BASE_IDX 1 324#define regUVD_GP_SCRATCH20 0x0132 325#define regUVD_GP_SCRATCH20_BASE_IDX 1 326#define regUVD_GP_SCRATCH21 0x0133 327#define regUVD_GP_SCRATCH21_BASE_IDX 1 328#define regUVD_GP_SCRATCH22 0x0134 329#define regUVD_GP_SCRATCH22_BASE_IDX 1 330#define regUVD_GP_SCRATCH23 0x0135 331#define regUVD_GP_SCRATCH23_BASE_IDX 1 332#define regUVD_AUDIO_RB_BASE_LO 0x0136 333#define regUVD_AUDIO_RB_BASE_LO_BASE_IDX 1 334#define regUVD_AUDIO_RB_BASE_HI 0x0137 335#define regUVD_AUDIO_RB_BASE_HI_BASE_IDX 1 336#define regUVD_AUDIO_RB_SIZE 0x0138 337#define regUVD_AUDIO_RB_SIZE_BASE_IDX 1 338#define regUVD_VCPU_INT_STATUS2 0x013b 339#define regUVD_VCPU_INT_STATUS2_BASE_IDX 1 340#define regUVD_VCPU_INT_ACK2 0x013c 341#define regUVD_VCPU_INT_ACK2_BASE_IDX 1 342#define regUVD_VCPU_INT_EN2 0x013d 343#define regUVD_VCPU_INT_EN2_BASE_IDX 1 344#define regUVD_SUVD_CGC_STATUS2 0x013e 345#define regUVD_SUVD_CGC_STATUS2_BASE_IDX 1 346#define regUVD_SUVD_INT_STATUS2 0x0140 347#define regUVD_SUVD_INT_STATUS2_BASE_IDX 1 348#define regUVD_SUVD_INT_EN2 0x0141 349#define regUVD_SUVD_INT_EN2_BASE_IDX 1 350#define regUVD_SUVD_INT_ACK2 0x0142 351#define regUVD_SUVD_INT_ACK2_BASE_IDX 1 352#define regUVD_STATUS 0x0143 353#define regUVD_STATUS_BASE_IDX 1 354#define regUVD_ENC_PIPE_BUSY 0x0144 355#define regUVD_ENC_PIPE_BUSY_BASE_IDX 1 356#define regUVD_FW_POWER_STATUS 0x0145 357#define regUVD_FW_POWER_STATUS_BASE_IDX 1 358#define regUVD_CNTL 0x0146 359#define regUVD_CNTL_BASE_IDX 1 360#define regUVD_SOFT_RESET 0x0147 361#define regUVD_SOFT_RESET_BASE_IDX 1 362#define regUVD_SOFT_RESET2 0x0148 363#define regUVD_SOFT_RESET2_BASE_IDX 1 364#define regUVD_MMSCH_SOFT_RESET 0x0149 365#define regUVD_MMSCH_SOFT_RESET_BASE_IDX 1 366#define regUVD_WIG_CTRL 0x014a 367#define regUVD_WIG_CTRL_BASE_IDX 1 368#define regUVD_CGC_STATUS 0x014c 369#define regUVD_CGC_STATUS_BASE_IDX 1 370#define regUVD_CGC_UDEC_STATUS 0x014e 371#define regUVD_CGC_UDEC_STATUS_BASE_IDX 1 372#define regUVD_SUVD_CGC_STATUS 0x0150 373#define regUVD_SUVD_CGC_STATUS_BASE_IDX 1 374#define regUVD_GPCOM_VCPU_CMD 0x0152 375#define regUVD_GPCOM_VCPU_CMD_BASE_IDX 1 376 377 378// addressBlock: aid_uvd0_ecpudec 379// base address: 0x1fe00 380#define regUVD_VCPU_CACHE_OFFSET0 0x0180 381#define regUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1 382#define regUVD_VCPU_CACHE_SIZE0 0x0181 383#define regUVD_VCPU_CACHE_SIZE0_BASE_IDX 1 384#define regUVD_VCPU_CACHE_OFFSET1 0x0182 385#define regUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1 386#define regUVD_VCPU_CACHE_SIZE1 0x0183 387#define regUVD_VCPU_CACHE_SIZE1_BASE_IDX 1 388#define regUVD_VCPU_CACHE_OFFSET2 0x0184 389#define regUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1 390#define regUVD_VCPU_CACHE_SIZE2 0x0185 391#define regUVD_VCPU_CACHE_SIZE2_BASE_IDX 1 392#define regUVD_VCPU_CACHE_OFFSET3 0x0186 393#define regUVD_VCPU_CACHE_OFFSET3_BASE_IDX 1 394#define regUVD_VCPU_CACHE_SIZE3 0x0187 395#define regUVD_VCPU_CACHE_SIZE3_BASE_IDX 1 396#define regUVD_VCPU_CACHE_OFFSET4 0x0188 397#define regUVD_VCPU_CACHE_OFFSET4_BASE_IDX 1 398#define regUVD_VCPU_CACHE_SIZE4 0x0189 399#define regUVD_VCPU_CACHE_SIZE4_BASE_IDX 1 400#define regUVD_VCPU_CACHE_OFFSET5 0x018a 401#define regUVD_VCPU_CACHE_OFFSET5_BASE_IDX 1 402#define regUVD_VCPU_CACHE_SIZE5 0x018b 403#define regUVD_VCPU_CACHE_SIZE5_BASE_IDX 1 404#define regUVD_VCPU_CACHE_OFFSET6 0x018c 405#define regUVD_VCPU_CACHE_OFFSET6_BASE_IDX 1 406#define regUVD_VCPU_CACHE_SIZE6 0x018d 407#define regUVD_VCPU_CACHE_SIZE6_BASE_IDX 1 408#define regUVD_VCPU_CACHE_OFFSET7 0x018e 409#define regUVD_VCPU_CACHE_OFFSET7_BASE_IDX 1 410#define regUVD_VCPU_CACHE_SIZE7 0x018f 411#define regUVD_VCPU_CACHE_SIZE7_BASE_IDX 1 412#define regUVD_VCPU_CACHE_OFFSET8 0x0190 413#define regUVD_VCPU_CACHE_OFFSET8_BASE_IDX 1 414#define regUVD_VCPU_CACHE_SIZE8 0x0191 415#define regUVD_VCPU_CACHE_SIZE8_BASE_IDX 1 416#define regUVD_VCPU_NONCACHE_OFFSET0 0x0192 417#define regUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX 1 418#define regUVD_VCPU_NONCACHE_SIZE0 0x0193 419#define regUVD_VCPU_NONCACHE_SIZE0_BASE_IDX 1 420#define regUVD_VCPU_NONCACHE_OFFSET1 0x0194 421#define regUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX 1 422#define regUVD_VCPU_NONCACHE_SIZE1 0x0195 423#define regUVD_VCPU_NONCACHE_SIZE1_BASE_IDX 1 424#define regUVD_VCPU_CNTL 0x0196 425#define regUVD_VCPU_CNTL_BASE_IDX 1 426#define regUVD_VCPU_PRID 0x0197 427#define regUVD_VCPU_PRID_BASE_IDX 1 428#define regUVD_VCPU_TRCE 0x0198 429#define regUVD_VCPU_TRCE_BASE_IDX 1 430#define regUVD_VCPU_TRCE_RD 0x0199 431#define regUVD_VCPU_TRCE_RD_BASE_IDX 1 432#define regUVD_VCPU_IND_INDEX 0x019b 433#define regUVD_VCPU_IND_INDEX_BASE_IDX 1 434#define regUVD_VCPU_IND_DATA 0x019c 435#define regUVD_VCPU_IND_DATA_BASE_IDX 1 436 437 438// addressBlock: aid_uvd0_uvd_mpcdec 439// base address: 0x1ff30 440#define regUVD_MP_SWAP_CNTL 0x01cc 441#define regUVD_MP_SWAP_CNTL_BASE_IDX 1 442#define regUVD_MP_SWAP_CNTL2 0x01cd 443#define regUVD_MP_SWAP_CNTL2_BASE_IDX 1 444#define regUVD_MPC_LUMA_SRCH 0x01ce 445#define regUVD_MPC_LUMA_SRCH_BASE_IDX 1 446#define regUVD_MPC_LUMA_HIT 0x01cf 447#define regUVD_MPC_LUMA_HIT_BASE_IDX 1 448#define regUVD_MPC_LUMA_HITPEND 0x01d0 449#define regUVD_MPC_LUMA_HITPEND_BASE_IDX 1 450#define regUVD_MPC_CHROMA_SRCH 0x01d1 451#define regUVD_MPC_CHROMA_SRCH_BASE_IDX 1 452#define regUVD_MPC_CHROMA_HIT 0x01d2 453#define regUVD_MPC_CHROMA_HIT_BASE_IDX 1 454#define regUVD_MPC_CHROMA_HITPEND 0x01d3 455#define regUVD_MPC_CHROMA_HITPEND_BASE_IDX 1 456#define regUVD_MPC_CNTL 0x01d4 457#define regUVD_MPC_CNTL_BASE_IDX 1 458#define regUVD_MPC_PITCH 0x01d5 459#define regUVD_MPC_PITCH_BASE_IDX 1 460#define regUVD_MPC_SET_MUXA0 0x01d6 461#define regUVD_MPC_SET_MUXA0_BASE_IDX 1 462#define regUVD_MPC_SET_MUXA1 0x01d7 463#define regUVD_MPC_SET_MUXA1_BASE_IDX 1 464#define regUVD_MPC_SET_MUXB0 0x01d8 465#define regUVD_MPC_SET_MUXB0_BASE_IDX 1 466#define regUVD_MPC_SET_MUXB1 0x01d9 467#define regUVD_MPC_SET_MUXB1_BASE_IDX 1 468#define regUVD_MPC_SET_MUX 0x01da 469#define regUVD_MPC_SET_MUX_BASE_IDX 1 470#define regUVD_MPC_SET_ALU 0x01db 471#define regUVD_MPC_SET_ALU_BASE_IDX 1 472#define regUVD_MPC_PERF0 0x01dc 473#define regUVD_MPC_PERF0_BASE_IDX 1 474#define regUVD_MPC_PERF1 0x01dd 475#define regUVD_MPC_PERF1_BASE_IDX 1 476#define regUVD_MPC_IND_INDEX 0x01de 477#define regUVD_MPC_IND_INDEX_BASE_IDX 1 478#define regUVD_MPC_IND_DATA 0x01df 479#define regUVD_MPC_IND_DATA_BASE_IDX 1 480 481 482// addressBlock: aid_uvd0_uvd_rbcdec 483// base address: 0x1ff90 484#define regUVD_RBC_IB_SIZE 0x01e4 485#define regUVD_RBC_IB_SIZE_BASE_IDX 1 486#define regUVD_RBC_IB_SIZE_UPDATE 0x01e5 487#define regUVD_RBC_IB_SIZE_UPDATE_BASE_IDX 1 488#define regUVD_RBC_RB_CNTL 0x01e6 489#define regUVD_RBC_RB_CNTL_BASE_IDX 1 490#define regUVD_RBC_RB_RPTR_ADDR 0x01e7 491#define regUVD_RBC_RB_RPTR_ADDR_BASE_IDX 1 492#define regUVD_RBC_VCPU_ACCESS 0x01ea 493#define regUVD_RBC_VCPU_ACCESS_BASE_IDX 1 494#define regUVD_FW_SEMAPHORE_CNTL 0x01eb 495#define regUVD_FW_SEMAPHORE_CNTL_BASE_IDX 1 496#define regUVD_RBC_READ_REQ_URGENT_CNTL 0x01ed 497#define regUVD_RBC_READ_REQ_URGENT_CNTL_BASE_IDX 1 498#define regUVD_RBC_RB_WPTR_CNTL 0x01ee 499#define regUVD_RBC_RB_WPTR_CNTL_BASE_IDX 1 500#define regUVD_RBC_WPTR_STATUS 0x01ef 501#define regUVD_RBC_WPTR_STATUS_BASE_IDX 1 502#define regUVD_RBC_WPTR_POLL_CNTL 0x01f0 503#define regUVD_RBC_WPTR_POLL_CNTL_BASE_IDX 1 504#define regUVD_RBC_WPTR_POLL_ADDR 0x01f1 505#define regUVD_RBC_WPTR_POLL_ADDR_BASE_IDX 1 506#define regUVD_SEMA_CMD 0x01f2 507#define regUVD_SEMA_CMD_BASE_IDX 1 508#define regUVD_SEMA_ADDR_LOW 0x01f3 509#define regUVD_SEMA_ADDR_LOW_BASE_IDX 1 510#define regUVD_SEMA_ADDR_HIGH 0x01f4 511#define regUVD_SEMA_ADDR_HIGH_BASE_IDX 1 512#define regUVD_ENGINE_CNTL 0x01f5 513#define regUVD_ENGINE_CNTL_BASE_IDX 1 514#define regUVD_SEMA_TIMEOUT_STATUS 0x01f6 515#define regUVD_SEMA_TIMEOUT_STATUS_BASE_IDX 1 516#define regUVD_SEMA_CNTL 0x01f7 517#define regUVD_SEMA_CNTL_BASE_IDX 1 518#define regUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x01f8 519#define regUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 520#define regUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x01f9 521#define regUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX 1 522#define regUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x01fa 523#define regUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 524#define regUVD_JOB_START 0x01fb 525#define regUVD_JOB_START_BASE_IDX 1 526#define regUVD_RBC_BUF_STATUS 0x01fc 527#define regUVD_RBC_BUF_STATUS_BASE_IDX 1 528#define regUVD_RBC_SWAP_CNTL 0x01fd 529#define regUVD_RBC_SWAP_CNTL_BASE_IDX 1 530 531 532// addressBlock: aid_uvd0_lmi_adpdec 533// base address: 0x20090 534#define regUVD_LMI_RE_64BIT_BAR_LOW 0x0224 535#define regUVD_LMI_RE_64BIT_BAR_LOW_BASE_IDX 1 536#define regUVD_LMI_RE_64BIT_BAR_HIGH 0x0225 537#define regUVD_LMI_RE_64BIT_BAR_HIGH_BASE_IDX 1 538#define regUVD_LMI_IT_64BIT_BAR_LOW 0x0226 539#define regUVD_LMI_IT_64BIT_BAR_LOW_BASE_IDX 1 540#define regUVD_LMI_IT_64BIT_BAR_HIGH 0x0227 541#define regUVD_LMI_IT_64BIT_BAR_HIGH_BASE_IDX 1 542#define regUVD_LMI_MP_64BIT_BAR_LOW 0x0228 543#define regUVD_LMI_MP_64BIT_BAR_LOW_BASE_IDX 1 544#define regUVD_LMI_MP_64BIT_BAR_HIGH 0x0229 545#define regUVD_LMI_MP_64BIT_BAR_HIGH_BASE_IDX 1 546#define regUVD_LMI_CM_64BIT_BAR_LOW 0x022a 547#define regUVD_LMI_CM_64BIT_BAR_LOW_BASE_IDX 1 548#define regUVD_LMI_CM_64BIT_BAR_HIGH 0x022b 549#define regUVD_LMI_CM_64BIT_BAR_HIGH_BASE_IDX 1 550#define regUVD_LMI_DB_64BIT_BAR_LOW 0x022c 551#define regUVD_LMI_DB_64BIT_BAR_LOW_BASE_IDX 1 552#define regUVD_LMI_DB_64BIT_BAR_HIGH 0x022d 553#define regUVD_LMI_DB_64BIT_BAR_HIGH_BASE_IDX 1 554#define regUVD_LMI_DBW_64BIT_BAR_LOW 0x022e 555#define regUVD_LMI_DBW_64BIT_BAR_LOW_BASE_IDX 1 556#define regUVD_LMI_DBW_64BIT_BAR_HIGH 0x022f 557#define regUVD_LMI_DBW_64BIT_BAR_HIGH_BASE_IDX 1 558#define regUVD_LMI_IDCT_64BIT_BAR_LOW 0x0230 559#define regUVD_LMI_IDCT_64BIT_BAR_LOW_BASE_IDX 1 560#define regUVD_LMI_IDCT_64BIT_BAR_HIGH 0x0231 561#define regUVD_LMI_IDCT_64BIT_BAR_HIGH_BASE_IDX 1 562#define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW 0x0232 563#define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW_BASE_IDX 1 564#define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH 0x0233 565#define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH_BASE_IDX 1 566#define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW 0x0234 567#define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW_BASE_IDX 1 568#define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH 0x0235 569#define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH_BASE_IDX 1 570#define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW 0x0236 571#define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW_BASE_IDX 1 572#define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH 0x0237 573#define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH_BASE_IDX 1 574#define regUVD_LMI_MPC_64BIT_BAR_LOW 0x0238 575#define regUVD_LMI_MPC_64BIT_BAR_LOW_BASE_IDX 1 576#define regUVD_LMI_MPC_64BIT_BAR_HIGH 0x0239 577#define regUVD_LMI_MPC_64BIT_BAR_HIGH_BASE_IDX 1 578#define regUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x023a 579#define regUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1 580#define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x023b 581#define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 582#define regUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x023c 583#define regUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1 584#define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x023d 585#define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 586#define regUVD_LMI_LBSI_64BIT_BAR_LOW 0x023e 587#define regUVD_LMI_LBSI_64BIT_BAR_LOW_BASE_IDX 1 588#define regUVD_LMI_LBSI_64BIT_BAR_HIGH 0x023f 589#define regUVD_LMI_LBSI_64BIT_BAR_HIGH_BASE_IDX 1 590#define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW 0x0240 591#define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX 1 592#define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 0x0241 593#define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX 1 594#define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW 0x0242 595#define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX 1 596#define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 0x0243 597#define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX 1 598#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x0244 599#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 600#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x0245 601#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 602#define regUVD_LMI_CENC_64BIT_BAR_LOW 0x0246 603#define regUVD_LMI_CENC_64BIT_BAR_LOW_BASE_IDX 1 604#define regUVD_LMI_CENC_64BIT_BAR_HIGH 0x0247 605#define regUVD_LMI_CENC_64BIT_BAR_HIGH_BASE_IDX 1 606#define regUVD_LMI_SRE_64BIT_BAR_LOW 0x0248 607#define regUVD_LMI_SRE_64BIT_BAR_LOW_BASE_IDX 1 608#define regUVD_LMI_SRE_64BIT_BAR_HIGH 0x0249 609#define regUVD_LMI_SRE_64BIT_BAR_HIGH_BASE_IDX 1 610#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW 0x024a 611#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW_BASE_IDX 1 612#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH 0x024b 613#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH_BASE_IDX 1 614#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW 0x024c 615#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW_BASE_IDX 1 616#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH 0x024d 617#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 618#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW 0x024e 619#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 620#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH 0x024f 621#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 622#define regUVD_LMI_MIF_REF_64BIT_BAR_LOW 0x0250 623#define regUVD_LMI_MIF_REF_64BIT_BAR_LOW_BASE_IDX 1 624#define regUVD_LMI_MIF_REF_64BIT_BAR_HIGH 0x0251 625#define regUVD_LMI_MIF_REF_64BIT_BAR_HIGH_BASE_IDX 1 626#define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW 0x0252 627#define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW_BASE_IDX 1 628#define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH 0x0253 629#define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH_BASE_IDX 1 630#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW 0x0254 631#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW_BASE_IDX 1 632#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH 0x0255 633#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH_BASE_IDX 1 634#define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW 0x0256 635#define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW_BASE_IDX 1 636#define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH 0x0257 637#define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH_BASE_IDX 1 638#define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW 0x0258 639#define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW_BASE_IDX 1 640#define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH 0x0259 641#define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH_BASE_IDX 1 642#define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW 0x025a 643#define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW_BASE_IDX 1 644#define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH 0x025b 645#define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH_BASE_IDX 1 646#define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW 0x025c 647#define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW_BASE_IDX 1 648#define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH 0x025d 649#define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH_BASE_IDX 1 650#define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW 0x025e 651#define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW_BASE_IDX 1 652#define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH 0x025f 653#define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH_BASE_IDX 1 654#define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW 0x0260 655#define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW_BASE_IDX 1 656#define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH 0x0261 657#define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH_BASE_IDX 1 658#define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW 0x0262 659#define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW_BASE_IDX 1 660#define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH 0x0263 661#define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH_BASE_IDX 1 662#define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW 0x0264 663#define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW_BASE_IDX 1 664#define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH 0x0265 665#define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH_BASE_IDX 1 666#define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW 0x0266 667#define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW_BASE_IDX 1 668#define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH 0x0267 669#define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH_BASE_IDX 1 670#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x0270 671#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1 672#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x0271 673#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1 674#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 0x0272 675#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX 1 676#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 0x0273 677#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX 1 678#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x0274 679#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1 680#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x0275 681#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1 682#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 0x0276 683#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX 1 684#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 0x0277 685#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX 1 686#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 0x0278 687#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX 1 688#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 0x0279 689#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX 1 690#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 0x027a 691#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX 1 692#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 0x027b 693#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX 1 694#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 0x027c 695#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX 1 696#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 0x027d 697#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX 1 698#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 0x027e 699#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX 1 700#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 0x027f 701#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX 1 702#define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW 0x0280 703#define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW_BASE_IDX 1 704#define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH 0x0281 705#define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH_BASE_IDX 1 706#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW 0x0282 707#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW_BASE_IDX 1 708#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH 0x0283 709#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH_BASE_IDX 1 710#define regUVD_LMI_SPH_64BIT_BAR_HIGH 0x0284 711#define regUVD_LMI_SPH_64BIT_BAR_HIGH_BASE_IDX 1 712#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW 0x0298 713#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW_BASE_IDX 1 714#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH 0x0299 715#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 716#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW 0x029a 717#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 718#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH 0x029b 719#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 720#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW 0x029c 721#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW_BASE_IDX 1 722#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH 0x029d 723#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 724#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW 0x029e 725#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 726#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH 0x029f 727#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 728#define regUVD_ADP_ATOMIC_CONFIG 0x02a1 729#define regUVD_ADP_ATOMIC_CONFIG_BASE_IDX 1 730#define regUVD_LMI_ARB_CTRL2 0x02a2 731#define regUVD_LMI_ARB_CTRL2_BASE_IDX 1 732#define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI 0x02a7 733#define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX 1 734#define regUVD_LMI_VCPU_NC_VMIDS_MULTI 0x02a8 735#define regUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX 1 736#define regUVD_LMI_LAT_CTRL 0x02a9 737#define regUVD_LMI_LAT_CTRL_BASE_IDX 1 738#define regUVD_LMI_LAT_CNTR 0x02aa 739#define regUVD_LMI_LAT_CNTR_BASE_IDX 1 740#define regUVD_LMI_AVG_LAT_CNTR 0x02ab 741#define regUVD_LMI_AVG_LAT_CNTR_BASE_IDX 1 742#define regUVD_LMI_SPH 0x02ac 743#define regUVD_LMI_SPH_BASE_IDX 1 744#define regUVD_LMI_VCPU_CACHE_VMID 0x02ad 745#define regUVD_LMI_VCPU_CACHE_VMID_BASE_IDX 1 746#define regUVD_LMI_CTRL2 0x02ae 747#define regUVD_LMI_CTRL2_BASE_IDX 1 748#define regUVD_LMI_URGENT_CTRL 0x02af 749#define regUVD_LMI_URGENT_CTRL_BASE_IDX 1 750#define regUVD_LMI_CTRL 0x02b0 751#define regUVD_LMI_CTRL_BASE_IDX 1 752#define regUVD_LMI_STATUS 0x02b1 753#define regUVD_LMI_STATUS_BASE_IDX 1 754#define regUVD_LMI_PERFMON_CTRL 0x02b4 755#define regUVD_LMI_PERFMON_CTRL_BASE_IDX 1 756#define regUVD_LMI_PERFMON_COUNT_LO 0x02b5 757#define regUVD_LMI_PERFMON_COUNT_LO_BASE_IDX 1 758#define regUVD_LMI_PERFMON_COUNT_HI 0x02b6 759#define regUVD_LMI_PERFMON_COUNT_HI_BASE_IDX 1 760#define regUVD_LMI_ADP_SWAP_CNTL 0x02b7 761#define regUVD_LMI_ADP_SWAP_CNTL_BASE_IDX 1 762#define regUVD_LMI_RBC_RB_VMID 0x02b8 763#define regUVD_LMI_RBC_RB_VMID_BASE_IDX 1 764#define regUVD_LMI_RBC_IB_VMID 0x02b9 765#define regUVD_LMI_RBC_IB_VMID_BASE_IDX 1 766#define regUVD_LMI_MC_CREDITS 0x02ba 767#define regUVD_LMI_MC_CREDITS_BASE_IDX 1 768#define regUVD_LMI_ADP_IND_INDEX 0x02be 769#define regUVD_LMI_ADP_IND_INDEX_BASE_IDX 1 770#define regUVD_LMI_ADP_IND_DATA 0x02bf 771#define regUVD_LMI_ADP_IND_DATA_BASE_IDX 1 772#define regUVD_LMI_ADP_PF_EN 0x02c0 773#define regUVD_LMI_ADP_PF_EN_BASE_IDX 1 774#define regUVD_LMI_PREF_CTRL 0x02c2 775#define regUVD_LMI_PREF_CTRL_BASE_IDX 1 776#define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW 0x02dd 777#define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW_BASE_IDX 1 778#define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH 0x02de 779#define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 780#define regVCN_RAS_CNTL 0x02df 781#define regVCN_RAS_CNTL_BASE_IDX 1 782#define regVCN_RRMT_CNTL 0x0940 783#define regVCN_RRMT_CNTL_BASE_IDX 1 784 785// addressBlock: aid_uvd0_uvd_jpeg0_jpegnpdec 786// base address: 0x20f00 787#define regUVD_JPEG_CNTL 0x05c0 788#define regUVD_JPEG_CNTL_BASE_IDX 1 789#define regUVD_JPEG_RB_BASE 0x05c1 790#define regUVD_JPEG_RB_BASE_BASE_IDX 1 791#define regUVD_JPEG_RB_WPTR 0x05c2 792#define regUVD_JPEG_RB_WPTR_BASE_IDX 1 793#define regUVD_JPEG_RB_RPTR 0x05c3 794#define regUVD_JPEG_RB_RPTR_BASE_IDX 1 795#define regUVD_JPEG_RB_SIZE 0x05c4 796#define regUVD_JPEG_RB_SIZE_BASE_IDX 1 797#define regUVD_JPEG_DEC_CNT 0x05c5 798#define regUVD_JPEG_DEC_CNT_BASE_IDX 1 799#define regUVD_JPEG_SPS_INFO 0x05c6 800#define regUVD_JPEG_SPS_INFO_BASE_IDX 1 801#define regUVD_JPEG_SPS1_INFO 0x05c7 802#define regUVD_JPEG_SPS1_INFO_BASE_IDX 1 803#define regUVD_JPEG_RE_TIMER 0x05c8 804#define regUVD_JPEG_RE_TIMER_BASE_IDX 1 805#define regUVD_JPEG_DEC_SCRATCH0 0x05c9 806#define regUVD_JPEG_DEC_SCRATCH0_BASE_IDX 1 807#define regUVD_JPEG_INT_EN 0x05ca 808#define regUVD_JPEG_INT_EN_BASE_IDX 1 809#define regUVD_JPEG_INT_STAT 0x05cb 810#define regUVD_JPEG_INT_STAT_BASE_IDX 1 811#define regUVD_JPEG_TIER_CNTL0 0x05cc 812#define regUVD_JPEG_TIER_CNTL0_BASE_IDX 1 813#define regUVD_JPEG_TIER_CNTL1 0x05cd 814#define regUVD_JPEG_TIER_CNTL1_BASE_IDX 1 815#define regUVD_JPEG_TIER_CNTL2 0x05ce 816#define regUVD_JPEG_TIER_CNTL2_BASE_IDX 1 817#define regUVD_JPEG_TIER_STATUS 0x05cf 818#define regUVD_JPEG_TIER_STATUS_BASE_IDX 1 819 820 821// addressBlock: aid_uvd0_uvd_jpeg_sclk0_jpegnpsclkdec 822// base address: 0x21000 823#define regUVD_JPEG_OUTBUF_CNTL 0x0600 824#define regUVD_JPEG_OUTBUF_CNTL_BASE_IDX 1 825#define regUVD_JPEG_OUTBUF_WPTR 0x0601 826#define regUVD_JPEG_OUTBUF_WPTR_BASE_IDX 1 827#define regUVD_JPEG_OUTBUF_RPTR 0x0602 828#define regUVD_JPEG_OUTBUF_RPTR_BASE_IDX 1 829#define regUVD_JPEG_PITCH 0x0603 830#define regUVD_JPEG_PITCH_BASE_IDX 1 831#define regUVD_JPEG_UV_PITCH 0x0604 832#define regUVD_JPEG_UV_PITCH_BASE_IDX 1 833#define regJPEG_DEC_Y_GFX8_TILING_SURFACE 0x0605 834#define regJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX 1 835#define regJPEG_DEC_UV_GFX8_TILING_SURFACE 0x0606 836#define regJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX 1 837#define regJPEG_DEC_GFX8_ADDR_CONFIG 0x0607 838#define regJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX 1 839#define regJPEG_DEC_Y_GFX10_TILING_SURFACE 0x0608 840#define regJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX 1 841#define regJPEG_DEC_UV_GFX10_TILING_SURFACE 0x0609 842#define regJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX 1 843#define regJPEG_DEC_GFX10_ADDR_CONFIG 0x060a 844#define regJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX 1 845#define regJPEG_DEC_ADDR_MODE 0x060b 846#define regJPEG_DEC_ADDR_MODE_BASE_IDX 1 847#define regUVD_JPEG_OUTPUT_XY 0x060c 848#define regUVD_JPEG_OUTPUT_XY_BASE_IDX 1 849#define regUVD_JPEG_GPCOM_CMD 0x060d 850#define regUVD_JPEG_GPCOM_CMD_BASE_IDX 1 851#define regUVD_JPEG_GPCOM_DATA0 0x060e 852#define regUVD_JPEG_GPCOM_DATA0_BASE_IDX 1 853#define regUVD_JPEG_GPCOM_DATA1 0x060f 854#define regUVD_JPEG_GPCOM_DATA1_BASE_IDX 1 855#define regUVD_JPEG_SCRATCH1 0x0610 856#define regUVD_JPEG_SCRATCH1_BASE_IDX 1 857#define regUVD_JPEG_DEC_SOFT_RST 0x0611 858#define regUVD_JPEG_DEC_SOFT_RST_BASE_IDX 1 859 860 861// addressBlock: aid_uvd0_uvd_jrbc0_uvd_jrbc_dec 862// base address: 0x21100 863#define regUVD_JRBC0_UVD_JRBC_RB_WPTR 0x0640 864#define regUVD_JRBC0_UVD_JRBC_RB_WPTR_BASE_IDX 1 865#define regUVD_JRBC0_UVD_JRBC_RB_CNTL 0x0641 866#define regUVD_JRBC0_UVD_JRBC_RB_CNTL_BASE_IDX 1 867#define regUVD_JRBC0_UVD_JRBC_IB_SIZE 0x0642 868#define regUVD_JRBC0_UVD_JRBC_IB_SIZE_BASE_IDX 1 869#define regUVD_JRBC0_UVD_JRBC_URGENT_CNTL 0x0643 870#define regUVD_JRBC0_UVD_JRBC_URGENT_CNTL_BASE_IDX 1 871#define regUVD_JRBC0_UVD_JRBC_RB_REF_DATA 0x0644 872#define regUVD_JRBC0_UVD_JRBC_RB_REF_DATA_BASE_IDX 1 873#define regUVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER 0x0645 874#define regUVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 1 875#define regUVD_JRBC0_UVD_JRBC_SOFT_RESET 0x0648 876#define regUVD_JRBC0_UVD_JRBC_SOFT_RESET_BASE_IDX 1 877#define regUVD_JRBC0_UVD_JRBC_STATUS 0x0649 878#define regUVD_JRBC0_UVD_JRBC_STATUS_BASE_IDX 1 879#define regUVD_JRBC0_UVD_JRBC_RB_RPTR 0x064a 880#define regUVD_JRBC0_UVD_JRBC_RB_RPTR_BASE_IDX 1 881#define regUVD_JRBC0_UVD_JRBC_RB_BUF_STATUS 0x064b 882#define regUVD_JRBC0_UVD_JRBC_RB_BUF_STATUS_BASE_IDX 1 883#define regUVD_JRBC0_UVD_JRBC_IB_BUF_STATUS 0x064c 884#define regUVD_JRBC0_UVD_JRBC_IB_BUF_STATUS_BASE_IDX 1 885#define regUVD_JRBC0_UVD_JRBC_IB_SIZE_UPDATE 0x064d 886#define regUVD_JRBC0_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 1 887#define regUVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER 0x064e 888#define regUVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 1 889#define regUVD_JRBC0_UVD_JRBC_IB_REF_DATA 0x064f 890#define regUVD_JRBC0_UVD_JRBC_IB_REF_DATA_BASE_IDX 1 891#define regUVD_JRBC0_UVD_JPEG_PREEMPT_CMD 0x0650 892#define regUVD_JRBC0_UVD_JPEG_PREEMPT_CMD_BASE_IDX 1 893#define regUVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA0 0x0651 894#define regUVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 1 895#define regUVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA1 0x0652 896#define regUVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 1 897#define regUVD_JRBC0_UVD_JRBC_RB_SIZE 0x0653 898#define regUVD_JRBC0_UVD_JRBC_RB_SIZE_BASE_IDX 1 899#define regUVD_JRBC0_UVD_JRBC_SCRATCH0 0x0654 900#define regUVD_JRBC0_UVD_JRBC_SCRATCH0_BASE_IDX 1 901 902 903// addressBlock: aid_uvd0_uvd_jmi0_uvd_jmi_dec 904// base address: 0x21180 905#define regUVD_JMI0_UVD_JPEG_DEC_PF_CTRL 0x0660 906#define regUVD_JMI0_UVD_JPEG_DEC_PF_CTRL_BASE_IDX 1 907#define regUVD_JMI0_UVD_LMI_JRBC_CTRL 0x0661 908#define regUVD_JMI0_UVD_LMI_JRBC_CTRL_BASE_IDX 1 909#define regUVD_JMI0_UVD_LMI_JPEG_CTRL 0x0662 910#define regUVD_JMI0_UVD_LMI_JPEG_CTRL_BASE_IDX 1 911#define regUVD_JMI0_JPEG_LMI_DROP 0x0663 912#define regUVD_JMI0_JPEG_LMI_DROP_BASE_IDX 1 913#define regUVD_JMI0_UVD_LMI_JRBC_IB_VMID 0x0664 914#define regUVD_JMI0_UVD_LMI_JRBC_IB_VMID_BASE_IDX 1 915#define regUVD_JMI0_UVD_LMI_JRBC_RB_VMID 0x0665 916#define regUVD_JMI0_UVD_LMI_JRBC_RB_VMID_BASE_IDX 1 917#define regUVD_JMI0_UVD_LMI_JPEG_VMID 0x0666 918#define regUVD_JMI0_UVD_LMI_JPEG_VMID_BASE_IDX 1 919#define regUVD_JMI0_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x0667 920#define regUVD_JMI0_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 1 921#define regUVD_JMI0_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x0668 922#define regUVD_JMI0_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 1 923#define regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0669 924#define regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 1 925#define regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x066a 926#define regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 927#define regUVD_JMI0_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x066b 928#define regUVD_JMI0_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 1 929#define regUVD_JMI0_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x066c 930#define regUVD_JMI0_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 1 931#define regUVD_JMI0_UVD_LMI_JPEG_PREEMPT_VMID 0x066d 932#define regUVD_JMI0_UVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 1 933#define regUVD_JMI0_UVD_JMI_DEC_SWAP_CNTL 0x066e 934#define regUVD_JMI0_UVD_JMI_DEC_SWAP_CNTL_BASE_IDX 1 935#define regUVD_JMI0_UVD_JMI_ATOMIC_CNTL 0x066f 936#define regUVD_JMI0_UVD_JMI_ATOMIC_CNTL_BASE_IDX 1 937#define regUVD_JMI0_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 0x0670 938#define regUVD_JMI0_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX 1 939#define regUVD_JMI0_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 0x0671 940#define regUVD_JMI0_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX 1 941#define regUVD_JMI0_UVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x0672 942#define regUVD_JMI0_UVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 1 943#define regUVD_JMI0_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x0673 944#define regUVD_JMI0_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 1 945#define regUVD_JMI0_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0674 946#define regUVD_JMI0_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 1 947#define regUVD_JMI0_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0675 948#define regUVD_JMI0_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 1 949#define regUVD_JMI0_UVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0676 950#define regUVD_JMI0_UVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 1 951#define regUVD_JMI0_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0677 952#define regUVD_JMI0_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 953#define regUVD_JMI0_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x0678 954#define regUVD_JMI0_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 1 955#define regUVD_JMI0_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x0679 956#define regUVD_JMI0_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 1 957#define regUVD_JMI0_UVD_JMI_CLIENT_STALL 0x067a 958#define regUVD_JMI0_UVD_JMI_CLIENT_STALL_BASE_IDX 1 959#define regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS 0x067b 960#define regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS_BASE_IDX 1 961#define regUVD_JMI0_UVD_JMI_ATOMIC_CNTL2 0x067d 962#define regUVD_JMI0_UVD_JMI_ATOMIC_CNTL2_BASE_IDX 1 963 964 965// addressBlock: aid_uvd0_uvd_jmi_common_dec 966// base address: 0x21300 967#define regUVD_JADP_MCIF_URGENT_CTRL 0x06c1 968#define regUVD_JADP_MCIF_URGENT_CTRL_BASE_IDX 1 969#define regUVD_JMI_URGENT_CTRL 0x06c2 970#define regUVD_JMI_URGENT_CTRL_BASE_IDX 1 971#define regUVD_JMI_CTRL 0x06c3 972#define regUVD_JMI_CTRL_BASE_IDX 1 973#define regJPEG_MEMCHECK_CLAMPING_CNTL 0x06c4 974#define regJPEG_MEMCHECK_CLAMPING_CNTL_BASE_IDX 1 975#define regJPEG_MEMCHECK_SAFE_ADDR 0x06c5 976#define regJPEG_MEMCHECK_SAFE_ADDR_BASE_IDX 1 977#define regJPEG_MEMCHECK_SAFE_ADDR_64BIT 0x06c6 978#define regJPEG_MEMCHECK_SAFE_ADDR_64BIT_BASE_IDX 1 979#define regUVD_JMI_LAT_CTRL 0x06c7 980#define regUVD_JMI_LAT_CTRL_BASE_IDX 1 981#define regUVD_JMI_LAT_CNTR 0x06c8 982#define regUVD_JMI_LAT_CNTR_BASE_IDX 1 983#define regUVD_JMI_AVG_LAT_CNTR 0x06c9 984#define regUVD_JMI_AVG_LAT_CNTR_BASE_IDX 1 985#define regUVD_JMI_PERFMON_CTRL 0x06ca 986#define regUVD_JMI_PERFMON_CTRL_BASE_IDX 1 987#define regUVD_JMI_PERFMON_COUNT_LO 0x06cb 988#define regUVD_JMI_PERFMON_COUNT_LO_BASE_IDX 1 989#define regUVD_JMI_PERFMON_COUNT_HI 0x06cc 990#define regUVD_JMI_PERFMON_COUNT_HI_BASE_IDX 1 991#define regUVD_JMI_CLEAN_STATUS 0x06cd 992#define regUVD_JMI_CLEAN_STATUS_BASE_IDX 1 993#define regUVD_JMI_CNTL 0x06ce 994#define regUVD_JMI_CNTL_BASE_IDX 1 995 996 997// addressBlock: aid_uvd0_uvd_jpeg_common_dec 998// base address: 0x21400 999#define regJPEG_SOFT_RESET_STATUS 0x0700 1000#define regJPEG_SOFT_RESET_STATUS_BASE_IDX 1 1001#define regJPEG_SYS_INT_EN 0x0701 1002#define regJPEG_SYS_INT_EN_BASE_IDX 1 1003#define regJPEG_SYS_INT_EN1 0x0702 1004#define regJPEG_SYS_INT_EN1_BASE_IDX 1 1005#define regJPEG_SYS_INT_STATUS 0x0703 1006#define regJPEG_SYS_INT_STATUS_BASE_IDX 1 1007#define regJPEG_SYS_INT_STATUS1 0x0704 1008#define regJPEG_SYS_INT_STATUS1_BASE_IDX 1 1009#define regJPEG_SYS_INT_ACK 0x0705 1010#define regJPEG_SYS_INT_ACK_BASE_IDX 1 1011#define regJPEG_SYS_INT_ACK1 0x0706 1012#define regJPEG_SYS_INT_ACK1_BASE_IDX 1 1013#define regJPEG_MEMCHECK_SYS_INT_EN 0x0707 1014#define regJPEG_MEMCHECK_SYS_INT_EN_BASE_IDX 1 1015#define regJPEG_MEMCHECK_SYS_INT_EN1 0x0708 1016#define regJPEG_MEMCHECK_SYS_INT_EN1_BASE_IDX 1 1017#define regJPEG_MEMCHECK_SYS_INT_STAT 0x0709 1018#define regJPEG_MEMCHECK_SYS_INT_STAT_BASE_IDX 1 1019#define regJPEG_MEMCHECK_SYS_INT_STAT1 0x070a 1020#define regJPEG_MEMCHECK_SYS_INT_STAT1_BASE_IDX 1 1021#define regJPEG_MEMCHECK_SYS_INT_STAT2 0x070b 1022#define regJPEG_MEMCHECK_SYS_INT_STAT2_BASE_IDX 1 1023#define regJPEG_MEMCHECK_SYS_INT_ACK 0x070c 1024#define regJPEG_MEMCHECK_SYS_INT_ACK_BASE_IDX 1 1025#define regJPEG_MEMCHECK_SYS_INT_ACK1 0x070d 1026#define regJPEG_MEMCHECK_SYS_INT_ACK1_BASE_IDX 1 1027#define regJPEG_MEMCHECK_SYS_INT_ACK2 0x070e 1028#define regJPEG_MEMCHECK_SYS_INT_ACK2_BASE_IDX 1 1029#define regJPEG_MASTINT_EN 0x0710 1030#define regJPEG_MASTINT_EN_BASE_IDX 1 1031#define regJPEG_IH_CTRL 0x0711 1032#define regJPEG_IH_CTRL_BASE_IDX 1 1033#define regJRBBM_ARB_CTRL 0x0713 1034#define regJRBBM_ARB_CTRL_BASE_IDX 1 1035 1036 1037// addressBlock: aid_uvd0_uvd_jpeg_common_sclk_dec 1038// base address: 0x21480 1039#define regJPEG_CGC_GATE 0x0720 1040#define regJPEG_CGC_GATE_BASE_IDX 1 1041#define regJPEG_CGC_CTRL 0x0721 1042#define regJPEG_CGC_CTRL_BASE_IDX 1 1043#define regJPEG_CGC_STATUS 0x0722 1044#define regJPEG_CGC_STATUS_BASE_IDX 1 1045#define regJPEG_COMN_CGC_MEM_CTRL 0x0723 1046#define regJPEG_COMN_CGC_MEM_CTRL_BASE_IDX 1 1047#define regJPEG_DEC_CGC_MEM_CTRL 0x0724 1048#define regJPEG_DEC_CGC_MEM_CTRL_BASE_IDX 1 1049#define regJPEG_ENC_CGC_MEM_CTRL 0x0726 1050#define regJPEG_ENC_CGC_MEM_CTRL_BASE_IDX 1 1051#define regJPEG_PERF_BANK_CONF 0x0727 1052#define regJPEG_PERF_BANK_CONF_BASE_IDX 1 1053#define regJPEG_PERF_BANK_EVENT_SEL 0x0728 1054#define regJPEG_PERF_BANK_EVENT_SEL_BASE_IDX 1 1055#define regJPEG_PERF_BANK_COUNT0 0x0729 1056#define regJPEG_PERF_BANK_COUNT0_BASE_IDX 1 1057#define regJPEG_PERF_BANK_COUNT1 0x072a 1058#define regJPEG_PERF_BANK_COUNT1_BASE_IDX 1 1059#define regJPEG_PERF_BANK_COUNT2 0x072b 1060#define regJPEG_PERF_BANK_COUNT2_BASE_IDX 1 1061#define regJPEG_PERF_BANK_COUNT3 0x072c 1062#define regJPEG_PERF_BANK_COUNT3_BASE_IDX 1 1063#define regJPEG_CORE_RST_CTRL 0x072e 1064#define regJPEG_CORE_RST_CTRL_BASE_IDX 1 1065 1066 1067// addressBlock: aid_uvd0_uvd_pg_dec 1068// base address: 0x1f800 1069#define regUVD_PGFSM_CONFIG 0x0000 1070#define regUVD_PGFSM_CONFIG_BASE_IDX 1 1071#define regUVD_PGFSM_STATUS 0x0001 1072#define regUVD_PGFSM_STATUS_BASE_IDX 1 1073#define regUVD_POWER_STATUS 0x0002 1074#define regUVD_POWER_STATUS_BASE_IDX 1 1075#define regUVD_JPEG_POWER_STATUS 0x0003 1076#define regUVD_JPEG_POWER_STATUS_BASE_IDX 1 1077#define regUVD_MC_DJPEG_RD_SPACE 0x0006 1078#define regUVD_MC_DJPEG_RD_SPACE_BASE_IDX 1 1079#define regUVD_MC_DJPEG_WR_SPACE 0x0007 1080#define regUVD_MC_DJPEG_WR_SPACE_BASE_IDX 1 1081#define regUVD_MC_EJPEG_RD_SPACE 0x0008 1082#define regUVD_MC_EJPEG_RD_SPACE_BASE_IDX 1 1083#define regUVD_MC_EJPEG_WR_SPACE 0x0009 1084#define regUVD_MC_EJPEG_WR_SPACE_BASE_IDX 1 1085#define regUVD_PG_IND_INDEX 0x000c 1086#define regUVD_PG_IND_INDEX_BASE_IDX 1 1087#define regUVD_PG_IND_DATA 0x000e 1088#define regUVD_PG_IND_DATA_BASE_IDX 1 1089#define regCC_UVD_HARVESTING 0x000f 1090#define regCC_UVD_HARVESTING_BASE_IDX 1 1091#define regUVD_DPG_LMA_CTL 0x0011 1092#define regUVD_DPG_LMA_CTL_BASE_IDX 1 1093#define regUVD_DPG_LMA_DATA 0x0012 1094#define regUVD_DPG_LMA_DATA_BASE_IDX 1 1095#define regUVD_DPG_LMA_MASK 0x0013 1096#define regUVD_DPG_LMA_MASK_BASE_IDX 1 1097#define regUVD_DPG_PAUSE 0x0014 1098#define regUVD_DPG_PAUSE_BASE_IDX 1 1099#define regUVD_SCRATCH1 0x0015 1100#define regUVD_SCRATCH1_BASE_IDX 1 1101#define regUVD_SCRATCH2 0x0016 1102#define regUVD_SCRATCH2_BASE_IDX 1 1103#define regUVD_SCRATCH3 0x0017 1104#define regUVD_SCRATCH3_BASE_IDX 1 1105#define regUVD_SCRATCH4 0x0018 1106#define regUVD_SCRATCH4_BASE_IDX 1 1107#define regUVD_SCRATCH5 0x0019 1108#define regUVD_SCRATCH5_BASE_IDX 1 1109#define regUVD_SCRATCH6 0x001a 1110#define regUVD_SCRATCH6_BASE_IDX 1 1111#define regUVD_SCRATCH7 0x001b 1112#define regUVD_SCRATCH7_BASE_IDX 1 1113#define regUVD_SCRATCH8 0x001c 1114#define regUVD_SCRATCH8_BASE_IDX 1 1115#define regUVD_SCRATCH9 0x001d 1116#define regUVD_SCRATCH9_BASE_IDX 1 1117#define regUVD_SCRATCH10 0x001e 1118#define regUVD_SCRATCH10_BASE_IDX 1 1119#define regUVD_SCRATCH11 0x001f 1120#define regUVD_SCRATCH11_BASE_IDX 1 1121#define regUVD_SCRATCH12 0x0020 1122#define regUVD_SCRATCH12_BASE_IDX 1 1123#define regUVD_SCRATCH13 0x0021 1124#define regUVD_SCRATCH13_BASE_IDX 1 1125#define regUVD_SCRATCH14 0x0022 1126#define regUVD_SCRATCH14_BASE_IDX 1 1127#define regUVD_FREE_COUNTER_REG 0x0023 1128#define regUVD_FREE_COUNTER_REG_BASE_IDX 1 1129#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x0024 1130#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 1131#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x0025 1132#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 1133#define regUVD_DPG_VCPU_CACHE_OFFSET0 0x0026 1134#define regUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1 1135#define regUVD_DPG_LMI_VCPU_CACHE_VMID 0x0027 1136#define regUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX 1 1137#define regUVD_REG_FILTER_EN 0x0028 1138#define regUVD_REG_FILTER_EN_BASE_IDX 1 1139#define regUVD_SECURITY_REG_VIO_REPORT 0x0029 1140#define regUVD_SECURITY_REG_VIO_REPORT_BASE_IDX 1 1141#define regUVD_FW_VERSION 0x002a 1142#define regUVD_FW_VERSION_BASE_IDX 1 1143#define regUVD_PF_STATUS 0x002c 1144#define regUVD_PF_STATUS_BASE_IDX 1 1145#define regUVD_DPG_CLK_EN_VCPU_REPORT 0x002e 1146#define regUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX 1 1147#define regCC_UVD_VCPU_ERR_DETECT_BOT_LO 0x002f 1148#define regCC_UVD_VCPU_ERR_DETECT_BOT_LO_BASE_IDX 1 1149#define regCC_UVD_VCPU_ERR_DETECT_BOT_HI 0x0030 1150#define regCC_UVD_VCPU_ERR_DETECT_BOT_HI_BASE_IDX 1 1151#define regCC_UVD_VCPU_ERR_DETECT_TOP_LO 0x0031 1152#define regCC_UVD_VCPU_ERR_DETECT_TOP_LO_BASE_IDX 1 1153#define regCC_UVD_VCPU_ERR_DETECT_TOP_HI 0x0032 1154#define regCC_UVD_VCPU_ERR_DETECT_TOP_HI_BASE_IDX 1 1155#define regCC_UVD_VCPU_ERR 0x0033 1156#define regCC_UVD_VCPU_ERR_BASE_IDX 1 1157#define regCC_UVD_VCPU_ERR_INST_ADDR_LO 0x0034 1158#define regCC_UVD_VCPU_ERR_INST_ADDR_LO_BASE_IDX 1 1159#define regCC_UVD_VCPU_ERR_INST_ADDR_HI 0x0035 1160#define regCC_UVD_VCPU_ERR_INST_ADDR_HI_BASE_IDX 1 1161#define regUVD_LMI_MMSCH_NC_SPACE 0x003d 1162#define regUVD_LMI_MMSCH_NC_SPACE_BASE_IDX 1 1163#define regUVD_LMI_ATOMIC_SPACE 0x003e 1164#define regUVD_LMI_ATOMIC_SPACE_BASE_IDX 1 1165#define regUVD_GFX8_ADDR_CONFIG 0x0041 1166#define regUVD_GFX8_ADDR_CONFIG_BASE_IDX 1 1167#define regUVD_GFX10_ADDR_CONFIG 0x0042 1168#define regUVD_GFX10_ADDR_CONFIG_BASE_IDX 1 1169#define regUVD_GPCNT2_CNTL 0x0043 1170#define regUVD_GPCNT2_CNTL_BASE_IDX 1 1171#define regUVD_GPCNT2_TARGET_LOWER 0x0044 1172#define regUVD_GPCNT2_TARGET_LOWER_BASE_IDX 1 1173#define regUVD_GPCNT2_STATUS_LOWER 0x0045 1174#define regUVD_GPCNT2_STATUS_LOWER_BASE_IDX 1 1175#define regUVD_GPCNT2_TARGET_UPPER 0x0046 1176#define regUVD_GPCNT2_TARGET_UPPER_BASE_IDX 1 1177#define regUVD_GPCNT2_STATUS_UPPER 0x0047 1178#define regUVD_GPCNT2_STATUS_UPPER_BASE_IDX 1 1179#define regUVD_GPCNT3_CNTL 0x0048 1180#define regUVD_GPCNT3_CNTL_BASE_IDX 1 1181#define regUVD_GPCNT3_TARGET_LOWER 0x0049 1182#define regUVD_GPCNT3_TARGET_LOWER_BASE_IDX 1 1183#define regUVD_GPCNT3_STATUS_LOWER 0x004a 1184#define regUVD_GPCNT3_STATUS_LOWER_BASE_IDX 1 1185#define regUVD_GPCNT3_TARGET_UPPER 0x004b 1186#define regUVD_GPCNT3_TARGET_UPPER_BASE_IDX 1 1187#define regUVD_GPCNT3_STATUS_UPPER 0x004c 1188#define regUVD_GPCNT3_STATUS_UPPER_BASE_IDX 1 1189#define regUVD_VCLK_DS_CNTL 0x004d 1190#define regUVD_VCLK_DS_CNTL_BASE_IDX 1 1191#define regUVD_DCLK_DS_CNTL 0x004e 1192#define regUVD_DCLK_DS_CNTL_BASE_IDX 1 1193#define regUVD_TSC_LOWER 0x004f 1194#define regUVD_TSC_LOWER_BASE_IDX 1 1195#define regUVD_TSC_UPPER 0x0050 1196#define regUVD_TSC_UPPER_BASE_IDX 1 1197#define regVCN_FEATURES 0x0051 1198#define regVCN_FEATURES_BASE_IDX 1 1199#define regUVD_GPUIOV_STATUS 0x0055 1200#define regUVD_GPUIOV_STATUS_BASE_IDX 1 1201#define regUVD_RAS_VCPU_VCODEC_STATUS 0x0057 1202#define regUVD_RAS_VCPU_VCODEC_STATUS_BASE_IDX 1 1203#define regUVD_RAS_MMSCH_FATAL_ERROR 0x0058 1204#define regUVD_RAS_MMSCH_FATAL_ERROR_BASE_IDX 1 1205#define regUVD_RAS_JPEG0_STATUS 0x0059 1206#define regUVD_RAS_JPEG0_STATUS_BASE_IDX 1 1207#define regUVD_RAS_JPEG1_STATUS 0x005a 1208#define regUVD_RAS_JPEG1_STATUS_BASE_IDX 1 1209#define regUVD_RAS_CNTL_PMI_ARB 0x005b 1210#define regUVD_RAS_CNTL_PMI_ARB_BASE_IDX 1 1211#define regUVD_SCRATCH15 0x005c 1212#define regUVD_SCRATCH15_BASE_IDX 1 1213#define regVCN_JPEG_DB_CTRL1 0x005d 1214#define regVCN_JPEG_DB_CTRL1_BASE_IDX 1 1215#define regVCN_JPEG_DB_CTRL2 0x005e 1216#define regVCN_JPEG_DB_CTRL2_BASE_IDX 1 1217#define regVCN_JPEG_DB_CTRL3 0x005f 1218#define regVCN_JPEG_DB_CTRL3_BASE_IDX 1 1219#define regVCN_JPEG_DB_CTRL4 0x0060 1220#define regVCN_JPEG_DB_CTRL4_BASE_IDX 1 1221#define regVCN_JPEG_DB_CTRL5 0x0061 1222#define regVCN_JPEG_DB_CTRL5_BASE_IDX 1 1223#define regVCN_JPEG_DB_CTRL6 0x0062 1224#define regVCN_JPEG_DB_CTRL6_BASE_IDX 1 1225#define regVCN_JPEG_DB_CTRL7 0x0063 1226#define regVCN_JPEG_DB_CTRL7_BASE_IDX 1 1227#define regUVD_SCRATCH32 0x006d 1228#define regUVD_SCRATCH32_BASE_IDX 1 1229#define regUVD_VERSION 0x006e 1230#define regUVD_VERSION_BASE_IDX 1 1231#define regVCN_RB_DB_CTRL 0x0070 1232#define regVCN_RB_DB_CTRL_BASE_IDX 1 1233#define regVCN_JPEG_DB_CTRL 0x0071 1234#define regVCN_JPEG_DB_CTRL_BASE_IDX 1 1235#define regVCN_RB1_DB_CTRL 0x0072 1236#define regVCN_RB1_DB_CTRL_BASE_IDX 1 1237#define regVCN_RB2_DB_CTRL 0x0073 1238#define regVCN_RB2_DB_CTRL_BASE_IDX 1 1239#define regVCN_RB3_DB_CTRL 0x0074 1240#define regVCN_RB3_DB_CTRL_BASE_IDX 1 1241#define regVCN_RB4_DB_CTRL 0x0075 1242#define regVCN_RB4_DB_CTRL_BASE_IDX 1 1243#define regVCN_RB_ENABLE 0x0085 1244#define regVCN_RB_ENABLE_BASE_IDX 1 1245#define regVCN_RB_WPTR_CTRL 0x0086 1246#define regVCN_RB_WPTR_CTRL_BASE_IDX 1 1247#define regUVD_RB_RPTR 0x00ac 1248#define regUVD_RB_RPTR_BASE_IDX 1 1249#define regUVD_RB_WPTR 0x00ad 1250#define regUVD_RB_WPTR_BASE_IDX 1 1251#define regUVD_RB_RPTR2 0x00ae 1252#define regUVD_RB_RPTR2_BASE_IDX 1 1253#define regUVD_RB_WPTR2 0x00af 1254#define regUVD_RB_WPTR2_BASE_IDX 1 1255#define regUVD_RB_RPTR3 0x00b0 1256#define regUVD_RB_RPTR3_BASE_IDX 1 1257#define regUVD_RB_WPTR3 0x00b1 1258#define regUVD_RB_WPTR3_BASE_IDX 1 1259#define regUVD_RB_RPTR4 0x00b2 1260#define regUVD_RB_RPTR4_BASE_IDX 1 1261#define regUVD_RB_WPTR4 0x00b3 1262#define regUVD_RB_WPTR4_BASE_IDX 1 1263#define regUVD_OUT_RB_RPTR 0x00b4 1264#define regUVD_OUT_RB_RPTR_BASE_IDX 1 1265#define regUVD_OUT_RB_WPTR 0x00b5 1266#define regUVD_OUT_RB_WPTR_BASE_IDX 1 1267#define regUVD_AUDIO_RB_RPTR 0x00b6 1268#define regUVD_AUDIO_RB_RPTR_BASE_IDX 1 1269#define regUVD_AUDIO_RB_WPTR 0x00b7 1270#define regUVD_AUDIO_RB_WPTR_BASE_IDX 1 1271#define regUVD_RBC_RB_RPTR 0x00b8 1272#define regUVD_RBC_RB_RPTR_BASE_IDX 1 1273#define regUVD_RBC_RB_WPTR 0x00b9 1274#define regUVD_RBC_RB_WPTR_BASE_IDX 1 1275#define regUVD_DPG_LMA_CTL2 0x00bb 1276#define regUVD_DPG_LMA_CTL2_BASE_IDX 1 1277 1278 1279// addressBlock: aid_uvd0_mmsch_dec 1280// base address: 0x20d00 1281#define regMMSCH_UCODE_ADDR 0x0540 1282#define regMMSCH_UCODE_ADDR_BASE_IDX 1 1283#define regMMSCH_UCODE_DATA 0x0541 1284#define regMMSCH_UCODE_DATA_BASE_IDX 1 1285#define regMMSCH_SRAM_ADDR 0x0542 1286#define regMMSCH_SRAM_ADDR_BASE_IDX 1 1287#define regMMSCH_SRAM_DATA 0x0543 1288#define regMMSCH_SRAM_DATA_BASE_IDX 1 1289#define regMMSCH_VF_SRAM_OFFSET 0x0544 1290#define regMMSCH_VF_SRAM_OFFSET_BASE_IDX 1 1291#define regMMSCH_DB_SRAM_OFFSET 0x0545 1292#define regMMSCH_DB_SRAM_OFFSET_BASE_IDX 1 1293#define regMMSCH_CTX_SRAM_OFFSET 0x0546 1294#define regMMSCH_CTX_SRAM_OFFSET_BASE_IDX 1 1295#define regMMSCH_CTL 0x0547 1296#define regMMSCH_CTL_BASE_IDX 1 1297#define regMMSCH_INTR 0x0548 1298#define regMMSCH_INTR_BASE_IDX 1 1299#define regMMSCH_INTR_ACK 0x0549 1300#define regMMSCH_INTR_ACK_BASE_IDX 1 1301#define regMMSCH_INTR_STATUS 0x054a 1302#define regMMSCH_INTR_STATUS_BASE_IDX 1 1303#define regMMSCH_VF_VMID 0x054b 1304#define regMMSCH_VF_VMID_BASE_IDX 1 1305#define regMMSCH_VF_CTX_ADDR_LO 0x054c 1306#define regMMSCH_VF_CTX_ADDR_LO_BASE_IDX 1 1307#define regMMSCH_VF_CTX_ADDR_HI 0x054d 1308#define regMMSCH_VF_CTX_ADDR_HI_BASE_IDX 1 1309#define regMMSCH_VF_CTX_SIZE 0x054e 1310#define regMMSCH_VF_CTX_SIZE_BASE_IDX 1 1311#define regMMSCH_VF_GPCOM_ADDR_LO 0x054f 1312#define regMMSCH_VF_GPCOM_ADDR_LO_BASE_IDX 1 1313#define regMMSCH_VF_GPCOM_ADDR_HI 0x0550 1314#define regMMSCH_VF_GPCOM_ADDR_HI_BASE_IDX 1 1315#define regMMSCH_VF_GPCOM_SIZE 0x0551 1316#define regMMSCH_VF_GPCOM_SIZE_BASE_IDX 1 1317#define regMMSCH_VF_MAILBOX_HOST 0x0552 1318#define regMMSCH_VF_MAILBOX_HOST_BASE_IDX 1 1319#define regMMSCH_VF_MAILBOX_RESP 0x0553 1320#define regMMSCH_VF_MAILBOX_RESP_BASE_IDX 1 1321#define regMMSCH_VF_MAILBOX_0 0x0554 1322#define regMMSCH_VF_MAILBOX_0_BASE_IDX 1 1323#define regMMSCH_VF_MAILBOX_0_RESP 0x0555 1324#define regMMSCH_VF_MAILBOX_0_RESP_BASE_IDX 1 1325#define regMMSCH_VF_MAILBOX_1 0x0556 1326#define regMMSCH_VF_MAILBOX_1_BASE_IDX 1 1327#define regMMSCH_VF_MAILBOX_1_RESP 0x0557 1328#define regMMSCH_VF_MAILBOX_1_RESP_BASE_IDX 1 1329#define regMMSCH_CNTL 0x055c 1330#define regMMSCH_CNTL_BASE_IDX 1 1331#define regMMSCH_NONCACHE_OFFSET0 0x055d 1332#define regMMSCH_NONCACHE_OFFSET0_BASE_IDX 1 1333#define regMMSCH_NONCACHE_SIZE0 0x055e 1334#define regMMSCH_NONCACHE_SIZE0_BASE_IDX 1 1335#define regMMSCH_NONCACHE_OFFSET1 0x055f 1336#define regMMSCH_NONCACHE_OFFSET1_BASE_IDX 1 1337#define regMMSCH_NONCACHE_SIZE1 0x0560 1338#define regMMSCH_NONCACHE_SIZE1_BASE_IDX 1 1339#define regMMSCH_PROC_STATE1 0x0566 1340#define regMMSCH_PROC_STATE1_BASE_IDX 1 1341#define regMMSCH_LAST_MC_ADDR 0x0567 1342#define regMMSCH_LAST_MC_ADDR_BASE_IDX 1 1343#define regMMSCH_LAST_MEM_ACCESS_HI 0x0568 1344#define regMMSCH_LAST_MEM_ACCESS_HI_BASE_IDX 1 1345#define regMMSCH_LAST_MEM_ACCESS_LO 0x0569 1346#define regMMSCH_LAST_MEM_ACCESS_LO_BASE_IDX 1 1347#define regMMSCH_IOV_ACTIVE_FCN_ID 0x056a 1348#define regMMSCH_IOV_ACTIVE_FCN_ID_BASE_IDX 1 1349#define regMMSCH_SCRATCH_0 0x056b 1350#define regMMSCH_SCRATCH_0_BASE_IDX 1 1351#define regMMSCH_SCRATCH_1 0x056c 1352#define regMMSCH_SCRATCH_1_BASE_IDX 1 1353#define regMMSCH_GPUIOV_SCH_BLOCK_0 0x056d 1354#define regMMSCH_GPUIOV_SCH_BLOCK_0_BASE_IDX 1 1355#define regMMSCH_GPUIOV_CMD_CONTROL_0 0x056e 1356#define regMMSCH_GPUIOV_CMD_CONTROL_0_BASE_IDX 1 1357#define regMMSCH_GPUIOV_CMD_STATUS_0 0x056f 1358#define regMMSCH_GPUIOV_CMD_STATUS_0_BASE_IDX 1 1359#define regMMSCH_GPUIOV_VM_BUSY_STATUS_0 0x0570 1360#define regMMSCH_GPUIOV_VM_BUSY_STATUS_0_BASE_IDX 1 1361#define regMMSCH_GPUIOV_ACTIVE_FCNS_0 0x0571 1362#define regMMSCH_GPUIOV_ACTIVE_FCNS_0_BASE_IDX 1 1363#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_0 0x0572 1364#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_0_BASE_IDX 1 1365#define regMMSCH_GPUIOV_DW6_0 0x0573 1366#define regMMSCH_GPUIOV_DW6_0_BASE_IDX 1 1367#define regMMSCH_GPUIOV_DW7_0 0x0574 1368#define regMMSCH_GPUIOV_DW7_0_BASE_IDX 1 1369#define regMMSCH_GPUIOV_DW8_0 0x0575 1370#define regMMSCH_GPUIOV_DW8_0_BASE_IDX 1 1371#define regMMSCH_GPUIOV_SCH_BLOCK_1 0x0576 1372#define regMMSCH_GPUIOV_SCH_BLOCK_1_BASE_IDX 1 1373#define regMMSCH_GPUIOV_CMD_CONTROL_1 0x0577 1374#define regMMSCH_GPUIOV_CMD_CONTROL_1_BASE_IDX 1 1375#define regMMSCH_GPUIOV_CMD_STATUS_1 0x0578 1376#define regMMSCH_GPUIOV_CMD_STATUS_1_BASE_IDX 1 1377#define regMMSCH_GPUIOV_VM_BUSY_STATUS_1 0x0579 1378#define regMMSCH_GPUIOV_VM_BUSY_STATUS_1_BASE_IDX 1 1379#define regMMSCH_GPUIOV_ACTIVE_FCNS_1 0x057a 1380#define regMMSCH_GPUIOV_ACTIVE_FCNS_1_BASE_IDX 1 1381#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_1 0x057b 1382#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_1_BASE_IDX 1 1383#define regMMSCH_GPUIOV_DW6_1 0x057c 1384#define regMMSCH_GPUIOV_DW6_1_BASE_IDX 1 1385#define regMMSCH_GPUIOV_DW7_1 0x057d 1386#define regMMSCH_GPUIOV_DW7_1_BASE_IDX 1 1387#define regMMSCH_GPUIOV_DW8_1 0x057e 1388#define regMMSCH_GPUIOV_DW8_1_BASE_IDX 1 1389#define regMMSCH_GPUIOV_CNTXT 0x057f 1390#define regMMSCH_GPUIOV_CNTXT_BASE_IDX 1 1391#define regMMSCH_SCRATCH_2 0x0580 1392#define regMMSCH_SCRATCH_2_BASE_IDX 1 1393#define regMMSCH_SCRATCH_3 0x0581 1394#define regMMSCH_SCRATCH_3_BASE_IDX 1 1395#define regMMSCH_SCRATCH_4 0x0582 1396#define regMMSCH_SCRATCH_4_BASE_IDX 1 1397#define regMMSCH_SCRATCH_5 0x0583 1398#define regMMSCH_SCRATCH_5_BASE_IDX 1 1399#define regMMSCH_SCRATCH_6 0x0584 1400#define regMMSCH_SCRATCH_6_BASE_IDX 1 1401#define regMMSCH_SCRATCH_7 0x0585 1402#define regMMSCH_SCRATCH_7_BASE_IDX 1 1403#define regMMSCH_VFID_FIFO_HEAD_0 0x0586 1404#define regMMSCH_VFID_FIFO_HEAD_0_BASE_IDX 1 1405#define regMMSCH_VFID_FIFO_TAIL_0 0x0587 1406#define regMMSCH_VFID_FIFO_TAIL_0_BASE_IDX 1 1407#define regMMSCH_VFID_FIFO_HEAD_1 0x0588 1408#define regMMSCH_VFID_FIFO_HEAD_1_BASE_IDX 1 1409#define regMMSCH_VFID_FIFO_TAIL_1 0x0589 1410#define regMMSCH_VFID_FIFO_TAIL_1_BASE_IDX 1 1411#define regMMSCH_NACK_STATUS 0x058a 1412#define regMMSCH_NACK_STATUS_BASE_IDX 1 1413#define regMMSCH_VF_MAILBOX0_DATA 0x058b 1414#define regMMSCH_VF_MAILBOX0_DATA_BASE_IDX 1 1415#define regMMSCH_VF_MAILBOX1_DATA 0x058c 1416#define regMMSCH_VF_MAILBOX1_DATA_BASE_IDX 1 1417#define regMMSCH_GPUIOV_SCH_BLOCK_IP_0 0x058d 1418#define regMMSCH_GPUIOV_SCH_BLOCK_IP_0_BASE_IDX 1 1419#define regMMSCH_GPUIOV_CMD_STATUS_IP_0 0x058e 1420#define regMMSCH_GPUIOV_CMD_STATUS_IP_0_BASE_IDX 1 1421#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 0x058f 1422#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0_BASE_IDX 1 1423#define regMMSCH_GPUIOV_SCH_BLOCK_IP_1 0x0590 1424#define regMMSCH_GPUIOV_SCH_BLOCK_IP_1_BASE_IDX 1 1425#define regMMSCH_GPUIOV_CMD_STATUS_IP_1 0x0591 1426#define regMMSCH_GPUIOV_CMD_STATUS_IP_1_BASE_IDX 1 1427#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 0x0592 1428#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1_BASE_IDX 1 1429#define regMMSCH_GPUIOV_CNTXT_IP 0x0593 1430#define regMMSCH_GPUIOV_CNTXT_IP_BASE_IDX 1 1431#define regMMSCH_GPUIOV_SCH_BLOCK_2 0x0594 1432#define regMMSCH_GPUIOV_SCH_BLOCK_2_BASE_IDX 1 1433#define regMMSCH_GPUIOV_CMD_CONTROL_2 0x0595 1434#define regMMSCH_GPUIOV_CMD_CONTROL_2_BASE_IDX 1 1435#define regMMSCH_GPUIOV_CMD_STATUS_2 0x0596 1436#define regMMSCH_GPUIOV_CMD_STATUS_2_BASE_IDX 1 1437#define regMMSCH_GPUIOV_VM_BUSY_STATUS_2 0x0597 1438#define regMMSCH_GPUIOV_VM_BUSY_STATUS_2_BASE_IDX 1 1439#define regMMSCH_GPUIOV_ACTIVE_FCNS_2 0x0598 1440#define regMMSCH_GPUIOV_ACTIVE_FCNS_2_BASE_IDX 1 1441#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_2 0x0599 1442#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_2_BASE_IDX 1 1443#define regMMSCH_GPUIOV_DW6_2 0x059a 1444#define regMMSCH_GPUIOV_DW6_2_BASE_IDX 1 1445#define regMMSCH_GPUIOV_DW7_2 0x059b 1446#define regMMSCH_GPUIOV_DW7_2_BASE_IDX 1 1447#define regMMSCH_GPUIOV_DW8_2 0x059c 1448#define regMMSCH_GPUIOV_DW8_2_BASE_IDX 1 1449#define regMMSCH_GPUIOV_SCH_BLOCK_IP_2 0x059d 1450#define regMMSCH_GPUIOV_SCH_BLOCK_IP_2_BASE_IDX 1 1451#define regMMSCH_GPUIOV_CMD_STATUS_IP_2 0x059e 1452#define regMMSCH_GPUIOV_CMD_STATUS_IP_2_BASE_IDX 1 1453#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 0x059f 1454#define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2_BASE_IDX 1 1455#define regMMSCH_VFID_FIFO_HEAD_2 0x05a0 1456#define regMMSCH_VFID_FIFO_HEAD_2_BASE_IDX 1 1457#define regMMSCH_VFID_FIFO_TAIL_2 0x05a1 1458#define regMMSCH_VFID_FIFO_TAIL_2_BASE_IDX 1 1459#define regMMSCH_VM_BUSY_STATUS_0 0x05a2 1460#define regMMSCH_VM_BUSY_STATUS_0_BASE_IDX 1 1461#define regMMSCH_VM_BUSY_STATUS_1 0x05a3 1462#define regMMSCH_VM_BUSY_STATUS_1_BASE_IDX 1 1463#define regMMSCH_VM_BUSY_STATUS_2 0x05a4 1464#define regMMSCH_VM_BUSY_STATUS_2_BASE_IDX 1 1465 1466 1467// addressBlock: aid_uvd0_slmi_adpdec 1468// base address: 0x21c00 1469#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 0x0900 1470#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX 1 1471#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 0x0901 1472#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX 1 1473#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 0x0902 1474#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX 1 1475#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 0x0903 1476#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX 1 1477#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 0x0904 1478#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX 1 1479#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 0x0905 1480#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX 1 1481#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 0x0906 1482#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX 1 1483#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 0x0907 1484#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX 1 1485#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 0x0908 1486#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX 1 1487#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 0x0909 1488#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX 1 1489#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 0x090a 1490#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX 1 1491#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 0x090b 1492#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX 1 1493#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 0x090c 1494#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX 1 1495#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 0x090d 1496#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX 1 1497#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 0x090e 1498#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX 1 1499#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 0x090f 1500#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX 1 1501#define regUVD_LMI_MMSCH_NC_VMID 0x0910 1502#define regUVD_LMI_MMSCH_NC_VMID_BASE_IDX 1 1503#define regUVD_LMI_MMSCH_CTRL 0x0911 1504#define regUVD_LMI_MMSCH_CTRL_BASE_IDX 1 1505#define regUVD_MMSCH_LMI_STATUS 0x0912 1506#define regUVD_MMSCH_LMI_STATUS_BASE_IDX 1 1507#define regVCN_RAS_CNTL_MMSCH 0x0914 1508#define regVCN_RAS_CNTL_MMSCH_BASE_IDX 1 1509 1510// addressBlock: aid_uvd0_vcn_edcc_dec 1511// base address: 0x21d20 1512#define regVCN_UE_ERR_STATUS_LO_VIDD 0x094c 1513#define regVCN_UE_ERR_STATUS_LO_VIDD_BASE_IDX 1 1514#define regVCN_UE_ERR_STATUS_HI_VIDD 0x094d 1515#define regVCN_UE_ERR_STATUS_HI_VIDD_BASE_IDX 1 1516#define regVCN_UE_ERR_STATUS_LO_VIDV 0x094e 1517#define regVCN_UE_ERR_STATUS_LO_VIDV_BASE_IDX 1 1518#define regVCN_UE_ERR_STATUS_HI_VIDV 0x094f 1519#define regVCN_UE_ERR_STATUS_HI_VIDV_BASE_IDX 1 1520#define regVCN_CE_ERR_STATUS_LO_MMSCHD 0x0950 1521#define regVCN_CE_ERR_STATUS_LO_MMSCHD_BASE_IDX 1 1522#define regVCN_CE_ERR_STATUS_HI_MMSCHD 0x0951 1523#define regVCN_CE_ERR_STATUS_HI_MMSCHD_BASE_IDX 1 1524#define regVCN_UE_ERR_STATUS_LO_JPEG0S 0x0952 1525#define regVCN_UE_ERR_STATUS_LO_JPEG0S_BASE_IDX 1 1526#define regVCN_UE_ERR_STATUS_HI_JPEG0S 0x0953 1527#define regVCN_UE_ERR_STATUS_HI_JPEG0S_BASE_IDX 1 1528#define regVCN_UE_ERR_STATUS_LO_JPEG0D 0x0954 1529#define regVCN_UE_ERR_STATUS_LO_JPEG0D_BASE_IDX 1 1530#define regVCN_UE_ERR_STATUS_HI_JPEG0D 0x0955 1531#define regVCN_UE_ERR_STATUS_HI_JPEG0D_BASE_IDX 1 1532#define regVCN_UE_ERR_STATUS_LO_JPEG1S 0x0956 1533#define regVCN_UE_ERR_STATUS_LO_JPEG1S_BASE_IDX 1 1534#define regVCN_UE_ERR_STATUS_HI_JPEG1S 0x0957 1535#define regVCN_UE_ERR_STATUS_HI_JPEG1S_BASE_IDX 1 1536#define regVCN_UE_ERR_STATUS_LO_JPEG1D 0x0958 1537#define regVCN_UE_ERR_STATUS_LO_JPEG1D_BASE_IDX 1 1538#define regVCN_UE_ERR_STATUS_HI_JPEG1D 0x0959 1539#define regVCN_UE_ERR_STATUS_HI_JPEG1D_BASE_IDX 1 1540#define regVCN_UE_ERR_STATUS_LO_JPEG2S 0x095a 1541#define regVCN_UE_ERR_STATUS_LO_JPEG2S_BASE_IDX 1 1542#define regVCN_UE_ERR_STATUS_HI_JPEG2S 0x095b 1543#define regVCN_UE_ERR_STATUS_HI_JPEG2S_BASE_IDX 1 1544#define regVCN_UE_ERR_STATUS_LO_JPEG2D 0x095c 1545#define regVCN_UE_ERR_STATUS_LO_JPEG2D_BASE_IDX 1 1546#define regVCN_UE_ERR_STATUS_HI_JPEG2D 0x095d 1547#define regVCN_UE_ERR_STATUS_HI_JPEG2D_BASE_IDX 1 1548#define regVCN_UE_ERR_STATUS_LO_JPEG3S 0x095e 1549#define regVCN_UE_ERR_STATUS_LO_JPEG3S_BASE_IDX 1 1550#define regVCN_UE_ERR_STATUS_HI_JPEG3S 0x095f 1551#define regVCN_UE_ERR_STATUS_HI_JPEG3S_BASE_IDX 1 1552#define regVCN_UE_ERR_STATUS_LO_JPEG3D 0x0960 1553#define regVCN_UE_ERR_STATUS_LO_JPEG3D_BASE_IDX 1 1554#define regVCN_UE_ERR_STATUS_HI_JPEG3D 0x0961 1555#define regVCN_UE_ERR_STATUS_HI_JPEG3D_BASE_IDX 1 1556#define regVCN_UE_ERR_STATUS_LO_JPEG4S 0x0962 1557#define regVCN_UE_ERR_STATUS_LO_JPEG4S_BASE_IDX 1 1558#define regVCN_UE_ERR_STATUS_HI_JPEG4S 0x0963 1559#define regVCN_UE_ERR_STATUS_HI_JPEG4S_BASE_IDX 1 1560#define regVCN_UE_ERR_STATUS_LO_JPEG4D 0x0964 1561#define regVCN_UE_ERR_STATUS_LO_JPEG4D_BASE_IDX 1 1562#define regVCN_UE_ERR_STATUS_HI_JPEG4D 0x0965 1563#define regVCN_UE_ERR_STATUS_HI_JPEG4D_BASE_IDX 1 1564#define regVCN_UE_ERR_STATUS_LO_JPEG5S 0x0966 1565#define regVCN_UE_ERR_STATUS_LO_JPEG5S_BASE_IDX 1 1566#define regVCN_UE_ERR_STATUS_HI_JPEG5S 0x0967 1567#define regVCN_UE_ERR_STATUS_HI_JPEG5S_BASE_IDX 1 1568#define regVCN_UE_ERR_STATUS_LO_JPEG5D 0x0968 1569#define regVCN_UE_ERR_STATUS_LO_JPEG5D_BASE_IDX 1 1570#define regVCN_UE_ERR_STATUS_HI_JPEG5D 0x0969 1571#define regVCN_UE_ERR_STATUS_HI_JPEG5D_BASE_IDX 1 1572#define regVCN_UE_ERR_STATUS_LO_JPEG6S 0x096a 1573#define regVCN_UE_ERR_STATUS_LO_JPEG6S_BASE_IDX 1 1574#define regVCN_UE_ERR_STATUS_HI_JPEG6S 0x096b 1575#define regVCN_UE_ERR_STATUS_HI_JPEG6S_BASE_IDX 1 1576#define regVCN_UE_ERR_STATUS_LO_JPEG6D 0x096c 1577#define regVCN_UE_ERR_STATUS_LO_JPEG6D_BASE_IDX 1 1578#define regVCN_UE_ERR_STATUS_HI_JPEG6D 0x096d 1579#define regVCN_UE_ERR_STATUS_HI_JPEG6D_BASE_IDX 1 1580#define regVCN_UE_ERR_STATUS_LO_JPEG7S 0x096e 1581#define regVCN_UE_ERR_STATUS_LO_JPEG7S_BASE_IDX 1 1582#define regVCN_UE_ERR_STATUS_HI_JPEG7S 0x096f 1583#define regVCN_UE_ERR_STATUS_HI_JPEG7S_BASE_IDX 1 1584#define regVCN_UE_ERR_STATUS_LO_JPEG7D 0x0970 1585#define regVCN_UE_ERR_STATUS_LO_JPEG7D_BASE_IDX 1 1586#define regVCN_UE_ERR_STATUS_HI_JPEG7D 0x0971 1587#define regVCN_UE_ERR_STATUS_HI_JPEG7D_BASE_IDX 1 1588 1589// addressBlock: aid_uvd0_uvd_jrbc1_uvd_jrbc_dec 1590// base address: 0x1e000 1591#define regUVD_JRBC1_UVD_JRBC_RB_WPTR 0x0000 1592#define regUVD_JRBC1_UVD_JRBC_RB_WPTR_BASE_IDX 0 1593#define regUVD_JRBC1_UVD_JRBC_RB_CNTL 0x0001 1594#define regUVD_JRBC1_UVD_JRBC_RB_CNTL_BASE_IDX 0 1595#define regUVD_JRBC1_UVD_JRBC_IB_SIZE 0x0002 1596#define regUVD_JRBC1_UVD_JRBC_IB_SIZE_BASE_IDX 0 1597#define regUVD_JRBC1_UVD_JRBC_URGENT_CNTL 0x0003 1598#define regUVD_JRBC1_UVD_JRBC_URGENT_CNTL_BASE_IDX 0 1599#define regUVD_JRBC1_UVD_JRBC_RB_REF_DATA 0x0004 1600#define regUVD_JRBC1_UVD_JRBC_RB_REF_DATA_BASE_IDX 0 1601#define regUVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER 0x0005 1602#define regUVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0 1603#define regUVD_JRBC1_UVD_JRBC_SOFT_RESET 0x0008 1604#define regUVD_JRBC1_UVD_JRBC_SOFT_RESET_BASE_IDX 0 1605#define regUVD_JRBC1_UVD_JRBC_STATUS 0x0009 1606#define regUVD_JRBC1_UVD_JRBC_STATUS_BASE_IDX 0 1607#define regUVD_JRBC1_UVD_JRBC_RB_RPTR 0x000a 1608#define regUVD_JRBC1_UVD_JRBC_RB_RPTR_BASE_IDX 0 1609#define regUVD_JRBC1_UVD_JRBC_RB_BUF_STATUS 0x000b 1610#define regUVD_JRBC1_UVD_JRBC_RB_BUF_STATUS_BASE_IDX 0 1611#define regUVD_JRBC1_UVD_JRBC_IB_BUF_STATUS 0x000c 1612#define regUVD_JRBC1_UVD_JRBC_IB_BUF_STATUS_BASE_IDX 0 1613#define regUVD_JRBC1_UVD_JRBC_IB_SIZE_UPDATE 0x000d 1614#define regUVD_JRBC1_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 0 1615#define regUVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER 0x000e 1616#define regUVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 0 1617#define regUVD_JRBC1_UVD_JRBC_IB_REF_DATA 0x000f 1618#define regUVD_JRBC1_UVD_JRBC_IB_REF_DATA_BASE_IDX 0 1619#define regUVD_JRBC1_UVD_JPEG_PREEMPT_CMD 0x0010 1620#define regUVD_JRBC1_UVD_JPEG_PREEMPT_CMD_BASE_IDX 0 1621#define regUVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA0 0x0011 1622#define regUVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 0 1623#define regUVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA1 0x0012 1624#define regUVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 0 1625#define regUVD_JRBC1_UVD_JRBC_RB_SIZE 0x0013 1626#define regUVD_JRBC1_UVD_JRBC_RB_SIZE_BASE_IDX 0 1627#define regUVD_JRBC1_UVD_JRBC_SCRATCH0 0x0014 1628#define regUVD_JRBC1_UVD_JRBC_SCRATCH0_BASE_IDX 0 1629 1630 1631// addressBlock: aid_uvd0_uvd_jrbc2_uvd_jrbc_dec 1632// base address: 0x1e100 1633#define regUVD_JRBC2_UVD_JRBC_RB_WPTR 0x0040 1634#define regUVD_JRBC2_UVD_JRBC_RB_WPTR_BASE_IDX 0 1635#define regUVD_JRBC2_UVD_JRBC_RB_CNTL 0x0041 1636#define regUVD_JRBC2_UVD_JRBC_RB_CNTL_BASE_IDX 0 1637#define regUVD_JRBC2_UVD_JRBC_IB_SIZE 0x0042 1638#define regUVD_JRBC2_UVD_JRBC_IB_SIZE_BASE_IDX 0 1639#define regUVD_JRBC2_UVD_JRBC_URGENT_CNTL 0x0043 1640#define regUVD_JRBC2_UVD_JRBC_URGENT_CNTL_BASE_IDX 0 1641#define regUVD_JRBC2_UVD_JRBC_RB_REF_DATA 0x0044 1642#define regUVD_JRBC2_UVD_JRBC_RB_REF_DATA_BASE_IDX 0 1643#define regUVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER 0x0045 1644#define regUVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0 1645#define regUVD_JRBC2_UVD_JRBC_SOFT_RESET 0x0048 1646#define regUVD_JRBC2_UVD_JRBC_SOFT_RESET_BASE_IDX 0 1647#define regUVD_JRBC2_UVD_JRBC_STATUS 0x0049 1648#define regUVD_JRBC2_UVD_JRBC_STATUS_BASE_IDX 0 1649#define regUVD_JRBC2_UVD_JRBC_RB_RPTR 0x004a 1650#define regUVD_JRBC2_UVD_JRBC_RB_RPTR_BASE_IDX 0 1651#define regUVD_JRBC2_UVD_JRBC_RB_BUF_STATUS 0x004b 1652#define regUVD_JRBC2_UVD_JRBC_RB_BUF_STATUS_BASE_IDX 0 1653#define regUVD_JRBC2_UVD_JRBC_IB_BUF_STATUS 0x004c 1654#define regUVD_JRBC2_UVD_JRBC_IB_BUF_STATUS_BASE_IDX 0 1655#define regUVD_JRBC2_UVD_JRBC_IB_SIZE_UPDATE 0x004d 1656#define regUVD_JRBC2_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 0 1657#define regUVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER 0x004e 1658#define regUVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 0 1659#define regUVD_JRBC2_UVD_JRBC_IB_REF_DATA 0x004f 1660#define regUVD_JRBC2_UVD_JRBC_IB_REF_DATA_BASE_IDX 0 1661#define regUVD_JRBC2_UVD_JPEG_PREEMPT_CMD 0x0050 1662#define regUVD_JRBC2_UVD_JPEG_PREEMPT_CMD_BASE_IDX 0 1663#define regUVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA0 0x0051 1664#define regUVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 0 1665#define regUVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA1 0x0052 1666#define regUVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 0 1667#define regUVD_JRBC2_UVD_JRBC_RB_SIZE 0x0053 1668#define regUVD_JRBC2_UVD_JRBC_RB_SIZE_BASE_IDX 0 1669#define regUVD_JRBC2_UVD_JRBC_SCRATCH0 0x0054 1670#define regUVD_JRBC2_UVD_JRBC_SCRATCH0_BASE_IDX 0 1671 1672 1673// addressBlock: aid_uvd0_uvd_jrbc3_uvd_jrbc_dec 1674// base address: 0x1e200 1675#define regUVD_JRBC3_UVD_JRBC_RB_WPTR 0x0080 1676#define regUVD_JRBC3_UVD_JRBC_RB_WPTR_BASE_IDX 0 1677#define regUVD_JRBC3_UVD_JRBC_RB_CNTL 0x0081 1678#define regUVD_JRBC3_UVD_JRBC_RB_CNTL_BASE_IDX 0 1679#define regUVD_JRBC3_UVD_JRBC_IB_SIZE 0x0082 1680#define regUVD_JRBC3_UVD_JRBC_IB_SIZE_BASE_IDX 0 1681#define regUVD_JRBC3_UVD_JRBC_URGENT_CNTL 0x0083 1682#define regUVD_JRBC3_UVD_JRBC_URGENT_CNTL_BASE_IDX 0 1683#define regUVD_JRBC3_UVD_JRBC_RB_REF_DATA 0x0084 1684#define regUVD_JRBC3_UVD_JRBC_RB_REF_DATA_BASE_IDX 0 1685#define regUVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER 0x0085 1686#define regUVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0 1687#define regUVD_JRBC3_UVD_JRBC_SOFT_RESET 0x0088 1688#define regUVD_JRBC3_UVD_JRBC_SOFT_RESET_BASE_IDX 0 1689#define regUVD_JRBC3_UVD_JRBC_STATUS 0x0089 1690#define regUVD_JRBC3_UVD_JRBC_STATUS_BASE_IDX 0 1691#define regUVD_JRBC3_UVD_JRBC_RB_RPTR 0x008a 1692#define regUVD_JRBC3_UVD_JRBC_RB_RPTR_BASE_IDX 0 1693#define regUVD_JRBC3_UVD_JRBC_RB_BUF_STATUS 0x008b 1694#define regUVD_JRBC3_UVD_JRBC_RB_BUF_STATUS_BASE_IDX 0 1695#define regUVD_JRBC3_UVD_JRBC_IB_BUF_STATUS 0x008c 1696#define regUVD_JRBC3_UVD_JRBC_IB_BUF_STATUS_BASE_IDX 0 1697#define regUVD_JRBC3_UVD_JRBC_IB_SIZE_UPDATE 0x008d 1698#define regUVD_JRBC3_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 0 1699#define regUVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER 0x008e 1700#define regUVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 0 1701#define regUVD_JRBC3_UVD_JRBC_IB_REF_DATA 0x008f 1702#define regUVD_JRBC3_UVD_JRBC_IB_REF_DATA_BASE_IDX 0 1703#define regUVD_JRBC3_UVD_JPEG_PREEMPT_CMD 0x0090 1704#define regUVD_JRBC3_UVD_JPEG_PREEMPT_CMD_BASE_IDX 0 1705#define regUVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA0 0x0091 1706#define regUVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 0 1707#define regUVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA1 0x0092 1708#define regUVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 0 1709#define regUVD_JRBC3_UVD_JRBC_RB_SIZE 0x0093 1710#define regUVD_JRBC3_UVD_JRBC_RB_SIZE_BASE_IDX 0 1711#define regUVD_JRBC3_UVD_JRBC_SCRATCH0 0x0094 1712#define regUVD_JRBC3_UVD_JRBC_SCRATCH0_BASE_IDX 0 1713 1714 1715// addressBlock: aid_uvd0_uvd_jrbc4_uvd_jrbc_dec 1716// base address: 0x1e300 1717#define regUVD_JRBC4_UVD_JRBC_RB_WPTR 0x00c0 1718#define regUVD_JRBC4_UVD_JRBC_RB_WPTR_BASE_IDX 0 1719#define regUVD_JRBC4_UVD_JRBC_RB_CNTL 0x00c1 1720#define regUVD_JRBC4_UVD_JRBC_RB_CNTL_BASE_IDX 0 1721#define regUVD_JRBC4_UVD_JRBC_IB_SIZE 0x00c2 1722#define regUVD_JRBC4_UVD_JRBC_IB_SIZE_BASE_IDX 0 1723#define regUVD_JRBC4_UVD_JRBC_URGENT_CNTL 0x00c3 1724#define regUVD_JRBC4_UVD_JRBC_URGENT_CNTL_BASE_IDX 0 1725#define regUVD_JRBC4_UVD_JRBC_RB_REF_DATA 0x00c4 1726#define regUVD_JRBC4_UVD_JRBC_RB_REF_DATA_BASE_IDX 0 1727#define regUVD_JRBC4_UVD_JRBC_RB_COND_RD_TIMER 0x00c5 1728#define regUVD_JRBC4_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0 1729#define regUVD_JRBC4_UVD_JRBC_SOFT_RESET 0x00c8 1730#define regUVD_JRBC4_UVD_JRBC_SOFT_RESET_BASE_IDX 0 1731#define regUVD_JRBC4_UVD_JRBC_STATUS 0x00c9 1732#define regUVD_JRBC4_UVD_JRBC_STATUS_BASE_IDX 0 1733#define regUVD_JRBC4_UVD_JRBC_RB_RPTR 0x00ca 1734#define regUVD_JRBC4_UVD_JRBC_RB_RPTR_BASE_IDX 0 1735#define regUVD_JRBC4_UVD_JRBC_RB_BUF_STATUS 0x00cb 1736#define regUVD_JRBC4_UVD_JRBC_RB_BUF_STATUS_BASE_IDX 0 1737#define regUVD_JRBC4_UVD_JRBC_IB_BUF_STATUS 0x00cc 1738#define regUVD_JRBC4_UVD_JRBC_IB_BUF_STATUS_BASE_IDX 0 1739#define regUVD_JRBC4_UVD_JRBC_IB_SIZE_UPDATE 0x00cd 1740#define regUVD_JRBC4_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 0 1741#define regUVD_JRBC4_UVD_JRBC_IB_COND_RD_TIMER 0x00ce 1742#define regUVD_JRBC4_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 0 1743#define regUVD_JRBC4_UVD_JRBC_IB_REF_DATA 0x00cf 1744#define regUVD_JRBC4_UVD_JRBC_IB_REF_DATA_BASE_IDX 0 1745#define regUVD_JRBC4_UVD_JPEG_PREEMPT_CMD 0x00d0 1746#define regUVD_JRBC4_UVD_JPEG_PREEMPT_CMD_BASE_IDX 0 1747#define regUVD_JRBC4_UVD_JPEG_PREEMPT_FENCE_DATA0 0x00d1 1748#define regUVD_JRBC4_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 0 1749#define regUVD_JRBC4_UVD_JPEG_PREEMPT_FENCE_DATA1 0x00d2 1750#define regUVD_JRBC4_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 0 1751#define regUVD_JRBC4_UVD_JRBC_RB_SIZE 0x00d3 1752#define regUVD_JRBC4_UVD_JRBC_RB_SIZE_BASE_IDX 0 1753#define regUVD_JRBC4_UVD_JRBC_SCRATCH0 0x00d4 1754#define regUVD_JRBC4_UVD_JRBC_SCRATCH0_BASE_IDX 0 1755 1756 1757// addressBlock: aid_uvd0_uvd_jrbc5_uvd_jrbc_dec 1758// base address: 0x1e400 1759#define regUVD_JRBC5_UVD_JRBC_RB_WPTR 0x0100 1760#define regUVD_JRBC5_UVD_JRBC_RB_WPTR_BASE_IDX 0 1761#define regUVD_JRBC5_UVD_JRBC_RB_CNTL 0x0101 1762#define regUVD_JRBC5_UVD_JRBC_RB_CNTL_BASE_IDX 0 1763#define regUVD_JRBC5_UVD_JRBC_IB_SIZE 0x0102 1764#define regUVD_JRBC5_UVD_JRBC_IB_SIZE_BASE_IDX 0 1765#define regUVD_JRBC5_UVD_JRBC_URGENT_CNTL 0x0103 1766#define regUVD_JRBC5_UVD_JRBC_URGENT_CNTL_BASE_IDX 0 1767#define regUVD_JRBC5_UVD_JRBC_RB_REF_DATA 0x0104 1768#define regUVD_JRBC5_UVD_JRBC_RB_REF_DATA_BASE_IDX 0 1769#define regUVD_JRBC5_UVD_JRBC_RB_COND_RD_TIMER 0x0105 1770#define regUVD_JRBC5_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0 1771#define regUVD_JRBC5_UVD_JRBC_SOFT_RESET 0x0108 1772#define regUVD_JRBC5_UVD_JRBC_SOFT_RESET_BASE_IDX 0 1773#define regUVD_JRBC5_UVD_JRBC_STATUS 0x0109 1774#define regUVD_JRBC5_UVD_JRBC_STATUS_BASE_IDX 0 1775#define regUVD_JRBC5_UVD_JRBC_RB_RPTR 0x010a 1776#define regUVD_JRBC5_UVD_JRBC_RB_RPTR_BASE_IDX 0 1777#define regUVD_JRBC5_UVD_JRBC_RB_BUF_STATUS 0x010b 1778#define regUVD_JRBC5_UVD_JRBC_RB_BUF_STATUS_BASE_IDX 0 1779#define regUVD_JRBC5_UVD_JRBC_IB_BUF_STATUS 0x010c 1780#define regUVD_JRBC5_UVD_JRBC_IB_BUF_STATUS_BASE_IDX 0 1781#define regUVD_JRBC5_UVD_JRBC_IB_SIZE_UPDATE 0x010d 1782#define regUVD_JRBC5_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 0 1783#define regUVD_JRBC5_UVD_JRBC_IB_COND_RD_TIMER 0x010e 1784#define regUVD_JRBC5_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 0 1785#define regUVD_JRBC5_UVD_JRBC_IB_REF_DATA 0x010f 1786#define regUVD_JRBC5_UVD_JRBC_IB_REF_DATA_BASE_IDX 0 1787#define regUVD_JRBC5_UVD_JPEG_PREEMPT_CMD 0x0110 1788#define regUVD_JRBC5_UVD_JPEG_PREEMPT_CMD_BASE_IDX 0 1789#define regUVD_JRBC5_UVD_JPEG_PREEMPT_FENCE_DATA0 0x0111 1790#define regUVD_JRBC5_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 0 1791#define regUVD_JRBC5_UVD_JPEG_PREEMPT_FENCE_DATA1 0x0112 1792#define regUVD_JRBC5_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 0 1793#define regUVD_JRBC5_UVD_JRBC_RB_SIZE 0x0113 1794#define regUVD_JRBC5_UVD_JRBC_RB_SIZE_BASE_IDX 0 1795#define regUVD_JRBC5_UVD_JRBC_SCRATCH0 0x0114 1796#define regUVD_JRBC5_UVD_JRBC_SCRATCH0_BASE_IDX 0 1797 1798 1799// addressBlock: aid_uvd0_uvd_jrbc6_uvd_jrbc_dec 1800// base address: 0x1e500 1801#define regUVD_JRBC6_UVD_JRBC_RB_WPTR 0x0140 1802#define regUVD_JRBC6_UVD_JRBC_RB_WPTR_BASE_IDX 0 1803#define regUVD_JRBC6_UVD_JRBC_RB_CNTL 0x0141 1804#define regUVD_JRBC6_UVD_JRBC_RB_CNTL_BASE_IDX 0 1805#define regUVD_JRBC6_UVD_JRBC_IB_SIZE 0x0142 1806#define regUVD_JRBC6_UVD_JRBC_IB_SIZE_BASE_IDX 0 1807#define regUVD_JRBC6_UVD_JRBC_URGENT_CNTL 0x0143 1808#define regUVD_JRBC6_UVD_JRBC_URGENT_CNTL_BASE_IDX 0 1809#define regUVD_JRBC6_UVD_JRBC_RB_REF_DATA 0x0144 1810#define regUVD_JRBC6_UVD_JRBC_RB_REF_DATA_BASE_IDX 0 1811#define regUVD_JRBC6_UVD_JRBC_RB_COND_RD_TIMER 0x0145 1812#define regUVD_JRBC6_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0 1813#define regUVD_JRBC6_UVD_JRBC_SOFT_RESET 0x0148 1814#define regUVD_JRBC6_UVD_JRBC_SOFT_RESET_BASE_IDX 0 1815#define regUVD_JRBC6_UVD_JRBC_STATUS 0x0149 1816#define regUVD_JRBC6_UVD_JRBC_STATUS_BASE_IDX 0 1817#define regUVD_JRBC6_UVD_JRBC_RB_RPTR 0x014a 1818#define regUVD_JRBC6_UVD_JRBC_RB_RPTR_BASE_IDX 0 1819#define regUVD_JRBC6_UVD_JRBC_RB_BUF_STATUS 0x014b 1820#define regUVD_JRBC6_UVD_JRBC_RB_BUF_STATUS_BASE_IDX 0 1821#define regUVD_JRBC6_UVD_JRBC_IB_BUF_STATUS 0x014c 1822#define regUVD_JRBC6_UVD_JRBC_IB_BUF_STATUS_BASE_IDX 0 1823#define regUVD_JRBC6_UVD_JRBC_IB_SIZE_UPDATE 0x014d 1824#define regUVD_JRBC6_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 0 1825#define regUVD_JRBC6_UVD_JRBC_IB_COND_RD_TIMER 0x014e 1826#define regUVD_JRBC6_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 0 1827#define regUVD_JRBC6_UVD_JRBC_IB_REF_DATA 0x014f 1828#define regUVD_JRBC6_UVD_JRBC_IB_REF_DATA_BASE_IDX 0 1829#define regUVD_JRBC6_UVD_JPEG_PREEMPT_CMD 0x0150 1830#define regUVD_JRBC6_UVD_JPEG_PREEMPT_CMD_BASE_IDX 0 1831#define regUVD_JRBC6_UVD_JPEG_PREEMPT_FENCE_DATA0 0x0151 1832#define regUVD_JRBC6_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 0 1833#define regUVD_JRBC6_UVD_JPEG_PREEMPT_FENCE_DATA1 0x0152 1834#define regUVD_JRBC6_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 0 1835#define regUVD_JRBC6_UVD_JRBC_RB_SIZE 0x0153 1836#define regUVD_JRBC6_UVD_JRBC_RB_SIZE_BASE_IDX 0 1837#define regUVD_JRBC6_UVD_JRBC_SCRATCH0 0x0154 1838#define regUVD_JRBC6_UVD_JRBC_SCRATCH0_BASE_IDX 0 1839 1840 1841// addressBlock: aid_uvd0_uvd_jrbc7_uvd_jrbc_dec 1842// base address: 0x1e600 1843#define regUVD_JRBC7_UVD_JRBC_RB_WPTR 0x0180 1844#define regUVD_JRBC7_UVD_JRBC_RB_WPTR_BASE_IDX 0 1845#define regUVD_JRBC7_UVD_JRBC_RB_CNTL 0x0181 1846#define regUVD_JRBC7_UVD_JRBC_RB_CNTL_BASE_IDX 0 1847#define regUVD_JRBC7_UVD_JRBC_IB_SIZE 0x0182 1848#define regUVD_JRBC7_UVD_JRBC_IB_SIZE_BASE_IDX 0 1849#define regUVD_JRBC7_UVD_JRBC_URGENT_CNTL 0x0183 1850#define regUVD_JRBC7_UVD_JRBC_URGENT_CNTL_BASE_IDX 0 1851#define regUVD_JRBC7_UVD_JRBC_RB_REF_DATA 0x0184 1852#define regUVD_JRBC7_UVD_JRBC_RB_REF_DATA_BASE_IDX 0 1853#define regUVD_JRBC7_UVD_JRBC_RB_COND_RD_TIMER 0x0185 1854#define regUVD_JRBC7_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0 1855#define regUVD_JRBC7_UVD_JRBC_SOFT_RESET 0x0188 1856#define regUVD_JRBC7_UVD_JRBC_SOFT_RESET_BASE_IDX 0 1857#define regUVD_JRBC7_UVD_JRBC_STATUS 0x0189 1858#define regUVD_JRBC7_UVD_JRBC_STATUS_BASE_IDX 0 1859#define regUVD_JRBC7_UVD_JRBC_RB_RPTR 0x018a 1860#define regUVD_JRBC7_UVD_JRBC_RB_RPTR_BASE_IDX 0 1861#define regUVD_JRBC7_UVD_JRBC_RB_BUF_STATUS 0x018b 1862#define regUVD_JRBC7_UVD_JRBC_RB_BUF_STATUS_BASE_IDX 0 1863#define regUVD_JRBC7_UVD_JRBC_IB_BUF_STATUS 0x018c 1864#define regUVD_JRBC7_UVD_JRBC_IB_BUF_STATUS_BASE_IDX 0 1865#define regUVD_JRBC7_UVD_JRBC_IB_SIZE_UPDATE 0x018d 1866#define regUVD_JRBC7_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 0 1867#define regUVD_JRBC7_UVD_JRBC_IB_COND_RD_TIMER 0x018e 1868#define regUVD_JRBC7_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 0 1869#define regUVD_JRBC7_UVD_JRBC_IB_REF_DATA 0x018f 1870#define regUVD_JRBC7_UVD_JRBC_IB_REF_DATA_BASE_IDX 0 1871#define regUVD_JRBC7_UVD_JPEG_PREEMPT_CMD 0x0190 1872#define regUVD_JRBC7_UVD_JPEG_PREEMPT_CMD_BASE_IDX 0 1873#define regUVD_JRBC7_UVD_JPEG_PREEMPT_FENCE_DATA0 0x0191 1874#define regUVD_JRBC7_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 0 1875#define regUVD_JRBC7_UVD_JPEG_PREEMPT_FENCE_DATA1 0x0192 1876#define regUVD_JRBC7_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 0 1877#define regUVD_JRBC7_UVD_JRBC_RB_SIZE 0x0193 1878#define regUVD_JRBC7_UVD_JRBC_RB_SIZE_BASE_IDX 0 1879#define regUVD_JRBC7_UVD_JRBC_SCRATCH0 0x0194 1880#define regUVD_JRBC7_UVD_JRBC_SCRATCH0_BASE_IDX 0 1881 1882 1883// addressBlock: aid_uvd0_uvd_jmi1_uvd_jmi_dec 1884// base address: 0x1e080 1885#define regUVD_JMI1_UVD_JPEG_DEC_PF_CTRL 0x0020 1886#define regUVD_JMI1_UVD_JPEG_DEC_PF_CTRL_BASE_IDX 0 1887#define regUVD_JMI1_UVD_LMI_JRBC_CTRL 0x0021 1888#define regUVD_JMI1_UVD_LMI_JRBC_CTRL_BASE_IDX 0 1889#define regUVD_JMI1_UVD_LMI_JPEG_CTRL 0x0022 1890#define regUVD_JMI1_UVD_LMI_JPEG_CTRL_BASE_IDX 0 1891#define regUVD_JMI1_JPEG_LMI_DROP 0x0023 1892#define regUVD_JMI1_JPEG_LMI_DROP_BASE_IDX 0 1893#define regUVD_JMI1_UVD_LMI_JRBC_IB_VMID 0x0024 1894#define regUVD_JMI1_UVD_LMI_JRBC_IB_VMID_BASE_IDX 0 1895#define regUVD_JMI1_UVD_LMI_JRBC_RB_VMID 0x0025 1896#define regUVD_JMI1_UVD_LMI_JRBC_RB_VMID_BASE_IDX 0 1897#define regUVD_JMI1_UVD_LMI_JPEG_VMID 0x0026 1898#define regUVD_JMI1_UVD_LMI_JPEG_VMID_BASE_IDX 0 1899#define regUVD_JMI1_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x0027 1900#define regUVD_JMI1_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 1901#define regUVD_JMI1_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x0028 1902#define regUVD_JMI1_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 1903#define regUVD_JMI1_UVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0029 1904#define regUVD_JMI1_UVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 1905#define regUVD_JMI1_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x002a 1906#define regUVD_JMI1_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 1907#define regUVD_JMI1_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x002b 1908#define regUVD_JMI1_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 1909#define regUVD_JMI1_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x002c 1910#define regUVD_JMI1_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 1911#define regUVD_JMI1_UVD_LMI_JPEG_PREEMPT_VMID 0x002d 1912#define regUVD_JMI1_UVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 0 1913#define regUVD_JMI1_UVD_JMI_DEC_SWAP_CNTL 0x002e 1914#define regUVD_JMI1_UVD_JMI_DEC_SWAP_CNTL_BASE_IDX 0 1915#define regUVD_JMI1_UVD_JMI_ATOMIC_CNTL 0x002f 1916#define regUVD_JMI1_UVD_JMI_ATOMIC_CNTL_BASE_IDX 0 1917#define regUVD_JMI1_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 0x0030 1918#define regUVD_JMI1_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX 0 1919#define regUVD_JMI1_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 0x0031 1920#define regUVD_JMI1_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 1921#define regUVD_JMI1_UVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x0032 1922#define regUVD_JMI1_UVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 0 1923#define regUVD_JMI1_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x0033 1924#define regUVD_JMI1_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 0 1925#define regUVD_JMI1_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0034 1926#define regUVD_JMI1_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 0 1927#define regUVD_JMI1_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0035 1928#define regUVD_JMI1_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 1929#define regUVD_JMI1_UVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0036 1930#define regUVD_JMI1_UVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 1931#define regUVD_JMI1_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0037 1932#define regUVD_JMI1_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 1933#define regUVD_JMI1_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x0038 1934#define regUVD_JMI1_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 1935#define regUVD_JMI1_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x0039 1936#define regUVD_JMI1_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 1937#define regUVD_JMI1_UVD_JMI_ATOMIC_CNTL2 0x003d 1938#define regUVD_JMI1_UVD_JMI_ATOMIC_CNTL2_BASE_IDX 0 1939#define regUVD_JMI1_UVD_JMI_CLIENT_STALL 0x003a 1940#define regUVD_JMI1_UVD_JMI_CLIENT_STALL_BASE_IDX 0 1941#define regUVD_JMI1_UVD_JMI_CLIENT_CLEAN_STATUS 0x003b 1942#define regUVD_JMI1_UVD_JMI_CLIENT_CLEAN_STATUS_BASE_IDX 0 1943 1944 1945// addressBlock: aid_uvd0_uvd_jmi2_uvd_jmi_dec 1946// base address: 0x1e180 1947#define regUVD_JMI2_UVD_JPEG_DEC_PF_CTRL 0x0060 1948#define regUVD_JMI2_UVD_JPEG_DEC_PF_CTRL_BASE_IDX 0 1949#define regUVD_JMI2_UVD_LMI_JRBC_CTRL 0x0061 1950#define regUVD_JMI2_UVD_LMI_JRBC_CTRL_BASE_IDX 0 1951#define regUVD_JMI2_UVD_LMI_JPEG_CTRL 0x0062 1952#define regUVD_JMI2_UVD_LMI_JPEG_CTRL_BASE_IDX 0 1953#define regUVD_JMI2_JPEG_LMI_DROP 0x0063 1954#define regUVD_JMI2_JPEG_LMI_DROP_BASE_IDX 0 1955#define regUVD_JMI2_UVD_LMI_JRBC_IB_VMID 0x0064 1956#define regUVD_JMI2_UVD_LMI_JRBC_IB_VMID_BASE_IDX 0 1957#define regUVD_JMI2_UVD_LMI_JRBC_RB_VMID 0x0065 1958#define regUVD_JMI2_UVD_LMI_JRBC_RB_VMID_BASE_IDX 0 1959#define regUVD_JMI2_UVD_LMI_JPEG_VMID 0x0066 1960#define regUVD_JMI2_UVD_LMI_JPEG_VMID_BASE_IDX 0 1961#define regUVD_JMI2_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x0067 1962#define regUVD_JMI2_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 1963#define regUVD_JMI2_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x0068 1964#define regUVD_JMI2_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 1965#define regUVD_JMI2_UVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0069 1966#define regUVD_JMI2_UVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 1967#define regUVD_JMI2_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x006a 1968#define regUVD_JMI2_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 1969#define regUVD_JMI2_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x006b 1970#define regUVD_JMI2_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 1971#define regUVD_JMI2_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x006c 1972#define regUVD_JMI2_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 1973#define regUVD_JMI2_UVD_LMI_JPEG_PREEMPT_VMID 0x006d 1974#define regUVD_JMI2_UVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 0 1975#define regUVD_JMI2_UVD_JMI_DEC_SWAP_CNTL 0x006e 1976#define regUVD_JMI2_UVD_JMI_DEC_SWAP_CNTL_BASE_IDX 0 1977#define regUVD_JMI2_UVD_JMI_ATOMIC_CNTL 0x006f 1978#define regUVD_JMI2_UVD_JMI_ATOMIC_CNTL_BASE_IDX 0 1979#define regUVD_JMI2_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 0x0070 1980#define regUVD_JMI2_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX 0 1981#define regUVD_JMI2_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 0x0071 1982#define regUVD_JMI2_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 1983#define regUVD_JMI2_UVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x0072 1984#define regUVD_JMI2_UVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 0 1985#define regUVD_JMI2_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x0073 1986#define regUVD_JMI2_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 0 1987#define regUVD_JMI2_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0074 1988#define regUVD_JMI2_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 0 1989#define regUVD_JMI2_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0075 1990#define regUVD_JMI2_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 1991#define regUVD_JMI2_UVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0076 1992#define regUVD_JMI2_UVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 1993#define regUVD_JMI2_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0077 1994#define regUVD_JMI2_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 1995#define regUVD_JMI2_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x0078 1996#define regUVD_JMI2_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 1997#define regUVD_JMI2_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x0079 1998#define regUVD_JMI2_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 1999#define regUVD_JMI2_UVD_JMI_ATOMIC_CNTL2 0x007d 2000#define regUVD_JMI2_UVD_JMI_ATOMIC_CNTL2_BASE_IDX 0 2001#define regUVD_JMI2_UVD_JMI_CLIENT_STALL 0x007a 2002#define regUVD_JMI2_UVD_JMI_CLIENT_STALL_BASE_IDX 0 2003#define regUVD_JMI2_UVD_JMI_CLIENT_CLEAN_STATUS 0x007b 2004#define regUVD_JMI2_UVD_JMI_CLIENT_CLEAN_STATUS_BASE_IDX 0 2005 2006 2007// addressBlock: aid_uvd0_uvd_jmi3_uvd_jmi_dec 2008// base address: 0x1e280 2009#define regUVD_JMI3_UVD_JPEG_DEC_PF_CTRL 0x00a0 2010#define regUVD_JMI3_UVD_JPEG_DEC_PF_CTRL_BASE_IDX 0 2011#define regUVD_JMI3_UVD_LMI_JRBC_CTRL 0x00a1 2012#define regUVD_JMI3_UVD_LMI_JRBC_CTRL_BASE_IDX 0 2013#define regUVD_JMI3_UVD_LMI_JPEG_CTRL 0x00a2 2014#define regUVD_JMI3_UVD_LMI_JPEG_CTRL_BASE_IDX 0 2015#define regUVD_JMI3_JPEG_LMI_DROP 0x00a3 2016#define regUVD_JMI3_JPEG_LMI_DROP_BASE_IDX 0 2017#define regUVD_JMI3_UVD_LMI_JRBC_IB_VMID 0x00a4 2018#define regUVD_JMI3_UVD_LMI_JRBC_IB_VMID_BASE_IDX 0 2019#define regUVD_JMI3_UVD_LMI_JRBC_RB_VMID 0x00a5 2020#define regUVD_JMI3_UVD_LMI_JRBC_RB_VMID_BASE_IDX 0 2021#define regUVD_JMI3_UVD_LMI_JPEG_VMID 0x00a6 2022#define regUVD_JMI3_UVD_LMI_JPEG_VMID_BASE_IDX 0 2023#define regUVD_JMI3_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x00a7 2024#define regUVD_JMI3_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 2025#define regUVD_JMI3_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x00a8 2026#define regUVD_JMI3_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 2027#define regUVD_JMI3_UVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x00a9 2028#define regUVD_JMI3_UVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 2029#define regUVD_JMI3_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x00aa 2030#define regUVD_JMI3_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 2031#define regUVD_JMI3_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x00ab 2032#define regUVD_JMI3_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 2033#define regUVD_JMI3_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x00ac 2034#define regUVD_JMI3_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 2035#define regUVD_JMI3_UVD_LMI_JPEG_PREEMPT_VMID 0x00ad 2036#define regUVD_JMI3_UVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 0 2037#define regUVD_JMI3_UVD_JMI_DEC_SWAP_CNTL 0x00ae 2038#define regUVD_JMI3_UVD_JMI_DEC_SWAP_CNTL_BASE_IDX 0 2039#define regUVD_JMI3_UVD_JMI_ATOMIC_CNTL 0x00af 2040#define regUVD_JMI3_UVD_JMI_ATOMIC_CNTL_BASE_IDX 0 2041#define regUVD_JMI3_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 0x00b0 2042#define regUVD_JMI3_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX 0 2043#define regUVD_JMI3_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 0x00b1 2044#define regUVD_JMI3_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 2045#define regUVD_JMI3_UVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x00b2 2046#define regUVD_JMI3_UVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 0 2047#define regUVD_JMI3_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x00b3 2048#define regUVD_JMI3_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 0 2049#define regUVD_JMI3_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x00b4 2050#define regUVD_JMI3_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 0 2051#define regUVD_JMI3_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x00b5 2052#define regUVD_JMI3_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 2053#define regUVD_JMI3_UVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x00b6 2054#define regUVD_JMI3_UVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 2055#define regUVD_JMI3_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x00b7 2056#define regUVD_JMI3_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 2057#define regUVD_JMI3_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x00b8 2058#define regUVD_JMI3_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 2059#define regUVD_JMI3_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x00b9 2060#define regUVD_JMI3_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 2061#define regUVD_JMI3_UVD_JMI_ATOMIC_CNTL2 0x00bd 2062#define regUVD_JMI3_UVD_JMI_ATOMIC_CNTL2_BASE_IDX 0 2063#define regUVD_JMI3_UVD_JMI_CLIENT_STALL 0x00ba 2064#define regUVD_JMI3_UVD_JMI_CLIENT_STALL_BASE_IDX 0 2065#define regUVD_JMI3_UVD_JMI_CLIENT_CLEAN_STATUS 0x00bb 2066#define regUVD_JMI3_UVD_JMI_CLIENT_CLEAN_STATUS_BASE_IDX 0 2067 2068 2069// addressBlock: aid_uvd0_uvd_jmi4_uvd_jmi_dec 2070// base address: 0x1e380 2071#define regUVD_JMI4_UVD_JPEG_DEC_PF_CTRL 0x00e0 2072#define regUVD_JMI4_UVD_JPEG_DEC_PF_CTRL_BASE_IDX 0 2073#define regUVD_JMI4_UVD_LMI_JRBC_CTRL 0x00e1 2074#define regUVD_JMI4_UVD_LMI_JRBC_CTRL_BASE_IDX 0 2075#define regUVD_JMI4_UVD_LMI_JPEG_CTRL 0x00e2 2076#define regUVD_JMI4_UVD_LMI_JPEG_CTRL_BASE_IDX 0 2077#define regUVD_JMI4_JPEG_LMI_DROP 0x00e3 2078#define regUVD_JMI4_JPEG_LMI_DROP_BASE_IDX 0 2079#define regUVD_JMI4_UVD_LMI_JRBC_IB_VMID 0x00e4 2080#define regUVD_JMI4_UVD_LMI_JRBC_IB_VMID_BASE_IDX 0 2081#define regUVD_JMI4_UVD_LMI_JRBC_RB_VMID 0x00e5 2082#define regUVD_JMI4_UVD_LMI_JRBC_RB_VMID_BASE_IDX 0 2083#define regUVD_JMI4_UVD_LMI_JPEG_VMID 0x00e6 2084#define regUVD_JMI4_UVD_LMI_JPEG_VMID_BASE_IDX 0 2085#define regUVD_JMI4_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x00e7 2086#define regUVD_JMI4_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 2087#define regUVD_JMI4_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x00e8 2088#define regUVD_JMI4_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 2089#define regUVD_JMI4_UVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x00e9 2090#define regUVD_JMI4_UVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 2091#define regUVD_JMI4_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x00ea 2092#define regUVD_JMI4_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 2093#define regUVD_JMI4_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x00eb 2094#define regUVD_JMI4_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 2095#define regUVD_JMI4_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x00ec 2096#define regUVD_JMI4_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 2097#define regUVD_JMI4_UVD_LMI_JPEG_PREEMPT_VMID 0x00ed 2098#define regUVD_JMI4_UVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 0 2099#define regUVD_JMI4_UVD_JMI_DEC_SWAP_CNTL 0x00ee 2100#define regUVD_JMI4_UVD_JMI_DEC_SWAP_CNTL_BASE_IDX 0 2101#define regUVD_JMI4_UVD_JMI_ATOMIC_CNTL 0x00ef 2102#define regUVD_JMI4_UVD_JMI_ATOMIC_CNTL_BASE_IDX 0 2103#define regUVD_JMI4_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 0x00f0 2104#define regUVD_JMI4_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX 0 2105#define regUVD_JMI4_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 0x00f1 2106#define regUVD_JMI4_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 2107#define regUVD_JMI4_UVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x00f2 2108#define regUVD_JMI4_UVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 0 2109#define regUVD_JMI4_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x00f3 2110#define regUVD_JMI4_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 0 2111#define regUVD_JMI4_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x00f4 2112#define regUVD_JMI4_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 0 2113#define regUVD_JMI4_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x00f5 2114#define regUVD_JMI4_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 2115#define regUVD_JMI4_UVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x00f6 2116#define regUVD_JMI4_UVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 2117#define regUVD_JMI4_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x00f7 2118#define regUVD_JMI4_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 2119#define regUVD_JMI4_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x00f8 2120#define regUVD_JMI4_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 2121#define regUVD_JMI4_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x00f9 2122#define regUVD_JMI4_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 2123#define regUVD_JMI4_UVD_JMI_ATOMIC_CNTL2 0x00fd 2124#define regUVD_JMI4_UVD_JMI_ATOMIC_CNTL2_BASE_IDX 0 2125#define regUVD_JMI4_UVD_JMI_CLIENT_STALL 0x00fa 2126#define regUVD_JMI4_UVD_JMI_CLIENT_STALL_BASE_IDX 0 2127#define regUVD_JMI4_UVD_JMI_CLIENT_CLEAN_STATUS 0x00fb 2128#define regUVD_JMI4_UVD_JMI_CLIENT_CLEAN_STATUS_BASE_IDX 0 2129 2130 2131// addressBlock: aid_uvd0_uvd_jmi5_uvd_jmi_dec 2132// base address: 0x1e480 2133#define regUVD_JMI5_UVD_JPEG_DEC_PF_CTRL 0x0120 2134#define regUVD_JMI5_UVD_JPEG_DEC_PF_CTRL_BASE_IDX 0 2135#define regUVD_JMI5_UVD_LMI_JRBC_CTRL 0x0121 2136#define regUVD_JMI5_UVD_LMI_JRBC_CTRL_BASE_IDX 0 2137#define regUVD_JMI5_UVD_LMI_JPEG_CTRL 0x0122 2138#define regUVD_JMI5_UVD_LMI_JPEG_CTRL_BASE_IDX 0 2139#define regUVD_JMI5_JPEG_LMI_DROP 0x0123 2140#define regUVD_JMI5_JPEG_LMI_DROP_BASE_IDX 0 2141#define regUVD_JMI5_UVD_LMI_JRBC_IB_VMID 0x0124 2142#define regUVD_JMI5_UVD_LMI_JRBC_IB_VMID_BASE_IDX 0 2143#define regUVD_JMI5_UVD_LMI_JRBC_RB_VMID 0x0125 2144#define regUVD_JMI5_UVD_LMI_JRBC_RB_VMID_BASE_IDX 0 2145#define regUVD_JMI5_UVD_LMI_JPEG_VMID 0x0126 2146#define regUVD_JMI5_UVD_LMI_JPEG_VMID_BASE_IDX 0 2147#define regUVD_JMI5_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x0127 2148#define regUVD_JMI5_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 2149#define regUVD_JMI5_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x0128 2150#define regUVD_JMI5_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 2151#define regUVD_JMI5_UVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0129 2152#define regUVD_JMI5_UVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 2153#define regUVD_JMI5_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x012a 2154#define regUVD_JMI5_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 2155#define regUVD_JMI5_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x012b 2156#define regUVD_JMI5_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 2157#define regUVD_JMI5_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x012c 2158#define regUVD_JMI5_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 2159#define regUVD_JMI5_UVD_LMI_JPEG_PREEMPT_VMID 0x012d 2160#define regUVD_JMI5_UVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 0 2161#define regUVD_JMI5_UVD_JMI_DEC_SWAP_CNTL 0x012e 2162#define regUVD_JMI5_UVD_JMI_DEC_SWAP_CNTL_BASE_IDX 0 2163#define regUVD_JMI5_UVD_JMI_ATOMIC_CNTL 0x012f 2164#define regUVD_JMI5_UVD_JMI_ATOMIC_CNTL_BASE_IDX 0 2165#define regUVD_JMI5_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 0x0130 2166#define regUVD_JMI5_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX 0 2167#define regUVD_JMI5_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 0x0131 2168#define regUVD_JMI5_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 2169#define regUVD_JMI5_UVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x0132 2170#define regUVD_JMI5_UVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 0 2171#define regUVD_JMI5_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x0133 2172#define regUVD_JMI5_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 0 2173#define regUVD_JMI5_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0134 2174#define regUVD_JMI5_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 0 2175#define regUVD_JMI5_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0135 2176#define regUVD_JMI5_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 2177#define regUVD_JMI5_UVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0136 2178#define regUVD_JMI5_UVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 2179#define regUVD_JMI5_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0137 2180#define regUVD_JMI5_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 2181#define regUVD_JMI5_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x0138 2182#define regUVD_JMI5_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 2183#define regUVD_JMI5_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x0139 2184#define regUVD_JMI5_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 2185#define regUVD_JMI5_UVD_JMI_ATOMIC_CNTL2 0x013d 2186#define regUVD_JMI5_UVD_JMI_ATOMIC_CNTL2_BASE_IDX 0 2187#define regUVD_JMI5_UVD_JMI_CLIENT_STALL 0x013a 2188#define regUVD_JMI5_UVD_JMI_CLIENT_STALL_BASE_IDX 0 2189#define regUVD_JMI5_UVD_JMI_CLIENT_CLEAN_STATUS 0x013b 2190#define regUVD_JMI5_UVD_JMI_CLIENT_CLEAN_STATUS_BASE_IDX 0 2191 2192 2193// addressBlock: aid_uvd0_uvd_jmi6_uvd_jmi_dec 2194// base address: 0x1e580 2195#define regUVD_JMI6_UVD_JPEG_DEC_PF_CTRL 0x0160 2196#define regUVD_JMI6_UVD_JPEG_DEC_PF_CTRL_BASE_IDX 0 2197#define regUVD_JMI6_UVD_LMI_JRBC_CTRL 0x0161 2198#define regUVD_JMI6_UVD_LMI_JRBC_CTRL_BASE_IDX 0 2199#define regUVD_JMI6_UVD_LMI_JPEG_CTRL 0x0162 2200#define regUVD_JMI6_UVD_LMI_JPEG_CTRL_BASE_IDX 0 2201#define regUVD_JMI6_JPEG_LMI_DROP 0x0163 2202#define regUVD_JMI6_JPEG_LMI_DROP_BASE_IDX 0 2203#define regUVD_JMI6_UVD_LMI_JRBC_IB_VMID 0x0164 2204#define regUVD_JMI6_UVD_LMI_JRBC_IB_VMID_BASE_IDX 0 2205#define regUVD_JMI6_UVD_LMI_JRBC_RB_VMID 0x0165 2206#define regUVD_JMI6_UVD_LMI_JRBC_RB_VMID_BASE_IDX 0 2207#define regUVD_JMI6_UVD_LMI_JPEG_VMID 0x0166 2208#define regUVD_JMI6_UVD_LMI_JPEG_VMID_BASE_IDX 0 2209#define regUVD_JMI6_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x0167 2210#define regUVD_JMI6_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 2211#define regUVD_JMI6_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x0168 2212#define regUVD_JMI6_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 2213#define regUVD_JMI6_UVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0169 2214#define regUVD_JMI6_UVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 2215#define regUVD_JMI6_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x016a 2216#define regUVD_JMI6_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 2217#define regUVD_JMI6_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x016b 2218#define regUVD_JMI6_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 2219#define regUVD_JMI6_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x016c 2220#define regUVD_JMI6_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 2221#define regUVD_JMI6_UVD_LMI_JPEG_PREEMPT_VMID 0x016d 2222#define regUVD_JMI6_UVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 0 2223#define regUVD_JMI6_UVD_JMI_DEC_SWAP_CNTL 0x016e 2224#define regUVD_JMI6_UVD_JMI_DEC_SWAP_CNTL_BASE_IDX 0 2225#define regUVD_JMI6_UVD_JMI_ATOMIC_CNTL 0x016f 2226#define regUVD_JMI6_UVD_JMI_ATOMIC_CNTL_BASE_IDX 0 2227#define regUVD_JMI6_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 0x0170 2228#define regUVD_JMI6_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX 0 2229#define regUVD_JMI6_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 0x0171 2230#define regUVD_JMI6_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 2231#define regUVD_JMI6_UVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x0172 2232#define regUVD_JMI6_UVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 0 2233#define regUVD_JMI6_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x0173 2234#define regUVD_JMI6_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 0 2235#define regUVD_JMI6_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0174 2236#define regUVD_JMI6_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 0 2237#define regUVD_JMI6_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0175 2238#define regUVD_JMI6_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 2239#define regUVD_JMI6_UVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0176 2240#define regUVD_JMI6_UVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 2241#define regUVD_JMI6_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0177 2242#define regUVD_JMI6_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 2243#define regUVD_JMI6_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x0178 2244#define regUVD_JMI6_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 2245#define regUVD_JMI6_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x0179 2246#define regUVD_JMI6_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 2247#define regUVD_JMI6_UVD_JMI_ATOMIC_CNTL2 0x017d 2248#define regUVD_JMI6_UVD_JMI_ATOMIC_CNTL2_BASE_IDX 0 2249#define regUVD_JMI6_UVD_JMI_CLIENT_STALL 0x017a 2250#define regUVD_JMI6_UVD_JMI_CLIENT_STALL_BASE_IDX 0 2251#define regUVD_JMI6_UVD_JMI_CLIENT_CLEAN_STATUS 0x017b 2252#define regUVD_JMI6_UVD_JMI_CLIENT_CLEAN_STATUS_BASE_IDX 0 2253 2254 2255// addressBlock: aid_uvd0_uvd_jmi7_uvd_jmi_dec 2256// base address: 0x1e680 2257#define regUVD_JMI7_UVD_JPEG_DEC_PF_CTRL 0x01a0 2258#define regUVD_JMI7_UVD_JPEG_DEC_PF_CTRL_BASE_IDX 0 2259#define regUVD_JMI7_UVD_LMI_JRBC_CTRL 0x01a1 2260#define regUVD_JMI7_UVD_LMI_JRBC_CTRL_BASE_IDX 0 2261#define regUVD_JMI7_UVD_LMI_JPEG_CTRL 0x01a2 2262#define regUVD_JMI7_UVD_LMI_JPEG_CTRL_BASE_IDX 0 2263#define regUVD_JMI7_JPEG_LMI_DROP 0x01a3 2264#define regUVD_JMI7_JPEG_LMI_DROP_BASE_IDX 0 2265#define regUVD_JMI7_UVD_LMI_JRBC_IB_VMID 0x01a4 2266#define regUVD_JMI7_UVD_LMI_JRBC_IB_VMID_BASE_IDX 0 2267#define regUVD_JMI7_UVD_LMI_JRBC_RB_VMID 0x01a5 2268#define regUVD_JMI7_UVD_LMI_JRBC_RB_VMID_BASE_IDX 0 2269#define regUVD_JMI7_UVD_LMI_JPEG_VMID 0x01a6 2270#define regUVD_JMI7_UVD_LMI_JPEG_VMID_BASE_IDX 0 2271#define regUVD_JMI7_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x01a7 2272#define regUVD_JMI7_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 2273#define regUVD_JMI7_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x01a8 2274#define regUVD_JMI7_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 2275#define regUVD_JMI7_UVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x01a9 2276#define regUVD_JMI7_UVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 2277#define regUVD_JMI7_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x01aa 2278#define regUVD_JMI7_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 2279#define regUVD_JMI7_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x01ab 2280#define regUVD_JMI7_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 2281#define regUVD_JMI7_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x01ac 2282#define regUVD_JMI7_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 2283#define regUVD_JMI7_UVD_LMI_JPEG_PREEMPT_VMID 0x01ad 2284#define regUVD_JMI7_UVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 0 2285#define regUVD_JMI7_UVD_JMI_DEC_SWAP_CNTL 0x01ae 2286#define regUVD_JMI7_UVD_JMI_DEC_SWAP_CNTL_BASE_IDX 0 2287#define regUVD_JMI7_UVD_JMI_ATOMIC_CNTL 0x01af 2288#define regUVD_JMI7_UVD_JMI_ATOMIC_CNTL_BASE_IDX 0 2289#define regUVD_JMI7_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 0x01b0 2290#define regUVD_JMI7_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX 0 2291#define regUVD_JMI7_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 0x01b1 2292#define regUVD_JMI7_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 2293#define regUVD_JMI7_UVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x01b2 2294#define regUVD_JMI7_UVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 0 2295#define regUVD_JMI7_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x01b3 2296#define regUVD_JMI7_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 0 2297#define regUVD_JMI7_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x01b4 2298#define regUVD_JMI7_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 0 2299#define regUVD_JMI7_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x01b5 2300#define regUVD_JMI7_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 2301#define regUVD_JMI7_UVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x01b6 2302#define regUVD_JMI7_UVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 2303#define regUVD_JMI7_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x01b7 2304#define regUVD_JMI7_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 2305#define regUVD_JMI7_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x01b8 2306#define regUVD_JMI7_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 2307#define regUVD_JMI7_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x01b9 2308#define regUVD_JMI7_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 2309#define regUVD_JMI7_UVD_JMI_ATOMIC_CNTL2 0x01bd 2310#define regUVD_JMI7_UVD_JMI_ATOMIC_CNTL2_BASE_IDX 0 2311#define regUVD_JMI7_UVD_JMI_CLIENT_STALL 0x01ba 2312#define regUVD_JMI7_UVD_JMI_CLIENT_STALL_BASE_IDX 0 2313#define regUVD_JMI7_UVD_JMI_CLIENT_CLEAN_STATUS 0x01bb 2314#define regUVD_JMI7_UVD_JMI_CLIENT_CLEAN_STATUS_BASE_IDX 0 2315 2316 2317// addressBlock: uvdctxind 2318// base address: 0x0 2319#define ixUVD_CGC_MEM_CTRL 0x0000 2320#define ixUVD_CGC_CTRL2 0x0001 2321#define ixUVD_CGC_MEM_DS_CTRL 0x0002 2322#define ixUVD_CGC_MEM_SD_CTRL 0x0003 2323#define ixUVD_SW_SCRATCH_00 0x0004 2324#define ixUVD_SW_SCRATCH_01 0x0005 2325#define ixUVD_SW_SCRATCH_02 0x0006 2326#define ixUVD_SW_SCRATCH_03 0x0007 2327#define ixUVD_SW_SCRATCH_04 0x0008 2328#define ixUVD_SW_SCRATCH_05 0x0009 2329#define ixUVD_SW_SCRATCH_06 0x000a 2330#define ixUVD_SW_SCRATCH_07 0x000b 2331#define ixUVD_SW_SCRATCH_08 0x000c 2332#define ixUVD_SW_SCRATCH_09 0x000d 2333#define ixUVD_SW_SCRATCH_10 0x000e 2334#define ixUVD_SW_SCRATCH_11 0x000f 2335#define ixUVD_SW_SCRATCH_12 0x0010 2336#define ixUVD_SW_SCRATCH_13 0x0011 2337#define ixUVD_SW_SCRATCH_14 0x0012 2338#define ixUVD_SW_SCRATCH_15 0x0013 2339#define ixUVD_IH_SEM_CTRL 0x001e 2340 2341 2342// addressBlock: lmi_adp_indirect 2343// base address: 0x0 2344#define ixUVD_LMI_CRC0 0x0000 2345#define ixUVD_LMI_CRC1 0x0001 2346#define ixUVD_LMI_CRC2 0x0002 2347#define ixUVD_LMI_CRC3 0x0003 2348#define ixUVD_LMI_CRC10 0x000a 2349#define ixUVD_LMI_CRC11 0x000b 2350#define ixUVD_LMI_CRC12 0x000c 2351#define ixUVD_LMI_CRC13 0x000d 2352#define ixUVD_LMI_CRC14 0x000e 2353#define ixUVD_LMI_CRC15 0x000f 2354#define ixUVD_LMI_SWAP_CNTL2 0x0029 2355#define ixUVD_MEMCHECK_SYS_INT_EN 0x0134 2356#define ixUVD_MEMCHECK_SYS_INT_STAT 0x0135 2357#define ixUVD_MEMCHECK_SYS_INT_ACK 0x0136 2358#define ixUVD_MEMCHECK_VCPU_INT_EN 0x0137 2359#define ixUVD_MEMCHECK_VCPU_INT_STAT 0x0138 2360#define ixUVD_MEMCHECK_VCPU_INT_ACK 0x0139 2361#define ixUVD_MEMCHECK2_SYS_INT_STAT 0x0140 2362#define ixUVD_MEMCHECK2_SYS_INT_ACK 0x0141 2363#define ixUVD_MEMCHECK2_VCPU_INT_STAT 0x0142 2364#define ixUVD_MEMCHECK2_VCPU_INT_ACK 0x0143 2365 2366 2367#endif
~/
Read-only file preview.