FILE
vcn_4_0_0_offset.h
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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_offset.h
1/* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef _vcn_4_0_0_OFFSET_HEADER 24#define _vcn_4_0_0_OFFSET_HEADER 25 26 27 28// addressBlock: uvd0_uvddec 29// base address: 0x1fb00 30#define regUVD_TOP_CTRL 0x00c0 31#define regUVD_TOP_CTRL_BASE_IDX 1 32#define regUVD_CGC_GATE 0x00c1 33#define regUVD_CGC_GATE_BASE_IDX 1 34#define regUVD_CGC_CTRL 0x00c2 35#define regUVD_CGC_CTRL_BASE_IDX 1 36#define regAVM_SUVD_CGC_GATE 0x00c4 37#define regAVM_SUVD_CGC_GATE_BASE_IDX 1 38#define regCDEFE_SUVD_CGC_GATE 0x00c4 39#define regCDEFE_SUVD_CGC_GATE_BASE_IDX 1 40#define regEFC_SUVD_CGC_GATE 0x00c4 41#define regEFC_SUVD_CGC_GATE_BASE_IDX 1 42#define regENT_SUVD_CGC_GATE 0x00c4 43#define regENT_SUVD_CGC_GATE_BASE_IDX 1 44#define regIME_SUVD_CGC_GATE 0x00c4 45#define regIME_SUVD_CGC_GATE_BASE_IDX 1 46#define regPPU_SUVD_CGC_GATE 0x00c4 47#define regPPU_SUVD_CGC_GATE_BASE_IDX 1 48#define regSAOE_SUVD_CGC_GATE 0x00c4 49#define regSAOE_SUVD_CGC_GATE_BASE_IDX 1 50#define regSCM_SUVD_CGC_GATE 0x00c4 51#define regSCM_SUVD_CGC_GATE_BASE_IDX 1 52#define regSDB_SUVD_CGC_GATE 0x00c4 53#define regSDB_SUVD_CGC_GATE_BASE_IDX 1 54#define regSIT0_NXT_SUVD_CGC_GATE 0x00c4 55#define regSIT0_NXT_SUVD_CGC_GATE_BASE_IDX 1 56#define regSIT1_NXT_SUVD_CGC_GATE 0x00c4 57#define regSIT1_NXT_SUVD_CGC_GATE_BASE_IDX 1 58#define regSIT2_NXT_SUVD_CGC_GATE 0x00c4 59#define regSIT2_NXT_SUVD_CGC_GATE_BASE_IDX 1 60#define regSIT_SUVD_CGC_GATE 0x00c4 61#define regSIT_SUVD_CGC_GATE_BASE_IDX 1 62#define regSMPA_SUVD_CGC_GATE 0x00c4 63#define regSMPA_SUVD_CGC_GATE_BASE_IDX 1 64#define regSMP_SUVD_CGC_GATE 0x00c4 65#define regSMP_SUVD_CGC_GATE_BASE_IDX 1 66#define regSRE_SUVD_CGC_GATE 0x00c4 67#define regSRE_SUVD_CGC_GATE_BASE_IDX 1 68#define regUVD_MPBE0_SUVD_CGC_GATE 0x00c4 69#define regUVD_MPBE0_SUVD_CGC_GATE_BASE_IDX 1 70#define regUVD_MPBE1_SUVD_CGC_GATE 0x00c4 71#define regUVD_MPBE1_SUVD_CGC_GATE_BASE_IDX 1 72#define regUVD_SUVD_CGC_GATE 0x00c4 73#define regUVD_SUVD_CGC_GATE_BASE_IDX 1 74#define regAVM_SUVD_CGC_GATE2 0x00c5 75#define regAVM_SUVD_CGC_GATE2_BASE_IDX 1 76#define regCDEFE_SUVD_CGC_GATE2 0x00c5 77#define regCDEFE_SUVD_CGC_GATE2_BASE_IDX 1 78#define regDBR_SUVD_CGC_GATE2 0x00c5 79#define regDBR_SUVD_CGC_GATE2_BASE_IDX 1 80#define regENT_SUVD_CGC_GATE2 0x00c5 81#define regENT_SUVD_CGC_GATE2_BASE_IDX 1 82#define regIME_SUVD_CGC_GATE2 0x00c5 83#define regIME_SUVD_CGC_GATE2_BASE_IDX 1 84#define regMPC1_SUVD_CGC_GATE2 0x00c5 85#define regMPC1_SUVD_CGC_GATE2_BASE_IDX 1 86#define regSAOE_SUVD_CGC_GATE2 0x00c5 87#define regSAOE_SUVD_CGC_GATE2_BASE_IDX 1 88#define regSDB_SUVD_CGC_GATE2 0x00c5 89#define regSDB_SUVD_CGC_GATE2_BASE_IDX 1 90#define regSIT0_NXT_SUVD_CGC_GATE2 0x00c5 91#define regSIT0_NXT_SUVD_CGC_GATE2_BASE_IDX 1 92#define regSIT1_NXT_SUVD_CGC_GATE2 0x00c5 93#define regSIT1_NXT_SUVD_CGC_GATE2_BASE_IDX 1 94#define regSIT2_NXT_SUVD_CGC_GATE2 0x00c5 95#define regSIT2_NXT_SUVD_CGC_GATE2_BASE_IDX 1 96#define regSIT_SUVD_CGC_GATE2 0x00c5 97#define regSIT_SUVD_CGC_GATE2_BASE_IDX 1 98#define regSMPA_SUVD_CGC_GATE2 0x00c5 99#define regSMPA_SUVD_CGC_GATE2_BASE_IDX 1 100#define regSMP_SUVD_CGC_GATE2 0x00c5 101#define regSMP_SUVD_CGC_GATE2_BASE_IDX 1 102#define regSRE_SUVD_CGC_GATE2 0x00c5 103#define regSRE_SUVD_CGC_GATE2_BASE_IDX 1 104#define regUVD_MPBE0_SUVD_CGC_GATE2 0x00c5 105#define regUVD_MPBE0_SUVD_CGC_GATE2_BASE_IDX 1 106#define regUVD_MPBE1_SUVD_CGC_GATE2 0x00c5 107#define regUVD_MPBE1_SUVD_CGC_GATE2_BASE_IDX 1 108#define regUVD_SUVD_CGC_GATE2 0x00c5 109#define regUVD_SUVD_CGC_GATE2_BASE_IDX 1 110#define regAVM_SUVD_CGC_CTRL 0x00c6 111#define regAVM_SUVD_CGC_CTRL_BASE_IDX 1 112#define regCDEFE_SUVD_CGC_CTRL 0x00c6 113#define regCDEFE_SUVD_CGC_CTRL_BASE_IDX 1 114#define regDBR_SUVD_CGC_CTRL 0x00c6 115#define regDBR_SUVD_CGC_CTRL_BASE_IDX 1 116#define regEFC_SUVD_CGC_CTRL 0x00c6 117#define regEFC_SUVD_CGC_CTRL_BASE_IDX 1 118#define regENT_SUVD_CGC_CTRL 0x00c6 119#define regENT_SUVD_CGC_CTRL_BASE_IDX 1 120#define regIME_SUVD_CGC_CTRL 0x00c6 121#define regIME_SUVD_CGC_CTRL_BASE_IDX 1 122#define regMPC1_SUVD_CGC_CTRL 0x00c6 123#define regMPC1_SUVD_CGC_CTRL_BASE_IDX 1 124#define regPPU_SUVD_CGC_CTRL 0x00c6 125#define regPPU_SUVD_CGC_CTRL_BASE_IDX 1 126#define regSAOE_SUVD_CGC_CTRL 0x00c6 127#define regSAOE_SUVD_CGC_CTRL_BASE_IDX 1 128#define regSCM_SUVD_CGC_CTRL 0x00c6 129#define regSCM_SUVD_CGC_CTRL_BASE_IDX 1 130#define regSDB_SUVD_CGC_CTRL 0x00c6 131#define regSDB_SUVD_CGC_CTRL_BASE_IDX 1 132#define regSIT0_NXT_SUVD_CGC_CTRL 0x00c6 133#define regSIT0_NXT_SUVD_CGC_CTRL_BASE_IDX 1 134#define regSIT1_NXT_SUVD_CGC_CTRL 0x00c6 135#define regSIT1_NXT_SUVD_CGC_CTRL_BASE_IDX 1 136#define regSIT2_NXT_SUVD_CGC_CTRL 0x00c6 137#define regSIT2_NXT_SUVD_CGC_CTRL_BASE_IDX 1 138#define regSIT_SUVD_CGC_CTRL 0x00c6 139#define regSIT_SUVD_CGC_CTRL_BASE_IDX 1 140#define regSMPA_SUVD_CGC_CTRL 0x00c6 141#define regSMPA_SUVD_CGC_CTRL_BASE_IDX 1 142#define regSMP_SUVD_CGC_CTRL 0x00c6 143#define regSMP_SUVD_CGC_CTRL_BASE_IDX 1 144#define regSRE_SUVD_CGC_CTRL 0x00c6 145#define regSRE_SUVD_CGC_CTRL_BASE_IDX 1 146#define regUVD_MPBE0_SUVD_CGC_CTRL 0x00c6 147#define regUVD_MPBE0_SUVD_CGC_CTRL_BASE_IDX 1 148#define regUVD_MPBE1_SUVD_CGC_CTRL 0x00c6 149#define regUVD_MPBE1_SUVD_CGC_CTRL_BASE_IDX 1 150#define regUVD_SUVD_CGC_CTRL 0x00c6 151#define regUVD_SUVD_CGC_CTRL_BASE_IDX 1 152#define regUVD_CGC_CTRL3 0x00ca 153#define regUVD_CGC_CTRL3_BASE_IDX 1 154#define regUVD_GPCOM_VCPU_DATA0 0x00d0 155#define regUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 156#define regUVD_GPCOM_VCPU_DATA1 0x00d1 157#define regUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 158#define regUVD_GPCOM_SYS_CMD 0x00d2 159#define regUVD_GPCOM_SYS_CMD_BASE_IDX 1 160#define regUVD_GPCOM_SYS_DATA0 0x00d3 161#define regUVD_GPCOM_SYS_DATA0_BASE_IDX 1 162#define regUVD_GPCOM_SYS_DATA1 0x00d4 163#define regUVD_GPCOM_SYS_DATA1_BASE_IDX 1 164#define regUVD_VCPU_INT_EN 0x00d5 165#define regUVD_VCPU_INT_EN_BASE_IDX 1 166#define regUVD_VCPU_INT_STATUS 0x00d6 167#define regUVD_VCPU_INT_STATUS_BASE_IDX 1 168#define regUVD_VCPU_INT_ACK 0x00d7 169#define regUVD_VCPU_INT_ACK_BASE_IDX 1 170#define regUVD_VCPU_INT_ROUTE 0x00d8 171#define regUVD_VCPU_INT_ROUTE_BASE_IDX 1 172#define regUVD_DRV_FW_MSG 0x00d9 173#define regUVD_DRV_FW_MSG_BASE_IDX 1 174#define regUVD_FW_DRV_MSG_ACK 0x00da 175#define regUVD_FW_DRV_MSG_ACK_BASE_IDX 1 176#define regUVD_SUVD_INT_EN 0x00db 177#define regUVD_SUVD_INT_EN_BASE_IDX 1 178#define regUVD_SUVD_INT_STATUS 0x00dc 179#define regUVD_SUVD_INT_STATUS_BASE_IDX 1 180#define regUVD_SUVD_INT_ACK 0x00dd 181#define regUVD_SUVD_INT_ACK_BASE_IDX 1 182#define regUVD_ENC_VCPU_INT_EN 0x00de 183#define regUVD_ENC_VCPU_INT_EN_BASE_IDX 1 184#define regUVD_ENC_VCPU_INT_STATUS 0x00df 185#define regUVD_ENC_VCPU_INT_STATUS_BASE_IDX 1 186#define regUVD_ENC_VCPU_INT_ACK 0x00e0 187#define regUVD_ENC_VCPU_INT_ACK_BASE_IDX 1 188#define regUVD_MASTINT_EN 0x00e1 189#define regUVD_MASTINT_EN_BASE_IDX 1 190#define regUVD_SYS_INT_EN 0x00e2 191#define regUVD_SYS_INT_EN_BASE_IDX 1 192#define regUVD_SYS_INT_STATUS 0x00e3 193#define regUVD_SYS_INT_STATUS_BASE_IDX 1 194#define regUVD_SYS_INT_ACK 0x00e4 195#define regUVD_SYS_INT_ACK_BASE_IDX 1 196#define regUVD_JOB_DONE 0x00e5 197#define regUVD_JOB_DONE_BASE_IDX 1 198#define regUVD_CBUF_ID 0x00e6 199#define regUVD_CBUF_ID_BASE_IDX 1 200#define regUVD_CONTEXT_ID 0x00e7 201#define regUVD_CONTEXT_ID_BASE_IDX 1 202#define regUVD_CONTEXT_ID2 0x00e8 203#define regUVD_CONTEXT_ID2_BASE_IDX 1 204#define regUVD_NO_OP 0x00e9 205#define regUVD_NO_OP_BASE_IDX 1 206#define regUVD_RB_BASE_LO 0x00ea 207#define regUVD_RB_BASE_LO_BASE_IDX 1 208#define regUVD_RB_BASE_HI 0x00eb 209#define regUVD_RB_BASE_HI_BASE_IDX 1 210#define regUVD_RB_SIZE 0x00ec 211#define regUVD_RB_SIZE_BASE_IDX 1 212#define regUVD_RB_BASE_LO2 0x00ef 213#define regUVD_RB_BASE_LO2_BASE_IDX 1 214#define regUVD_RB_BASE_HI2 0x00f0 215#define regUVD_RB_BASE_HI2_BASE_IDX 1 216#define regUVD_RB_SIZE2 0x00f1 217#define regUVD_RB_SIZE2_BASE_IDX 1 218#define regUVD_RB_BASE_LO3 0x00f4 219#define regUVD_RB_BASE_LO3_BASE_IDX 1 220#define regUVD_RB_BASE_HI3 0x00f5 221#define regUVD_RB_BASE_HI3_BASE_IDX 1 222#define regUVD_RB_SIZE3 0x00f6 223#define regUVD_RB_SIZE3_BASE_IDX 1 224#define regUVD_RB_BASE_LO4 0x00f9 225#define regUVD_RB_BASE_LO4_BASE_IDX 1 226#define regUVD_RB_BASE_HI4 0x00fa 227#define regUVD_RB_BASE_HI4_BASE_IDX 1 228#define regUVD_RB_SIZE4 0x00fb 229#define regUVD_RB_SIZE4_BASE_IDX 1 230#define regUVD_OUT_RB_BASE_LO 0x00fe 231#define regUVD_OUT_RB_BASE_LO_BASE_IDX 1 232#define regUVD_OUT_RB_BASE_HI 0x00ff 233#define regUVD_OUT_RB_BASE_HI_BASE_IDX 1 234#define regUVD_OUT_RB_SIZE 0x0100 235#define regUVD_OUT_RB_SIZE_BASE_IDX 1 236#define regUVD_IOV_MAILBOX 0x0104 237#define regUVD_IOV_MAILBOX_BASE_IDX 1 238#define regUVD_IOV_MAILBOX_RESP 0x0105 239#define regUVD_IOV_MAILBOX_RESP_BASE_IDX 1 240#define regUVD_RB_ARB_CTRL 0x0106 241#define regUVD_RB_ARB_CTRL_BASE_IDX 1 242#define regUVD_CTX_INDEX 0x0107 243#define regUVD_CTX_INDEX_BASE_IDX 1 244#define regUVD_CTX_DATA 0x0108 245#define regUVD_CTX_DATA_BASE_IDX 1 246#define regUVD_CXW_WR 0x0109 247#define regUVD_CXW_WR_BASE_IDX 1 248#define regUVD_CXW_WR_INT_ID 0x010a 249#define regUVD_CXW_WR_INT_ID_BASE_IDX 1 250#define regUVD_CXW_WR_INT_CTX_ID 0x010b 251#define regUVD_CXW_WR_INT_CTX_ID_BASE_IDX 1 252#define regUVD_CXW_INT_ID 0x010c 253#define regUVD_CXW_INT_ID_BASE_IDX 1 254#define regUVD_MPEG2_ERROR 0x010d 255#define regUVD_MPEG2_ERROR_BASE_IDX 1 256#define regUVD_YBASE 0x0110 257#define regUVD_YBASE_BASE_IDX 1 258#define regUVD_UVBASE 0x0111 259#define regUVD_UVBASE_BASE_IDX 1 260#define regUVD_PITCH 0x0112 261#define regUVD_PITCH_BASE_IDX 1 262#define regUVD_WIDTH 0x0113 263#define regUVD_WIDTH_BASE_IDX 1 264#define regUVD_HEIGHT 0x0114 265#define regUVD_HEIGHT_BASE_IDX 1 266#define regUVD_PICCOUNT 0x0115 267#define regUVD_PICCOUNT_BASE_IDX 1 268#define regUVD_MPRD_INITIAL_XY 0x0116 269#define regUVD_MPRD_INITIAL_XY_BASE_IDX 1 270#define regUVD_MPEG2_CTRL 0x0117 271#define regUVD_MPEG2_CTRL_BASE_IDX 1 272#define regUVD_MB_CTL_BUF_BASE 0x0118 273#define regUVD_MB_CTL_BUF_BASE_BASE_IDX 1 274#define regUVD_PIC_CTL_BUF_BASE 0x0119 275#define regUVD_PIC_CTL_BUF_BASE_BASE_IDX 1 276#define regUVD_DXVA_BUF_SIZE 0x011a 277#define regUVD_DXVA_BUF_SIZE_BASE_IDX 1 278#define regUVD_SCRATCH_NP 0x011b 279#define regUVD_SCRATCH_NP_BASE_IDX 1 280#define regUVD_CLK_SWT_HANDSHAKE 0x011c 281#define regUVD_CLK_SWT_HANDSHAKE_BASE_IDX 1 282#define regUVD_GP_SCRATCH0 0x011e 283#define regUVD_GP_SCRATCH0_BASE_IDX 1 284#define regUVD_GP_SCRATCH1 0x011f 285#define regUVD_GP_SCRATCH1_BASE_IDX 1 286#define regUVD_GP_SCRATCH2 0x0120 287#define regUVD_GP_SCRATCH2_BASE_IDX 1 288#define regUVD_GP_SCRATCH3 0x0121 289#define regUVD_GP_SCRATCH3_BASE_IDX 1 290#define regUVD_GP_SCRATCH4 0x0122 291#define regUVD_GP_SCRATCH4_BASE_IDX 1 292#define regUVD_GP_SCRATCH5 0x0123 293#define regUVD_GP_SCRATCH5_BASE_IDX 1 294#define regUVD_GP_SCRATCH6 0x0124 295#define regUVD_GP_SCRATCH6_BASE_IDX 1 296#define regUVD_GP_SCRATCH7 0x0125 297#define regUVD_GP_SCRATCH7_BASE_IDX 1 298#define regUVD_GP_SCRATCH8 0x0126 299#define regUVD_GP_SCRATCH8_BASE_IDX 1 300#define regUVD_GP_SCRATCH9 0x0127 301#define regUVD_GP_SCRATCH9_BASE_IDX 1 302#define regUVD_GP_SCRATCH10 0x0128 303#define regUVD_GP_SCRATCH10_BASE_IDX 1 304#define regUVD_GP_SCRATCH11 0x0129 305#define regUVD_GP_SCRATCH11_BASE_IDX 1 306#define regUVD_GP_SCRATCH12 0x012a 307#define regUVD_GP_SCRATCH12_BASE_IDX 1 308#define regUVD_GP_SCRATCH13 0x012b 309#define regUVD_GP_SCRATCH13_BASE_IDX 1 310#define regUVD_GP_SCRATCH14 0x012c 311#define regUVD_GP_SCRATCH14_BASE_IDX 1 312#define regUVD_GP_SCRATCH15 0x012d 313#define regUVD_GP_SCRATCH15_BASE_IDX 1 314#define regUVD_GP_SCRATCH16 0x012e 315#define regUVD_GP_SCRATCH16_BASE_IDX 1 316#define regUVD_GP_SCRATCH17 0x012f 317#define regUVD_GP_SCRATCH17_BASE_IDX 1 318#define regUVD_GP_SCRATCH18 0x0130 319#define regUVD_GP_SCRATCH18_BASE_IDX 1 320#define regUVD_GP_SCRATCH19 0x0131 321#define regUVD_GP_SCRATCH19_BASE_IDX 1 322#define regUVD_GP_SCRATCH20 0x0132 323#define regUVD_GP_SCRATCH20_BASE_IDX 1 324#define regUVD_GP_SCRATCH21 0x0133 325#define regUVD_GP_SCRATCH21_BASE_IDX 1 326#define regUVD_GP_SCRATCH22 0x0134 327#define regUVD_GP_SCRATCH22_BASE_IDX 1 328#define regUVD_GP_SCRATCH23 0x0135 329#define regUVD_GP_SCRATCH23_BASE_IDX 1 330#define regUVD_AUDIO_RB_BASE_LO 0x0136 331#define regUVD_AUDIO_RB_BASE_LO_BASE_IDX 1 332#define regUVD_AUDIO_RB_BASE_HI 0x0137 333#define regUVD_AUDIO_RB_BASE_HI_BASE_IDX 1 334#define regUVD_AUDIO_RB_SIZE 0x0138 335#define regUVD_AUDIO_RB_SIZE_BASE_IDX 1 336#define regUVD_VCPU_INT_STATUS2 0x013b 337#define regUVD_VCPU_INT_STATUS2_BASE_IDX 1 338#define regUVD_VCPU_INT_ACK2 0x013c 339#define regUVD_VCPU_INT_ACK2_BASE_IDX 1 340#define regUVD_VCPU_INT_EN2 0x013d 341#define regUVD_VCPU_INT_EN2_BASE_IDX 1 342#define regUVD_SUVD_CGC_STATUS2 0x013e 343#define regUVD_SUVD_CGC_STATUS2_BASE_IDX 1 344#define regUVD_SUVD_INT_STATUS2 0x0140 345#define regUVD_SUVD_INT_STATUS2_BASE_IDX 1 346#define regUVD_SUVD_INT_EN2 0x0141 347#define regUVD_SUVD_INT_EN2_BASE_IDX 1 348#define regUVD_SUVD_INT_ACK2 0x0142 349#define regUVD_SUVD_INT_ACK2_BASE_IDX 1 350#define regUVD_STATUS 0x0143 351#define regUVD_STATUS_BASE_IDX 1 352#define regUVD_ENC_PIPE_BUSY 0x0144 353#define regUVD_ENC_PIPE_BUSY_BASE_IDX 1 354#define regUVD_FW_POWER_STATUS 0x0145 355#define regUVD_FW_POWER_STATUS_BASE_IDX 1 356#define regUVD_CNTL 0x0146 357#define regUVD_CNTL_BASE_IDX 1 358#define regUVD_SOFT_RESET 0x0147 359#define regUVD_SOFT_RESET_BASE_IDX 1 360#define regUVD_SOFT_RESET2 0x0148 361#define regUVD_SOFT_RESET2_BASE_IDX 1 362#define regUVD_MMSCH_SOFT_RESET 0x0149 363#define regUVD_MMSCH_SOFT_RESET_BASE_IDX 1 364#define regUVD_WIG_CTRL 0x014a 365#define regUVD_WIG_CTRL_BASE_IDX 1 366#define regUVD_CGC_STATUS 0x014c 367#define regUVD_CGC_STATUS_BASE_IDX 1 368#define regUVD_CGC_UDEC_STATUS 0x014e 369#define regUVD_CGC_UDEC_STATUS_BASE_IDX 1 370#define regUVD_SUVD_CGC_STATUS 0x0150 371#define regUVD_SUVD_CGC_STATUS_BASE_IDX 1 372#define regUVD_GPCOM_VCPU_CMD 0x0152 373#define regUVD_GPCOM_VCPU_CMD_BASE_IDX 1 374 375 376// addressBlock: uvd0_ecpudec 377// base address: 0x1fe00 378#define regUVD_VCPU_CACHE_OFFSET0 0x0180 379#define regUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1 380#define regUVD_VCPU_CACHE_SIZE0 0x0181 381#define regUVD_VCPU_CACHE_SIZE0_BASE_IDX 1 382#define regUVD_VCPU_CACHE_OFFSET1 0x0182 383#define regUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1 384#define regUVD_VCPU_CACHE_SIZE1 0x0183 385#define regUVD_VCPU_CACHE_SIZE1_BASE_IDX 1 386#define regUVD_VCPU_CACHE_OFFSET2 0x0184 387#define regUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1 388#define regUVD_VCPU_CACHE_SIZE2 0x0185 389#define regUVD_VCPU_CACHE_SIZE2_BASE_IDX 1 390#define regUVD_VCPU_CACHE_OFFSET3 0x0186 391#define regUVD_VCPU_CACHE_OFFSET3_BASE_IDX 1 392#define regUVD_VCPU_CACHE_SIZE3 0x0187 393#define regUVD_VCPU_CACHE_SIZE3_BASE_IDX 1 394#define regUVD_VCPU_CACHE_OFFSET4 0x0188 395#define regUVD_VCPU_CACHE_OFFSET4_BASE_IDX 1 396#define regUVD_VCPU_CACHE_SIZE4 0x0189 397#define regUVD_VCPU_CACHE_SIZE4_BASE_IDX 1 398#define regUVD_VCPU_CACHE_OFFSET5 0x018a 399#define regUVD_VCPU_CACHE_OFFSET5_BASE_IDX 1 400#define regUVD_VCPU_CACHE_SIZE5 0x018b 401#define regUVD_VCPU_CACHE_SIZE5_BASE_IDX 1 402#define regUVD_VCPU_CACHE_OFFSET6 0x018c 403#define regUVD_VCPU_CACHE_OFFSET6_BASE_IDX 1 404#define regUVD_VCPU_CACHE_SIZE6 0x018d 405#define regUVD_VCPU_CACHE_SIZE6_BASE_IDX 1 406#define regUVD_VCPU_CACHE_OFFSET7 0x018e 407#define regUVD_VCPU_CACHE_OFFSET7_BASE_IDX 1 408#define regUVD_VCPU_CACHE_SIZE7 0x018f 409#define regUVD_VCPU_CACHE_SIZE7_BASE_IDX 1 410#define regUVD_VCPU_CACHE_OFFSET8 0x0190 411#define regUVD_VCPU_CACHE_OFFSET8_BASE_IDX 1 412#define regUVD_VCPU_CACHE_SIZE8 0x0191 413#define regUVD_VCPU_CACHE_SIZE8_BASE_IDX 1 414#define regUVD_VCPU_NONCACHE_OFFSET0 0x0192 415#define regUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX 1 416#define regUVD_VCPU_NONCACHE_SIZE0 0x0193 417#define regUVD_VCPU_NONCACHE_SIZE0_BASE_IDX 1 418#define regUVD_VCPU_NONCACHE_OFFSET1 0x0194 419#define regUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX 1 420#define regUVD_VCPU_NONCACHE_SIZE1 0x0195 421#define regUVD_VCPU_NONCACHE_SIZE1_BASE_IDX 1 422#define regUVD_VCPU_CNTL 0x0196 423#define regUVD_VCPU_CNTL_BASE_IDX 1 424#define regUVD_VCPU_PRID 0x0197 425#define regUVD_VCPU_PRID_BASE_IDX 1 426#define regUVD_VCPU_TRCE 0x0198 427#define regUVD_VCPU_TRCE_BASE_IDX 1 428#define regUVD_VCPU_TRCE_RD 0x0199 429#define regUVD_VCPU_TRCE_RD_BASE_IDX 1 430#define regUVD_VCPU_IND_INDEX 0x019b 431#define regUVD_VCPU_IND_INDEX_BASE_IDX 1 432#define regUVD_VCPU_IND_DATA 0x019c 433#define regUVD_VCPU_IND_DATA_BASE_IDX 1 434 435 436// addressBlock: uvd0_uvd_mpcdec 437// base address: 0x1ff30 438#define regUVD_MP_SWAP_CNTL 0x01cc 439#define regUVD_MP_SWAP_CNTL_BASE_IDX 1 440#define regUVD_MP_SWAP_CNTL2 0x01cd 441#define regUVD_MP_SWAP_CNTL2_BASE_IDX 1 442#define regUVD_MPC_LUMA_SRCH 0x01ce 443#define regUVD_MPC_LUMA_SRCH_BASE_IDX 1 444#define regUVD_MPC_LUMA_HIT 0x01cf 445#define regUVD_MPC_LUMA_HIT_BASE_IDX 1 446#define regUVD_MPC_LUMA_HITPEND 0x01d0 447#define regUVD_MPC_LUMA_HITPEND_BASE_IDX 1 448#define regUVD_MPC_CHROMA_SRCH 0x01d1 449#define regUVD_MPC_CHROMA_SRCH_BASE_IDX 1 450#define regUVD_MPC_CHROMA_HIT 0x01d2 451#define regUVD_MPC_CHROMA_HIT_BASE_IDX 1 452#define regUVD_MPC_CHROMA_HITPEND 0x01d3 453#define regUVD_MPC_CHROMA_HITPEND_BASE_IDX 1 454#define regUVD_MPC_CNTL 0x01d4 455#define regUVD_MPC_CNTL_BASE_IDX 1 456#define regUVD_MPC_PITCH 0x01d5 457#define regUVD_MPC_PITCH_BASE_IDX 1 458#define regUVD_MPC_SET_MUXA0 0x01d6 459#define regUVD_MPC_SET_MUXA0_BASE_IDX 1 460#define regUVD_MPC_SET_MUXA1 0x01d7 461#define regUVD_MPC_SET_MUXA1_BASE_IDX 1 462#define regUVD_MPC_SET_MUXB0 0x01d8 463#define regUVD_MPC_SET_MUXB0_BASE_IDX 1 464#define regUVD_MPC_SET_MUXB1 0x01d9 465#define regUVD_MPC_SET_MUXB1_BASE_IDX 1 466#define regUVD_MPC_SET_MUX 0x01da 467#define regUVD_MPC_SET_MUX_BASE_IDX 1 468#define regUVD_MPC_SET_ALU 0x01db 469#define regUVD_MPC_SET_ALU_BASE_IDX 1 470#define regUVD_MPC_PERF0 0x01dc 471#define regUVD_MPC_PERF0_BASE_IDX 1 472#define regUVD_MPC_PERF1 0x01dd 473#define regUVD_MPC_PERF1_BASE_IDX 1 474#define regUVD_MPC_IND_INDEX 0x01de 475#define regUVD_MPC_IND_INDEX_BASE_IDX 1 476#define regUVD_MPC_IND_DATA 0x01df 477#define regUVD_MPC_IND_DATA_BASE_IDX 1 478 479 480// addressBlock: uvd0_uvd_rbcdec 481// base address: 0x1ff90 482#define regUVD_RBC_IB_SIZE 0x01e4 483#define regUVD_RBC_IB_SIZE_BASE_IDX 1 484#define regUVD_RBC_IB_SIZE_UPDATE 0x01e5 485#define regUVD_RBC_IB_SIZE_UPDATE_BASE_IDX 1 486#define regUVD_RBC_RB_CNTL 0x01e6 487#define regUVD_RBC_RB_CNTL_BASE_IDX 1 488#define regUVD_RBC_RB_RPTR_ADDR 0x01e7 489#define regUVD_RBC_RB_RPTR_ADDR_BASE_IDX 1 490#define regUVD_RBC_VCPU_ACCESS 0x01ea 491#define regUVD_RBC_VCPU_ACCESS_BASE_IDX 1 492#define regUVD_FW_SEMAPHORE_CNTL 0x01eb 493#define regUVD_FW_SEMAPHORE_CNTL_BASE_IDX 1 494#define regUVD_RBC_READ_REQ_URGENT_CNTL 0x01ed 495#define regUVD_RBC_READ_REQ_URGENT_CNTL_BASE_IDX 1 496#define regUVD_RBC_RB_WPTR_CNTL 0x01ee 497#define regUVD_RBC_RB_WPTR_CNTL_BASE_IDX 1 498#define regUVD_RBC_WPTR_STATUS 0x01ef 499#define regUVD_RBC_WPTR_STATUS_BASE_IDX 1 500#define regUVD_RBC_WPTR_POLL_CNTL 0x01f0 501#define regUVD_RBC_WPTR_POLL_CNTL_BASE_IDX 1 502#define regUVD_RBC_WPTR_POLL_ADDR 0x01f1 503#define regUVD_RBC_WPTR_POLL_ADDR_BASE_IDX 1 504#define regUVD_SEMA_CMD 0x01f2 505#define regUVD_SEMA_CMD_BASE_IDX 1 506#define regUVD_SEMA_ADDR_LOW 0x01f3 507#define regUVD_SEMA_ADDR_LOW_BASE_IDX 1 508#define regUVD_SEMA_ADDR_HIGH 0x01f4 509#define regUVD_SEMA_ADDR_HIGH_BASE_IDX 1 510#define regUVD_ENGINE_CNTL 0x01f5 511#define regUVD_ENGINE_CNTL_BASE_IDX 1 512#define regUVD_SEMA_TIMEOUT_STATUS 0x01f6 513#define regUVD_SEMA_TIMEOUT_STATUS_BASE_IDX 1 514#define regUVD_SEMA_CNTL 0x01f7 515#define regUVD_SEMA_CNTL_BASE_IDX 1 516#define regUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x01f8 517#define regUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 518#define regUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x01f9 519#define regUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX 1 520#define regUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x01fa 521#define regUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 522#define regUVD_JOB_START 0x01fb 523#define regUVD_JOB_START_BASE_IDX 1 524#define regUVD_RBC_BUF_STATUS 0x01fc 525#define regUVD_RBC_BUF_STATUS_BASE_IDX 1 526#define regUVD_RBC_SWAP_CNTL 0x01fd 527#define regUVD_RBC_SWAP_CNTL_BASE_IDX 1 528 529 530// addressBlock: uvd0_lmi_adpdec 531// base address: 0x20090 532#define regUVD_LMI_RE_64BIT_BAR_LOW 0x0224 533#define regUVD_LMI_RE_64BIT_BAR_LOW_BASE_IDX 1 534#define regUVD_LMI_RE_64BIT_BAR_HIGH 0x0225 535#define regUVD_LMI_RE_64BIT_BAR_HIGH_BASE_IDX 1 536#define regUVD_LMI_IT_64BIT_BAR_LOW 0x0226 537#define regUVD_LMI_IT_64BIT_BAR_LOW_BASE_IDX 1 538#define regUVD_LMI_IT_64BIT_BAR_HIGH 0x0227 539#define regUVD_LMI_IT_64BIT_BAR_HIGH_BASE_IDX 1 540#define regUVD_LMI_MP_64BIT_BAR_LOW 0x0228 541#define regUVD_LMI_MP_64BIT_BAR_LOW_BASE_IDX 1 542#define regUVD_LMI_MP_64BIT_BAR_HIGH 0x0229 543#define regUVD_LMI_MP_64BIT_BAR_HIGH_BASE_IDX 1 544#define regUVD_LMI_CM_64BIT_BAR_LOW 0x022a 545#define regUVD_LMI_CM_64BIT_BAR_LOW_BASE_IDX 1 546#define regUVD_LMI_CM_64BIT_BAR_HIGH 0x022b 547#define regUVD_LMI_CM_64BIT_BAR_HIGH_BASE_IDX 1 548#define regUVD_LMI_DB_64BIT_BAR_LOW 0x022c 549#define regUVD_LMI_DB_64BIT_BAR_LOW_BASE_IDX 1 550#define regUVD_LMI_DB_64BIT_BAR_HIGH 0x022d 551#define regUVD_LMI_DB_64BIT_BAR_HIGH_BASE_IDX 1 552#define regUVD_LMI_DBW_64BIT_BAR_LOW 0x022e 553#define regUVD_LMI_DBW_64BIT_BAR_LOW_BASE_IDX 1 554#define regUVD_LMI_DBW_64BIT_BAR_HIGH 0x022f 555#define regUVD_LMI_DBW_64BIT_BAR_HIGH_BASE_IDX 1 556#define regUVD_LMI_IDCT_64BIT_BAR_LOW 0x0230 557#define regUVD_LMI_IDCT_64BIT_BAR_LOW_BASE_IDX 1 558#define regUVD_LMI_IDCT_64BIT_BAR_HIGH 0x0231 559#define regUVD_LMI_IDCT_64BIT_BAR_HIGH_BASE_IDX 1 560#define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW 0x0232 561#define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW_BASE_IDX 1 562#define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH 0x0233 563#define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH_BASE_IDX 1 564#define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW 0x0234 565#define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW_BASE_IDX 1 566#define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH 0x0235 567#define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH_BASE_IDX 1 568#define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW 0x0236 569#define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW_BASE_IDX 1 570#define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH 0x0237 571#define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH_BASE_IDX 1 572#define regUVD_LMI_MPC_64BIT_BAR_LOW 0x0238 573#define regUVD_LMI_MPC_64BIT_BAR_LOW_BASE_IDX 1 574#define regUVD_LMI_MPC_64BIT_BAR_HIGH 0x0239 575#define regUVD_LMI_MPC_64BIT_BAR_HIGH_BASE_IDX 1 576#define regUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x023a 577#define regUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1 578#define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x023b 579#define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 580#define regUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x023c 581#define regUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1 582#define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x023d 583#define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 584#define regUVD_LMI_LBSI_64BIT_BAR_LOW 0x023e 585#define regUVD_LMI_LBSI_64BIT_BAR_LOW_BASE_IDX 1 586#define regUVD_LMI_LBSI_64BIT_BAR_HIGH 0x023f 587#define regUVD_LMI_LBSI_64BIT_BAR_HIGH_BASE_IDX 1 588#define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW 0x0240 589#define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX 1 590#define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 0x0241 591#define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX 1 592#define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW 0x0242 593#define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX 1 594#define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 0x0243 595#define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX 1 596#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x0244 597#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 598#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x0245 599#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 600#define regUVD_LMI_CENC_64BIT_BAR_LOW 0x0246 601#define regUVD_LMI_CENC_64BIT_BAR_LOW_BASE_IDX 1 602#define regUVD_LMI_CENC_64BIT_BAR_HIGH 0x0247 603#define regUVD_LMI_CENC_64BIT_BAR_HIGH_BASE_IDX 1 604#define regUVD_LMI_SRE_64BIT_BAR_LOW 0x0248 605#define regUVD_LMI_SRE_64BIT_BAR_LOW_BASE_IDX 1 606#define regUVD_LMI_SRE_64BIT_BAR_HIGH 0x0249 607#define regUVD_LMI_SRE_64BIT_BAR_HIGH_BASE_IDX 1 608#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW 0x024a 609#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW_BASE_IDX 1 610#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH 0x024b 611#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH_BASE_IDX 1 612#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW 0x024c 613#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW_BASE_IDX 1 614#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH 0x024d 615#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 616#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW 0x024e 617#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 618#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH 0x024f 619#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 620#define regUVD_LMI_MIF_REF_64BIT_BAR_LOW 0x0250 621#define regUVD_LMI_MIF_REF_64BIT_BAR_LOW_BASE_IDX 1 622#define regUVD_LMI_MIF_REF_64BIT_BAR_HIGH 0x0251 623#define regUVD_LMI_MIF_REF_64BIT_BAR_HIGH_BASE_IDX 1 624#define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW 0x0252 625#define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW_BASE_IDX 1 626#define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH 0x0253 627#define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH_BASE_IDX 1 628#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW 0x0254 629#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW_BASE_IDX 1 630#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH 0x0255 631#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH_BASE_IDX 1 632#define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW 0x0256 633#define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW_BASE_IDX 1 634#define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH 0x0257 635#define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH_BASE_IDX 1 636#define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW 0x0258 637#define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW_BASE_IDX 1 638#define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH 0x0259 639#define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH_BASE_IDX 1 640#define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW 0x025a 641#define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW_BASE_IDX 1 642#define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH 0x025b 643#define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH_BASE_IDX 1 644#define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW 0x025c 645#define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW_BASE_IDX 1 646#define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH 0x025d 647#define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH_BASE_IDX 1 648#define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW 0x025e 649#define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW_BASE_IDX 1 650#define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH 0x025f 651#define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH_BASE_IDX 1 652#define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW 0x0260 653#define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW_BASE_IDX 1 654#define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH 0x0261 655#define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH_BASE_IDX 1 656#define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW 0x0262 657#define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW_BASE_IDX 1 658#define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH 0x0263 659#define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH_BASE_IDX 1 660#define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW 0x0264 661#define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW_BASE_IDX 1 662#define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH 0x0265 663#define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH_BASE_IDX 1 664#define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW 0x0266 665#define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW_BASE_IDX 1 666#define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH 0x0267 667#define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH_BASE_IDX 1 668#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x0270 669#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1 670#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x0271 671#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1 672#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 0x0272 673#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX 1 674#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 0x0273 675#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX 1 676#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x0274 677#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1 678#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x0275 679#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1 680#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 0x0276 681#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX 1 682#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 0x0277 683#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX 1 684#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 0x0278 685#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX 1 686#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 0x0279 687#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX 1 688#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 0x027a 689#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX 1 690#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 0x027b 691#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX 1 692#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 0x027c 693#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX 1 694#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 0x027d 695#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX 1 696#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 0x027e 697#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX 1 698#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 0x027f 699#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX 1 700#define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW 0x0280 701#define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW_BASE_IDX 1 702#define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH 0x0281 703#define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH_BASE_IDX 1 704#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW 0x0282 705#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW_BASE_IDX 1 706#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH 0x0283 707#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH_BASE_IDX 1 708#define regUVD_LMI_SPH_64BIT_BAR_HIGH 0x0284 709#define regUVD_LMI_SPH_64BIT_BAR_HIGH_BASE_IDX 1 710#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW 0x0298 711#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW_BASE_IDX 1 712#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH 0x0299 713#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 714#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW 0x029a 715#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 716#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH 0x029b 717#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 718#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW 0x029c 719#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW_BASE_IDX 1 720#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH 0x029d 721#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 722#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW 0x029e 723#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 724#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH 0x029f 725#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 726#define regUVD_ADP_ATOMIC_CONFIG 0x02a1 727#define regUVD_ADP_ATOMIC_CONFIG_BASE_IDX 1 728#define regUVD_LMI_ARB_CTRL2 0x02a2 729#define regUVD_LMI_ARB_CTRL2_BASE_IDX 1 730#define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI 0x02a7 731#define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX 1 732#define regUVD_LMI_VCPU_NC_VMIDS_MULTI 0x02a8 733#define regUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX 1 734#define regUVD_LMI_LAT_CTRL 0x02a9 735#define regUVD_LMI_LAT_CTRL_BASE_IDX 1 736#define regUVD_LMI_LAT_CNTR 0x02aa 737#define regUVD_LMI_LAT_CNTR_BASE_IDX 1 738#define regUVD_LMI_AVG_LAT_CNTR 0x02ab 739#define regUVD_LMI_AVG_LAT_CNTR_BASE_IDX 1 740#define regUVD_LMI_SPH 0x02ac 741#define regUVD_LMI_SPH_BASE_IDX 1 742#define regUVD_LMI_VCPU_CACHE_VMID 0x02ad 743#define regUVD_LMI_VCPU_CACHE_VMID_BASE_IDX 1 744#define regUVD_LMI_CTRL2 0x02ae 745#define regUVD_LMI_CTRL2_BASE_IDX 1 746#define regUVD_LMI_URGENT_CTRL 0x02af 747#define regUVD_LMI_URGENT_CTRL_BASE_IDX 1 748#define regUVD_LMI_CTRL 0x02b0 749#define regUVD_LMI_CTRL_BASE_IDX 1 750#define regUVD_LMI_STATUS 0x02b1 751#define regUVD_LMI_STATUS_BASE_IDX 1 752#define regUVD_LMI_PERFMON_CTRL 0x02b4 753#define regUVD_LMI_PERFMON_CTRL_BASE_IDX 1 754#define regUVD_LMI_PERFMON_COUNT_LO 0x02b5 755#define regUVD_LMI_PERFMON_COUNT_LO_BASE_IDX 1 756#define regUVD_LMI_PERFMON_COUNT_HI 0x02b6 757#define regUVD_LMI_PERFMON_COUNT_HI_BASE_IDX 1 758#define regUVD_LMI_ADP_SWAP_CNTL 0x02b7 759#define regUVD_LMI_ADP_SWAP_CNTL_BASE_IDX 1 760#define regUVD_LMI_RBC_RB_VMID 0x02b8 761#define regUVD_LMI_RBC_RB_VMID_BASE_IDX 1 762#define regUVD_LMI_RBC_IB_VMID 0x02b9 763#define regUVD_LMI_RBC_IB_VMID_BASE_IDX 1 764#define regUVD_LMI_MC_CREDITS 0x02ba 765#define regUVD_LMI_MC_CREDITS_BASE_IDX 1 766#define regUVD_LMI_ADP_IND_INDEX 0x02be 767#define regUVD_LMI_ADP_IND_INDEX_BASE_IDX 1 768#define regUVD_LMI_ADP_IND_DATA 0x02bf 769#define regUVD_LMI_ADP_IND_DATA_BASE_IDX 1 770#define regUVD_LMI_PREF_CTRL 0x02c2 771#define regUVD_LMI_PREF_CTRL_BASE_IDX 1 772#define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW 0x02dd 773#define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW_BASE_IDX 1 774#define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH 0x02de 775#define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 776#define regVCN_RAS_CNTL 0x02df 777#define regVCN_RAS_CNTL_BASE_IDX 1 778 779 780// addressBlock: uvd0_jpegnpdec 781// base address: 0x20f00 782#define regUVD_JPEG_CNTL 0x05c0 783#define regUVD_JPEG_CNTL_BASE_IDX 1 784#define regUVD_JPEG_RB_BASE 0x05c1 785#define regUVD_JPEG_RB_BASE_BASE_IDX 1 786#define regUVD_JPEG_RB_WPTR 0x05c2 787#define regUVD_JPEG_RB_WPTR_BASE_IDX 1 788#define regUVD_JPEG_RB_RPTR 0x05c3 789#define regUVD_JPEG_RB_RPTR_BASE_IDX 1 790#define regUVD_JPEG_RB_SIZE 0x05c4 791#define regUVD_JPEG_RB_SIZE_BASE_IDX 1 792#define regUVD_JPEG_DEC_CNT 0x05c5 793#define regUVD_JPEG_DEC_CNT_BASE_IDX 1 794#define regUVD_JPEG_SPS_INFO 0x05c6 795#define regUVD_JPEG_SPS_INFO_BASE_IDX 1 796#define regUVD_JPEG_SPS1_INFO 0x05c7 797#define regUVD_JPEG_SPS1_INFO_BASE_IDX 1 798#define regUVD_JPEG_RE_TIMER 0x05c8 799#define regUVD_JPEG_RE_TIMER_BASE_IDX 1 800#define regUVD_JPEG_DEC_SCRATCH0 0x05c9 801#define regUVD_JPEG_DEC_SCRATCH0_BASE_IDX 1 802#define regUVD_JPEG_INT_EN 0x05ca 803#define regUVD_JPEG_INT_EN_BASE_IDX 1 804#define regUVD_JPEG_INT_STAT 0x05cb 805#define regUVD_JPEG_INT_STAT_BASE_IDX 1 806#define regUVD_JPEG_TIER_CNTL0 0x05cd 807#define regUVD_JPEG_TIER_CNTL0_BASE_IDX 1 808#define regUVD_JPEG_TIER_CNTL1 0x05ce 809#define regUVD_JPEG_TIER_CNTL1_BASE_IDX 1 810#define regUVD_JPEG_TIER_CNTL2 0x05cf 811#define regUVD_JPEG_TIER_CNTL2_BASE_IDX 1 812#define regUVD_JPEG_TIER_STATUS 0x05d0 813#define regUVD_JPEG_TIER_STATUS_BASE_IDX 1 814#define regUVD_JPEG_OUTBUF_CNTL 0x05dc 815#define regUVD_JPEG_OUTBUF_CNTL_BASE_IDX 1 816#define regUVD_JPEG_OUTBUF_WPTR 0x05dd 817#define regUVD_JPEG_OUTBUF_WPTR_BASE_IDX 1 818#define regUVD_JPEG_OUTBUF_RPTR 0x05de 819#define regUVD_JPEG_OUTBUF_RPTR_BASE_IDX 1 820#define regUVD_JPEG_PITCH 0x05df 821#define regUVD_JPEG_PITCH_BASE_IDX 1 822#define regUVD_JPEG_UV_PITCH 0x05e0 823#define regUVD_JPEG_UV_PITCH_BASE_IDX 1 824#define regJPEG_DEC_Y_GFX8_TILING_SURFACE 0x05e1 825#define regJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX 1 826#define regJPEG_DEC_UV_GFX8_TILING_SURFACE 0x05e2 827#define regJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX 1 828#define regJPEG_DEC_GFX8_ADDR_CONFIG 0x05e3 829#define regJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX 1 830#define regJPEG_DEC_Y_GFX10_TILING_SURFACE 0x05e4 831#define regJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX 1 832#define regJPEG_DEC_UV_GFX10_TILING_SURFACE 0x05e5 833#define regJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX 1 834#define regJPEG_DEC_GFX10_ADDR_CONFIG 0x05e6 835#define regJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX 1 836#define regJPEG_DEC_ADDR_MODE 0x05e7 837#define regJPEG_DEC_ADDR_MODE_BASE_IDX 1 838#define regUVD_JPEG_OUTPUT_XY 0x05e8 839#define regUVD_JPEG_OUTPUT_XY_BASE_IDX 1 840#define regUVD_JPEG_GPCOM_CMD 0x05e9 841#define regUVD_JPEG_GPCOM_CMD_BASE_IDX 1 842#define regUVD_JPEG_GPCOM_DATA0 0x05ea 843#define regUVD_JPEG_GPCOM_DATA0_BASE_IDX 1 844#define regUVD_JPEG_GPCOM_DATA1 0x05eb 845#define regUVD_JPEG_GPCOM_DATA1_BASE_IDX 1 846#define regUVD_JPEG_INDEX 0x05ec 847#define regUVD_JPEG_INDEX_BASE_IDX 1 848#define regUVD_JPEG_DATA 0x05ed 849#define regUVD_JPEG_DATA_BASE_IDX 1 850#define regUVD_JPEG_SCRATCH1 0x05ee 851#define regUVD_JPEG_SCRATCH1_BASE_IDX 1 852#define regUVD_JPEG_DEC_SOFT_RST 0x05ef 853#define regUVD_JPEG_DEC_SOFT_RST_BASE_IDX 1 854 855 856// addressBlock: uvd0_uvd_jrbc_dec 857// base address: 0x21100 858#define regUVD_JRBC_RB_WPTR 0x0640 859#define regUVD_JRBC_RB_WPTR_BASE_IDX 1 860#define regUVD_JRBC_RB_CNTL 0x0641 861#define regUVD_JRBC_RB_CNTL_BASE_IDX 1 862#define regUVD_JRBC_IB_SIZE 0x0642 863#define regUVD_JRBC_IB_SIZE_BASE_IDX 1 864#define regUVD_JRBC_URGENT_CNTL 0x0643 865#define regUVD_JRBC_URGENT_CNTL_BASE_IDX 1 866#define regUVD_JRBC_RB_REF_DATA 0x0644 867#define regUVD_JRBC_RB_REF_DATA_BASE_IDX 1 868#define regUVD_JRBC_RB_COND_RD_TIMER 0x0645 869#define regUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 1 870#define regUVD_JRBC_SOFT_RESET 0x0648 871#define regUVD_JRBC_SOFT_RESET_BASE_IDX 1 872#define regUVD_JRBC_STATUS 0x0649 873#define regUVD_JRBC_STATUS_BASE_IDX 1 874#define regUVD_JRBC_RB_RPTR 0x064a 875#define regUVD_JRBC_RB_RPTR_BASE_IDX 1 876#define regUVD_JRBC_RB_BUF_STATUS 0x064b 877#define regUVD_JRBC_RB_BUF_STATUS_BASE_IDX 1 878#define regUVD_JRBC_IB_BUF_STATUS 0x064c 879#define regUVD_JRBC_IB_BUF_STATUS_BASE_IDX 1 880#define regUVD_JRBC_IB_SIZE_UPDATE 0x064d 881#define regUVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 1 882#define regUVD_JRBC_IB_COND_RD_TIMER 0x064e 883#define regUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 1 884#define regUVD_JRBC_IB_REF_DATA 0x064f 885#define regUVD_JRBC_IB_REF_DATA_BASE_IDX 1 886#define regUVD_JPEG_PREEMPT_CMD 0x0650 887#define regUVD_JPEG_PREEMPT_CMD_BASE_IDX 1 888#define regUVD_JPEG_PREEMPT_FENCE_DATA0 0x0651 889#define regUVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 1 890#define regUVD_JPEG_PREEMPT_FENCE_DATA1 0x0652 891#define regUVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 1 892#define regUVD_JRBC_RB_SIZE 0x0653 893#define regUVD_JRBC_RB_SIZE_BASE_IDX 1 894#define regUVD_JRBC_SCRATCH0 0x0654 895#define regUVD_JRBC_SCRATCH0_BASE_IDX 1 896 897 898// addressBlock: uvd0_uvd_jmi_dec 899// base address: 0x21200 900#define regUVD_JADP_MCIF_URGENT_CTRL 0x0681 901#define regUVD_JADP_MCIF_URGENT_CTRL_BASE_IDX 1 902#define regUVD_JMI_URGENT_CTRL 0x0682 903#define regUVD_JMI_URGENT_CTRL_BASE_IDX 1 904#define regUVD_JPEG_DEC_PF_CTRL 0x0683 905#define regUVD_JPEG_DEC_PF_CTRL_BASE_IDX 1 906#define regUVD_JPEG_ENC_PF_CTRL 0x0684 907#define regUVD_JPEG_ENC_PF_CTRL_BASE_IDX 1 908#define regUVD_JMI_CTRL 0x0685 909#define regUVD_JMI_CTRL_BASE_IDX 1 910#define regUVD_LMI_JRBC_CTRL 0x0686 911#define regUVD_LMI_JRBC_CTRL_BASE_IDX 1 912#define regUVD_LMI_JPEG_CTRL 0x0687 913#define regUVD_LMI_JPEG_CTRL_BASE_IDX 1 914#define regUVD_JMI_EJRBC_CTRL 0x0688 915#define regUVD_JMI_EJRBC_CTRL_BASE_IDX 1 916#define regUVD_LMI_EJPEG_CTRL 0x0689 917#define regUVD_LMI_EJPEG_CTRL_BASE_IDX 1 918#define regUVD_JMI_SCALER_CTRL 0x068a 919#define regUVD_JMI_SCALER_CTRL_BASE_IDX 1 920#define regJPEG_LMI_DROP 0x068b 921#define regJPEG_LMI_DROP_BASE_IDX 1 922#define regUVD_JMI_EJPEG_DROP 0x068c 923#define regUVD_JMI_EJPEG_DROP_BASE_IDX 1 924#define regJPEG_MEMCHECK_CLAMPING 0x068d 925#define regJPEG_MEMCHECK_CLAMPING_BASE_IDX 1 926#define regUVD_JMI_EJPEG_MEMCHECK_CLAMPING 0x068e 927#define regUVD_JMI_EJPEG_MEMCHECK_CLAMPING_BASE_IDX 1 928#define regUVD_LMI_JRBC_IB_VMID 0x068f 929#define regUVD_LMI_JRBC_IB_VMID_BASE_IDX 1 930#define regUVD_LMI_JRBC_RB_VMID 0x0690 931#define regUVD_LMI_JRBC_RB_VMID_BASE_IDX 1 932#define regUVD_LMI_JPEG_VMID 0x0691 933#define regUVD_LMI_JPEG_VMID_BASE_IDX 1 934#define regUVD_JMI_ENC_JRBC_IB_VMID 0x0692 935#define regUVD_JMI_ENC_JRBC_IB_VMID_BASE_IDX 1 936#define regUVD_JMI_ENC_JRBC_RB_VMID 0x0693 937#define regUVD_JMI_ENC_JRBC_RB_VMID_BASE_IDX 1 938#define regUVD_JMI_ENC_JPEG_VMID 0x0694 939#define regUVD_JMI_ENC_JPEG_VMID_BASE_IDX 1 940#define regJPEG_MEMCHECK_SAFE_ADDR 0x0697 941#define regJPEG_MEMCHECK_SAFE_ADDR_BASE_IDX 1 942#define regJPEG_MEMCHECK_SAFE_ADDR_64BIT 0x0698 943#define regJPEG_MEMCHECK_SAFE_ADDR_64BIT_BASE_IDX 1 944#define regUVD_JMI_LAT_CTRL 0x0699 945#define regUVD_JMI_LAT_CTRL_BASE_IDX 1 946#define regUVD_JMI_LAT_CNTR 0x069a 947#define regUVD_JMI_LAT_CNTR_BASE_IDX 1 948#define regUVD_JMI_AVG_LAT_CNTR 0x069b 949#define regUVD_JMI_AVG_LAT_CNTR_BASE_IDX 1 950#define regUVD_JMI_PERFMON_CTRL 0x069c 951#define regUVD_JMI_PERFMON_CTRL_BASE_IDX 1 952#define regUVD_JMI_PERFMON_COUNT_LO 0x069d 953#define regUVD_JMI_PERFMON_COUNT_LO_BASE_IDX 1 954#define regUVD_JMI_PERFMON_COUNT_HI 0x069e 955#define regUVD_JMI_PERFMON_COUNT_HI_BASE_IDX 1 956#define regUVD_JMI_CLEAN_STATUS 0x069f 957#define regUVD_JMI_CLEAN_STATUS_BASE_IDX 1 958#define regUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x06a0 959#define regUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 1 960#define regUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x06a1 961#define regUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 1 962#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x06a2 963#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 1 964#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x06a3 965#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 1 966#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x06a4 967#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 1 968#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x06a5 969#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 1 970#define regUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x06a6 971#define regUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 1 972#define regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x06a7 973#define regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 974#define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x06a8 975#define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 1 976#define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x06a9 977#define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 978#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x06aa 979#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 1 980#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x06ab 981#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 1 982#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 0x06ac 983#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 1 984#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x06ad 985#define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 1 986#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x06ae 987#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 1 988#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x06af 989#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 1 990#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 0x06b0 991#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 1 992#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x06b1 993#define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 1 994#define regUVD_JMI_PEL_RD_64BIT_BAR_LOW 0x06b2 995#define regUVD_JMI_PEL_RD_64BIT_BAR_LOW_BASE_IDX 1 996#define regUVD_JMI_PEL_RD_64BIT_BAR_HIGH 0x06b3 997#define regUVD_JMI_PEL_RD_64BIT_BAR_HIGH_BASE_IDX 1 998#define regUVD_JMI_BS_WR_64BIT_BAR_LOW 0x06b4 999#define regUVD_JMI_BS_WR_64BIT_BAR_LOW_BASE_IDX 1 1000#define regUVD_JMI_BS_WR_64BIT_BAR_HIGH 0x06b5 1001#define regUVD_JMI_BS_WR_64BIT_BAR_HIGH_BASE_IDX 1 1002#define regUVD_JMI_SCALAR_RD_64BIT_BAR_LOW 0x06b6 1003#define regUVD_JMI_SCALAR_RD_64BIT_BAR_LOW_BASE_IDX 1 1004#define regUVD_JMI_SCALAR_RD_64BIT_BAR_HIGH 0x06b7 1005#define regUVD_JMI_SCALAR_RD_64BIT_BAR_HIGH_BASE_IDX 1 1006#define regUVD_JMI_SCALAR_WR_64BIT_BAR_LOW 0x06b8 1007#define regUVD_JMI_SCALAR_WR_64BIT_BAR_LOW_BASE_IDX 1 1008#define regUVD_JMI_SCALAR_WR_64BIT_BAR_HIGH 0x06b9 1009#define regUVD_JMI_SCALAR_WR_64BIT_BAR_HIGH_BASE_IDX 1 1010#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x06ba 1011#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 1 1012#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x06bb 1013#define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 1 1014#define regUVD_LMI_EJRBC_RB_64BIT_BAR_LOW 0x06bc 1015#define regUVD_LMI_EJRBC_RB_64BIT_BAR_LOW_BASE_IDX 1 1016#define regUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 0x06bd 1017#define regUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 1018#define regUVD_LMI_EJRBC_IB_64BIT_BAR_LOW 0x06be 1019#define regUVD_LMI_EJRBC_IB_64BIT_BAR_LOW_BASE_IDX 1 1020#define regUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 0x06bf 1021#define regUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 1022#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 0x06c0 1023#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 1 1024#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x06c1 1025#define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 1 1026#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 0x06c2 1027#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 1 1028#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x06c3 1029#define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 1 1030#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 0x06c4 1031#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 1 1032#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x06c5 1033#define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 1 1034#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 0x06c6 1035#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 1 1036#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x06c7 1037#define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 1 1038#define regUVD_LMI_JPEG_PREEMPT_VMID 0x06c8 1039#define regUVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 1 1040#define regUVD_LMI_ENC_JPEG_PREEMPT_VMID 0x06c9 1041#define regUVD_LMI_ENC_JPEG_PREEMPT_VMID_BASE_IDX 1 1042#define regUVD_LMI_JPEG2_VMID 0x06ca 1043#define regUVD_LMI_JPEG2_VMID_BASE_IDX 1 1044#define regUVD_LMI_JPEG2_READ_64BIT_BAR_LOW 0x06cb 1045#define regUVD_LMI_JPEG2_READ_64BIT_BAR_LOW_BASE_IDX 1 1046#define regUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 0x06cc 1047#define regUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH_BASE_IDX 1 1048#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 0x06cd 1049#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW_BASE_IDX 1 1050#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 0x06ce 1051#define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH_BASE_IDX 1 1052#define regUVD_LMI_JPEG_CTRL2 0x06cf 1053#define regUVD_LMI_JPEG_CTRL2_BASE_IDX 1 1054#define regUVD_JMI_DEC_SWAP_CNTL 0x06d0 1055#define regUVD_JMI_DEC_SWAP_CNTL_BASE_IDX 1 1056#define regUVD_JMI_ENC_SWAP_CNTL 0x06d1 1057#define regUVD_JMI_ENC_SWAP_CNTL_BASE_IDX 1 1058#define regUVD_JMI_CNTL 0x06d2 1059#define regUVD_JMI_CNTL_BASE_IDX 1 1060#define regUVD_JMI_ATOMIC_CNTL 0x06d3 1061#define regUVD_JMI_ATOMIC_CNTL_BASE_IDX 1 1062#define regUVD_JMI_ATOMIC_CNTL2 0x06d4 1063#define regUVD_JMI_ATOMIC_CNTL2_BASE_IDX 1 1064#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 0x06d5 1065#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX 1 1066#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 0x06d6 1067#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX 1 1068#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW 0x06d7 1069#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW_BASE_IDX 1 1070#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH 0x06d8 1071#define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH_BASE_IDX 1 1072#define regJPEG2_LMI_DROP 0x06d9 1073#define regJPEG2_LMI_DROP_BASE_IDX 1 1074#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 0x06da 1075#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW_BASE_IDX 1 1076#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 0x06db 1077#define regUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH_BASE_IDX 1 1078#define regUVD_JMI_DEC_SWAP_CNTL2 0x06dc 1079#define regUVD_JMI_DEC_SWAP_CNTL2_BASE_IDX 1 1080#define regUVD_JMI_DJPEG_RAS_CNTL 0x06dd 1081#define regUVD_JMI_DJPEG_RAS_CNTL_BASE_IDX 1 1082#define regUVD_JMI_EJPEG_RAS_CNTL 0x06de 1083#define regUVD_JMI_EJPEG_RAS_CNTL_BASE_IDX 1 1084#define regUVD_JPEG_DEC2_PF_CTRL 0x06df 1085#define regUVD_JPEG_DEC2_PF_CTRL_BASE_IDX 1 1086 1087 1088// addressBlock: uvd0_uvd_jpeg_common_dec 1089// base address: 0x21400 1090#define regJPEG_SOFT_RESET_STATUS 0x0700 1091#define regJPEG_SOFT_RESET_STATUS_BASE_IDX 1 1092#define regJPEG_SYS_INT_EN 0x0701 1093#define regJPEG_SYS_INT_EN_BASE_IDX 1 1094#define regJPEG_SYS_INT_STATUS 0x0702 1095#define regJPEG_SYS_INT_STATUS_BASE_IDX 1 1096#define regJPEG_SYS_INT_ACK 0x0703 1097#define regJPEG_SYS_INT_ACK_BASE_IDX 1 1098#define regJPEG_MEMCHECK_SYS_INT_EN 0x0704 1099#define regJPEG_MEMCHECK_SYS_INT_EN_BASE_IDX 1 1100#define regJPEG_MEMCHECK_SYS_INT_STAT 0x0705 1101#define regJPEG_MEMCHECK_SYS_INT_STAT_BASE_IDX 1 1102#define regJPEG_MEMCHECK_SYS_INT_ACK 0x0706 1103#define regJPEG_MEMCHECK_SYS_INT_ACK_BASE_IDX 1 1104#define regJPEG_MASTINT_EN 0x0708 1105#define regJPEG_MASTINT_EN_BASE_IDX 1 1106#define regJPEG_IH_CTRL 0x0709 1107#define regJPEG_IH_CTRL_BASE_IDX 1 1108#define regJRBBM_ARB_CTRL 0x070b 1109#define regJRBBM_ARB_CTRL_BASE_IDX 1 1110 1111 1112// addressBlock: uvd0_uvd_jpeg_common_sclk_dec 1113// base address: 0x21480 1114#define regJPEG_CGC_GATE 0x0720 1115#define regJPEG_CGC_GATE_BASE_IDX 1 1116#define regJPEG_CGC_CTRL 0x0721 1117#define regJPEG_CGC_CTRL_BASE_IDX 1 1118#define regJPEG_CGC_STATUS 0x0722 1119#define regJPEG_CGC_STATUS_BASE_IDX 1 1120#define regJPEG_COMN_CGC_MEM_CTRL 0x0723 1121#define regJPEG_COMN_CGC_MEM_CTRL_BASE_IDX 1 1122#define regJPEG_DEC_CGC_MEM_CTRL 0x0724 1123#define regJPEG_DEC_CGC_MEM_CTRL_BASE_IDX 1 1124#define regJPEG2_DEC_CGC_MEM_CTRL 0x0725 1125#define regJPEG2_DEC_CGC_MEM_CTRL_BASE_IDX 1 1126#define regJPEG_ENC_CGC_MEM_CTRL 0x0726 1127#define regJPEG_ENC_CGC_MEM_CTRL_BASE_IDX 1 1128#define regJPEG_SOFT_RESET2 0x0727 1129#define regJPEG_SOFT_RESET2_BASE_IDX 1 1130#define regJPEG_PERF_BANK_CONF 0x0728 1131#define regJPEG_PERF_BANK_CONF_BASE_IDX 1 1132#define regJPEG_PERF_BANK_EVENT_SEL 0x0729 1133#define regJPEG_PERF_BANK_EVENT_SEL_BASE_IDX 1 1134#define regJPEG_PERF_BANK_COUNT0 0x072a 1135#define regJPEG_PERF_BANK_COUNT0_BASE_IDX 1 1136#define regJPEG_PERF_BANK_COUNT1 0x072b 1137#define regJPEG_PERF_BANK_COUNT1_BASE_IDX 1 1138#define regJPEG_PERF_BANK_COUNT2 0x072c 1139#define regJPEG_PERF_BANK_COUNT2_BASE_IDX 1 1140#define regJPEG_PERF_BANK_COUNT3 0x072d 1141#define regJPEG_PERF_BANK_COUNT3_BASE_IDX 1 1142 1143 1144// addressBlock: uvd0_uvd_pg_dec 1145// base address: 0x1f800 1146#define regUVD_PGFSM_CONFIG 0x0000 1147#define regUVD_PGFSM_CONFIG_BASE_IDX 1 1148#define regUVD_PGFSM_STATUS 0x0001 1149#define regUVD_PGFSM_STATUS_BASE_IDX 1 1150#define regUVD_POWER_STATUS 0x0002 1151#define regUVD_POWER_STATUS_BASE_IDX 1 1152#define regUVD_JPEG_POWER_STATUS 0x0003 1153#define regUVD_JPEG_POWER_STATUS_BASE_IDX 1 1154#define regUVD_PG_IND_INDEX 0x000c 1155#define regUVD_PG_IND_INDEX_BASE_IDX 1 1156#define regUVD_PG_IND_DATA 0x000e 1157#define regUVD_PG_IND_DATA_BASE_IDX 1 1158#define regCC_UVD_HARVESTING 0x000f 1159#define regCC_UVD_HARVESTING_BASE_IDX 1 1160#define regUVD_DPG_LMA_CTL 0x0011 1161#define regUVD_DPG_LMA_CTL_BASE_IDX 1 1162#define regUVD_DPG_LMA_DATA 0x0012 1163#define regUVD_DPG_LMA_DATA_BASE_IDX 1 1164#define regUVD_DPG_LMA_MASK 0x0013 1165#define regUVD_DPG_LMA_MASK_BASE_IDX 1 1166#define regUVD_DPG_PAUSE 0x0014 1167#define regUVD_DPG_PAUSE_BASE_IDX 1 1168#define regUVD_SCRATCH1 0x0015 1169#define regUVD_SCRATCH1_BASE_IDX 1 1170#define regUVD_SCRATCH2 0x0016 1171#define regUVD_SCRATCH2_BASE_IDX 1 1172#define regUVD_SCRATCH3 0x0017 1173#define regUVD_SCRATCH3_BASE_IDX 1 1174#define regUVD_SCRATCH4 0x0018 1175#define regUVD_SCRATCH4_BASE_IDX 1 1176#define regUVD_SCRATCH5 0x0019 1177#define regUVD_SCRATCH5_BASE_IDX 1 1178#define regUVD_SCRATCH6 0x001a 1179#define regUVD_SCRATCH6_BASE_IDX 1 1180#define regUVD_SCRATCH7 0x001b 1181#define regUVD_SCRATCH7_BASE_IDX 1 1182#define regUVD_SCRATCH8 0x001c 1183#define regUVD_SCRATCH8_BASE_IDX 1 1184#define regUVD_SCRATCH9 0x001d 1185#define regUVD_SCRATCH9_BASE_IDX 1 1186#define regUVD_SCRATCH10 0x001e 1187#define regUVD_SCRATCH10_BASE_IDX 1 1188#define regUVD_SCRATCH11 0x001f 1189#define regUVD_SCRATCH11_BASE_IDX 1 1190#define regUVD_SCRATCH12 0x0020 1191#define regUVD_SCRATCH12_BASE_IDX 1 1192#define regUVD_SCRATCH13 0x0021 1193#define regUVD_SCRATCH13_BASE_IDX 1 1194#define regUVD_SCRATCH14 0x0022 1195#define regUVD_SCRATCH14_BASE_IDX 1 1196#define regUVD_FREE_COUNTER_REG 0x0023 1197#define regUVD_FREE_COUNTER_REG_BASE_IDX 1 1198#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x0024 1199#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 1200#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x0025 1201#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 1202#define regUVD_DPG_VCPU_CACHE_OFFSET0 0x0026 1203#define regUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1 1204#define regUVD_DPG_LMI_VCPU_CACHE_VMID 0x0027 1205#define regUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX 1 1206#define regUVD_FW_VERSION 0x002a 1207#define regUVD_FW_VERSION_BASE_IDX 1 1208#define regUVD_PF_STATUS 0x002c 1209#define regUVD_PF_STATUS_BASE_IDX 1 1210#define regUVD_DPG_CLK_EN_VCPU_REPORT 0x002e 1211#define regUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX 1 1212#define regUVD_GFX8_ADDR_CONFIG 0x0041 1213#define regUVD_GFX8_ADDR_CONFIG_BASE_IDX 1 1214#define regUVD_GFX10_ADDR_CONFIG 0x0042 1215#define regUVD_GFX10_ADDR_CONFIG_BASE_IDX 1 1216#define regUVD_GPCNT2_CNTL 0x0043 1217#define regUVD_GPCNT2_CNTL_BASE_IDX 1 1218#define regUVD_GPCNT2_TARGET_LOWER 0x0044 1219#define regUVD_GPCNT2_TARGET_LOWER_BASE_IDX 1 1220#define regUVD_GPCNT2_STATUS_LOWER 0x0045 1221#define regUVD_GPCNT2_STATUS_LOWER_BASE_IDX 1 1222#define regUVD_GPCNT2_TARGET_UPPER 0x0046 1223#define regUVD_GPCNT2_TARGET_UPPER_BASE_IDX 1 1224#define regUVD_GPCNT2_STATUS_UPPER 0x0047 1225#define regUVD_GPCNT2_STATUS_UPPER_BASE_IDX 1 1226#define regUVD_GPCNT3_CNTL 0x0048 1227#define regUVD_GPCNT3_CNTL_BASE_IDX 1 1228#define regUVD_GPCNT3_TARGET_LOWER 0x0049 1229#define regUVD_GPCNT3_TARGET_LOWER_BASE_IDX 1 1230#define regUVD_GPCNT3_STATUS_LOWER 0x004a 1231#define regUVD_GPCNT3_STATUS_LOWER_BASE_IDX 1 1232#define regUVD_GPCNT3_TARGET_UPPER 0x004b 1233#define regUVD_GPCNT3_TARGET_UPPER_BASE_IDX 1 1234#define regUVD_GPCNT3_STATUS_UPPER 0x004c 1235#define regUVD_GPCNT3_STATUS_UPPER_BASE_IDX 1 1236#define regUVD_VCLK_DS_CNTL 0x004d 1237#define regUVD_VCLK_DS_CNTL_BASE_IDX 1 1238#define regUVD_DCLK_DS_CNTL 0x004e 1239#define regUVD_DCLK_DS_CNTL_BASE_IDX 1 1240#define regUVD_TSC_LOWER 0x004f 1241#define regUVD_TSC_LOWER_BASE_IDX 1 1242#define regUVD_TSC_UPPER 0x0050 1243#define regUVD_TSC_UPPER_BASE_IDX 1 1244#define regVCN_FEATURES 0x0051 1245#define regVCN_FEATURES_BASE_IDX 1 1246#define regUVD_GPUIOV_STATUS 0x0055 1247#define regUVD_GPUIOV_STATUS_BASE_IDX 1 1248#define regUVD_RAS_VCPU_VCODEC_STATUS 0x0057 1249#define regUVD_RAS_VCPU_VCODEC_STATUS_BASE_IDX 1 1250#define regUVD_RAS_MMSCH_FATAL_ERROR 0x0058 1251#define regUVD_RAS_MMSCH_FATAL_ERROR_BASE_IDX 1 1252#define regUVD_RAS_JPEG0_STATUS 0x0059 1253#define regUVD_RAS_JPEG0_STATUS_BASE_IDX 1 1254#define regUVD_RAS_JPEG1_STATUS 0x005a 1255#define regUVD_RAS_JPEG1_STATUS_BASE_IDX 1 1256#define regUVD_RAS_CNTL_PMI_ARB 0x005b 1257#define regUVD_RAS_CNTL_PMI_ARB_BASE_IDX 1 1258#define regUVD_SCRATCH15 0x005c 1259#define regUVD_SCRATCH15_BASE_IDX 1 1260#define regUVD_SCRATCH16 0x005d 1261#define regUVD_SCRATCH16_BASE_IDX 1 1262#define regUVD_SCRATCH17 0x005e 1263#define regUVD_SCRATCH17_BASE_IDX 1 1264#define regUVD_SCRATCH18 0x005f 1265#define regUVD_SCRATCH18_BASE_IDX 1 1266#define regUVD_SCRATCH19 0x0060 1267#define regUVD_SCRATCH19_BASE_IDX 1 1268#define regUVD_SCRATCH20 0x0061 1269#define regUVD_SCRATCH20_BASE_IDX 1 1270#define regUVD_SCRATCH21 0x0062 1271#define regUVD_SCRATCH21_BASE_IDX 1 1272#define regUVD_SCRATCH22 0x0063 1273#define regUVD_SCRATCH22_BASE_IDX 1 1274#define regUVD_SCRATCH23 0x0064 1275#define regUVD_SCRATCH23_BASE_IDX 1 1276#define regUVD_SCRATCH24 0x0065 1277#define regUVD_SCRATCH24_BASE_IDX 1 1278#define regUVD_SCRATCH25 0x0066 1279#define regUVD_SCRATCH25_BASE_IDX 1 1280#define regUVD_SCRATCH26 0x0067 1281#define regUVD_SCRATCH26_BASE_IDX 1 1282#define regUVD_SCRATCH27 0x0068 1283#define regUVD_SCRATCH27_BASE_IDX 1 1284#define regUVD_SCRATCH28 0x0069 1285#define regUVD_SCRATCH28_BASE_IDX 1 1286#define regUVD_SCRATCH29 0x006a 1287#define regUVD_SCRATCH29_BASE_IDX 1 1288#define regUVD_SCRATCH30 0x006b 1289#define regUVD_SCRATCH30_BASE_IDX 1 1290#define regUVD_SCRATCH31 0x006c 1291#define regUVD_SCRATCH31_BASE_IDX 1 1292#define regUVD_SCRATCH32 0x006d 1293#define regUVD_SCRATCH32_BASE_IDX 1 1294#define regUVD_VERSION 0x006e 1295#define regUVD_VERSION_BASE_IDX 1 1296#define regVCN_RB_DB_CTRL 0x0070 1297#define regVCN_RB_DB_CTRL_BASE_IDX 1 1298#define regVCN_JPEG_DB_CTRL 0x0071 1299#define regVCN_JPEG_DB_CTRL_BASE_IDX 1 1300#define regVCN_RB1_DB_CTRL 0x0072 1301#define regVCN_RB1_DB_CTRL_BASE_IDX 1 1302#define regVCN_RB2_DB_CTRL 0x0073 1303#define regVCN_RB2_DB_CTRL_BASE_IDX 1 1304#define regVCN_RB3_DB_CTRL 0x0074 1305#define regVCN_RB3_DB_CTRL_BASE_IDX 1 1306#define regVCN_RB4_DB_CTRL 0x0075 1307#define regVCN_RB4_DB_CTRL_BASE_IDX 1 1308#define regVCN_UMSCH_RB_DB_CTRL 0x0076 1309#define regVCN_UMSCH_RB_DB_CTRL_BASE_IDX 1 1310#define regVCN_AGDB_CTRL0 0x0079 1311#define regVCN_AGDB_CTRL0_BASE_IDX 1 1312#define regVCN_AGDB_CTRL1 0x007a 1313#define regVCN_AGDB_CTRL1_BASE_IDX 1 1314#define regVCN_AGDB_CTRL2 0x007b 1315#define regVCN_AGDB_CTRL2_BASE_IDX 1 1316#define regVCN_AGDB_CTRL3 0x007c 1317#define regVCN_AGDB_CTRL3_BASE_IDX 1 1318#define regVCN_AGDB_CTRL4 0x007d 1319#define regVCN_AGDB_CTRL4_BASE_IDX 1 1320#define regVCN_AGDB_CTRL5 0x007e 1321#define regVCN_AGDB_CTRL5_BASE_IDX 1 1322#define regVCN_AGDB_MASK0 0x007f 1323#define regVCN_AGDB_MASK0_BASE_IDX 1 1324#define regVCN_AGDB_MASK1 0x0080 1325#define regVCN_AGDB_MASK1_BASE_IDX 1 1326#define regVCN_AGDB_MASK2 0x0081 1327#define regVCN_AGDB_MASK2_BASE_IDX 1 1328#define regVCN_AGDB_MASK3 0x0082 1329#define regVCN_AGDB_MASK3_BASE_IDX 1 1330#define regVCN_AGDB_MASK4 0x0083 1331#define regVCN_AGDB_MASK4_BASE_IDX 1 1332#define regVCN_AGDB_MASK5 0x0084 1333#define regVCN_AGDB_MASK5_BASE_IDX 1 1334#define regVCN_RB_ENABLE 0x0085 1335#define regVCN_RB_ENABLE_BASE_IDX 1 1336#define regVCN_RB_WPTR_CTRL 0x0086 1337#define regVCN_RB_WPTR_CTRL_BASE_IDX 1 1338#define regUVD_RB_RPTR 0x00ac 1339#define regUVD_RB_RPTR_BASE_IDX 1 1340#define regUVD_RB_WPTR 0x00ad 1341#define regUVD_RB_WPTR_BASE_IDX 1 1342#define regUVD_RB_RPTR2 0x00ae 1343#define regUVD_RB_RPTR2_BASE_IDX 1 1344#define regUVD_RB_WPTR2 0x00af 1345#define regUVD_RB_WPTR2_BASE_IDX 1 1346#define regUVD_RB_RPTR3 0x00b0 1347#define regUVD_RB_RPTR3_BASE_IDX 1 1348#define regUVD_RB_WPTR3 0x00b1 1349#define regUVD_RB_WPTR3_BASE_IDX 1 1350#define regUVD_RB_RPTR4 0x00b2 1351#define regUVD_RB_RPTR4_BASE_IDX 1 1352#define regUVD_RB_WPTR4 0x00b3 1353#define regUVD_RB_WPTR4_BASE_IDX 1 1354#define regUVD_OUT_RB_RPTR 0x00b4 1355#define regUVD_OUT_RB_RPTR_BASE_IDX 1 1356#define regUVD_OUT_RB_WPTR 0x00b5 1357#define regUVD_OUT_RB_WPTR_BASE_IDX 1 1358#define regUVD_AUDIO_RB_RPTR 0x00b6 1359#define regUVD_AUDIO_RB_RPTR_BASE_IDX 1 1360#define regUVD_AUDIO_RB_WPTR 0x00b7 1361#define regUVD_AUDIO_RB_WPTR_BASE_IDX 1 1362#define regUVD_RBC_RB_RPTR 0x00b8 1363#define regUVD_RBC_RB_RPTR_BASE_IDX 1 1364#define regUVD_RBC_RB_WPTR 0x00b9 1365#define regUVD_RBC_RB_WPTR_BASE_IDX 1 1366#define regUVD_DPG_LMA_CTL2 0x00bb 1367#define regUVD_DPG_LMA_CTL2_BASE_IDX 1 1368 1369 1370// addressBlock: uvd0_mmsch_dec 1371// base address: 0x20d00 1372#define regMMSCH_UCODE_ADDR 0x0540 1373#define regMMSCH_UCODE_ADDR_BASE_IDX 1 1374#define regMMSCH_UCODE_DATA 0x0541 1375#define regMMSCH_UCODE_DATA_BASE_IDX 1 1376#define regMMSCH_SRAM_ADDR 0x0542 1377#define regMMSCH_SRAM_ADDR_BASE_IDX 1 1378#define regMMSCH_SRAM_DATA 0x0543 1379#define regMMSCH_SRAM_DATA_BASE_IDX 1 1380#define regMMSCH_VF_SRAM_OFFSET 0x0544 1381#define regMMSCH_VF_SRAM_OFFSET_BASE_IDX 1 1382#define regMMSCH_DB_SRAM_OFFSET 0x0545 1383#define regMMSCH_DB_SRAM_OFFSET_BASE_IDX 1 1384#define regMMSCH_CTX_SRAM_OFFSET 0x0546 1385#define regMMSCH_CTX_SRAM_OFFSET_BASE_IDX 1 1386#define regMMSCH_INTR 0x0548 1387#define regMMSCH_INTR_BASE_IDX 1 1388#define regMMSCH_INTR_ACK 0x0549 1389#define regMMSCH_INTR_ACK_BASE_IDX 1 1390#define regMMSCH_INTR_STATUS 0x054a 1391#define regMMSCH_INTR_STATUS_BASE_IDX 1 1392#define regMMSCH_VF_VMID 0x054b 1393#define regMMSCH_VF_VMID_BASE_IDX 1 1394#define regMMSCH_VF_CTX_ADDR_LO 0x054c 1395#define regMMSCH_VF_CTX_ADDR_LO_BASE_IDX 1 1396#define regMMSCH_VF_CTX_ADDR_HI 0x054d 1397#define regMMSCH_VF_CTX_ADDR_HI_BASE_IDX 1 1398#define regMMSCH_VF_CTX_SIZE 0x054e 1399#define regMMSCH_VF_CTX_SIZE_BASE_IDX 1 1400#define regMMSCH_VF_GPCOM_ADDR_LO 0x054f 1401#define regMMSCH_VF_GPCOM_ADDR_LO_BASE_IDX 1 1402#define regMMSCH_VF_GPCOM_ADDR_HI 0x0550 1403#define regMMSCH_VF_GPCOM_ADDR_HI_BASE_IDX 1 1404#define regMMSCH_VF_GPCOM_SIZE 0x0551 1405#define regMMSCH_VF_GPCOM_SIZE_BASE_IDX 1 1406#define regMMSCH_VF_MAILBOX_HOST 0x0552 1407#define regMMSCH_VF_MAILBOX_HOST_BASE_IDX 1 1408#define regMMSCH_VF_MAILBOX_RESP 0x0553 1409#define regMMSCH_VF_MAILBOX_RESP_BASE_IDX 1 1410#define regMMSCH_VF_MAILBOX_0 0x0554 1411#define regMMSCH_VF_MAILBOX_0_BASE_IDX 1 1412#define regMMSCH_VF_MAILBOX_0_RESP 0x0555 1413#define regMMSCH_VF_MAILBOX_0_RESP_BASE_IDX 1 1414#define regMMSCH_VF_MAILBOX_1 0x0556 1415#define regMMSCH_VF_MAILBOX_1_BASE_IDX 1 1416#define regMMSCH_VF_MAILBOX_1_RESP 0x0557 1417#define regMMSCH_VF_MAILBOX_1_RESP_BASE_IDX 1 1418#define regMMSCH_CNTL 0x055c 1419#define regMMSCH_CNTL_BASE_IDX 1 1420#define regMMSCH_NONCACHE_OFFSET0 0x055d 1421#define regMMSCH_NONCACHE_OFFSET0_BASE_IDX 1 1422#define regMMSCH_NONCACHE_SIZE0 0x055e 1423#define regMMSCH_NONCACHE_SIZE0_BASE_IDX 1 1424#define regMMSCH_NONCACHE_OFFSET1 0x055f 1425#define regMMSCH_NONCACHE_OFFSET1_BASE_IDX 1 1426#define regMMSCH_NONCACHE_SIZE1 0x0560 1427#define regMMSCH_NONCACHE_SIZE1_BASE_IDX 1 1428#define regMMSCH_PROC_STATE1 0x0566 1429#define regMMSCH_PROC_STATE1_BASE_IDX 1 1430#define regMMSCH_LAST_MC_ADDR 0x0567 1431#define regMMSCH_LAST_MC_ADDR_BASE_IDX 1 1432#define regMMSCH_LAST_MEM_ACCESS_HI 0x0568 1433#define regMMSCH_LAST_MEM_ACCESS_HI_BASE_IDX 1 1434#define regMMSCH_LAST_MEM_ACCESS_LO 0x0569 1435#define regMMSCH_LAST_MEM_ACCESS_LO_BASE_IDX 1 1436#define regMMSCH_SCRATCH_0 0x056b 1437#define regMMSCH_SCRATCH_0_BASE_IDX 1 1438#define regMMSCH_SCRATCH_1 0x056c 1439#define regMMSCH_SCRATCH_1_BASE_IDX 1 1440#define regMMSCH_GPUIOV_SCH_BLOCK_0 0x056d 1441#define regMMSCH_GPUIOV_SCH_BLOCK_0_BASE_IDX 1 1442#define regMMSCH_GPUIOV_CMD_CONTROL_0 0x056e 1443#define regMMSCH_GPUIOV_CMD_CONTROL_0_BASE_IDX 1 1444#define regMMSCH_GPUIOV_CMD_STATUS_0 0x056f 1445#define regMMSCH_GPUIOV_CMD_STATUS_0_BASE_IDX 1 1446#define regMMSCH_GPUIOV_VM_BUSY_STATUS_0 0x0570 1447#define regMMSCH_GPUIOV_VM_BUSY_STATUS_0_BASE_IDX 1 1448#define regMMSCH_GPUIOV_ACTIVE_FCNS_0 0x0571 1449#define regMMSCH_GPUIOV_ACTIVE_FCNS_0_BASE_IDX 1 1450#define regMMSCH_GPUIOV_DW6_0 0x0573 1451#define regMMSCH_GPUIOV_DW6_0_BASE_IDX 1 1452#define regMMSCH_GPUIOV_DW7_0 0x0574 1453#define regMMSCH_GPUIOV_DW7_0_BASE_IDX 1 1454#define regMMSCH_GPUIOV_DW8_0 0x0575 1455#define regMMSCH_GPUIOV_DW8_0_BASE_IDX 1 1456#define regMMSCH_GPUIOV_SCH_BLOCK_1 0x0576 1457#define regMMSCH_GPUIOV_SCH_BLOCK_1_BASE_IDX 1 1458#define regMMSCH_GPUIOV_CMD_CONTROL_1 0x0577 1459#define regMMSCH_GPUIOV_CMD_CONTROL_1_BASE_IDX 1 1460#define regMMSCH_GPUIOV_CMD_STATUS_1 0x0578 1461#define regMMSCH_GPUIOV_CMD_STATUS_1_BASE_IDX 1 1462#define regMMSCH_GPUIOV_VM_BUSY_STATUS_1 0x0579 1463#define regMMSCH_GPUIOV_VM_BUSY_STATUS_1_BASE_IDX 1 1464#define regMMSCH_GPUIOV_ACTIVE_FCNS_1 0x057a 1465#define regMMSCH_GPUIOV_ACTIVE_FCNS_1_BASE_IDX 1 1466#define regMMSCH_GPUIOV_DW6_1 0x057c 1467#define regMMSCH_GPUIOV_DW6_1_BASE_IDX 1 1468#define regMMSCH_GPUIOV_DW7_1 0x057d 1469#define regMMSCH_GPUIOV_DW7_1_BASE_IDX 1 1470#define regMMSCH_GPUIOV_DW8_1 0x057e 1471#define regMMSCH_GPUIOV_DW8_1_BASE_IDX 1 1472#define regMMSCH_GPUIOV_CNTXT 0x057f 1473#define regMMSCH_GPUIOV_CNTXT_BASE_IDX 1 1474#define regMMSCH_SCRATCH_2 0x0580 1475#define regMMSCH_SCRATCH_2_BASE_IDX 1 1476#define regMMSCH_SCRATCH_3 0x0581 1477#define regMMSCH_SCRATCH_3_BASE_IDX 1 1478#define regMMSCH_SCRATCH_4 0x0582 1479#define regMMSCH_SCRATCH_4_BASE_IDX 1 1480#define regMMSCH_SCRATCH_5 0x0583 1481#define regMMSCH_SCRATCH_5_BASE_IDX 1 1482#define regMMSCH_SCRATCH_6 0x0584 1483#define regMMSCH_SCRATCH_6_BASE_IDX 1 1484#define regMMSCH_SCRATCH_7 0x0585 1485#define regMMSCH_SCRATCH_7_BASE_IDX 1 1486#define regMMSCH_VFID_FIFO_HEAD_0 0x0586 1487#define regMMSCH_VFID_FIFO_HEAD_0_BASE_IDX 1 1488#define regMMSCH_VFID_FIFO_TAIL_0 0x0587 1489#define regMMSCH_VFID_FIFO_TAIL_0_BASE_IDX 1 1490#define regMMSCH_VFID_FIFO_HEAD_1 0x0588 1491#define regMMSCH_VFID_FIFO_HEAD_1_BASE_IDX 1 1492#define regMMSCH_VFID_FIFO_TAIL_1 0x0589 1493#define regMMSCH_VFID_FIFO_TAIL_1_BASE_IDX 1 1494#define regMMSCH_NACK_STATUS 0x058a 1495#define regMMSCH_NACK_STATUS_BASE_IDX 1 1496#define regMMSCH_VF_MAILBOX0_DATA 0x058b 1497#define regMMSCH_VF_MAILBOX0_DATA_BASE_IDX 1 1498#define regMMSCH_VF_MAILBOX1_DATA 0x058c 1499#define regMMSCH_VF_MAILBOX1_DATA_BASE_IDX 1 1500#define regMMSCH_GPUIOV_SCH_BLOCK_IP_0 0x058d 1501#define regMMSCH_GPUIOV_SCH_BLOCK_IP_0_BASE_IDX 1 1502#define regMMSCH_GPUIOV_CMD_STATUS_IP_0 0x058e 1503#define regMMSCH_GPUIOV_CMD_STATUS_IP_0_BASE_IDX 1 1504#define regMMSCH_GPUIOV_SCH_BLOCK_IP_1 0x0590 1505#define regMMSCH_GPUIOV_SCH_BLOCK_IP_1_BASE_IDX 1 1506#define regMMSCH_GPUIOV_CMD_STATUS_IP_1 0x0591 1507#define regMMSCH_GPUIOV_CMD_STATUS_IP_1_BASE_IDX 1 1508#define regMMSCH_GPUIOV_CNTXT_IP 0x0593 1509#define regMMSCH_GPUIOV_CNTXT_IP_BASE_IDX 1 1510#define regMMSCH_GPUIOV_SCH_BLOCK_2 0x0594 1511#define regMMSCH_GPUIOV_SCH_BLOCK_2_BASE_IDX 1 1512#define regMMSCH_GPUIOV_CMD_CONTROL_2 0x0595 1513#define regMMSCH_GPUIOV_CMD_CONTROL_2_BASE_IDX 1 1514#define regMMSCH_GPUIOV_CMD_STATUS_2 0x0596 1515#define regMMSCH_GPUIOV_CMD_STATUS_2_BASE_IDX 1 1516#define regMMSCH_GPUIOV_VM_BUSY_STATUS_2 0x0597 1517#define regMMSCH_GPUIOV_VM_BUSY_STATUS_2_BASE_IDX 1 1518#define regMMSCH_GPUIOV_ACTIVE_FCNS_2 0x0598 1519#define regMMSCH_GPUIOV_ACTIVE_FCNS_2_BASE_IDX 1 1520#define regMMSCH_GPUIOV_DW6_2 0x059a 1521#define regMMSCH_GPUIOV_DW6_2_BASE_IDX 1 1522#define regMMSCH_GPUIOV_DW7_2 0x059b 1523#define regMMSCH_GPUIOV_DW7_2_BASE_IDX 1 1524#define regMMSCH_GPUIOV_DW8_2 0x059c 1525#define regMMSCH_GPUIOV_DW8_2_BASE_IDX 1 1526#define regMMSCH_GPUIOV_SCH_BLOCK_IP_2 0x059d 1527#define regMMSCH_GPUIOV_SCH_BLOCK_IP_2_BASE_IDX 1 1528#define regMMSCH_GPUIOV_CMD_STATUS_IP_2 0x059e 1529#define regMMSCH_GPUIOV_CMD_STATUS_IP_2_BASE_IDX 1 1530#define regMMSCH_VFID_FIFO_HEAD_2 0x05a0 1531#define regMMSCH_VFID_FIFO_HEAD_2_BASE_IDX 1 1532#define regMMSCH_VFID_FIFO_TAIL_2 0x05a1 1533#define regMMSCH_VFID_FIFO_TAIL_2_BASE_IDX 1 1534#define regMMSCH_VM_BUSY_STATUS_0 0x05a2 1535#define regMMSCH_VM_BUSY_STATUS_0_BASE_IDX 1 1536#define regMMSCH_VM_BUSY_STATUS_1 0x05a3 1537#define regMMSCH_VM_BUSY_STATUS_1_BASE_IDX 1 1538#define regMMSCH_VM_BUSY_STATUS_2 0x05a4 1539#define regMMSCH_VM_BUSY_STATUS_2_BASE_IDX 1 1540 1541 1542// addressBlock: uvd0_slmi_adpdec 1543// base address: 0x21c00 1544#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 0x0900 1545#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX 1 1546#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 0x0901 1547#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX 1 1548#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 0x0902 1549#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX 1 1550#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 0x0903 1551#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX 1 1552#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 0x0904 1553#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX 1 1554#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 0x0905 1555#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX 1 1556#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 0x0906 1557#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX 1 1558#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 0x0907 1559#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX 1 1560#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 0x0908 1561#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX 1 1562#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 0x0909 1563#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX 1 1564#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 0x090a 1565#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX 1 1566#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 0x090b 1567#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX 1 1568#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 0x090c 1569#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX 1 1570#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 0x090d 1571#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX 1 1572#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 0x090e 1573#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX 1 1574#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 0x090f 1575#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX 1 1576#define regUVD_LMI_MMSCH_NC_VMID 0x0910 1577#define regUVD_LMI_MMSCH_NC_VMID_BASE_IDX 1 1578#define regUVD_LMI_MMSCH_CTRL 0x0911 1579#define regUVD_LMI_MMSCH_CTRL_BASE_IDX 1 1580#define regUVD_MMSCH_LMI_STATUS 0x0912 1581#define regUVD_MMSCH_LMI_STATUS_BASE_IDX 1 1582#define regVCN_RAS_CNTL_MMSCH 0x0914 1583#define regVCN_RAS_CNTL_MMSCH_BASE_IDX 1 1584 1585#define regVCN_UMSCH_MES_UTCL1_CNTL 0x0759 1586#define regVCN_UMSCH_MES_UTCL1_CNTL_BASE_IDX 1 1587#define regVCN_UMSCH_MES_BUSY 0x075a 1588#define regVCN_UMSCH_MES_BUSY_BASE_IDX 1 1589#define regVCN_UMSCH_RB_BASE_LO 0x075b 1590#define regVCN_UMSCH_RB_BASE_LO_BASE_IDX 1 1591#define regVCN_UMSCH_RB_BASE_HI 0x075c 1592#define regVCN_UMSCH_RB_BASE_HI_BASE_IDX 1 1593#define regVCN_UMSCH_RB_SIZE 0x075d 1594#define regVCN_UMSCH_RB_SIZE_BASE_IDX 1 1595#define regVCN_UMSCH_RB_RPTR 0x075e 1596#define regVCN_UMSCH_RB_RPTR_BASE_IDX 1 1597#define regVCN_UMSCH_RB_WPTR 0x075f 1598#define regVCN_UMSCH_RB_WPTR_BASE_IDX 1 1599#define regVCN_UMSCH_MASTINT_EN 0x0760 1600#define regVCN_UMSCH_MASTINT_EN_BASE_IDX 1 1601#define regVCN_UMSCH_IH_CTRL 0x0761 1602#define regVCN_UMSCH_IH_CTRL_BASE_IDX 1 1603#define regVCN_UMSCH_SYS_INT_EN 0x0762 1604#define regVCN_UMSCH_SYS_INT_EN_BASE_IDX 1 1605#define regVCN_UMSCH_SYS_INT_STATUS 0x0763 1606#define regVCN_UMSCH_SYS_INT_STATUS_BASE_IDX 1 1607#define regVCN_UMSCH_SYS_INT_ACK 0x0764 1608#define regVCN_UMSCH_SYS_INT_ACK_BASE_IDX 1 1609#define regVCN_UMSCH_SYS_INT_SRC 0x0765 1610#define regVCN_UMSCH_SYS_INT_SRC_BASE_IDX 1 1611#define regVCN_UMSCH_IH_CTX_CTRL 0x0766 1612#define regVCN_UMSCH_IH_CTX_CTRL_BASE_IDX 1 1613#define regVCN_UMSCH_CGC_CTRL 0x0767 1614#define regVCN_UMSCH_CGC_CTRL_BASE_IDX 1 1615#define regVCN_UMSCH_CGC_STATUS 0x0768 1616#define regVCN_UMSCH_CGC_STATUS_BASE_IDX 1 1617#define regVCN_UMSCH_CGC_MEM_CTRL 0x0769 1618#define regVCN_UMSCH_CGC_MEM_CTRL_BASE_IDX 1 1619#define regUVD_INTERNAL_REG_VIOLATION_8 0x076a 1620#define regUVD_INTERNAL_REG_VIOLATION_8_BASE_IDX 1 1621#define regUVD_UMSCH_FORCE 0x076b 1622#define regUVD_UMSCH_FORCE_BASE_IDX 1 1623#define regUVD_UMSCH_DEBUG_INDEX 0x076c 1624#define regUVD_UMSCH_DEBUG_INDEX_BASE_IDX 1 1625#define regUVD_UMSCH_DEBUG_DATA_LO 0x076d 1626#define regUVD_UMSCH_DEBUG_DATA_LO_BASE_IDX 1 1627#define regUVD_UMSCH_DEBUG_DATA_HI 0x076e 1628#define regUVD_UMSCH_DEBUG_DATA_HI_BASE_IDX 1 1629#define regUVD_UMSCH_DEBUG_UTCL2_TCIU_IF 0x076f 1630#define regUVD_UMSCH_DEBUG_UTCL2_TCIU_IF_BASE_IDX 1 1631#define regUMSCH_MES_RESET_CTRL 0x0770 1632#define regUMSCH_MES_RESET_CTRL_BASE_IDX 1 1633 1634#define regVCN_MES_PRGRM_CNTR_START 0x0780 1635#define regVCN_MES_PRGRM_CNTR_START_BASE_IDX 1 1636#define regVCN_MES_INTR_ROUTINE_START 0x0781 1637#define regVCN_MES_INTR_ROUTINE_START_BASE_IDX 1 1638#define regVCN_MES_MTVEC_LO 0x0781 1639#define regVCN_MES_MTVEC_LO_BASE_IDX 1 1640#define regVCN_MES_INTR_ROUTINE_START_HI 0x0782 1641#define regVCN_MES_INTR_ROUTINE_START_HI_BASE_IDX 1 1642#define regVCN_MES_MTVEC_HI 0x0782 1643#define regVCN_MES_MTVEC_HI_BASE_IDX 1 1644#define regVCN_MES_CNTL 0x0787 1645#define regVCN_MES_CNTL_BASE_IDX 1 1646#define regVCN_MES_PIPE_PRIORITY_CNTS 0x0788 1647#define regVCN_MES_PIPE_PRIORITY_CNTS_BASE_IDX 1 1648#define regVCN_MES_PIPE0_PRIORITY 0x0789 1649#define regVCN_MES_PIPE0_PRIORITY_BASE_IDX 1 1650#define regVCN_MES_PIPE1_PRIORITY 0x078a 1651#define regVCN_MES_PIPE1_PRIORITY_BASE_IDX 1 1652#define regVCN_MES_PIPE2_PRIORITY 0x078b 1653#define regVCN_MES_PIPE2_PRIORITY_BASE_IDX 1 1654#define regVCN_MES_PIPE3_PRIORITY 0x078c 1655#define regVCN_MES_PIPE3_PRIORITY_BASE_IDX 1 1656#define regVCN_MES_HEADER_DUMP 0x078d 1657#define regVCN_MES_HEADER_DUMP_BASE_IDX 1 1658#define regVCN_MES_MIE_LO 0x078e 1659#define regVCN_MES_MIE_LO_BASE_IDX 1 1660#define regVCN_MES_MIE_HI 0x078f 1661#define regVCN_MES_MIE_HI_BASE_IDX 1 1662#define regVCN_MES_INTERRUPT 0x0790 1663#define regVCN_MES_INTERRUPT_BASE_IDX 1 1664#define regVCN_MES_SCRATCH_INDEX 0x0791 1665#define regVCN_MES_SCRATCH_INDEX_BASE_IDX 1 1666#define regVCN_MES_SCRATCH_DATA 0x0792 1667#define regVCN_MES_SCRATCH_DATA_BASE_IDX 1 1668#define regVCN_MES_INSTR_PNTR 0x0793 1669#define regVCN_MES_INSTR_PNTR_BASE_IDX 1 1670#define regVCN_MES_MSCRATCH_HI 0x0794 1671#define regVCN_MES_MSCRATCH_HI_BASE_IDX 1 1672#define regVCN_MES_MSCRATCH_LO 0x0795 1673#define regVCN_MES_MSCRATCH_LO_BASE_IDX 1 1674#define regVCN_MES_MSTATUS_LO 0x0796 1675#define regVCN_MES_MSTATUS_LO_BASE_IDX 1 1676#define regVCN_MES_MSTATUS_HI 0x0797 1677#define regVCN_MES_MSTATUS_HI_BASE_IDX 1 1678#define regVCN_MES_MEPC_LO 0x0798 1679#define regVCN_MES_MEPC_LO_BASE_IDX 1 1680#define regVCN_MES_MEPC_HI 0x0799 1681#define regVCN_MES_MEPC_HI_BASE_IDX 1 1682#define regVCN_MES_MCAUSE_LO 0x079a 1683#define regVCN_MES_MCAUSE_LO_BASE_IDX 1 1684#define regVCN_MES_MCAUSE_HI 0x079b 1685#define regVCN_MES_MCAUSE_HI_BASE_IDX 1 1686#define regVCN_MES_MBADADDR_LO 0x079c 1687#define regVCN_MES_MBADADDR_LO_BASE_IDX 1 1688#define regVCN_MES_MBADADDR_HI 0x079d 1689#define regVCN_MES_MBADADDR_HI_BASE_IDX 1 1690#define regVCN_MES_MIP_LO 0x079e 1691#define regVCN_MES_MIP_LO_BASE_IDX 1 1692#define regVCN_MES_MIP_HI 0x079f 1693#define regVCN_MES_MIP_HI_BASE_IDX 1 1694#define regVCN_MES_IC_OP_CNTL 0x07a0 1695#define regVCN_MES_IC_OP_CNTL_BASE_IDX 1 1696#define regVCN_MES_MCYCLE_LO 0x07a6 1697#define regVCN_MES_MCYCLE_LO_BASE_IDX 1 1698#define regVCN_MES_MCYCLE_HI 0x07a7 1699#define regVCN_MES_MCYCLE_HI_BASE_IDX 1 1700#define regVCN_MES_MTIME_LO 0x07a8 1701#define regVCN_MES_MTIME_LO_BASE_IDX 1 1702#define regVCN_MES_MTIME_HI 0x07a9 1703#define regVCN_MES_MTIME_HI_BASE_IDX 1 1704#define regVCN_MES_MINSTRET_LO 0x07aa 1705#define regVCN_MES_MINSTRET_LO_BASE_IDX 1 1706#define regVCN_MES_MINSTRET_HI 0x07ab 1707#define regVCN_MES_MINSTRET_HI_BASE_IDX 1 1708#define regVCN_MES_MISA_LO 0x07ac 1709#define regVCN_MES_MISA_LO_BASE_IDX 1 1710#define regVCN_MES_MISA_HI 0x07ad 1711#define regVCN_MES_MISA_HI_BASE_IDX 1 1712#define regVCN_MES_MVENDORID_LO 0x07ae 1713#define regVCN_MES_MVENDORID_LO_BASE_IDX 1 1714#define regVCN_MES_MVENDORID_HI 0x07af 1715#define regVCN_MES_MVENDORID_HI_BASE_IDX 1 1716#define regVCN_MES_MARCHID_LO 0x07b0 1717#define regVCN_MES_MARCHID_LO_BASE_IDX 1 1718#define regVCN_MES_MARCHID_HI 0x07b1 1719#define regVCN_MES_MARCHID_HI_BASE_IDX 1 1720#define regVCN_MES_MIMPID_LO 0x07b2 1721#define regVCN_MES_MIMPID_LO_BASE_IDX 1 1722#define regVCN_MES_MIMPID_HI 0x07b3 1723#define regVCN_MES_MIMPID_HI_BASE_IDX 1 1724#define regVCN_MES_MHARTID_LO 0x07b4 1725#define regVCN_MES_MHARTID_LO_BASE_IDX 1 1726#define regVCN_MES_MHARTID_HI 0x07b5 1727#define regVCN_MES_MHARTID_HI_BASE_IDX 1 1728#define regVCN_MES_DC_BASE_CNTL 0x07b6 1729#define regVCN_MES_DC_BASE_CNTL_BASE_IDX 1 1730#define regVCN_MES_DC_OP_CNTL 0x07b7 1731#define regVCN_MES_DC_OP_CNTL_BASE_IDX 1 1732#define regVCN_MES_MTIMECMP_LO 0x07b8 1733#define regVCN_MES_MTIMECMP_LO_BASE_IDX 1 1734#define regVCN_MES_MTIMECMP_HI 0x07b9 1735#define regVCN_MES_MTIMECMP_HI_BASE_IDX 1 1736#define regVCN_MES_DEBUG_INTERRUPT_INSTR_PNTR 0x07c2 1737#define regVCN_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX 1 1738#define regVCN_MES_GP0_LO 0x07c3 1739#define regVCN_MES_GP0_LO_BASE_IDX 1 1740#define regVCN_MES_GP0_HI 0x07c4 1741#define regVCN_MES_GP0_HI_BASE_IDX 1 1742#define regVCN_MES_GP1_LO 0x07c5 1743#define regVCN_MES_GP1_LO_BASE_IDX 1 1744#define regVCN_MES_GP1_HI 0x07c6 1745#define regVCN_MES_GP1_HI_BASE_IDX 1 1746#define regVCN_MES_GP2_LO 0x07c7 1747#define regVCN_MES_GP2_LO_BASE_IDX 1 1748#define regVCN_MES_GP2_HI 0x07c8 1749#define regVCN_MES_GP2_HI_BASE_IDX 1 1750#define regVCN_MES_GP3_LO 0x07c9 1751#define regVCN_MES_GP3_LO_BASE_IDX 1 1752#define regVCN_MES_GP3_HI 0x07ca 1753#define regVCN_MES_GP3_HI_BASE_IDX 1 1754#define regVCN_MES_GP4_LO 0x07cb 1755#define regVCN_MES_GP4_LO_BASE_IDX 1 1756#define regVCN_MES_GP4_HI 0x07cc 1757#define regVCN_MES_GP4_HI_BASE_IDX 1 1758#define regVCN_MES_GP5_LO 0x07cd 1759#define regVCN_MES_GP5_LO_BASE_IDX 1 1760#define regVCN_MES_GP5_HI 0x07ce 1761#define regVCN_MES_GP5_HI_BASE_IDX 1 1762#define regVCN_MES_GP6_LO 0x07cf 1763#define regVCN_MES_GP6_LO_BASE_IDX 1 1764#define regVCN_MES_GP6_HI 0x07d0 1765#define regVCN_MES_GP6_HI_BASE_IDX 1 1766#define regVCN_MES_GP7_LO 0x07d1 1767#define regVCN_MES_GP7_LO_BASE_IDX 1 1768#define regVCN_MES_GP7_HI 0x07d2 1769#define regVCN_MES_GP7_HI_BASE_IDX 1 1770#define regVCN_MES_GP8_LO 0x07d3 1771#define regVCN_MES_GP8_LO_BASE_IDX 1 1772#define regVCN_MES_GP8_HI 0x07d4 1773#define regVCN_MES_GP8_HI_BASE_IDX 1 1774#define regVCN_MES_GP9_LO 0x07d5 1775#define regVCN_MES_GP9_LO_BASE_IDX 1 1776#define regVCN_MES_GP9_HI 0x07d6 1777#define regVCN_MES_GP9_HI_BASE_IDX 1 1778#define regVCN_MES_DM_INDEX_ADDR 0x0800 1779#define regVCN_MES_DM_INDEX_ADDR_BASE_IDX 1 1780#define regVCN_MES_DM_INDEX_DATA 0x0801 1781#define regVCN_MES_DM_INDEX_DATA_BASE_IDX 1 1782#define regVCN_MES_DBG_FROM_RST 0x0802 1783#define regVCN_MES_DBG_FROM_RST_BASE_IDX 1 1784#define regVCN_MES_LOCAL_BASE0_LO 0x0803 1785#define regVCN_MES_LOCAL_BASE0_LO_BASE_IDX 1 1786#define regVCN_MES_LOCAL_BASE0_HI 0x0804 1787#define regVCN_MES_LOCAL_BASE0_HI_BASE_IDX 1 1788#define regVCN_MES_LOCAL_MASK0_LO 0x0805 1789#define regVCN_MES_LOCAL_MASK0_LO_BASE_IDX 1 1790#define regVCN_MES_LOCAL_MASK0_HI 0x0806 1791#define regVCN_MES_LOCAL_MASK0_HI_BASE_IDX 1 1792#define regVCN_MES_LOCAL_APERTURE 0x0807 1793#define regVCN_MES_LOCAL_APERTURE_BASE_IDX 1 1794#define regVCN_MES_LOCAL_INSTR_BASE_LO 0x0808 1795#define regVCN_MES_LOCAL_INSTR_BASE_LO_BASE_IDX 1 1796#define regVCN_MES_LOCAL_INSTR_BASE_HI 0x0809 1797#define regVCN_MES_LOCAL_INSTR_BASE_HI_BASE_IDX 1 1798#define regVCN_MES_LOCAL_INSTR_MASK_LO 0x080a 1799#define regVCN_MES_LOCAL_INSTR_MASK_LO_BASE_IDX 1 1800#define regVCN_MES_LOCAL_INSTR_MASK_HI 0x080b 1801#define regVCN_MES_LOCAL_INSTR_MASK_HI_BASE_IDX 1 1802#define regVCN_MES_LOCAL_INSTR_APERTURE 0x080c 1803#define regVCN_MES_LOCAL_INSTR_APERTURE_BASE_IDX 1 1804#define regVCN_MES_LOCAL_SCRATCH_APERTURE 0x080d 1805#define regVCN_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 1806#define regVCN_MES_LOCAL_SCRATCH_BASE_LO 0x080e 1807#define regVCN_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 1808#define regVCN_MES_LOCAL_SCRATCH_BASE_HI 0x080f 1809#define regVCN_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 1810#define regVCN_MES_PERFCOUNT_CNTL 0x0819 1811#define regVCN_MES_PERFCOUNT_CNTL_BASE_IDX 1 1812#define regVCN_MES_PENDING_INTERRUPT 0x081a 1813#define regVCN_MES_PENDING_INTERRUPT_BASE_IDX 1 1814#define regVCN_MES_PRIV_LEVEL 0x081b 1815#define regVCN_MES_PRIV_LEVEL_BASE_IDX 1 1816#define regVCN_MES_PRIV_LEVEL_VIOLATION_STATUS 0x081c 1817#define regVCN_MES_PRIV_LEVEL_VIOLATION_STATUS_BASE_IDX 1 1818#define regVCN_MES_PRGRM_CNTR_START_HI 0x081d 1819#define regVCN_MES_PRGRM_CNTR_START_HI_BASE_IDX 1 1820#define regVCN_MES_DEBUG_INTERRUPT_INSTR_PNTR_HI 0x081e 1821#define regVCN_MES_DEBUG_INTERRUPT_INSTR_PNTR_HI_BASE_IDX 1 1822#define regVCN_MES_INTERRUPT_DATA_16 0x081f 1823#define regVCN_MES_INTERRUPT_DATA_16_BASE_IDX 1 1824#define regVCN_MES_INTERRUPT_DATA_17 0x0820 1825#define regVCN_MES_INTERRUPT_DATA_17_BASE_IDX 1 1826#define regVCN_MES_INTERRUPT_DATA_18 0x0821 1827#define regVCN_MES_INTERRUPT_DATA_18_BASE_IDX 1 1828#define regVCN_MES_INTERRUPT_DATA_19 0x0822 1829#define regVCN_MES_INTERRUPT_DATA_19_BASE_IDX 1 1830#define regVCN_MES_INTERRUPT_DATA_20 0x0823 1831#define regVCN_MES_INTERRUPT_DATA_20_BASE_IDX 1 1832#define regVCN_MES_INTERRUPT_DATA_21 0x0824 1833#define regVCN_MES_INTERRUPT_DATA_21_BASE_IDX 1 1834#define regVCN_MES_INTERRUPT_DATA_22 0x0825 1835#define regVCN_MES_INTERRUPT_DATA_22_BASE_IDX 1 1836#define regVCN_MES_INTERRUPT_DATA_23 0x0826 1837#define regVCN_MES_INTERRUPT_DATA_23_BASE_IDX 1 1838#define regVCN_MES_INTERRUPT_DATA_24 0x0827 1839#define regVCN_MES_INTERRUPT_DATA_24_BASE_IDX 1 1840#define regVCN_MES_INTERRUPT_DATA_25 0x0828 1841#define regVCN_MES_INTERRUPT_DATA_25_BASE_IDX 1 1842#define regVCN_MES_INTERRUPT_DATA_26 0x0829 1843#define regVCN_MES_INTERRUPT_DATA_26_BASE_IDX 1 1844#define regVCN_MES_INTERRUPT_DATA_27 0x082a 1845#define regVCN_MES_INTERRUPT_DATA_27_BASE_IDX 1 1846#define regVCN_MES_INTERRUPT_DATA_28 0x082b 1847#define regVCN_MES_INTERRUPT_DATA_28_BASE_IDX 1 1848#define regVCN_MES_INTERRUPT_DATA_29 0x082c 1849#define regVCN_MES_INTERRUPT_DATA_29_BASE_IDX 1 1850#define regVCN_MES_INTERRUPT_DATA_30 0x082d 1851#define regVCN_MES_INTERRUPT_DATA_30_BASE_IDX 1 1852#define regVCN_MES_INTERRUPT_DATA_31 0x082e 1853#define regVCN_MES_INTERRUPT_DATA_31_BASE_IDX 1 1854#define regVCN_MES_DC_APERTURE0_BASE 0x082f 1855#define regVCN_MES_DC_APERTURE0_BASE_BASE_IDX 1 1856#define regVCN_MES_DC_APERTURE0_MASK 0x0830 1857#define regVCN_MES_DC_APERTURE0_MASK_BASE_IDX 1 1858#define regVCN_MES_DC_APERTURE0_CNTL 0x0831 1859#define regVCN_MES_DC_APERTURE0_CNTL_BASE_IDX 1 1860#define regVCN_MES_DC_APERTURE1_BASE 0x0832 1861#define regVCN_MES_DC_APERTURE1_BASE_BASE_IDX 1 1862#define regVCN_MES_DC_APERTURE1_MASK 0x0833 1863#define regVCN_MES_DC_APERTURE1_MASK_BASE_IDX 1 1864#define regVCN_MES_DC_APERTURE1_CNTL 0x0834 1865#define regVCN_MES_DC_APERTURE1_CNTL_BASE_IDX 1 1866#define regVCN_MES_DC_APERTURE2_BASE 0x0835 1867#define regVCN_MES_DC_APERTURE2_BASE_BASE_IDX 1 1868#define regVCN_MES_DC_APERTURE2_MASK 0x0836 1869#define regVCN_MES_DC_APERTURE2_MASK_BASE_IDX 1 1870#define regVCN_MES_DC_APERTURE2_CNTL 0x0837 1871#define regVCN_MES_DC_APERTURE2_CNTL_BASE_IDX 1 1872#define regVCN_MES_DC_APERTURE3_BASE 0x0838 1873#define regVCN_MES_DC_APERTURE3_BASE_BASE_IDX 1 1874#define regVCN_MES_DC_APERTURE3_MASK 0x0839 1875#define regVCN_MES_DC_APERTURE3_MASK_BASE_IDX 1 1876#define regVCN_MES_DC_APERTURE3_CNTL 0x083a 1877#define regVCN_MES_DC_APERTURE3_CNTL_BASE_IDX 1 1878#define regVCN_MES_DC_APERTURE4_BASE 0x083b 1879#define regVCN_MES_DC_APERTURE4_BASE_BASE_IDX 1 1880#define regVCN_MES_DC_APERTURE4_MASK 0x083c 1881#define regVCN_MES_DC_APERTURE4_MASK_BASE_IDX 1 1882#define regVCN_MES_DC_APERTURE4_CNTL 0x083d 1883#define regVCN_MES_DC_APERTURE4_CNTL_BASE_IDX 1 1884#define regVCN_MES_DC_APERTURE5_BASE 0x083e 1885#define regVCN_MES_DC_APERTURE5_BASE_BASE_IDX 1 1886#define regVCN_MES_DC_APERTURE5_MASK 0x083f 1887#define regVCN_MES_DC_APERTURE5_MASK_BASE_IDX 1 1888#define regVCN_MES_DC_APERTURE5_CNTL 0x0840 1889#define regVCN_MES_DC_APERTURE5_CNTL_BASE_IDX 1 1890#define regVCN_MES_DC_APERTURE6_BASE 0x0841 1891#define regVCN_MES_DC_APERTURE6_BASE_BASE_IDX 1 1892#define regVCN_MES_DC_APERTURE6_MASK 0x0842 1893#define regVCN_MES_DC_APERTURE6_MASK_BASE_IDX 1 1894#define regVCN_MES_DC_APERTURE6_CNTL 0x0843 1895#define regVCN_MES_DC_APERTURE6_CNTL_BASE_IDX 1 1896#define regVCN_MES_DC_APERTURE7_BASE 0x0844 1897#define regVCN_MES_DC_APERTURE7_BASE_BASE_IDX 1 1898#define regVCN_MES_DC_APERTURE7_MASK 0x0845 1899#define regVCN_MES_DC_APERTURE7_MASK_BASE_IDX 1 1900#define regVCN_MES_DC_APERTURE7_CNTL 0x0846 1901#define regVCN_MES_DC_APERTURE7_CNTL_BASE_IDX 1 1902#define regVCN_MES_DC_APERTURE8_BASE 0x0847 1903#define regVCN_MES_DC_APERTURE8_BASE_BASE_IDX 1 1904#define regVCN_MES_DC_APERTURE8_MASK 0x0848 1905#define regVCN_MES_DC_APERTURE8_MASK_BASE_IDX 1 1906#define regVCN_MES_DC_APERTURE8_CNTL 0x0849 1907#define regVCN_MES_DC_APERTURE8_CNTL_BASE_IDX 1 1908#define regVCN_MES_DC_APERTURE9_BASE 0x084a 1909#define regVCN_MES_DC_APERTURE9_BASE_BASE_IDX 1 1910#define regVCN_MES_DC_APERTURE9_MASK 0x084b 1911#define regVCN_MES_DC_APERTURE9_MASK_BASE_IDX 1 1912#define regVCN_MES_DC_APERTURE9_CNTL 0x084c 1913#define regVCN_MES_DC_APERTURE9_CNTL_BASE_IDX 1 1914#define regVCN_MES_DC_APERTURE10_BASE 0x084d 1915#define regVCN_MES_DC_APERTURE10_BASE_BASE_IDX 1 1916#define regVCN_MES_DC_APERTURE10_MASK 0x084e 1917#define regVCN_MES_DC_APERTURE10_MASK_BASE_IDX 1 1918#define regVCN_MES_DC_APERTURE10_CNTL 0x084f 1919#define regVCN_MES_DC_APERTURE10_CNTL_BASE_IDX 1 1920#define regVCN_MES_DC_APERTURE11_BASE 0x0850 1921#define regVCN_MES_DC_APERTURE11_BASE_BASE_IDX 1 1922#define regVCN_MES_DC_APERTURE11_MASK 0x0851 1923#define regVCN_MES_DC_APERTURE11_MASK_BASE_IDX 1 1924#define regVCN_MES_DC_APERTURE11_CNTL 0x0852 1925#define regVCN_MES_DC_APERTURE11_CNTL_BASE_IDX 1 1926#define regVCN_MES_DC_APERTURE12_BASE 0x0853 1927#define regVCN_MES_DC_APERTURE12_BASE_BASE_IDX 1 1928#define regVCN_MES_DC_APERTURE12_MASK 0x0854 1929#define regVCN_MES_DC_APERTURE12_MASK_BASE_IDX 1 1930#define regVCN_MES_DC_APERTURE12_CNTL 0x0855 1931#define regVCN_MES_DC_APERTURE12_CNTL_BASE_IDX 1 1932#define regVCN_MES_DC_APERTURE13_BASE 0x0856 1933#define regVCN_MES_DC_APERTURE13_BASE_BASE_IDX 1 1934#define regVCN_MES_DC_APERTURE13_MASK 0x0857 1935#define regVCN_MES_DC_APERTURE13_MASK_BASE_IDX 1 1936#define regVCN_MES_DC_APERTURE13_CNTL 0x0858 1937#define regVCN_MES_DC_APERTURE13_CNTL_BASE_IDX 1 1938#define regVCN_MES_DC_APERTURE14_BASE 0x0859 1939#define regVCN_MES_DC_APERTURE14_BASE_BASE_IDX 1 1940#define regVCN_MES_DC_APERTURE14_MASK 0x085a 1941#define regVCN_MES_DC_APERTURE14_MASK_BASE_IDX 1 1942#define regVCN_MES_DC_APERTURE14_CNTL 0x085b 1943#define regVCN_MES_DC_APERTURE14_CNTL_BASE_IDX 1 1944#define regVCN_MES_DC_APERTURE15_BASE 0x085c 1945#define regVCN_MES_DC_APERTURE15_BASE_BASE_IDX 1 1946#define regVCN_MES_DC_APERTURE15_MASK 0x085d 1947#define regVCN_MES_DC_APERTURE15_MASK_BASE_IDX 1 1948#define regVCN_MES_DC_APERTURE15_CNTL 0x085e 1949#define regVCN_MES_DC_APERTURE15_CNTL_BASE_IDX 1 1950 1951#define regVCN_HYP_ME1_PIPE0_VMID_CNTL 0x0890 1952#define regVCN_HYP_ME1_PIPE0_VMID_CNTL_BASE_IDX 1 1953#define regVCN_HYP_ME1_PIPE1_VMID_CNTL 0x0891 1954#define regVCN_HYP_ME1_PIPE1_VMID_CNTL_BASE_IDX 1 1955#define regVCN_MES_IC_BASE_LO 0x08d0 1956#define regVCN_MES_IC_BASE_LO_BASE_IDX 1 1957#define regVCN_MES_MIBASE_LO 0x08d0 1958#define regVCN_MES_MIBASE_LO_BASE_IDX 1 1959#define regVCN_MES_IC_BASE_HI 0x08d1 1960#define regVCN_MES_IC_BASE_HI_BASE_IDX 1 1961#define regVCN_MES_MIBASE_HI 0x08d1 1962#define regVCN_MES_MIBASE_HI_BASE_IDX 1 1963#define regVCN_MES_IC_BASE_CNTL 0x08d2 1964#define regVCN_MES_IC_BASE_CNTL_BASE_IDX 1 1965#define regVCN_MES_DC_BASE_LO 0x08d4 1966#define regVCN_MES_DC_BASE_LO_BASE_IDX 1 1967#define regVCN_MES_MDBASE_LO 0x08d4 1968#define regVCN_MES_MDBASE_LO_BASE_IDX 1 1969#define regVCN_MES_DC_BASE_HI 0x08d5 1970#define regVCN_MES_DC_BASE_HI_BASE_IDX 1 1971#define regVCN_MES_MDBASE_HI 0x08d5 1972#define regVCN_MES_MDBASE_HI_BASE_IDX 1 1973#define regVCN_MES_MIBOUND_LO 0x08db 1974#define regVCN_MES_MIBOUND_LO_BASE_IDX 1 1975#define regVCN_MES_MIBOUND_HI 0x08dc 1976#define regVCN_MES_MIBOUND_HI_BASE_IDX 1 1977#define regVCN_MES_MDBOUND_LO 0x08dd 1978#define regVCN_MES_MDBOUND_LO_BASE_IDX 1 1979#define regVCN_MES_MDBOUND_HI 0x08de 1980#define regVCN_MES_MDBOUND_HI_BASE_IDX 1 1981 1982// addressBlock: uvdctxind 1983// base address: 0x0 1984#define ixUVD_CGC_MEM_CTRL 0x0000 1985#define ixUVD_CGC_CTRL2 0x0001 1986#define ixUVD_CGC_MEM_DS_CTRL 0x0002 1987#define ixUVD_CGC_MEM_SD_CTRL 0x0003 1988#define ixUVD_SW_SCRATCH_00 0x0004 1989#define ixUVD_SW_SCRATCH_01 0x0005 1990#define ixUVD_SW_SCRATCH_02 0x0006 1991#define ixUVD_SW_SCRATCH_03 0x0007 1992#define ixUVD_SW_SCRATCH_04 0x0008 1993#define ixUVD_SW_SCRATCH_05 0x0009 1994#define ixUVD_SW_SCRATCH_06 0x000a 1995#define ixUVD_SW_SCRATCH_07 0x000b 1996#define ixUVD_SW_SCRATCH_08 0x000c 1997#define ixUVD_SW_SCRATCH_09 0x000d 1998#define ixUVD_SW_SCRATCH_10 0x000e 1999#define ixUVD_SW_SCRATCH_11 0x000f 2000#define ixUVD_SW_SCRATCH_12 0x0010 2001#define ixUVD_SW_SCRATCH_13 0x0011 2002#define ixUVD_SW_SCRATCH_14 0x0012 2003#define ixUVD_SW_SCRATCH_15 0x0013 2004#define ixUVD_IH_SEM_CTRL 0x001e 2005 2006 2007// addressBlock: lmi_adp_indirect 2008// base address: 0x0 2009#define ixUVD_LMI_CRC0 0x0000 2010#define ixUVD_LMI_CRC1 0x0001 2011#define ixUVD_LMI_CRC2 0x0002 2012#define ixUVD_LMI_CRC3 0x0003 2013#define ixUVD_LMI_CRC10 0x000a 2014#define ixUVD_LMI_CRC11 0x000b 2015#define ixUVD_LMI_CRC12 0x000c 2016#define ixUVD_LMI_CRC13 0x000d 2017#define ixUVD_LMI_CRC14 0x000e 2018#define ixUVD_LMI_CRC15 0x000f 2019#define ixUVD_LMI_SWAP_CNTL2 0x0029 2020#define ixUVD_MEMCHECK_SYS_INT_EN 0x0134 2021#define ixUVD_MEMCHECK_SYS_INT_STAT 0x0135 2022#define ixUVD_MEMCHECK_SYS_INT_ACK 0x0136 2023#define ixUVD_MEMCHECK_VCPU_INT_EN 0x0137 2024#define ixUVD_MEMCHECK_VCPU_INT_STAT 0x0138 2025#define ixUVD_MEMCHECK_VCPU_INT_ACK 0x0139 2026#define ixUVD_MEMCHECK2_SYS_INT_STAT 0x0140 2027#define ixUVD_MEMCHECK2_SYS_INT_ACK 0x0141 2028#define ixUVD_MEMCHECK2_VCPU_INT_STAT 0x0142 2029#define ixUVD_MEMCHECK2_VCPU_INT_ACK 0x0143 2030 2031 2032#endif
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