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vcn_2_5_offset.h
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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h
1/* 2 * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 22#ifndef _vcn_2_5_OFFSET_HEADER 23#define _vcn_2_5_OFFSET_HEADER 24 25// addressBlock: uvd0_mmsch_dec 26// base address: 0x1e000 27#define mmMMSCH_VF_VMID 0x000b 28#define mmMMSCH_VF_VMID_BASE_IDX 0 29#define mmMMSCH_VF_CTX_ADDR_LO 0x000c 30#define mmMMSCH_VF_CTX_ADDR_LO_BASE_IDX 0 31#define mmMMSCH_VF_CTX_ADDR_HI 0x000d 32#define mmMMSCH_VF_CTX_ADDR_HI_BASE_IDX 0 33#define mmMMSCH_VF_CTX_SIZE 0x000e 34#define mmMMSCH_VF_CTX_SIZE_BASE_IDX 0 35#define mmMMSCH_VF_MAILBOX_HOST 0x0012 36#define mmMMSCH_VF_MAILBOX_HOST_BASE_IDX 0 37#define mmMMSCH_VF_MAILBOX_RESP 0x0013 38#define mmMMSCH_VF_MAILBOX_RESP_BASE_IDX 0 39 40 41// addressBlock: uvd0_jpegnpdec 42// base address: 0x1e200 43#define mmUVD_JPEG_CNTL 0x0080 44#define mmUVD_JPEG_CNTL_BASE_IDX 0 45#define mmUVD_JPEG_RB_BASE 0x0081 46#define mmUVD_JPEG_RB_BASE_BASE_IDX 0 47#define mmUVD_JPEG_RB_WPTR 0x0082 48#define mmUVD_JPEG_RB_WPTR_BASE_IDX 0 49#define mmUVD_JPEG_RB_RPTR 0x0083 50#define mmUVD_JPEG_RB_RPTR_BASE_IDX 0 51#define mmUVD_JPEG_RB_SIZE 0x0084 52#define mmUVD_JPEG_RB_SIZE_BASE_IDX 0 53#define mmUVD_JPEG_DEC_SCRATCH0 0x0089 54#define mmUVD_JPEG_DEC_SCRATCH0_BASE_IDX 0 55#define mmUVD_JPEG_INT_EN 0x008a 56#define mmUVD_JPEG_INT_EN_BASE_IDX 0 57#define mmUVD_JPEG_INT_STAT 0x008b 58#define mmUVD_JPEG_INT_STAT_BASE_IDX 0 59#define mmUVD_JPEG_PITCH 0x009f 60#define mmUVD_JPEG_PITCH_BASE_IDX 0 61#define mmUVD_JPEG_UV_PITCH 0x00a0 62#define mmUVD_JPEG_UV_PITCH_BASE_IDX 0 63#define mmJPEG_DEC_Y_GFX8_TILING_SURFACE 0x00a1 64#define mmJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX 0 65#define mmJPEG_DEC_UV_GFX8_TILING_SURFACE 0x00a2 66#define mmJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX 0 67#define mmJPEG_DEC_GFX8_ADDR_CONFIG 0x00a3 68#define mmJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX 0 69#define mmJPEG_DEC_Y_GFX10_TILING_SURFACE 0x00a4 70#define mmJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX 0 71#define mmJPEG_DEC_UV_GFX10_TILING_SURFACE 0x00a5 72#define mmJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX 0 73#define mmJPEG_DEC_GFX10_ADDR_CONFIG 0x00a6 74#define mmJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX 0 75#define mmJPEG_DEC_ADDR_MODE 0x00a7 76#define mmJPEG_DEC_ADDR_MODE_BASE_IDX 0 77#define mmUVD_JPEG_GPCOM_CMD 0x00a9 78#define mmUVD_JPEG_GPCOM_CMD_BASE_IDX 0 79#define mmUVD_JPEG_GPCOM_DATA0 0x00aa 80#define mmUVD_JPEG_GPCOM_DATA0_BASE_IDX 0 81#define mmUVD_JPEG_GPCOM_DATA1 0x00ab 82#define mmUVD_JPEG_GPCOM_DATA1_BASE_IDX 0 83#define mmUVD_JPEG_SCRATCH1 0x00ae 84#define mmUVD_JPEG_SCRATCH1_BASE_IDX 0 85#define mmUVD_JPEG_DEC_SOFT_RST 0x00af 86#define mmUVD_JPEG_DEC_SOFT_RST_BASE_IDX 0 87 88 89// addressBlock: uvd0_uvd_jpeg_enc_dec 90// base address: 0x1e300 91#define mmUVD_JPEG_ENC_INT_EN 0x00c1 92#define mmUVD_JPEG_ENC_INT_EN_BASE_IDX 0 93#define mmUVD_JPEG_ENC_INT_STATUS 0x00c2 94#define mmUVD_JPEG_ENC_INT_STATUS_BASE_IDX 0 95#define mmUVD_JPEG_ENC_ENGINE_CNTL 0x00c5 96#define mmUVD_JPEG_ENC_ENGINE_CNTL_BASE_IDX 0 97#define mmUVD_JPEG_ENC_SCRATCH1 0x00ce 98#define mmUVD_JPEG_ENC_SCRATCH1_BASE_IDX 0 99 100 101// addressBlock: uvd0_uvd_jpeg_enc_sclk_dec 102// base address: 0x1e380 103#define mmUVD_JPEG_ENC_STATUS 0x00e5 104#define mmUVD_JPEG_ENC_STATUS_BASE_IDX 0 105#define mmUVD_JPEG_ENC_PITCH 0x00e6 106#define mmUVD_JPEG_ENC_PITCH_BASE_IDX 0 107#define mmUVD_JPEG_ENC_LUMA_BASE 0x00e7 108#define mmUVD_JPEG_ENC_LUMA_BASE_BASE_IDX 0 109#define mmUVD_JPEG_ENC_CHROMAU_BASE 0x00e8 110#define mmUVD_JPEG_ENC_CHROMAU_BASE_BASE_IDX 0 111#define mmUVD_JPEG_ENC_CHROMAV_BASE 0x00e9 112#define mmUVD_JPEG_ENC_CHROMAV_BASE_BASE_IDX 0 113#define mmJPEG_ENC_Y_GFX10_TILING_SURFACE 0x00ea 114#define mmJPEG_ENC_Y_GFX10_TILING_SURFACE_BASE_IDX 0 115#define mmJPEG_ENC_UV_GFX10_TILING_SURFACE 0x00eb 116#define mmJPEG_ENC_UV_GFX10_TILING_SURFACE_BASE_IDX 0 117#define mmJPEG_ENC_GFX10_ADDR_CONFIG 0x00ec 118#define mmJPEG_ENC_GFX10_ADDR_CONFIG_BASE_IDX 0 119#define mmJPEG_ENC_ADDR_MODE 0x00ed 120#define mmJPEG_ENC_ADDR_MODE_BASE_IDX 0 121#define mmUVD_JPEG_ENC_GPCOM_CMD 0x00ee 122#define mmUVD_JPEG_ENC_GPCOM_CMD_BASE_IDX 0 123#define mmUVD_JPEG_ENC_GPCOM_DATA0 0x00ef 124#define mmUVD_JPEG_ENC_GPCOM_DATA0_BASE_IDX 0 125#define mmUVD_JPEG_ENC_GPCOM_DATA1 0x00f0 126#define mmUVD_JPEG_ENC_GPCOM_DATA1_BASE_IDX 0 127#define mmUVD_JPEG_ENC_CGC_CNTL 0x00f5 128#define mmUVD_JPEG_ENC_CGC_CNTL_BASE_IDX 0 129#define mmUVD_JPEG_ENC_SCRATCH0 0x00f6 130#define mmUVD_JPEG_ENC_SCRATCH0_BASE_IDX 0 131#define mmUVD_JPEG_ENC_SOFT_RST 0x00f7 132#define mmUVD_JPEG_ENC_SOFT_RST_BASE_IDX 0 133 134 135// addressBlock: uvd0_uvd_jrbc_dec 136// base address: 0x1e400 137#define mmUVD_JRBC_RB_WPTR 0x0100 138#define mmUVD_JRBC_RB_WPTR_BASE_IDX 0 139#define mmUVD_JRBC_RB_CNTL 0x0101 140#define mmUVD_JRBC_RB_CNTL_BASE_IDX 0 141#define mmUVD_JRBC_IB_SIZE 0x0102 142#define mmUVD_JRBC_IB_SIZE_BASE_IDX 0 143#define mmUVD_JRBC_URGENT_CNTL 0x0103 144#define mmUVD_JRBC_URGENT_CNTL_BASE_IDX 0 145#define mmUVD_JRBC_RB_REF_DATA 0x0104 146#define mmUVD_JRBC_RB_REF_DATA_BASE_IDX 0 147#define mmUVD_JRBC_RB_COND_RD_TIMER 0x0105 148#define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0 149#define mmUVD_JRBC_SOFT_RESET 0x0108 150#define mmUVD_JRBC_SOFT_RESET_BASE_IDX 0 151#define mmUVD_JRBC_STATUS 0x0109 152#define mmUVD_JRBC_STATUS_BASE_IDX 0 153#define mmUVD_JRBC_RB_RPTR 0x010a 154#define mmUVD_JRBC_RB_RPTR_BASE_IDX 0 155#define mmUVD_JRBC_RB_BUF_STATUS 0x010b 156#define mmUVD_JRBC_RB_BUF_STATUS_BASE_IDX 0 157#define mmUVD_JRBC_IB_BUF_STATUS 0x010c 158#define mmUVD_JRBC_IB_BUF_STATUS_BASE_IDX 0 159#define mmUVD_JRBC_IB_SIZE_UPDATE 0x010d 160#define mmUVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 0 161#define mmUVD_JRBC_IB_COND_RD_TIMER 0x010e 162#define mmUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 0 163#define mmUVD_JRBC_IB_REF_DATA 0x010f 164#define mmUVD_JRBC_IB_REF_DATA_BASE_IDX 0 165#define mmUVD_JPEG_PREEMPT_CMD 0x0110 166#define mmUVD_JPEG_PREEMPT_CMD_BASE_IDX 0 167#define mmUVD_JPEG_PREEMPT_FENCE_DATA0 0x0111 168#define mmUVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 0 169#define mmUVD_JPEG_PREEMPT_FENCE_DATA1 0x0112 170#define mmUVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 0 171#define mmUVD_JRBC_RB_SIZE 0x0113 172#define mmUVD_JRBC_RB_SIZE_BASE_IDX 0 173#define mmUVD_JRBC_SCRATCH0 0x0114 174#define mmUVD_JRBC_SCRATCH0_BASE_IDX 0 175 176 177// addressBlock: uvd0_uvd_jrbc_enc_dec 178// base address: 0x1e480 179#define mmUVD_JRBC_ENC_RB_WPTR 0x0120 180#define mmUVD_JRBC_ENC_RB_WPTR_BASE_IDX 0 181#define mmUVD_JRBC_ENC_RB_CNTL 0x0121 182#define mmUVD_JRBC_ENC_RB_CNTL_BASE_IDX 0 183#define mmUVD_JRBC_ENC_IB_SIZE 0x0122 184#define mmUVD_JRBC_ENC_IB_SIZE_BASE_IDX 0 185#define mmUVD_JRBC_ENC_URGENT_CNTL 0x0123 186#define mmUVD_JRBC_ENC_URGENT_CNTL_BASE_IDX 0 187#define mmUVD_JRBC_ENC_RB_REF_DATA 0x0124 188#define mmUVD_JRBC_ENC_RB_REF_DATA_BASE_IDX 0 189#define mmUVD_JRBC_ENC_RB_COND_RD_TIMER 0x0125 190#define mmUVD_JRBC_ENC_RB_COND_RD_TIMER_BASE_IDX 0 191#define mmUVD_JRBC_ENC_SOFT_RESET 0x0128 192#define mmUVD_JRBC_ENC_SOFT_RESET_BASE_IDX 0 193#define mmUVD_JRBC_ENC_STATUS 0x0129 194#define mmUVD_JRBC_ENC_STATUS_BASE_IDX 0 195#define mmUVD_JRBC_ENC_RB_RPTR 0x012a 196#define mmUVD_JRBC_ENC_RB_RPTR_BASE_IDX 0 197#define mmUVD_JRBC_ENC_RB_BUF_STATUS 0x012b 198#define mmUVD_JRBC_ENC_RB_BUF_STATUS_BASE_IDX 0 199#define mmUVD_JRBC_ENC_IB_BUF_STATUS 0x012c 200#define mmUVD_JRBC_ENC_IB_BUF_STATUS_BASE_IDX 0 201#define mmUVD_JRBC_ENC_IB_SIZE_UPDATE 0x012d 202#define mmUVD_JRBC_ENC_IB_SIZE_UPDATE_BASE_IDX 0 203#define mmUVD_JRBC_ENC_IB_COND_RD_TIMER 0x012e 204#define mmUVD_JRBC_ENC_IB_COND_RD_TIMER_BASE_IDX 0 205#define mmUVD_JRBC_ENC_IB_REF_DATA 0x012f 206#define mmUVD_JRBC_ENC_IB_REF_DATA_BASE_IDX 0 207#define mmUVD_JPEG_ENC_PREEMPT_CMD 0x0130 208#define mmUVD_JPEG_ENC_PREEMPT_CMD_BASE_IDX 0 209#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0 0x0131 210#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0_BASE_IDX 0 211#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1 0x0132 212#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1_BASE_IDX 0 213#define mmUVD_JRBC_ENC_RB_SIZE 0x0133 214#define mmUVD_JRBC_ENC_RB_SIZE_BASE_IDX 0 215#define mmUVD_JRBC_ENC_SCRATCH0 0x0134 216#define mmUVD_JRBC_ENC_SCRATCH0_BASE_IDX 0 217 218 219// addressBlock: uvd0_uvd_jmi_dec 220// base address: 0x1e500 221#define mmUVD_JMI_CTRL 0x0145 222#define mmUVD_JMI_CTRL_BASE_IDX 0 223#define mmUVD_LMI_JRBC_CTRL 0x0146 224#define mmUVD_LMI_JRBC_CTRL_BASE_IDX 0 225#define mmUVD_LMI_JPEG_CTRL 0x0147 226#define mmUVD_LMI_JPEG_CTRL_BASE_IDX 0 227#define mmUVD_JMI_EJRBC_CTRL 0x0148 228#define mmUVD_JMI_EJRBC_CTRL_BASE_IDX 0 229#define mmUVD_LMI_EJPEG_CTRL 0x0149 230#define mmUVD_LMI_EJPEG_CTRL_BASE_IDX 0 231#define mmUVD_LMI_JRBC_IB_VMID 0x014f 232#define mmUVD_LMI_JRBC_IB_VMID_BASE_IDX 0 233#define mmUVD_LMI_JRBC_RB_VMID 0x0150 234#define mmUVD_LMI_JRBC_RB_VMID_BASE_IDX 0 235#define mmUVD_LMI_JPEG_VMID 0x0151 236#define mmUVD_LMI_JPEG_VMID_BASE_IDX 0 237#define mmUVD_JMI_ENC_JRBC_IB_VMID 0x0152 238#define mmUVD_JMI_ENC_JRBC_IB_VMID_BASE_IDX 0 239#define mmUVD_JMI_ENC_JRBC_RB_VMID 0x0153 240#define mmUVD_JMI_ENC_JRBC_RB_VMID_BASE_IDX 0 241#define mmUVD_JMI_ENC_JPEG_VMID 0x0154 242#define mmUVD_JMI_ENC_JPEG_VMID_BASE_IDX 0 243#define mmUVD_JMI_PERFMON_CTRL 0x015c 244#define mmUVD_JMI_PERFMON_CTRL_BASE_IDX 0 245#define mmUVD_JMI_PERFMON_COUNT_LO 0x015d 246#define mmUVD_JMI_PERFMON_COUNT_LO_BASE_IDX 0 247#define mmUVD_JMI_PERFMON_COUNT_HI 0x015e 248#define mmUVD_JMI_PERFMON_COUNT_HI_BASE_IDX 0 249#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x0160 250#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 0 251#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x0161 252#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 0 253#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0162 254#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 0 255#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0163 256#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 257#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x0164 258#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 259#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x0165 260#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 261#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0166 262#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 263#define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x0167 264#define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 265#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0168 266#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 267#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0169 268#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 269#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x016a 270#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 271#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x016b 272#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 273#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 0x016c 274#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 275#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x016d 276#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 277#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x016e 278#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 279#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x016f 280#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 281#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0170 282#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 283#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0171 284#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 285#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x017a 286#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 287#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x017b 288#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 289#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW 0x017c 290#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 291#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 0x017d 292#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 293#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW 0x017e 294#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 295#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 0x017f 296#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 297#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 0x0180 298#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 299#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x0181 300#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 301#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 0x0182 302#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 303#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x0183 304#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 305#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 0x0184 306#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 307#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x0185 308#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 309#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0186 310#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 311#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0187 312#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 313#define mmUVD_LMI_JPEG_PREEMPT_VMID 0x0188 314#define mmUVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 0 315#define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID 0x0189 316#define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID_BASE_IDX 0 317#define mmUVD_LMI_JPEG2_VMID 0x018a 318#define mmUVD_LMI_JPEG2_VMID_BASE_IDX 0 319#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW 0x018b 320#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW_BASE_IDX 0 321#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 0x018c 322#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH_BASE_IDX 0 323#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 0x018d 324#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW_BASE_IDX 0 325#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 0x018e 326#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 327#define mmUVD_LMI_JPEG_CTRL2 0x018f 328#define mmUVD_LMI_JPEG_CTRL2_BASE_IDX 0 329#define mmUVD_JMI_DEC_SWAP_CNTL 0x0190 330#define mmUVD_JMI_DEC_SWAP_CNTL_BASE_IDX 0 331#define mmUVD_JMI_ENC_SWAP_CNTL 0x0191 332#define mmUVD_JMI_ENC_SWAP_CNTL_BASE_IDX 0 333#define mmUVD_JMI_CNTL 0x0192 334#define mmUVD_JMI_CNTL_BASE_IDX 0 335#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 0x019a 336#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW_BASE_IDX 0 337#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 0x019b 338#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 339#define mmUVD_JMI_DEC_SWAP_CNTL2 0x019c 340#define mmUVD_JMI_DEC_SWAP_CNTL2_BASE_IDX 0 341 342 343// addressBlock: uvd0_uvd_jpeg_common_dec 344// base address: 0x1e700 345#define mmJPEG_SOFT_RESET_STATUS 0x01c0 346#define mmJPEG_SOFT_RESET_STATUS_BASE_IDX 0 347#define mmJPEG_SYS_INT_EN 0x01c1 348#define mmJPEG_SYS_INT_EN_BASE_IDX 0 349#define mmJPEG_SYS_INT_STATUS 0x01c2 350#define mmJPEG_SYS_INT_STATUS_BASE_IDX 0 351#define mmJPEG_SYS_INT_ACK 0x01c3 352#define mmJPEG_SYS_INT_ACK_BASE_IDX 0 353#define mmJPEG_MASTINT_EN 0x01c8 354#define mmJPEG_MASTINT_EN_BASE_IDX 0 355#define mmJPEG_IH_CTRL 0x01c9 356#define mmJPEG_IH_CTRL_BASE_IDX 0 357#define mmJRBBM_ARB_CTRL 0x01cb 358#define mmJRBBM_ARB_CTRL_BASE_IDX 0 359 360 361// addressBlock: uvd0_uvd_jpeg_common_sclk_dec 362// base address: 0x1e780 363#define mmJPEG_CGC_GATE 0x01e0 364#define mmJPEG_CGC_GATE_BASE_IDX 0 365#define mmJPEG_CGC_CTRL 0x01e1 366#define mmJPEG_CGC_CTRL_BASE_IDX 0 367#define mmJPEG_CGC_STATUS 0x01e2 368#define mmJPEG_CGC_STATUS_BASE_IDX 0 369#define mmJPEG_COMN_CGC_MEM_CTRL 0x01e3 370#define mmJPEG_COMN_CGC_MEM_CTRL_BASE_IDX 0 371#define mmJPEG_DEC_CGC_MEM_CTRL 0x01e4 372#define mmJPEG_DEC_CGC_MEM_CTRL_BASE_IDX 0 373#define mmJPEG2_DEC_CGC_MEM_CTRL 0x01e5 374#define mmJPEG2_DEC_CGC_MEM_CTRL_BASE_IDX 0 375#define mmJPEG_ENC_CGC_MEM_CTRL 0x01e6 376#define mmJPEG_ENC_CGC_MEM_CTRL_BASE_IDX 0 377#define mmJPEG_SOFT_RESET2 0x01e7 378#define mmJPEG_SOFT_RESET2_BASE_IDX 0 379#define mmJPEG_PERF_BANK_CONF 0x01e8 380#define mmJPEG_PERF_BANK_CONF_BASE_IDX 0 381#define mmJPEG_PERF_BANK_EVENT_SEL 0x01e9 382#define mmJPEG_PERF_BANK_EVENT_SEL_BASE_IDX 0 383#define mmJPEG_PERF_BANK_COUNT0 0x01ea 384#define mmJPEG_PERF_BANK_COUNT0_BASE_IDX 0 385#define mmJPEG_PERF_BANK_COUNT1 0x01eb 386#define mmJPEG_PERF_BANK_COUNT1_BASE_IDX 0 387#define mmJPEG_PERF_BANK_COUNT2 0x01ec 388#define mmJPEG_PERF_BANK_COUNT2_BASE_IDX 0 389#define mmJPEG_PERF_BANK_COUNT3 0x01ed 390#define mmJPEG_PERF_BANK_COUNT3_BASE_IDX 0 391 392 393// addressBlock: uvd0_uvd_pg_dec 394// base address: 0x1f800 395#define mmUVD_PGFSM_CONFIG 0x0000 396#define mmUVD_PGFSM_CONFIG_BASE_IDX 1 397#define mmUVD_PGFSM_STATUS 0x0001 398#define mmUVD_PGFSM_STATUS_BASE_IDX 1 399#define mmUVD_POWER_STATUS 0x0004 400#define mmUVD_POWER_STATUS_BASE_IDX 1 401#define mmUVD_PG_IND_INDEX 0x0005 402#define mmUVD_PG_IND_INDEX_BASE_IDX 1 403#define mmUVD_PG_IND_DATA 0x0006 404#define mmUVD_PG_IND_DATA_BASE_IDX 1 405#define mmCC_UVD_HARVESTING 0x0007 406#define mmCC_UVD_HARVESTING_BASE_IDX 1 407#define mmUVD_JPEG_POWER_STATUS 0x000a 408#define mmUVD_JPEG_POWER_STATUS_BASE_IDX 1 409#define mmUVD_DPG_LMA_CTL 0x0011 410#define mmUVD_DPG_LMA_CTL_BASE_IDX 1 411#define mmUVD_DPG_LMA_DATA 0x0012 412#define mmUVD_DPG_LMA_DATA_BASE_IDX 1 413#define mmUVD_DPG_LMA_MASK 0x0013 414#define mmUVD_DPG_LMA_MASK_BASE_IDX 1 415#define mmUVD_DPG_PAUSE 0x0014 416#define mmUVD_DPG_PAUSE_BASE_IDX 1 417#define mmUVD_SCRATCH1 0x0015 418#define mmUVD_SCRATCH1_BASE_IDX 1 419#define mmUVD_SCRATCH2 0x0016 420#define mmUVD_SCRATCH2_BASE_IDX 1 421#define mmUVD_SCRATCH3 0x0017 422#define mmUVD_SCRATCH3_BASE_IDX 1 423#define mmUVD_SCRATCH4 0x0018 424#define mmUVD_SCRATCH4_BASE_IDX 1 425#define mmUVD_SCRATCH5 0x0019 426#define mmUVD_SCRATCH5_BASE_IDX 1 427#define mmUVD_SCRATCH6 0x001a 428#define mmUVD_SCRATCH6_BASE_IDX 1 429#define mmUVD_SCRATCH7 0x001b 430#define mmUVD_SCRATCH7_BASE_IDX 1 431#define mmUVD_SCRATCH8 0x001c 432#define mmUVD_SCRATCH8_BASE_IDX 1 433#define mmUVD_SCRATCH9 0x001d 434#define mmUVD_SCRATCH9_BASE_IDX 1 435#define mmUVD_SCRATCH10 0x001e 436#define mmUVD_SCRATCH10_BASE_IDX 1 437#define mmUVD_SCRATCH11 0x001f 438#define mmUVD_SCRATCH11_BASE_IDX 1 439#define mmUVD_SCRATCH12 0x0020 440#define mmUVD_SCRATCH12_BASE_IDX 1 441#define mmUVD_SCRATCH13 0x0021 442#define mmUVD_SCRATCH13_BASE_IDX 1 443#define mmUVD_SCRATCH14 0x0022 444#define mmUVD_SCRATCH14_BASE_IDX 1 445#define mmUVD_FREE_COUNTER_REG 0x0024 446#define mmUVD_FREE_COUNTER_REG_BASE_IDX 1 447#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x0025 448#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 449#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x0026 450#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 451#define mmUVD_DPG_VCPU_CACHE_OFFSET0 0x0027 452#define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1 453#define mmUVD_DPG_LMI_VCPU_CACHE_VMID 0x0028 454#define mmUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX 1 455#define mmUVD_PF_STATUS 0x0039 456#define mmUVD_PF_STATUS_BASE_IDX 1 457#define mmUVD_DPG_CLK_EN_VCPU_REPORT 0x003c 458#define mmUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX 1 459#define mmUVD_GFX8_ADDR_CONFIG 0x0049 460#define mmUVD_GFX8_ADDR_CONFIG_BASE_IDX 1 461#define mmUVD_GFX10_ADDR_CONFIG 0x004a 462#define mmUVD_GFX10_ADDR_CONFIG_BASE_IDX 1 463#define mmUVD_GPCNT2_CNTL 0x004b 464#define mmUVD_GPCNT2_CNTL_BASE_IDX 1 465#define mmUVD_GPCNT2_TARGET_LOWER 0x004c 466#define mmUVD_GPCNT2_TARGET_LOWER_BASE_IDX 1 467#define mmUVD_GPCNT2_STATUS_LOWER 0x004d 468#define mmUVD_GPCNT2_STATUS_LOWER_BASE_IDX 1 469#define mmUVD_GPCNT2_TARGET_UPPER 0x004e 470#define mmUVD_GPCNT2_TARGET_UPPER_BASE_IDX 1 471#define mmUVD_GPCNT2_STATUS_UPPER 0x004f 472#define mmUVD_GPCNT2_STATUS_UPPER_BASE_IDX 1 473#define mmUVD_GPCNT3_CNTL 0x0050 474#define mmUVD_GPCNT3_CNTL_BASE_IDX 1 475#define mmUVD_GPCNT3_TARGET_LOWER 0x0051 476#define mmUVD_GPCNT3_TARGET_LOWER_BASE_IDX 1 477#define mmUVD_GPCNT3_STATUS_LOWER 0x0052 478#define mmUVD_GPCNT3_STATUS_LOWER_BASE_IDX 1 479#define mmUVD_GPCNT3_TARGET_UPPER 0x0053 480#define mmUVD_GPCNT3_TARGET_UPPER_BASE_IDX 1 481#define mmUVD_GPCNT3_STATUS_UPPER 0x0054 482#define mmUVD_GPCNT3_STATUS_UPPER_BASE_IDX 1 483 484 485// addressBlock: uvd0_uvddec 486// base address: 0x1fa00 487#define mmUVD_STATUS 0x0080 488#define mmUVD_STATUS_BASE_IDX 1 489#define mmUVD_ENC_PIPE_BUSY 0x0081 490#define mmUVD_ENC_PIPE_BUSY_BASE_IDX 1 491#define mmUVD_SOFT_RESET 0x0084 492#define mmUVD_SOFT_RESET_BASE_IDX 1 493#define mmUVD_SOFT_RESET2 0x0085 494#define mmUVD_SOFT_RESET2_BASE_IDX 1 495#define mmUVD_MMSCH_SOFT_RESET 0x0086 496#define mmUVD_MMSCH_SOFT_RESET_BASE_IDX 1 497#define mmUVD_CGC_GATE 0x0088 498#define mmUVD_CGC_GATE_BASE_IDX 1 499#define mmUVD_CGC_STATUS 0x0089 500#define mmUVD_CGC_STATUS_BASE_IDX 1 501#define mmUVD_CGC_CTRL 0x008a 502#define mmUVD_CGC_CTRL_BASE_IDX 1 503#define mmUVD_CGC_UDEC_STATUS 0x008b 504#define mmUVD_CGC_UDEC_STATUS_BASE_IDX 1 505#define mmUVD_SUVD_CGC_GATE 0x008c 506#define mmUVD_SUVD_CGC_GATE_BASE_IDX 1 507#define mmUVD_SUVD_CGC_STATUS 0x008d 508#define mmUVD_SUVD_CGC_STATUS_BASE_IDX 1 509#define mmUVD_SUVD_CGC_CTRL 0x008e 510#define mmUVD_SUVD_CGC_CTRL_BASE_IDX 1 511#define mmUVD_GPCOM_VCPU_CMD 0x008f 512#define mmUVD_GPCOM_VCPU_CMD_BASE_IDX 1 513#define mmUVD_GPCOM_VCPU_DATA0 0x0090 514#define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 515#define mmUVD_GPCOM_VCPU_DATA1 0x0091 516#define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 517#define mmUVD_GPCOM_SYS_CMD 0x0092 518#define mmUVD_GPCOM_SYS_CMD_BASE_IDX 1 519#define mmUVD_GPCOM_SYS_DATA0 0x0093 520#define mmUVD_GPCOM_SYS_DATA0_BASE_IDX 1 521#define mmUVD_GPCOM_SYS_DATA1 0x0094 522#define mmUVD_GPCOM_SYS_DATA1_BASE_IDX 1 523#define mmUVD_VCPU_INT_EN 0x0095 524#define mmUVD_VCPU_INT_EN_BASE_IDX 1 525#define mmUVD_VCPU_INT_ACK 0x0097 526#define mmUVD_VCPU_INT_ACK_BASE_IDX 1 527#define mmUVD_VCPU_INT_ROUTE 0x0098 528#define mmUVD_VCPU_INT_ROUTE_BASE_IDX 1 529#define mmUVD_ENC_VCPU_INT_EN 0x009e 530#define mmUVD_ENC_VCPU_INT_EN_BASE_IDX 1 531#define mmUVD_ENC_VCPU_INT_ACK 0x00a0 532#define mmUVD_ENC_VCPU_INT_ACK_BASE_IDX 1 533#define mmUVD_MASTINT_EN 0x00a1 534#define mmUVD_MASTINT_EN_BASE_IDX 1 535#define mmUVD_SYS_INT_EN 0x00a2 536#define mmUVD_SYS_INT_EN_BASE_IDX 1 537#define mmUVD_SYS_INT_STATUS 0x00a3 538#define mmUVD_SYS_INT_STATUS_BASE_IDX 1 539#define mmUVD_SYS_INT_ACK 0x00a4 540#define mmUVD_SYS_INT_ACK_BASE_IDX 1 541#define mmUVD_JOB_DONE 0x00a5 542#define mmUVD_JOB_DONE_BASE_IDX 1 543#define mmUVD_CBUF_ID 0x00a6 544#define mmUVD_CBUF_ID_BASE_IDX 1 545#define mmUVD_CONTEXT_ID 0x00a7 546#define mmUVD_CONTEXT_ID_BASE_IDX 1 547#define mmUVD_CONTEXT_ID2 0x00a8 548#define mmUVD_CONTEXT_ID2_BASE_IDX 1 549#define mmUVD_NO_OP 0x00a9 550#define mmUVD_NO_OP_BASE_IDX 1 551#define mmUVD_RB_BASE_LO 0x00aa 552#define mmUVD_RB_BASE_LO_BASE_IDX 1 553#define mmUVD_RB_BASE_HI 0x00ab 554#define mmUVD_RB_BASE_HI_BASE_IDX 1 555#define mmUVD_RB_SIZE 0x00ac 556#define mmUVD_RB_SIZE_BASE_IDX 1 557#define mmUVD_RB_RPTR 0x00ad 558#define mmUVD_RB_RPTR_BASE_IDX 1 559#define mmUVD_RB_WPTR 0x00ae 560#define mmUVD_RB_WPTR_BASE_IDX 1 561#define mmUVD_RB_BASE_LO2 0x00af 562#define mmUVD_RB_BASE_LO2_BASE_IDX 1 563#define mmUVD_RB_BASE_HI2 0x00b0 564#define mmUVD_RB_BASE_HI2_BASE_IDX 1 565#define mmUVD_RB_SIZE2 0x00b1 566#define mmUVD_RB_SIZE2_BASE_IDX 1 567#define mmUVD_RB_RPTR2 0x00b2 568#define mmUVD_RB_RPTR2_BASE_IDX 1 569#define mmUVD_RB_WPTR2 0x00b3 570#define mmUVD_RB_WPTR2_BASE_IDX 1 571#define mmUVD_RB_BASE_LO3 0x00b4 572#define mmUVD_RB_BASE_LO3_BASE_IDX 1 573#define mmUVD_RB_BASE_HI3 0x00b5 574#define mmUVD_RB_BASE_HI3_BASE_IDX 1 575#define mmUVD_RB_SIZE3 0x00b6 576#define mmUVD_RB_SIZE3_BASE_IDX 1 577#define mmUVD_RB_RPTR3 0x00b7 578#define mmUVD_RB_RPTR3_BASE_IDX 1 579#define mmUVD_RB_WPTR3 0x00b8 580#define mmUVD_RB_WPTR3_BASE_IDX 1 581#define mmUVD_RB_BASE_LO4 0x00b9 582#define mmUVD_RB_BASE_LO4_BASE_IDX 1 583#define mmUVD_RB_BASE_HI4 0x00ba 584#define mmUVD_RB_BASE_HI4_BASE_IDX 1 585#define mmUVD_RB_SIZE4 0x00bb 586#define mmUVD_RB_SIZE4_BASE_IDX 1 587#define mmUVD_RB_RPTR4 0x00bc 588#define mmUVD_RB_RPTR4_BASE_IDX 1 589#define mmUVD_RB_WPTR4 0x00bd 590#define mmUVD_RB_WPTR4_BASE_IDX 1 591#define mmUVD_OUT_RB_BASE_LO 0x00be 592#define mmUVD_OUT_RB_BASE_LO_BASE_IDX 1 593#define mmUVD_OUT_RB_BASE_HI 0x00bf 594#define mmUVD_OUT_RB_BASE_HI_BASE_IDX 1 595#define mmUVD_OUT_RB_SIZE 0x00c0 596#define mmUVD_OUT_RB_SIZE_BASE_IDX 1 597#define mmUVD_OUT_RB_RPTR 0x00c1 598#define mmUVD_OUT_RB_RPTR_BASE_IDX 1 599#define mmUVD_OUT_RB_WPTR 0x00c2 600#define mmUVD_OUT_RB_WPTR_BASE_IDX 1 601#define mmUVD_RB_ARB_CTRL 0x00c6 602#define mmUVD_RB_ARB_CTRL_BASE_IDX 1 603#define mmUVD_CTX_INDEX 0x00c7 604#define mmUVD_CTX_INDEX_BASE_IDX 1 605#define mmUVD_CTX_DATA 0x00c8 606#define mmUVD_CTX_DATA_BASE_IDX 1 607#define mmUVD_CXW_WR 0x00c9 608#define mmUVD_CXW_WR_BASE_IDX 1 609#define mmUVD_CXW_WR_INT_ID 0x00ca 610#define mmUVD_CXW_WR_INT_ID_BASE_IDX 1 611#define mmUVD_CXW_WR_INT_CTX_ID 0x00cb 612#define mmUVD_CXW_WR_INT_CTX_ID_BASE_IDX 1 613#define mmUVD_CXW_INT_ID 0x00cc 614#define mmUVD_CXW_INT_ID_BASE_IDX 1 615#define mmUVD_TOP_CTRL 0x00cf 616#define mmUVD_TOP_CTRL_BASE_IDX 1 617#define mmUVD_YBASE 0x00d0 618#define mmUVD_YBASE_BASE_IDX 1 619#define mmUVD_UVBASE 0x00d1 620#define mmUVD_UVBASE_BASE_IDX 1 621#define mmUVD_PITCH 0x00d2 622#define mmUVD_PITCH_BASE_IDX 1 623#define mmUVD_WIDTH 0x00d3 624#define mmUVD_WIDTH_BASE_IDX 1 625#define mmUVD_HEIGHT 0x00d4 626#define mmUVD_HEIGHT_BASE_IDX 1 627#define mmUVD_PICCOUNT 0x00d5 628#define mmUVD_PICCOUNT_BASE_IDX 1 629#define mmUVD_SCRATCH_NP 0x00db 630#define mmUVD_SCRATCH_NP_BASE_IDX 1 631#define mmUVD_VERSION 0x00dd 632#define mmUVD_VERSION_BASE_IDX 1 633#define mmUVD_GP_SCRATCH0 0x00de 634#define mmUVD_GP_SCRATCH0_BASE_IDX 1 635#define mmUVD_GP_SCRATCH1 0x00df 636#define mmUVD_GP_SCRATCH1_BASE_IDX 1 637#define mmUVD_GP_SCRATCH2 0x00e0 638#define mmUVD_GP_SCRATCH2_BASE_IDX 1 639#define mmUVD_GP_SCRATCH3 0x00e1 640#define mmUVD_GP_SCRATCH3_BASE_IDX 1 641#define mmUVD_GP_SCRATCH4 0x00e2 642#define mmUVD_GP_SCRATCH4_BASE_IDX 1 643#define mmUVD_GP_SCRATCH5 0x00e3 644#define mmUVD_GP_SCRATCH5_BASE_IDX 1 645#define mmUVD_GP_SCRATCH6 0x00e4 646#define mmUVD_GP_SCRATCH6_BASE_IDX 1 647#define mmUVD_GP_SCRATCH7 0x00e5 648#define mmUVD_GP_SCRATCH7_BASE_IDX 1 649#define mmUVD_GP_SCRATCH8 0x00e6 650#define mmUVD_GP_SCRATCH8_BASE_IDX 1 651#define mmUVD_GP_SCRATCH9 0x00e7 652#define mmUVD_GP_SCRATCH9_BASE_IDX 1 653#define mmUVD_GP_SCRATCH10 0x00e8 654#define mmUVD_GP_SCRATCH10_BASE_IDX 1 655#define mmUVD_GP_SCRATCH11 0x00e9 656#define mmUVD_GP_SCRATCH11_BASE_IDX 1 657#define mmUVD_GP_SCRATCH12 0x00ea 658#define mmUVD_GP_SCRATCH12_BASE_IDX 1 659#define mmUVD_GP_SCRATCH13 0x00eb 660#define mmUVD_GP_SCRATCH13_BASE_IDX 1 661#define mmUVD_GP_SCRATCH14 0x00ec 662#define mmUVD_GP_SCRATCH14_BASE_IDX 1 663#define mmUVD_GP_SCRATCH15 0x00ed 664#define mmUVD_GP_SCRATCH15_BASE_IDX 1 665#define mmUVD_GP_SCRATCH16 0x00ee 666#define mmUVD_GP_SCRATCH16_BASE_IDX 1 667#define mmUVD_GP_SCRATCH17 0x00ef 668#define mmUVD_GP_SCRATCH17_BASE_IDX 1 669#define mmUVD_GP_SCRATCH18 0x00f0 670#define mmUVD_GP_SCRATCH18_BASE_IDX 1 671#define mmUVD_GP_SCRATCH19 0x00f1 672#define mmUVD_GP_SCRATCH19_BASE_IDX 1 673#define mmUVD_GP_SCRATCH20 0x00f2 674#define mmUVD_GP_SCRATCH20_BASE_IDX 1 675#define mmUVD_GP_SCRATCH21 0x00f3 676#define mmUVD_GP_SCRATCH21_BASE_IDX 1 677#define mmUVD_GP_SCRATCH22 0x00f4 678#define mmUVD_GP_SCRATCH22_BASE_IDX 1 679#define mmUVD_GP_SCRATCH23 0x00f5 680#define mmUVD_GP_SCRATCH23_BASE_IDX 1 681 682 683// addressBlock: uvd0_ecpudec 684// base address: 0x1fd00 685#define mmUVD_VCPU_CACHE_OFFSET0 0x0140 686#define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1 687#define mmUVD_VCPU_CACHE_SIZE0 0x0141 688#define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX 1 689#define mmUVD_VCPU_CACHE_OFFSET1 0x0142 690#define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1 691#define mmUVD_VCPU_CACHE_SIZE1 0x0143 692#define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX 1 693#define mmUVD_VCPU_CACHE_OFFSET2 0x0144 694#define mmUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1 695#define mmUVD_VCPU_CACHE_SIZE2 0x0145 696#define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX 1 697#define mmUVD_VCPU_CACHE_OFFSET3 0x0146 698#define mmUVD_VCPU_CACHE_OFFSET3_BASE_IDX 1 699#define mmUVD_VCPU_CACHE_SIZE3 0x0147 700#define mmUVD_VCPU_CACHE_SIZE3_BASE_IDX 1 701#define mmUVD_VCPU_CACHE_OFFSET4 0x0148 702#define mmUVD_VCPU_CACHE_OFFSET4_BASE_IDX 1 703#define mmUVD_VCPU_CACHE_SIZE4 0x0149 704#define mmUVD_VCPU_CACHE_SIZE4_BASE_IDX 1 705#define mmUVD_VCPU_CACHE_OFFSET5 0x014a 706#define mmUVD_VCPU_CACHE_OFFSET5_BASE_IDX 1 707#define mmUVD_VCPU_CACHE_SIZE5 0x014b 708#define mmUVD_VCPU_CACHE_SIZE5_BASE_IDX 1 709#define mmUVD_VCPU_CACHE_OFFSET6 0x014c 710#define mmUVD_VCPU_CACHE_OFFSET6_BASE_IDX 1 711#define mmUVD_VCPU_CACHE_SIZE6 0x014d 712#define mmUVD_VCPU_CACHE_SIZE6_BASE_IDX 1 713#define mmUVD_VCPU_CACHE_OFFSET7 0x014e 714#define mmUVD_VCPU_CACHE_OFFSET7_BASE_IDX 1 715#define mmUVD_VCPU_CACHE_SIZE7 0x014f 716#define mmUVD_VCPU_CACHE_SIZE7_BASE_IDX 1 717#define mmUVD_VCPU_CACHE_OFFSET8 0x0150 718#define mmUVD_VCPU_CACHE_OFFSET8_BASE_IDX 1 719#define mmUVD_VCPU_CACHE_SIZE8 0x0151 720#define mmUVD_VCPU_CACHE_SIZE8_BASE_IDX 1 721#define mmUVD_VCPU_NONCACHE_OFFSET0 0x0152 722#define mmUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX 1 723#define mmUVD_VCPU_NONCACHE_SIZE0 0x0153 724#define mmUVD_VCPU_NONCACHE_SIZE0_BASE_IDX 1 725#define mmUVD_VCPU_NONCACHE_OFFSET1 0x0154 726#define mmUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX 1 727#define mmUVD_VCPU_NONCACHE_SIZE1 0x0155 728#define mmUVD_VCPU_NONCACHE_SIZE1_BASE_IDX 1 729#define mmUVD_VCPU_CNTL 0x0156 730#define mmUVD_VCPU_CNTL_BASE_IDX 1 731#define mmUVD_VCPU_PRID 0x0157 732#define mmUVD_VCPU_PRID_BASE_IDX 1 733#define mmUVD_VCPU_TRCE 0x0158 734#define mmUVD_VCPU_TRCE_BASE_IDX 1 735#define mmUVD_VCPU_TRCE_RD 0x0159 736#define mmUVD_VCPU_TRCE_RD_BASE_IDX 1 737 738 739// addressBlock: uvd0_uvd_mpcdec 740// base address: 0x20310 741#define mmUVD_MP_SWAP_CNTL 0x02c4 742#define mmUVD_MP_SWAP_CNTL_BASE_IDX 1 743#define mmUVD_MP_SWAP_CNTL2 0x02c5 744#define mmUVD_MP_SWAP_CNTL2_BASE_IDX 1 745#define mmUVD_MPC_LUMA_SRCH 0x02c6 746#define mmUVD_MPC_LUMA_SRCH_BASE_IDX 1 747#define mmUVD_MPC_LUMA_HIT 0x02c7 748#define mmUVD_MPC_LUMA_HIT_BASE_IDX 1 749#define mmUVD_MPC_LUMA_HITPEND 0x02c8 750#define mmUVD_MPC_LUMA_HITPEND_BASE_IDX 1 751#define mmUVD_MPC_CHROMA_SRCH 0x02c9 752#define mmUVD_MPC_CHROMA_SRCH_BASE_IDX 1 753#define mmUVD_MPC_CHROMA_HIT 0x02ca 754#define mmUVD_MPC_CHROMA_HIT_BASE_IDX 1 755#define mmUVD_MPC_CHROMA_HITPEND 0x02cb 756#define mmUVD_MPC_CHROMA_HITPEND_BASE_IDX 1 757#define mmUVD_MPC_CNTL 0x02cc 758#define mmUVD_MPC_CNTL_BASE_IDX 1 759#define mmUVD_MPC_PITCH 0x02cd 760#define mmUVD_MPC_PITCH_BASE_IDX 1 761#define mmUVD_MPC_SET_MUXA0 0x02ce 762#define mmUVD_MPC_SET_MUXA0_BASE_IDX 1 763#define mmUVD_MPC_SET_MUXA1 0x02cf 764#define mmUVD_MPC_SET_MUXA1_BASE_IDX 1 765#define mmUVD_MPC_SET_MUXB0 0x02d0 766#define mmUVD_MPC_SET_MUXB0_BASE_IDX 1 767#define mmUVD_MPC_SET_MUXB1 0x02d1 768#define mmUVD_MPC_SET_MUXB1_BASE_IDX 1 769#define mmUVD_MPC_SET_MUX 0x02d2 770#define mmUVD_MPC_SET_MUX_BASE_IDX 1 771#define mmUVD_MPC_SET_ALU 0x02d3 772#define mmUVD_MPC_SET_ALU_BASE_IDX 1 773#define mmUVD_MPC_PERF0 0x02d4 774#define mmUVD_MPC_PERF0_BASE_IDX 1 775#define mmUVD_MPC_PERF1 0x02d5 776#define mmUVD_MPC_PERF1_BASE_IDX 1 777 778 779// addressBlock: uvd0_uvd_rbcdec 780// base address: 0x20370 781#define mmUVD_RBC_IB_SIZE 0x02dc 782#define mmUVD_RBC_IB_SIZE_BASE_IDX 1 783#define mmUVD_RBC_IB_SIZE_UPDATE 0x02dd 784#define mmUVD_RBC_IB_SIZE_UPDATE_BASE_IDX 1 785#define mmUVD_RBC_RB_CNTL 0x02de 786#define mmUVD_RBC_RB_CNTL_BASE_IDX 1 787#define mmUVD_RBC_RB_RPTR_ADDR 0x02df 788#define mmUVD_RBC_RB_RPTR_ADDR_BASE_IDX 1 789#define mmUVD_RBC_RB_RPTR 0x02e0 790#define mmUVD_RBC_RB_RPTR_BASE_IDX 1 791#define mmUVD_RBC_RB_WPTR 0x02e1 792#define mmUVD_RBC_RB_WPTR_BASE_IDX 1 793#define mmUVD_RBC_VCPU_ACCESS 0x02e2 794#define mmUVD_RBC_VCPU_ACCESS_BASE_IDX 1 795#define mmUVD_RBC_READ_REQ_URGENT_CNTL 0x02e5 796#define mmUVD_RBC_READ_REQ_URGENT_CNTL_BASE_IDX 1 797#define mmUVD_RBC_RB_WPTR_CNTL 0x02e6 798#define mmUVD_RBC_RB_WPTR_CNTL_BASE_IDX 1 799#define mmUVD_RBC_WPTR_STATUS 0x02e7 800#define mmUVD_RBC_WPTR_STATUS_BASE_IDX 1 801#define mmUVD_RBC_WPTR_POLL_CNTL 0x02e8 802#define mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX 1 803#define mmUVD_RBC_WPTR_POLL_ADDR 0x02e9 804#define mmUVD_RBC_WPTR_POLL_ADDR_BASE_IDX 1 805#define mmUVD_SEMA_CMD 0x02ea 806#define mmUVD_SEMA_CMD_BASE_IDX 1 807#define mmUVD_SEMA_ADDR_LOW 0x02eb 808#define mmUVD_SEMA_ADDR_LOW_BASE_IDX 1 809#define mmUVD_SEMA_ADDR_HIGH 0x02ec 810#define mmUVD_SEMA_ADDR_HIGH_BASE_IDX 1 811#define mmUVD_ENGINE_CNTL 0x02ed 812#define mmUVD_ENGINE_CNTL_BASE_IDX 1 813#define mmUVD_SEMA_TIMEOUT_STATUS 0x02ee 814#define mmUVD_SEMA_TIMEOUT_STATUS_BASE_IDX 1 815#define mmUVD_SEMA_CNTL 0x02ef 816#define mmUVD_SEMA_CNTL_BASE_IDX 1 817#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x02f0 818#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 819#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x02f1 820#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX 1 821#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x02f2 822#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 823#define mmUVD_JOB_START 0x02f3 824#define mmUVD_JOB_START_BASE_IDX 1 825#define mmUVD_RBC_BUF_STATUS 0x02f4 826#define mmUVD_RBC_BUF_STATUS_BASE_IDX 1 827 828 829// addressBlock: uvd0_uvdgendec 830// base address: 0x20470 831#define mmUVD_LCM_CGC_CNTRL 0x033f 832#define mmUVD_LCM_CGC_CNTRL_BASE_IDX 1 833#define mmUVD_MIF_CURR_UV_ADDR_CONFIG 0x03a0 834#define mmUVD_MIF_CURR_UV_ADDR_CONFIG_BASE_IDX 1 835#define mmUVD_MIF_REF_UV_ADDR_CONFIG 0x03a1 836#define mmUVD_MIF_REF_UV_ADDR_CONFIG_BASE_IDX 1 837#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG 0x03a2 838#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG_BASE_IDX 1 839#define mmUVD_MIF_CURR_ADDR_CONFIG 0x03ae 840#define mmUVD_MIF_CURR_ADDR_CONFIG_BASE_IDX 1 841#define mmUVD_MIF_REF_ADDR_CONFIG 0x03af 842#define mmUVD_MIF_REF_ADDR_CONFIG_BASE_IDX 1 843#define mmUVD_MIF_RECON1_ADDR_CONFIG 0x03e1 844#define mmUVD_MIF_RECON1_ADDR_CONFIG_BASE_IDX 1 845 846 847// addressBlock: uvd0_lmi_adpdec 848// base address: 0x20870 849#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x0432 850#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1 851#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x0433 852#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 853#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x0434 854#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1 855#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0435 856#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 857#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW 0x0438 858#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX 1 859#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 0x0439 860#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX 1 861#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW 0x043a 862#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX 1 863#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 0x043b 864#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX 1 865#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x043c 866#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 867#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x043d 868#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 869#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x0468 870#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1 871#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x0469 872#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1 873#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 0x046a 874#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX 1 875#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 0x046b 876#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX 1 877#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x046c 878#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1 879#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x046d 880#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1 881#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 0x046e 882#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX 1 883#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 0x046f 884#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX 1 885#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 0x0470 886#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX 1 887#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 0x0471 888#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX 1 889#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 0x0472 890#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX 1 891#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 0x0473 892#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX 1 893#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 0x0474 894#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX 1 895#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 0x0475 896#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX 1 897#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 0x0476 898#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX 1 899#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 0x0477 900#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX 1 901#define mmUVD_LMI_SPH_64BIT_BAR_HIGH 0x047c 902#define mmUVD_LMI_SPH_64BIT_BAR_HIGH_BASE_IDX 1 903#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 0x047d 904#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX 1 905#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 0x047e 906#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX 1 907#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 0x047f 908#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX 1 909#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 0x0480 910#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX 1 911#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 0x0481 912#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX 1 913#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 0x0482 914#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX 1 915#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 0x0483 916#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX 1 917#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 0x0484 918#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX 1 919#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 0x0485 920#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX 1 921#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 0x0486 922#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX 1 923#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 0x0487 924#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX 1 925#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 0x0488 926#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX 1 927#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 0x0489 928#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX 1 929#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 0x048a 930#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX 1 931#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 0x048b 932#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX 1 933#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 0x048c 934#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX 1 935#define mmUVD_LMI_MMSCH_NC_VMID 0x048d 936#define mmUVD_LMI_MMSCH_NC_VMID_BASE_IDX 1 937#define mmUVD_LMI_MMSCH_CTRL 0x048e 938#define mmUVD_LMI_MMSCH_CTRL_BASE_IDX 1 939#define mmUVD_LMI_ARB_CTRL2 0x049a 940#define mmUVD_LMI_ARB_CTRL2_BASE_IDX 1 941#define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI 0x049f 942#define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX 1 943#define mmUVD_LMI_VCPU_NC_VMIDS_MULTI 0x04a0 944#define mmUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX 1 945#define mmUVD_LMI_LAT_CTRL 0x04a1 946#define mmUVD_LMI_LAT_CTRL_BASE_IDX 1 947#define mmUVD_LMI_LAT_CNTR 0x04a2 948#define mmUVD_LMI_LAT_CNTR_BASE_IDX 1 949#define mmUVD_LMI_AVG_LAT_CNTR 0x04a3 950#define mmUVD_LMI_AVG_LAT_CNTR_BASE_IDX 1 951#define mmUVD_LMI_SPH 0x04a4 952#define mmUVD_LMI_SPH_BASE_IDX 1 953#define mmUVD_LMI_VCPU_CACHE_VMID 0x04a5 954#define mmUVD_LMI_VCPU_CACHE_VMID_BASE_IDX 1 955#define mmUVD_LMI_CTRL2 0x04a6 956#define mmUVD_LMI_CTRL2_BASE_IDX 1 957#define mmUVD_LMI_URGENT_CTRL 0x04a7 958#define mmUVD_LMI_URGENT_CTRL_BASE_IDX 1 959#define mmUVD_LMI_CTRL 0x04a8 960#define mmUVD_LMI_CTRL_BASE_IDX 1 961#define mmUVD_LMI_STATUS 0x04a9 962#define mmUVD_LMI_STATUS_BASE_IDX 1 963#define mmUVD_LMI_PERFMON_CTRL 0x04ac 964#define mmUVD_LMI_PERFMON_CTRL_BASE_IDX 1 965#define mmUVD_LMI_PERFMON_COUNT_LO 0x04ad 966#define mmUVD_LMI_PERFMON_COUNT_LO_BASE_IDX 1 967#define mmUVD_LMI_PERFMON_COUNT_HI 0x04ae 968#define mmUVD_LMI_PERFMON_COUNT_HI_BASE_IDX 1 969#define mmUVD_LMI_RBC_RB_VMID 0x04b0 970#define mmUVD_LMI_RBC_RB_VMID_BASE_IDX 1 971#define mmUVD_LMI_RBC_IB_VMID 0x04b1 972#define mmUVD_LMI_RBC_IB_VMID_BASE_IDX 1 973#define mmUVD_LMI_MC_CREDITS 0x04b2 974#define mmUVD_LMI_MC_CREDITS_BASE_IDX 1 975 976 977// addressBlock: uvd0_uvdnpdec 978// base address: 0x20bd0 979#define mmMDM_DMA_CMD 0x06f4 980#define mmMDM_DMA_CMD_BASE_IDX 1 981#define mmMDM_DMA_STATUS 0x06f5 982#define mmMDM_DMA_STATUS_BASE_IDX 1 983#define mmMDM_DMA_CTL 0x06f6 984#define mmMDM_DMA_CTL_BASE_IDX 1 985#define mmMDM_ENC_PIPE_BUSY 0x06f7 986#define mmMDM_ENC_PIPE_BUSY_BASE_IDX 1 987#define mmMDM_WIG_PIPE_BUSY 0x06f9 988#define mmMDM_WIG_PIPE_BUSY_BASE_IDX 1 989 990 991/* VCN 2_6_0 regs */ 992#define mmUVD_RAS_VCPU_VCODEC_STATUS 0x0057 993#define mmUVD_RAS_VCPU_VCODEC_STATUS_BASE_IDX 1 994#define mmUVD_RAS_MMSCH_FATAL_ERROR 0x0058 995#define mmUVD_RAS_MMSCH_FATAL_ERROR_BASE_IDX 1 996#define mmVCN_RAS_CNTL 0x04b9 997#define mmVCN_RAS_CNTL_BASE_IDX 1 998 999/* JPEG 2_6_0 regs */ 1000#define mmUVD_RAS_JPEG0_STATUS 0x0059 1001#define mmUVD_RAS_JPEG0_STATUS_BASE_IDX 1 1002#define mmUVD_RAS_JPEG1_STATUS 0x005a 1003#define mmUVD_RAS_JPEG1_STATUS_BASE_IDX 1 1004 1005#endif
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