FILE
vce_4_0_sh_mask.h
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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_sh_mask.h
1/* 2 * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _vce_4_0_SH_MASK_HEADER 22#define _vce_4_0_SH_MASK_HEADER 23 24 25// addressBlock: vce0_vce_dec 26//VCE_STATUS 27#define VCE_STATUS__JOB_BUSY__SHIFT 0x0 28#define VCE_STATUS__VCPU_REPORT__SHIFT 0x1 29#define VCE_STATUS__UENC_BUSY__SHIFT 0x8 30#define VCE_STATUS__VCE_CONFIGURATION__SHIFT 0x16 31#define VCE_STATUS__VCE_INSTANCE_ID__SHIFT 0x18 32#define VCE_STATUS__JOB_BUSY_MASK 0x00000001L 33#define VCE_STATUS__VCPU_REPORT_MASK 0x000000FEL 34#define VCE_STATUS__UENC_BUSY_MASK 0x00000100L 35#define VCE_STATUS__VCE_CONFIGURATION_MASK 0x00C00000L 36#define VCE_STATUS__VCE_INSTANCE_ID_MASK 0x03000000L 37//VCE_VCPU_CNTL 38#define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x0 39#define VCE_VCPU_CNTL__ED_ENABLE__SHIFT 0x1 40#define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x12 41#define VCE_VCPU_CNTL__ONE_CACHE_SURFACE_EN__SHIFT 0x15 42#define VCE_VCPU_CNTL__CLK_EN_MASK 0x00000001L 43#define VCE_VCPU_CNTL__ED_ENABLE_MASK 0x00000002L 44#define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00040000L 45#define VCE_VCPU_CNTL__ONE_CACHE_SURFACE_EN_MASK 0x00200000L 46//VCE_VCPU_CACHE_OFFSET0 47#define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x0 48#define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL 49//VCE_VCPU_CACHE_SIZE0 50#define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x0 51#define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0x00FFFFFFL 52//VCE_VCPU_CACHE_OFFSET1 53#define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x0 54#define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL 55//VCE_VCPU_CACHE_SIZE1 56#define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x0 57#define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0x00FFFFFFL 58//VCE_VCPU_CACHE_OFFSET2 59#define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x0 60#define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0x0FFFFFFFL 61//VCE_VCPU_CACHE_SIZE2 62#define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x0 63#define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0x00FFFFFFL 64//VCE_VCPU_CACHE_OFFSET3 65#define VCE_VCPU_CACHE_OFFSET3__OFFSET__SHIFT 0x0 66#define VCE_VCPU_CACHE_OFFSET3__OFFSET_MASK 0x0FFFFFFFL 67//VCE_VCPU_CACHE_SIZE3 68#define VCE_VCPU_CACHE_SIZE3__SIZE__SHIFT 0x0 69#define VCE_VCPU_CACHE_SIZE3__SIZE_MASK 0x00FFFFFFL 70//VCE_VCPU_CACHE_OFFSET4 71#define VCE_VCPU_CACHE_OFFSET4__OFFSET__SHIFT 0x0 72#define VCE_VCPU_CACHE_OFFSET4__OFFSET_MASK 0x0FFFFFFFL 73//VCE_VCPU_CACHE_SIZE4 74#define VCE_VCPU_CACHE_SIZE4__SIZE__SHIFT 0x0 75#define VCE_VCPU_CACHE_SIZE4__SIZE_MASK 0x00FFFFFFL 76//VCE_VCPU_CACHE_OFFSET5 77#define VCE_VCPU_CACHE_OFFSET5__OFFSET__SHIFT 0x0 78#define VCE_VCPU_CACHE_OFFSET5__OFFSET_MASK 0x0FFFFFFFL 79//VCE_VCPU_CACHE_SIZE5 80#define VCE_VCPU_CACHE_SIZE5__SIZE__SHIFT 0x0 81#define VCE_VCPU_CACHE_SIZE5__SIZE_MASK 0x00FFFFFFL 82//VCE_VCPU_CACHE_OFFSET6 83#define VCE_VCPU_CACHE_OFFSET6__OFFSET__SHIFT 0x0 84#define VCE_VCPU_CACHE_OFFSET6__OFFSET_MASK 0x0FFFFFFFL 85//VCE_VCPU_CACHE_SIZE6 86#define VCE_VCPU_CACHE_SIZE6__SIZE__SHIFT 0x0 87#define VCE_VCPU_CACHE_SIZE6__SIZE_MASK 0x00FFFFFFL 88//VCE_VCPU_CACHE_OFFSET7 89#define VCE_VCPU_CACHE_OFFSET7__OFFSET__SHIFT 0x0 90#define VCE_VCPU_CACHE_OFFSET7__OFFSET_MASK 0x0FFFFFFFL 91//VCE_VCPU_CACHE_SIZE7 92#define VCE_VCPU_CACHE_SIZE7__SIZE__SHIFT 0x0 93#define VCE_VCPU_CACHE_SIZE7__SIZE_MASK 0x00FFFFFFL 94//VCE_VCPU_CACHE_OFFSET8 95#define VCE_VCPU_CACHE_OFFSET8__OFFSET__SHIFT 0x0 96#define VCE_VCPU_CACHE_OFFSET8__OFFSET_MASK 0x0FFFFFFFL 97//VCE_VCPU_CACHE_SIZE8 98#define VCE_VCPU_CACHE_SIZE8__SIZE__SHIFT 0x0 99#define VCE_VCPU_CACHE_SIZE8__SIZE_MASK 0x00FFFFFFL 100//VCE_SOFT_RESET 101#define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x0 102#define VCE_SOFT_RESET__UENC_SOFT_RESET__SHIFT 0x1 103#define VCE_SOFT_RESET__FME_SOFT_RESET__SHIFT 0x2 104#define VCE_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0x3 105#define VCE_SOFT_RESET__DBF_SOFT_RESET__SHIFT 0x4 106#define VCE_SOFT_RESET__ENT_SOFT_RESET__SHIFT 0x5 107#define VCE_SOFT_RESET__TBE_SOFT_RESET__SHIFT 0x6 108#define VCE_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x7 109#define VCE_SOFT_RESET__CTL_SOFT_RESET__SHIFT 0x8 110#define VCE_SOFT_RESET__IME_SOFT_RESET__SHIFT 0x9 111#define VCE_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 112#define VCE_SOFT_RESET__SEM_SOFT_RESET__SHIFT 0xb 113#define VCE_SOFT_RESET__DCAP_SOFT_RESET__SHIFT 0xc 114#define VCE_SOFT_RESET__ACAP_SOFT_RESET__SHIFT 0xd 115#define VCE_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0xe 116#define VCE_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0xf 117#define VCE_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0x10 118#define VCE_SOFT_RESET__AVMUX_SOFT_RESET__SHIFT 0x13 119#define VCE_SOFT_RESET__VREG_SOFT_RESET__SHIFT 0x14 120#define VCE_SOFT_RESET__DCAP_FSM_SOFT_RESET__SHIFT 0x15 121#define VCE_SOFT_RESET__VEP_SOFT_RESET__SHIFT 0x16 122#define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x00000001L 123#define VCE_SOFT_RESET__UENC_SOFT_RESET_MASK 0x00000002L 124#define VCE_SOFT_RESET__FME_SOFT_RESET_MASK 0x00000004L 125#define VCE_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00000008L 126#define VCE_SOFT_RESET__DBF_SOFT_RESET_MASK 0x00000010L 127#define VCE_SOFT_RESET__ENT_SOFT_RESET_MASK 0x00000020L 128#define VCE_SOFT_RESET__TBE_SOFT_RESET_MASK 0x00000040L 129#define VCE_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00000080L 130#define VCE_SOFT_RESET__CTL_SOFT_RESET_MASK 0x00000100L 131#define VCE_SOFT_RESET__IME_SOFT_RESET_MASK 0x00000200L 132#define VCE_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L 133#define VCE_SOFT_RESET__SEM_SOFT_RESET_MASK 0x00000800L 134#define VCE_SOFT_RESET__DCAP_SOFT_RESET_MASK 0x00001000L 135#define VCE_SOFT_RESET__ACAP_SOFT_RESET_MASK 0x00002000L 136#define VCE_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00004000L 137#define VCE_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00008000L 138#define VCE_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00010000L 139#define VCE_SOFT_RESET__AVMUX_SOFT_RESET_MASK 0x00080000L 140#define VCE_SOFT_RESET__VREG_SOFT_RESET_MASK 0x00100000L 141#define VCE_SOFT_RESET__DCAP_FSM_SOFT_RESET_MASK 0x00200000L 142#define VCE_SOFT_RESET__VEP_SOFT_RESET_MASK 0x00400000L 143//VCE_RB_BASE_LO2 144#define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 145#define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L 146//VCE_RB_BASE_HI2 147#define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 148#define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL 149//VCE_RB_SIZE2 150#define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x4 151#define VCE_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L 152//VCE_RB_RPTR2 153#define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x4 154#define VCE_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L 155//VCE_RB_WPTR2 156#define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x4 157#define VCE_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L 158//VCE_RB_BASE_LO 159#define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 160#define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 161//VCE_RB_BASE_HI 162#define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 163#define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 164//VCE_RB_SIZE 165#define VCE_RB_SIZE__RB_SIZE__SHIFT 0x4 166#define VCE_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 167//VCE_RB_RPTR 168#define VCE_RB_RPTR__RB_RPTR__SHIFT 0x4 169#define VCE_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 170//VCE_RB_WPTR 171#define VCE_RB_WPTR__RB_WPTR__SHIFT 0x4 172#define VCE_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 173//VCE_RB_ARB_CTRL 174#define VCE_RB_ARB_CTRL__RB_ARB_CTRL__SHIFT 0x0 175#define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE__SHIFT 0x10 176#define VCE_RB_ARB_CTRL__RB_ARB_CTRL_MASK 0x000001FFL 177#define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE_MASK 0x00010000L 178//VCE_CLOCK_GATING_A 179#define VCE_CLOCK_GATING_A__CGC_CLK_ON_DELAY__SHIFT 0x0 180#define VCE_CLOCK_GATING_A__CGC_CLK_OFF_DELAY__SHIFT 0x4 181#define VCE_CLOCK_GATING_A__CGC_REG_AWAKE__SHIFT 0x11 182#define VCE_CLOCK_GATING_A__CGC_CLK_ON_DELAY_MASK 0x0000000FL 183#define VCE_CLOCK_GATING_A__CGC_CLK_OFF_DELAY_MASK 0x00000FF0L 184#define VCE_CLOCK_GATING_A__CGC_REG_AWAKE_MASK 0x00020000L 185//VCE_CLOCK_GATING_B 186#define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_ON__SHIFT 0x0 187#define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_ON__SHIFT 0x1 188#define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_ON__SHIFT 0x2 189#define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_ON__SHIFT 0x3 190#define VCE_CLOCK_GATING_B__CGC_VREG_CLK_FORCE_ON__SHIFT 0x4 191#define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_ON__SHIFT 0x5 192#define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_ON__SHIFT 0x6 193#define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_ON__SHIFT 0x7 194#define VCE_CLOCK_GATING_B__CGC_CTLREG_CLK_FORCE_ON__SHIFT 0x8 195#define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_ON__SHIFT 0x9 196#define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_OFF__SHIFT 0x10 197#define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_OFF__SHIFT 0x11 198#define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_OFF__SHIFT 0x12 199#define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_OFF__SHIFT 0x13 200#define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_OFF__SHIFT 0x15 201#define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_OFF__SHIFT 0x16 202#define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_OFF__SHIFT 0x17 203#define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_OFF__SHIFT 0x18 204#define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_ON_MASK 0x00000001L 205#define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_ON_MASK 0x00000002L 206#define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_ON_MASK 0x00000004L 207#define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_ON_MASK 0x00000008L 208#define VCE_CLOCK_GATING_B__CGC_VREG_CLK_FORCE_ON_MASK 0x00000010L 209#define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_ON_MASK 0x00000020L 210#define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_ON_MASK 0x00000040L 211#define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_ON_MASK 0x00000080L 212#define VCE_CLOCK_GATING_B__CGC_CTLREG_CLK_FORCE_ON_MASK 0x00000100L 213#define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_ON_MASK 0x00000200L 214#define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_OFF_MASK 0x00010000L 215#define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_OFF_MASK 0x00020000L 216#define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_OFF_MASK 0x00040000L 217#define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_OFF_MASK 0x00080000L 218#define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_OFF_MASK 0x00200000L 219#define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_OFF_MASK 0x00400000L 220#define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_OFF_MASK 0x00800000L 221#define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_OFF_MASK 0x01000000L 222//VCE_RB_BASE_LO3 223#define VCE_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 224#define VCE_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L 225//VCE_RB_BASE_HI3 226#define VCE_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 227#define VCE_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL 228//VCE_RB_SIZE3 229#define VCE_RB_SIZE3__RB_SIZE__SHIFT 0x4 230#define VCE_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L 231//VCE_RB_RPTR3 232#define VCE_RB_RPTR3__RB_RPTR__SHIFT 0x4 233#define VCE_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L 234//VCE_RB_WPTR3 235#define VCE_RB_WPTR3__RB_WPTR__SHIFT 0x4 236#define VCE_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L 237//VCE_SYS_INT_EN 238#define VCE_SYS_INT_EN__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_EN__SHIFT 0x0 239#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x3 240#define VCE_SYS_INT_EN__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_EN_MASK 0x00000001L 241#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x00000008L 242//VCE_SYS_INT_ACK 243#define VCE_SYS_INT_ACK__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_ACK__SHIFT 0x0 244#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x3 245#define VCE_SYS_INT_ACK__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_ACK_MASK 0x00000001L 246#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x00000008L 247//VCE_SYS_INT_STATUS 248#define VCE_SYS_INT_STATUS__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_INT__SHIFT 0x0 249#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x3 250#define VCE_SYS_INT_STATUS__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_INT_MASK 0x00000001L 251#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x00000008L 252 253 254// addressBlock: vce0_ctl_dec 255//VCE_UENC_CLOCK_GATING 256#define VCE_UENC_CLOCK_GATING__CLOCK_ON_DELAY__SHIFT 0x0 257#define VCE_UENC_CLOCK_GATING__CLOCK_OFF_DELAY__SHIFT 0x4 258#define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_ON__SHIFT 0xc 259#define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_ON__SHIFT 0xd 260#define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_ON__SHIFT 0xe 261#define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_ON__SHIFT 0xf 262#define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_ON__SHIFT 0x10 263#define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_ON__SHIFT 0x11 264#define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_ON__SHIFT 0x12 265#define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_ON__SHIFT 0x13 266#define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_ON__SHIFT 0x14 267#define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_ON__SHIFT 0x15 268#define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_OFF__SHIFT 0x16 269#define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_OFF__SHIFT 0x17 270#define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_OFF__SHIFT 0x18 271#define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_OFF__SHIFT 0x19 272#define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_OFF__SHIFT 0x1a 273#define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_OFF__SHIFT 0x1b 274#define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_OFF__SHIFT 0x1c 275#define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_OFF__SHIFT 0x1d 276#define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_OFF__SHIFT 0x1e 277#define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_OFF__SHIFT 0x1f 278#define VCE_UENC_CLOCK_GATING__CLOCK_ON_DELAY_MASK 0x0000000FL 279#define VCE_UENC_CLOCK_GATING__CLOCK_OFF_DELAY_MASK 0x00000FF0L 280#define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_ON_MASK 0x00001000L 281#define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_ON_MASK 0x00002000L 282#define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_ON_MASK 0x00004000L 283#define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_ON_MASK 0x00008000L 284#define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_ON_MASK 0x00010000L 285#define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_ON_MASK 0x00020000L 286#define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_ON_MASK 0x00040000L 287#define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_ON_MASK 0x00080000L 288#define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_ON_MASK 0x00100000L 289#define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_ON_MASK 0x00200000L 290#define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_OFF_MASK 0x00400000L 291#define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_OFF_MASK 0x00800000L 292#define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_OFF_MASK 0x01000000L 293#define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_OFF_MASK 0x02000000L 294#define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_OFF_MASK 0x04000000L 295#define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_OFF_MASK 0x08000000L 296#define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_OFF_MASK 0x10000000L 297#define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_OFF_MASK 0x20000000L 298#define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_OFF_MASK 0x40000000L 299#define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_OFF_MASK 0x80000000L 300//VCE_UENC_REG_CLOCK_GATING 301#define VCE_UENC_REG_CLOCK_GATING__MIFREGCLK_FORCE_ON__SHIFT 0x0 302#define VCE_UENC_REG_CLOCK_GATING__IMEREGCLK_FORCE_ON__SHIFT 0x1 303#define VCE_UENC_REG_CLOCK_GATING__FMEREGCLK_FORCE_ON__SHIFT 0x2 304#define VCE_UENC_REG_CLOCK_GATING__TBEREGCLK_FORCE_ON__SHIFT 0x3 305#define VCE_UENC_REG_CLOCK_GATING__DBFREGCLK_FORCE_ON__SHIFT 0x4 306#define VCE_UENC_REG_CLOCK_GATING__ENTREGCLK_FORCE_ON__SHIFT 0x5 307#define VCE_UENC_REG_CLOCK_GATING__LCMREGCLK_FORCE_ON__SHIFT 0x6 308#define VCE_UENC_REG_CLOCK_GATING__RESERVED__SHIFT 0x7 309#define VCE_UENC_REG_CLOCK_GATING__AVMREGCLK_FORCE_ON__SHIFT 0x8 310#define VCE_UENC_REG_CLOCK_GATING__DCAPREGCLK_FORCE_ON__SHIFT 0x9 311#define VCE_UENC_REG_CLOCK_GATING__VEPREGCLK_FORCE_ON__SHIFT 0xa 312#define VCE_UENC_REG_CLOCK_GATING__MIFREGCLK_FORCE_ON_MASK 0x00000001L 313#define VCE_UENC_REG_CLOCK_GATING__IMEREGCLK_FORCE_ON_MASK 0x00000002L 314#define VCE_UENC_REG_CLOCK_GATING__FMEREGCLK_FORCE_ON_MASK 0x00000004L 315#define VCE_UENC_REG_CLOCK_GATING__TBEREGCLK_FORCE_ON_MASK 0x00000008L 316#define VCE_UENC_REG_CLOCK_GATING__DBFREGCLK_FORCE_ON_MASK 0x00000010L 317#define VCE_UENC_REG_CLOCK_GATING__ENTREGCLK_FORCE_ON_MASK 0x00000020L 318#define VCE_UENC_REG_CLOCK_GATING__LCMREGCLK_FORCE_ON_MASK 0x00000040L 319#define VCE_UENC_REG_CLOCK_GATING__RESERVED_MASK 0x00000080L 320#define VCE_UENC_REG_CLOCK_GATING__AVMREGCLK_FORCE_ON_MASK 0x00000100L 321#define VCE_UENC_REG_CLOCK_GATING__DCAPREGCLK_FORCE_ON_MASK 0x00000200L 322#define VCE_UENC_REG_CLOCK_GATING__VEPREGCLK_FORCE_ON_MASK 0x00000400L 323//VCE_UENC_CLOCK_GATING_2 324#define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_ON__SHIFT 0x1 325#define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_OFF__SHIFT 0x10 326#define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_ON_MASK 0x00000002L 327#define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_OFF_MASK 0x00010000L 328 329 330// addressBlock: vce0_vce_sclk_dec 331//VCE_LMI_VCPU_CACHE_40BIT_BAR 332#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x0 333#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xFFFFFFFFL 334//VCE_LMI_CTRL2 335#define VCE_LMI_CTRL2__STALL_ARB__SHIFT 0x1 336#define VCE_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 337#define VCE_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 338#define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 339#define VCE_LMI_CTRL2__STALL_ARB_MASK 0x00000002L 340#define VCE_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L 341#define VCE_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L 342#define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L 343//VCE_LMI_SWAP_CNTL3 344#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP__SHIFT 0x0 345#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_TRAN__SHIFT 0x14 346#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_URG__SHIFT 0x1a 347#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP_MASK 0x00000003L 348#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_TRAN_MASK 0x00100000L 349#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_URG_MASK 0x04000000L 350//VCE_LMI_CTRL 351#define VCE_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 352#define VCE_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 353#define VCE_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 354#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 355#define VCE_LMI_CTRL__MIF_DATA_COHERENCY_EN__SHIFT 0x16 356#define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_EN__SHIFT 0x17 357#define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_RESET__SHIFT 0x18 358#define VCE_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L 359#define VCE_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L 360#define VCE_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L 361#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L 362#define VCE_LMI_CTRL__MIF_DATA_COHERENCY_EN_MASK 0x00400000L 363#define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_EN_MASK 0x00800000L 364#define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_RESET_MASK 0x01000000L 365//VCE_LMI_SWAP_CNTL 366#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x0 367#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x2 368#define VCE_LMI_SWAP_CNTL__WR_MC_CID_TRAN__SHIFT 0x14 369#define VCE_LMI_SWAP_CNTL__WR_MC_CID_URG__SHIFT 0x1a 370#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000003L 371#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x00003FFCL 372#define VCE_LMI_SWAP_CNTL__WR_MC_CID_TRAN_MASK 0x03F00000L 373#define VCE_LMI_SWAP_CNTL__WR_MC_CID_URG_MASK 0xFC000000L 374//VCE_LMI_SWAP_CNTL1 375#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x0 376#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x2 377#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_TRAN__SHIFT 0x14 378#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_URG__SHIFT 0x1a 379#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x00000003L 380#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x00003FFCL 381#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_TRAN_MASK 0x03F00000L 382#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_URG_MASK 0xFC000000L 383//VCE_LMI_SWAP_CNTL2 384#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP__SHIFT 0x0 385#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_TRAN__SHIFT 0x14 386#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_URG__SHIFT 0x1a 387#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP_MASK 0x000000FFL 388#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_TRAN_MASK 0x00F00000L 389#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_URG_MASK 0x3C000000L 390//VCE_LMI_CACHE_CTRL 391#define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x0 392#define VCE_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x1 393#define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x00000001L 394#define VCE_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x00000002L 395//VCE_LMI_VCPU_CACHE_64BIT_BAR0 396#define VCE_LMI_VCPU_CACHE_64BIT_BAR0__BAR__SHIFT 0x0 397#define VCE_LMI_VCPU_CACHE_64BIT_BAR0__BAR_MASK 0x000000FFL 398//VCE_LMI_VCPU_CACHE_64BIT_BAR1 399#define VCE_LMI_VCPU_CACHE_64BIT_BAR1__BAR__SHIFT 0x0 400#define VCE_LMI_VCPU_CACHE_64BIT_BAR1__BAR_MASK 0x000000FFL 401//VCE_LMI_VCPU_CACHE_64BIT_BAR2 402#define VCE_LMI_VCPU_CACHE_64BIT_BAR2__BAR__SHIFT 0x0 403#define VCE_LMI_VCPU_CACHE_64BIT_BAR2__BAR_MASK 0x000000FFL 404//VCE_LMI_VCPU_CACHE_64BIT_BAR3 405#define VCE_LMI_VCPU_CACHE_64BIT_BAR3__BAR__SHIFT 0x0 406#define VCE_LMI_VCPU_CACHE_64BIT_BAR3__BAR_MASK 0x000000FFL 407//VCE_LMI_VCPU_CACHE_64BIT_BAR4 408#define VCE_LMI_VCPU_CACHE_64BIT_BAR4__BAR__SHIFT 0x0 409#define VCE_LMI_VCPU_CACHE_64BIT_BAR4__BAR_MASK 0x000000FFL 410//VCE_LMI_VCPU_CACHE_64BIT_BAR5 411#define VCE_LMI_VCPU_CACHE_64BIT_BAR5__BAR__SHIFT 0x0 412#define VCE_LMI_VCPU_CACHE_64BIT_BAR5__BAR_MASK 0x000000FFL 413//VCE_LMI_VCPU_CACHE_64BIT_BAR6 414#define VCE_LMI_VCPU_CACHE_64BIT_BAR6__BAR__SHIFT 0x0 415#define VCE_LMI_VCPU_CACHE_64BIT_BAR6__BAR_MASK 0x000000FFL 416//VCE_LMI_VCPU_CACHE_64BIT_BAR7 417#define VCE_LMI_VCPU_CACHE_64BIT_BAR7__BAR__SHIFT 0x0 418#define VCE_LMI_VCPU_CACHE_64BIT_BAR7__BAR_MASK 0x000000FFL 419//VCE_LMI_VCPU_CACHE_40BIT_BAR0 420#define VCE_LMI_VCPU_CACHE_40BIT_BAR0__BAR__SHIFT 0x0 421#define VCE_LMI_VCPU_CACHE_40BIT_BAR0__BAR_MASK 0xFFFFFFFFL 422//VCE_LMI_VCPU_CACHE_40BIT_BAR1 423#define VCE_LMI_VCPU_CACHE_40BIT_BAR1__BAR__SHIFT 0x0 424#define VCE_LMI_VCPU_CACHE_40BIT_BAR1__BAR_MASK 0xFFFFFFFFL 425//VCE_LMI_VCPU_CACHE_40BIT_BAR2 426#define VCE_LMI_VCPU_CACHE_40BIT_BAR2__BAR__SHIFT 0x0 427#define VCE_LMI_VCPU_CACHE_40BIT_BAR2__BAR_MASK 0xFFFFFFFFL 428//VCE_LMI_VCPU_CACHE_40BIT_BAR3 429#define VCE_LMI_VCPU_CACHE_40BIT_BAR3__BAR__SHIFT 0x0 430#define VCE_LMI_VCPU_CACHE_40BIT_BAR3__BAR_MASK 0xFFFFFFFFL 431//VCE_LMI_VCPU_CACHE_40BIT_BAR4 432#define VCE_LMI_VCPU_CACHE_40BIT_BAR4__BAR__SHIFT 0x0 433#define VCE_LMI_VCPU_CACHE_40BIT_BAR4__BAR_MASK 0xFFFFFFFFL 434//VCE_LMI_VCPU_CACHE_40BIT_BAR5 435#define VCE_LMI_VCPU_CACHE_40BIT_BAR5__BAR__SHIFT 0x0 436#define VCE_LMI_VCPU_CACHE_40BIT_BAR5__BAR_MASK 0xFFFFFFFFL 437//VCE_LMI_VCPU_CACHE_40BIT_BAR6 438#define VCE_LMI_VCPU_CACHE_40BIT_BAR6__BAR__SHIFT 0x0 439#define VCE_LMI_VCPU_CACHE_40BIT_BAR6__BAR_MASK 0xFFFFFFFFL 440//VCE_LMI_VCPU_CACHE_40BIT_BAR7 441#define VCE_LMI_VCPU_CACHE_40BIT_BAR7__BAR__SHIFT 0x0 442#define VCE_LMI_VCPU_CACHE_40BIT_BAR7__BAR_MASK 0xFFFFFFFFL 443 444 445// addressBlock: vce0_mmsch_dec 446//VCE_MMSCH_VF_VMID 447#define VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0 448#define VCE_MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x4 449#define VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000000FL 450#define VCE_MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000000F0L 451//VCE_MMSCH_VF_CTX_ADDR_LO 452#define VCE_MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6 453#define VCE_MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L 454//VCE_MMSCH_VF_CTX_ADDR_HI 455#define VCE_MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0 456#define VCE_MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL 457//VCE_MMSCH_VF_CTX_SIZE 458#define VCE_MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0 459#define VCE_MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL 460//VCE_MMSCH_VF_GPCOM_ADDR_LO 461#define VCE_MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6 462#define VCE_MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L 463//VCE_MMSCH_VF_GPCOM_ADDR_HI 464#define VCE_MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0 465#define VCE_MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL 466//VCE_MMSCH_VF_GPCOM_SIZE 467#define VCE_MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0 468#define VCE_MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL 469//VCE_MMSCH_VF_MAILBOX_HOST 470#define VCE_MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0 471#define VCE_MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL 472//VCE_MMSCH_VF_MAILBOX_RESP 473#define VCE_MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0 474#define VCE_MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL 475 476 477// addressBlock: vce0_vce_rb_pg_dec 478//VCE_HW_VERSION 479#define VCE_HW_VERSION__VCE_VERSION__SHIFT 0x0 480#define VCE_HW_VERSION__VCE_CONFIGURATION__SHIFT 0x8 481#define VCE_HW_VERSION__VCE_INSTANCE_ID__SHIFT 0xa 482#define VCE_HW_VERSION__VCE_VERSION_MASK 0x000000FFL 483#define VCE_HW_VERSION__VCE_CONFIGURATION_MASK 0x00000300L 484#define VCE_HW_VERSION__VCE_INSTANCE_ID_MASK 0x00000C00L 485 486 487 488#endif
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