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vce_4_0_default.h
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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_default.h
1/* 2 * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _vce_4_0_DEFAULT_HEADER 22#define _vce_4_0_DEFAULT_HEADER 23 24 25// addressBlock: vce0_vce_dec 26#define mmVCE_STATUS_DEFAULT 0x00000000 27#define mmVCE_VCPU_CNTL_DEFAULT 0x00200000 28#define mmVCE_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000 29#define mmVCE_VCPU_CACHE_SIZE0_DEFAULT 0x00000000 30#define mmVCE_VCPU_CACHE_OFFSET1_DEFAULT 0x00000000 31#define mmVCE_VCPU_CACHE_SIZE1_DEFAULT 0x00000000 32#define mmVCE_VCPU_CACHE_OFFSET2_DEFAULT 0x00000000 33#define mmVCE_VCPU_CACHE_SIZE2_DEFAULT 0x00000000 34#define mmVCE_VCPU_CACHE_OFFSET3_DEFAULT 0x00000000 35#define mmVCE_VCPU_CACHE_SIZE3_DEFAULT 0x00000000 36#define mmVCE_VCPU_CACHE_OFFSET4_DEFAULT 0x00000000 37#define mmVCE_VCPU_CACHE_SIZE4_DEFAULT 0x00000000 38#define mmVCE_VCPU_CACHE_OFFSET5_DEFAULT 0x00000000 39#define mmVCE_VCPU_CACHE_SIZE5_DEFAULT 0x00000000 40#define mmVCE_VCPU_CACHE_OFFSET6_DEFAULT 0x00000000 41#define mmVCE_VCPU_CACHE_SIZE6_DEFAULT 0x00000000 42#define mmVCE_VCPU_CACHE_OFFSET7_DEFAULT 0x00000000 43#define mmVCE_VCPU_CACHE_SIZE7_DEFAULT 0x00000000 44#define mmVCE_VCPU_CACHE_OFFSET8_DEFAULT 0x00000000 45#define mmVCE_VCPU_CACHE_SIZE8_DEFAULT 0x00000000 46#define mmVCE_SOFT_RESET_DEFAULT 0x00000001 47#define mmVCE_RB_BASE_LO2_DEFAULT 0x00000000 48#define mmVCE_RB_BASE_HI2_DEFAULT 0x00000000 49#define mmVCE_RB_SIZE2_DEFAULT 0x00000000 50#define mmVCE_RB_RPTR2_DEFAULT 0x00000000 51#define mmVCE_RB_WPTR2_DEFAULT 0x00000000 52#define mmVCE_RB_BASE_LO_DEFAULT 0x00000000 53#define mmVCE_RB_BASE_HI_DEFAULT 0x00000000 54#define mmVCE_RB_SIZE_DEFAULT 0x00000000 55#define mmVCE_RB_RPTR_DEFAULT 0x00000000 56#define mmVCE_RB_WPTR_DEFAULT 0x00000000 57#define mmVCE_RB_ARB_CTRL_DEFAULT 0x00010000 58#define mmVCE_CLOCK_GATING_A_DEFAULT 0x00000040 59#define mmVCE_CLOCK_GATING_B_DEFAULT 0x01ef0100 60#define mmVCE_RB_BASE_LO3_DEFAULT 0x00000000 61#define mmVCE_RB_BASE_HI3_DEFAULT 0x00000000 62#define mmVCE_RB_SIZE3_DEFAULT 0x00000000 63#define mmVCE_RB_RPTR3_DEFAULT 0x00000000 64#define mmVCE_RB_WPTR3_DEFAULT 0x00000000 65#define mmVCE_SYS_INT_EN_DEFAULT 0x00000000 66#define mmVCE_SYS_INT_ACK_DEFAULT 0x00000000 67#define mmVCE_SYS_INT_STATUS_DEFAULT 0x00000000 68 69 70// addressBlock: vce0_ctl_dec 71#define mmVCE_UENC_CLOCK_GATING_DEFAULT 0xffc00040 72#define mmVCE_UENC_REG_CLOCK_GATING_DEFAULT 0x000007ff 73#define mmVCE_UENC_CLOCK_GATING_2_DEFAULT 0x00010000 74 75 76// addressBlock: vce0_vce_sclk_dec 77#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR_DEFAULT 0x00000000 78#define mmVCE_LMI_CTRL2_DEFAULT 0x00000000 79#define mmVCE_LMI_SWAP_CNTL3_DEFAULT 0x00000000 80#define mmVCE_LMI_CTRL_DEFAULT 0x00104000 81#define mmVCE_LMI_STATUS_DEFAULT 0x00003f7f 82#define mmVCE_LMI_VM_CTRL_DEFAULT 0x00000000 83#define mmVCE_LMI_SWAP_CNTL_DEFAULT 0x00000000 84#define mmVCE_LMI_SWAP_CNTL1_DEFAULT 0x00000000 85#define mmVCE_LMI_SWAP_CNTL2_DEFAULT 0x00000000 86#define mmVCE_LMI_CACHE_CTRL_DEFAULT 0x00000000 87#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0_DEFAULT 0x00000000 88#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1_DEFAULT 0x00000000 89#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2_DEFAULT 0x00000000 90#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3_DEFAULT 0x00000000 91#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4_DEFAULT 0x00000000 92#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5_DEFAULT 0x00000000 93#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6_DEFAULT 0x00000000 94#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7_DEFAULT 0x00000000 95#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0_DEFAULT 0x00000000 96#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1_DEFAULT 0x00000000 97#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2_DEFAULT 0x00000000 98#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3_DEFAULT 0x00000000 99#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4_DEFAULT 0x00000000 100#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5_DEFAULT 0x00000000 101#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6_DEFAULT 0x00000000 102#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7_DEFAULT 0x00000000 103 104 105// addressBlock: vce0_mmsch_dec 106#define mmVCE_MMSCH_VF_VMID_DEFAULT 0x00000000 107#define mmVCE_MMSCH_VF_CTX_ADDR_LO_DEFAULT 0x00000000 108#define mmVCE_MMSCH_VF_CTX_ADDR_HI_DEFAULT 0x00000000 109#define mmVCE_MMSCH_VF_CTX_SIZE_DEFAULT 0x00000000 110#define mmVCE_MMSCH_VF_GPCOM_ADDR_LO_DEFAULT 0x00000000 111#define mmVCE_MMSCH_VF_GPCOM_ADDR_HI_DEFAULT 0x00000000 112#define mmVCE_MMSCH_VF_GPCOM_SIZE_DEFAULT 0x00000000 113#define mmVCE_MMSCH_VF_MAILBOX_HOST_DEFAULT 0x00000000 114#define mmVCE_MMSCH_VF_MAILBOX_RESP_DEFAULT 0x00000000 115 116 117// addressBlock: vce0_vce_rb_pg_dec 118#define mmVCE_HW_VERSION_DEFAULT 0x00000000 119 120 121 122#endif
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