vce_1_0_sh_mask.h

  1/*
  2 *
  3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
  4 *
  5 * Permission is hereby granted, free of charge, to any person obtaining a
  6 * copy of this software and associated documentation files (the "Software"),
  7 * to deal in the Software without restriction, including without limitation
  8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9 * and/or sell copies of the Software, and to permit persons to whom the
 10 * Software is furnished to do so, subject to the following conditions:
 11 *
 12 * The above copyright notice and this permission notice shall be included
 13 * in all copies or substantial portions of the Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 21 */
 22
 23#ifndef VCE_1_0_SH_MASK_H
 24#define VCE_1_0_SH_MASK_H
 25
 26#define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x00000001L
 27#define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x00000000
 28#define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L
 29#define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x00000008
 30#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L
 31#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x00000015
 32#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x00003ffcL
 33#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x00000002
 34#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x00000003L
 35#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x00000000
 36#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000003L
 37#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x00000000
 38#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x00003ffcL
 39#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x00000002
 40#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xffffffffL
 41#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x00000000
 42#define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xffffffffL
 43#define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x00000000
 44#define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xffffffffL
 45#define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x00000000
 46#define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xffffffc0L
 47#define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x00000006
 48#define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xffffffc0L
 49#define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x00000006
 50#define VCE_RB_RPTR2__RB_RPTR_MASK 0x007ffff0L
 51#define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x00000004
 52#define VCE_RB_RPTR__RB_RPTR_MASK 0x007ffff0L
 53#define VCE_RB_RPTR__RB_RPTR__SHIFT 0x00000004
 54#define VCE_RB_SIZE2__RB_SIZE_MASK 0x007ffff0L
 55#define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x00000004
 56#define VCE_RB_SIZE__RB_SIZE_MASK 0x007ffff0L
 57#define VCE_RB_SIZE__RB_SIZE__SHIFT 0x00000004
 58#define VCE_RB_WPTR2__RB_WPTR_MASK 0x007ffff0L
 59#define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x00000004
 60#define VCE_RB_WPTR__RB_WPTR_MASK 0x007ffff0L
 61#define VCE_RB_WPTR__RB_WPTR__SHIFT 0x00000004
 62#define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x00000001L
 63#define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x00000000
 64#define VCE_SOFT_RESET__FME_SOFT_RESET_MASK 0x00000004L
 65#define VCE_SOFT_RESET__FME_SOFT_RESET__SHIFT 0x00000002
 66#define VCE_STATUS__JOB_BUSY_MASK 0x00000001L
 67#define VCE_STATUS__JOB_BUSY__SHIFT 0x00000000
 68#define VCE_STATUS__UENC_BUSY_MASK 0x00000100L
 69#define VCE_STATUS__UENC_BUSY__SHIFT 0x00000008
 70#define VCE_STATUS__VCPU_REPORT_MASK 0x000000feL
 71#define VCE_STATUS__VCPU_REPORT__SHIFT 0x00000001
 72#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x00000008L
 73#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x00000003
 74#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x00000008L
 75#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x00000003
 76#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x00000008L
 77#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x00000003
 78#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK 0x00000002L
 79#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON__SHIFT 0x00000001
 80#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK 0x00000004L
 81#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON__SHIFT 0x00000002
 82#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK 0x00000001L
 83#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON__SHIFT 0x00000000
 84#define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0x0fffffffL
 85#define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x00000000
 86#define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0x0fffffffL
 87#define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x00000000
 88#define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0x0fffffffL
 89#define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x00000000
 90#define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0x00ffffffL
 91#define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x00000000
 92#define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0x00ffffffL
 93#define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x00000000
 94#define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0x00ffffffL
 95#define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x00000000
 96#define VCE_VCPU_CNTL__CLK_EN_MASK 0x00000001L
 97#define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x00000000
 98#define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00040000L
 99#define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x00000012
100#define VCE_CLOCK_GATING_A__CGC_DYN_CLOCK_MODE_MASK 0x00010000
101#define VCE_CLOCK_GATING_A__CGC_DYN_CLOCK_MODE_SHIFT 0x00000010
102#define VCE_FW_REG_STATUS__BUSY_MASK 0x0000001
103#define VCE_FW_REG_STATUS__BUSY__SHIFT 0x0000001
104#define VCE_FW_REG_STATUS__PASS_MASK 0x0000008
105#define VCE_FW_REG_STATUS__PASS__SHIFT 0x0000003
106#define VCE_FW_REG_STATUS__DONE_MASK 0x0000800
107#define VCE_FW_REG_STATUS__DONE__SHIFT 0x000000b
108
109#endif