FILE
uvd_7_0_offset.h
File preview with syntax highlighting.
linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h
1/* 2 * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _uvd_7_0_OFFSET_HEADER 22#define _uvd_7_0_OFFSET_HEADER 23 24 25 26// addressBlock: uvd0_uvd_pg_dec 27// base address: 0x1fb00 28#define mmUVD_POWER_STATUS 0x00c4 29#define mmUVD_POWER_STATUS_BASE_IDX 1 30#define mmUVD_DPG_RBC_RB_CNTL 0x00cb 31#define mmUVD_DPG_RBC_RB_CNTL_BASE_IDX 1 32#define mmUVD_DPG_RBC_RB_BASE_LOW 0x00cc 33#define mmUVD_DPG_RBC_RB_BASE_LOW_BASE_IDX 1 34#define mmUVD_DPG_RBC_RB_BASE_HIGH 0x00cd 35#define mmUVD_DPG_RBC_RB_BASE_HIGH_BASE_IDX 1 36#define mmUVD_DPG_RBC_RB_WPTR_CNTL 0x00ce 37#define mmUVD_DPG_RBC_RB_WPTR_CNTL_BASE_IDX 1 38#define mmUVD_DPG_RBC_RB_RPTR 0x00cf 39#define mmUVD_DPG_RBC_RB_RPTR_BASE_IDX 1 40#define mmUVD_DPG_RBC_RB_WPTR 0x00d0 41#define mmUVD_DPG_RBC_RB_WPTR_BASE_IDX 1 42#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x00e5 43#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 44#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x00e6 45#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 46#define mmUVD_DPG_VCPU_CACHE_OFFSET0 0x00e7 47#define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1 48 49 50// addressBlock: uvd0_uvdnpdec 51// base address: 0x20000 52#define mmUVD_JPEG_ADDR_CONFIG 0x021f 53#define mmUVD_JPEG_ADDR_CONFIG_BASE_IDX 1 54#define mmUVD_GPCOM_VCPU_CMD 0x03c3 55#define mmUVD_GPCOM_VCPU_CMD_BASE_IDX 1 56#define mmUVD_GPCOM_VCPU_DATA0 0x03c4 57#define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 58#define mmUVD_GPCOM_VCPU_DATA1 0x03c5 59#define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 60#define mmUVD_UDEC_ADDR_CONFIG 0x03d3 61#define mmUVD_UDEC_ADDR_CONFIG_BASE_IDX 1 62#define mmUVD_UDEC_DB_ADDR_CONFIG 0x03d4 63#define mmUVD_UDEC_DB_ADDR_CONFIG_BASE_IDX 1 64#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x03d5 65#define mmUVD_UDEC_DBW_ADDR_CONFIG_BASE_IDX 1 66#define mmUVD_SUVD_CGC_GATE 0x03e4 67#define mmUVD_SUVD_CGC_GATE_BASE_IDX 1 68#define mmUVD_SUVD_CGC_CTRL 0x03e6 69#define mmUVD_SUVD_CGC_CTRL_BASE_IDX 1 70#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x03ec 71#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1 72#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x03ed 73#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1 74#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x03f0 75#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1 76#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x03f1 77#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1 78#define mmUVD_POWER_STATUS_U 0x03fd 79#define mmUVD_POWER_STATUS_U_BASE_IDX 1 80#define mmUVD_NO_OP 0x03ff 81#define mmUVD_NO_OP_BASE_IDX 1 82#define mmUVD_GP_SCRATCH8 0x040a 83#define mmUVD_GP_SCRATCH8_BASE_IDX 1 84#define mmUVD_RB_BASE_LO2 0x0421 85#define mmUVD_RB_BASE_LO2_BASE_IDX 1 86#define mmUVD_RB_BASE_HI2 0x0422 87#define mmUVD_RB_BASE_HI2_BASE_IDX 1 88#define mmUVD_RB_SIZE2 0x0423 89#define mmUVD_RB_SIZE2_BASE_IDX 1 90#define mmUVD_RB_RPTR2 0x0424 91#define mmUVD_RB_RPTR2_BASE_IDX 1 92#define mmUVD_RB_WPTR2 0x0425 93#define mmUVD_RB_WPTR2_BASE_IDX 1 94#define mmUVD_RB_BASE_LO 0x0426 95#define mmUVD_RB_BASE_LO_BASE_IDX 1 96#define mmUVD_RB_BASE_HI 0x0427 97#define mmUVD_RB_BASE_HI_BASE_IDX 1 98#define mmUVD_RB_SIZE 0x0428 99#define mmUVD_RB_SIZE_BASE_IDX 1 100#define mmUVD_RB_RPTR 0x0429 101#define mmUVD_RB_RPTR_BASE_IDX 1 102#define mmUVD_RB_WPTR 0x042a 103#define mmUVD_RB_WPTR_BASE_IDX 1 104#define mmUVD_JRBC_RB_RPTR 0x0457 105#define mmUVD_JRBC_RB_RPTR_BASE_IDX 1 106#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x045e 107#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 108#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x045f 109#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 110#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0466 111#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 112#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x0467 113#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1 114#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x0468 115#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 116#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x0469 117#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1 118 119 120// addressBlock: uvd0_uvddec 121// base address: 0x20c00 122#define mmUVD_SEMA_CNTL 0x0500 123#define mmUVD_SEMA_CNTL_BASE_IDX 1 124#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0503 125#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 1 126#define mmUVD_JRBC_RB_WPTR 0x0509 127#define mmUVD_JRBC_RB_WPTR_BASE_IDX 1 128#define mmUVD_RB_RPTR3 0x051b 129#define mmUVD_RB_RPTR3_BASE_IDX 1 130#define mmUVD_RB_WPTR3 0x051c 131#define mmUVD_RB_WPTR3_BASE_IDX 1 132#define mmUVD_RB_BASE_LO3 0x051d 133#define mmUVD_RB_BASE_LO3_BASE_IDX 1 134#define mmUVD_RB_BASE_HI3 0x051e 135#define mmUVD_RB_BASE_HI3_BASE_IDX 1 136#define mmUVD_RB_SIZE3 0x051f 137#define mmUVD_RB_SIZE3_BASE_IDX 1 138#define mmJPEG_CGC_GATE 0x0526 139#define mmJPEG_CGC_GATE_BASE_IDX 1 140#define mmUVD_CTX_INDEX 0x0528 141#define mmUVD_CTX_INDEX_BASE_IDX 1 142#define mmUVD_CTX_DATA 0x0529 143#define mmUVD_CTX_DATA_BASE_IDX 1 144#define mmUVD_CGC_GATE 0x052a 145#define mmUVD_CGC_GATE_BASE_IDX 1 146#define mmUVD_CGC_CTRL 0x052c 147#define mmUVD_CGC_CTRL_BASE_IDX 1 148#define mmUVD_GP_SCRATCH4 0x0538 149#define mmUVD_GP_SCRATCH4_BASE_IDX 1 150#define mmUVD_LMI_CTRL2 0x053d 151#define mmUVD_LMI_CTRL2_BASE_IDX 1 152#define mmUVD_MASTINT_EN 0x0540 153#define mmUVD_MASTINT_EN_BASE_IDX 1 154#define mmUVD_FW_STATUS 0x0557 155#define mmUVD_FW_STATUS_BASE_IDX 1 156#define mmJPEG_CGC_CTRL 0x0565 157#define mmJPEG_CGC_CTRL_BASE_IDX 1 158#define mmUVD_LMI_CTRL 0x0566 159#define mmUVD_LMI_CTRL_BASE_IDX 1 160#define mmUVD_LMI_VM_CTRL 0x0568 161#define mmUVD_LMI_VM_CTRL_BASE_IDX 1 162#define mmUVD_LMI_SWAP_CNTL 0x056d 163#define mmUVD_LMI_SWAP_CNTL_BASE_IDX 1 164#define mmUVD_MP_SWAP_CNTL 0x056f 165#define mmUVD_MP_SWAP_CNTL_BASE_IDX 1 166#define mmUVD_MPC_SET_MUXA0 0x0579 167#define mmUVD_MPC_SET_MUXA0_BASE_IDX 1 168#define mmUVD_MPC_SET_MUXA1 0x057a 169#define mmUVD_MPC_SET_MUXA1_BASE_IDX 1 170#define mmUVD_MPC_SET_MUXB0 0x057b 171#define mmUVD_MPC_SET_MUXB0_BASE_IDX 1 172#define mmUVD_MPC_SET_MUXB1 0x057c 173#define mmUVD_MPC_SET_MUXB1_BASE_IDX 1 174#define mmUVD_MPC_SET_MUX 0x057d 175#define mmUVD_MPC_SET_MUX_BASE_IDX 1 176#define mmUVD_MPC_SET_ALU 0x057e 177#define mmUVD_MPC_SET_ALU_BASE_IDX 1 178#define mmUVD_VCPU_CACHE_OFFSET0 0x0582 179#define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1 180#define mmUVD_VCPU_CACHE_SIZE0 0x0583 181#define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX 1 182#define mmUVD_VCPU_CACHE_OFFSET1 0x0584 183#define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1 184#define mmUVD_VCPU_CACHE_SIZE1 0x0585 185#define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX 1 186#define mmUVD_VCPU_CACHE_OFFSET2 0x0586 187#define mmUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1 188#define mmUVD_VCPU_CACHE_SIZE2 0x0587 189#define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX 1 190#define mmUVD_VCPU_CNTL 0x0598 191#define mmUVD_VCPU_CNTL_BASE_IDX 1 192#define mmUVD_SOFT_RESET 0x05a0 193#define mmUVD_SOFT_RESET_BASE_IDX 1 194#define mmUVD_LMI_RBC_IB_VMID 0x05a1 195#define mmUVD_LMI_RBC_IB_VMID_BASE_IDX 1 196#define mmUVD_RBC_IB_SIZE 0x05a2 197#define mmUVD_RBC_IB_SIZE_BASE_IDX 1 198#define mmUVD_RBC_RB_RPTR 0x05a4 199#define mmUVD_RBC_RB_RPTR_BASE_IDX 1 200#define mmUVD_RBC_RB_WPTR 0x05a5 201#define mmUVD_RBC_RB_WPTR_BASE_IDX 1 202#define mmUVD_RBC_RB_WPTR_CNTL 0x05a6 203#define mmUVD_RBC_RB_WPTR_CNTL_BASE_IDX 1 204#define mmUVD_RBC_RB_CNTL 0x05a9 205#define mmUVD_RBC_RB_CNTL_BASE_IDX 1 206#define mmUVD_RBC_RB_RPTR_ADDR 0x05aa 207#define mmUVD_RBC_RB_RPTR_ADDR_BASE_IDX 1 208#define mmUVD_STATUS 0x05af 209#define mmUVD_STATUS_BASE_IDX 1 210#define mmUVD_SEMA_TIMEOUT_STATUS 0x05b0 211#define mmUVD_SEMA_TIMEOUT_STATUS_BASE_IDX 1 212#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x05b1 213#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 214#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x05b2 215#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX 1 216#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x05b3 217#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 218#define mmUVD_CONTEXT_ID 0x05bd 219#define mmUVD_CONTEXT_ID_BASE_IDX 1 220#define mmUVD_CONTEXT_ID2 0x05bf 221#define mmUVD_CONTEXT_ID2_BASE_IDX 1 222 223 224 225#endif
~/
Read-only file preview.