FILE
thm_9_0_sh_mask.h
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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h
1/* 2 * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _thm_9_0_SH_MASK_HEADER 22#define _thm_9_0_SH_MASK_HEADER 23 24 25// addressBlock: thm_thm_SmuThmDec 26//THM_TCON_CUR_TMP 27#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0 28#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5 29#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7 30#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8 31#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10 32#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12 33#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13 34#define THM_TCON_CUR_TMP__MCM_EN__SHIFT 0x14 35#define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT 0x15 36#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK 0x0000001FL 37#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK 0x00000060L 38#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK 0x00000080L 39#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK 0x00001F00L 40#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK 0x00030000L 41#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK 0x00040000L 42#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK 0x00080000L 43#define THM_TCON_CUR_TMP__MCM_EN_MASK 0x00100000L 44#define THM_TCON_CUR_TMP__CUR_TEMP_MASK 0xFFE00000L 45//THM_TCON_HTC 46#define THM_TCON_HTC__HTC_EN__SHIFT 0x0 47#define THM_TCON_HTC__EXTERNAL_PROCHOT__SHIFT 0x2 48#define THM_TCON_HTC__INTERNAL_PROCHOT__SHIFT 0x3 49#define THM_TCON_HTC__HTC_ACTIVE__SHIFT 0x4 50#define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT 0x5 51#define THM_TCON_HTC__HTC_DIAG__SHIFT 0x8 52#define THM_TCON_HTC__DIS_PROCHOT_PIN__SHIFT 0x9 53#define THM_TCON_HTC__HTC_TO_IH_EN__SHIFT 0xa 54#define THM_TCON_HTC__PROCHOT_TO_IH_EN__SHIFT 0xb 55#define THM_TCON_HTC__PROCHOT_EVENT_SRC__SHIFT 0xc 56#define THM_TCON_HTC__HTC_TMP_LMT__SHIFT 0x10 57#define THM_TCON_HTC__HTC_HYST_LMT__SHIFT 0x17 58#define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT 0x1b 59#define THM_TCON_HTC__HTC_EN_MASK 0x00000001L 60#define THM_TCON_HTC__EXTERNAL_PROCHOT_MASK 0x00000004L 61#define THM_TCON_HTC__INTERNAL_PROCHOT_MASK 0x00000008L 62#define THM_TCON_HTC__HTC_ACTIVE_MASK 0x00000010L 63#define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK 0x00000020L 64#define THM_TCON_HTC__HTC_DIAG_MASK 0x00000100L 65#define THM_TCON_HTC__DIS_PROCHOT_PIN_MASK 0x00000200L 66#define THM_TCON_HTC__HTC_TO_IH_EN_MASK 0x00000400L 67#define THM_TCON_HTC__PROCHOT_TO_IH_EN_MASK 0x00000800L 68#define THM_TCON_HTC__PROCHOT_EVENT_SRC_MASK 0x00007000L 69#define THM_TCON_HTC__HTC_TMP_LMT_MASK 0x007F0000L 70#define THM_TCON_HTC__HTC_HYST_LMT_MASK 0x07800000L 71#define THM_TCON_HTC__HTC_SLEW_SEL_MASK 0x18000000L 72//THM_TCON_THERM_TRIP 73#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY__SHIFT 0x0 74#define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1 75#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED__SHIFT 0x2 76#define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3 77#define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4 78#define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5 79#define THM_TCON_THERM_TRIP__THERM_TP_LMT__SHIFT 0x6 80#define THM_TCON_THERM_TRIP__RSVD3__SHIFT 0xe 81#define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f 82#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY_MASK 0x00000001L 83#define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x00000002L 84#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED_MASK 0x00000004L 85#define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x00000008L 86#define THM_TCON_THERM_TRIP__RSVD2_MASK 0x00000010L 87#define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x00000020L 88#define THM_TCON_THERM_TRIP__THERM_TP_LMT_MASK 0x00003FC0L 89#define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7FFFC000L 90#define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000L 91//THM_GPIO_PROCHOT_CTRL 92#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL__SHIFT 0x0 93#define THM_GPIO_PROCHOT_CTRL__PD__SHIFT 0x1 94#define THM_GPIO_PROCHOT_CTRL__PU__SHIFT 0x2 95#define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT 0x3 96#define THM_GPIO_PROCHOT_CTRL__S0__SHIFT 0x4 97#define THM_GPIO_PROCHOT_CTRL__S1__SHIFT 0x5 98#define THM_GPIO_PROCHOT_CTRL__RXEN__SHIFT 0x6 99#define THM_GPIO_PROCHOT_CTRL__RXSEL0__SHIFT 0x7 100#define THM_GPIO_PROCHOT_CTRL__RXSEL1__SHIFT 0x8 101#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT 0x10 102#define THM_GPIO_PROCHOT_CTRL__OE__SHIFT 0x11 103#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT 0x12 104#define THM_GPIO_PROCHOT_CTRL__A__SHIFT 0x13 105#define THM_GPIO_PROCHOT_CTRL__Y__SHIFT 0x1f 106#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL_MASK 0x00000001L 107#define THM_GPIO_PROCHOT_CTRL__PD_MASK 0x00000002L 108#define THM_GPIO_PROCHOT_CTRL__PU_MASK 0x00000004L 109#define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK 0x00000008L 110#define THM_GPIO_PROCHOT_CTRL__S0_MASK 0x00000010L 111#define THM_GPIO_PROCHOT_CTRL__S1_MASK 0x00000020L 112#define THM_GPIO_PROCHOT_CTRL__RXEN_MASK 0x00000040L 113#define THM_GPIO_PROCHOT_CTRL__RXSEL0_MASK 0x00000080L 114#define THM_GPIO_PROCHOT_CTRL__RXSEL1_MASK 0x00000100L 115#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK 0x00010000L 116#define THM_GPIO_PROCHOT_CTRL__OE_MASK 0x00020000L 117#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK 0x00040000L 118#define THM_GPIO_PROCHOT_CTRL__A_MASK 0x00080000L 119#define THM_GPIO_PROCHOT_CTRL__Y_MASK 0x80000000L 120//THM_GPIO_THERMTRIP_CTRL 121#define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL__SHIFT 0x0 122#define THM_GPIO_THERMTRIP_CTRL__PD__SHIFT 0x1 123#define THM_GPIO_THERMTRIP_CTRL__PU__SHIFT 0x2 124#define THM_GPIO_THERMTRIP_CTRL__SCHMEN__SHIFT 0x3 125#define THM_GPIO_THERMTRIP_CTRL__S0__SHIFT 0x4 126#define THM_GPIO_THERMTRIP_CTRL__S1__SHIFT 0x5 127#define THM_GPIO_THERMTRIP_CTRL__RXEN__SHIFT 0x6 128#define THM_GPIO_THERMTRIP_CTRL__RXSEL0__SHIFT 0x7 129#define THM_GPIO_THERMTRIP_CTRL__RXSEL1__SHIFT 0x8 130#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE__SHIFT 0x10 131#define THM_GPIO_THERMTRIP_CTRL__OE__SHIFT 0x11 132#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE__SHIFT 0x12 133#define THM_GPIO_THERMTRIP_CTRL__A__SHIFT 0x13 134#define THM_GPIO_THERMTRIP_CTRL__CTFEN__SHIFT 0x14 135#define THM_GPIO_THERMTRIP_CTRL__Y__SHIFT 0x1f 136#define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL_MASK 0x00000001L 137#define THM_GPIO_THERMTRIP_CTRL__PD_MASK 0x00000002L 138#define THM_GPIO_THERMTRIP_CTRL__PU_MASK 0x00000004L 139#define THM_GPIO_THERMTRIP_CTRL__SCHMEN_MASK 0x00000008L 140#define THM_GPIO_THERMTRIP_CTRL__S0_MASK 0x00000010L 141#define THM_GPIO_THERMTRIP_CTRL__S1_MASK 0x00000020L 142#define THM_GPIO_THERMTRIP_CTRL__RXEN_MASK 0x00000040L 143#define THM_GPIO_THERMTRIP_CTRL__RXSEL0_MASK 0x00000080L 144#define THM_GPIO_THERMTRIP_CTRL__RXSEL1_MASK 0x00000100L 145#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE_MASK 0x00010000L 146#define THM_GPIO_THERMTRIP_CTRL__OE_MASK 0x00020000L 147#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE_MASK 0x00040000L 148#define THM_GPIO_THERMTRIP_CTRL__A_MASK 0x00080000L 149#define THM_GPIO_THERMTRIP_CTRL__CTFEN_MASK 0x00100000L 150#define THM_GPIO_THERMTRIP_CTRL__Y_MASK 0x80000000L 151//THM_GPIO_PWM_CTRL 152#define THM_GPIO_PWM_CTRL__TXIMPSEL__SHIFT 0x0 153#define THM_GPIO_PWM_CTRL__PD__SHIFT 0x1 154#define THM_GPIO_PWM_CTRL__PU__SHIFT 0x2 155#define THM_GPIO_PWM_CTRL__SCHMEN__SHIFT 0x3 156#define THM_GPIO_PWM_CTRL__S0__SHIFT 0x4 157#define THM_GPIO_PWM_CTRL__S1__SHIFT 0x5 158#define THM_GPIO_PWM_CTRL__RXEN__SHIFT 0x6 159#define THM_GPIO_PWM_CTRL__RXSEL0__SHIFT 0x7 160#define THM_GPIO_PWM_CTRL__RXSEL1__SHIFT 0x8 161#define THM_GPIO_PWM_CTRL__OE_OVERRIDE__SHIFT 0x10 162#define THM_GPIO_PWM_CTRL__OE__SHIFT 0x11 163#define THM_GPIO_PWM_CTRL__A_OVERRIDE__SHIFT 0x12 164#define THM_GPIO_PWM_CTRL__A__SHIFT 0x13 165#define THM_GPIO_PWM_CTRL__Y__SHIFT 0x1f 166#define THM_GPIO_PWM_CTRL__TXIMPSEL_MASK 0x00000001L 167#define THM_GPIO_PWM_CTRL__PD_MASK 0x00000002L 168#define THM_GPIO_PWM_CTRL__PU_MASK 0x00000004L 169#define THM_GPIO_PWM_CTRL__SCHMEN_MASK 0x00000008L 170#define THM_GPIO_PWM_CTRL__S0_MASK 0x00000010L 171#define THM_GPIO_PWM_CTRL__S1_MASK 0x00000020L 172#define THM_GPIO_PWM_CTRL__RXEN_MASK 0x00000040L 173#define THM_GPIO_PWM_CTRL__RXSEL0_MASK 0x00000080L 174#define THM_GPIO_PWM_CTRL__RXSEL1_MASK 0x00000100L 175#define THM_GPIO_PWM_CTRL__OE_OVERRIDE_MASK 0x00010000L 176#define THM_GPIO_PWM_CTRL__OE_MASK 0x00020000L 177#define THM_GPIO_PWM_CTRL__A_OVERRIDE_MASK 0x00040000L 178#define THM_GPIO_PWM_CTRL__A_MASK 0x00080000L 179#define THM_GPIO_PWM_CTRL__Y_MASK 0x80000000L 180//THM_GPIO_TACHIN_CTRL 181#define THM_GPIO_TACHIN_CTRL__TXIMPSEL__SHIFT 0x0 182#define THM_GPIO_TACHIN_CTRL__PD__SHIFT 0x1 183#define THM_GPIO_TACHIN_CTRL__PU__SHIFT 0x2 184#define THM_GPIO_TACHIN_CTRL__SCHMEN__SHIFT 0x3 185#define THM_GPIO_TACHIN_CTRL__S0__SHIFT 0x4 186#define THM_GPIO_TACHIN_CTRL__S1__SHIFT 0x5 187#define THM_GPIO_TACHIN_CTRL__RXEN__SHIFT 0x6 188#define THM_GPIO_TACHIN_CTRL__RXSEL0__SHIFT 0x7 189#define THM_GPIO_TACHIN_CTRL__RXSEL1__SHIFT 0x8 190#define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE__SHIFT 0x10 191#define THM_GPIO_TACHIN_CTRL__OE__SHIFT 0x11 192#define THM_GPIO_TACHIN_CTRL__A_OVERRIDE__SHIFT 0x12 193#define THM_GPIO_TACHIN_CTRL__A__SHIFT 0x13 194#define THM_GPIO_TACHIN_CTRL__Y__SHIFT 0x1f 195#define THM_GPIO_TACHIN_CTRL__TXIMPSEL_MASK 0x00000001L 196#define THM_GPIO_TACHIN_CTRL__PD_MASK 0x00000002L 197#define THM_GPIO_TACHIN_CTRL__PU_MASK 0x00000004L 198#define THM_GPIO_TACHIN_CTRL__SCHMEN_MASK 0x00000008L 199#define THM_GPIO_TACHIN_CTRL__S0_MASK 0x00000010L 200#define THM_GPIO_TACHIN_CTRL__S1_MASK 0x00000020L 201#define THM_GPIO_TACHIN_CTRL__RXEN_MASK 0x00000040L 202#define THM_GPIO_TACHIN_CTRL__RXSEL0_MASK 0x00000080L 203#define THM_GPIO_TACHIN_CTRL__RXSEL1_MASK 0x00000100L 204#define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE_MASK 0x00010000L 205#define THM_GPIO_TACHIN_CTRL__OE_MASK 0x00020000L 206#define THM_GPIO_TACHIN_CTRL__A_OVERRIDE_MASK 0x00040000L 207#define THM_GPIO_TACHIN_CTRL__A_MASK 0x00080000L 208#define THM_GPIO_TACHIN_CTRL__Y_MASK 0x80000000L 209//THM_GPIO_PUMPOUT_CTRL 210#define THM_GPIO_PUMPOUT_CTRL__TXIMPSEL__SHIFT 0x0 211#define THM_GPIO_PUMPOUT_CTRL__PD__SHIFT 0x1 212#define THM_GPIO_PUMPOUT_CTRL__PU__SHIFT 0x2 213#define THM_GPIO_PUMPOUT_CTRL__SCHMEN__SHIFT 0x3 214#define THM_GPIO_PUMPOUT_CTRL__S0__SHIFT 0x4 215#define THM_GPIO_PUMPOUT_CTRL__S1__SHIFT 0x5 216#define THM_GPIO_PUMPOUT_CTRL__RXEN__SHIFT 0x6 217#define THM_GPIO_PUMPOUT_CTRL__RXSEL0__SHIFT 0x7 218#define THM_GPIO_PUMPOUT_CTRL__RXSEL1__SHIFT 0x8 219#define THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE__SHIFT 0x10 220#define THM_GPIO_PUMPOUT_CTRL__OE__SHIFT 0x11 221#define THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE__SHIFT 0x12 222#define THM_GPIO_PUMPOUT_CTRL__A__SHIFT 0x13 223#define THM_GPIO_PUMPOUT_CTRL__Y__SHIFT 0x1f 224#define THM_GPIO_PUMPOUT_CTRL__TXIMPSEL_MASK 0x00000001L 225#define THM_GPIO_PUMPOUT_CTRL__PD_MASK 0x00000002L 226#define THM_GPIO_PUMPOUT_CTRL__PU_MASK 0x00000004L 227#define THM_GPIO_PUMPOUT_CTRL__SCHMEN_MASK 0x00000008L 228#define THM_GPIO_PUMPOUT_CTRL__S0_MASK 0x00000010L 229#define THM_GPIO_PUMPOUT_CTRL__S1_MASK 0x00000020L 230#define THM_GPIO_PUMPOUT_CTRL__RXEN_MASK 0x00000040L 231#define THM_GPIO_PUMPOUT_CTRL__RXSEL0_MASK 0x00000080L 232#define THM_GPIO_PUMPOUT_CTRL__RXSEL1_MASK 0x00000100L 233#define THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE_MASK 0x00010000L 234#define THM_GPIO_PUMPOUT_CTRL__OE_MASK 0x00020000L 235#define THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE_MASK 0x00040000L 236#define THM_GPIO_PUMPOUT_CTRL__A_MASK 0x00080000L 237#define THM_GPIO_PUMPOUT_CTRL__Y_MASK 0x80000000L 238//THM_GPIO_PUMPIN_CTRL 239#define THM_GPIO_PUMPIN_CTRL__TXIMPSEL__SHIFT 0x0 240#define THM_GPIO_PUMPIN_CTRL__PD__SHIFT 0x1 241#define THM_GPIO_PUMPIN_CTRL__PU__SHIFT 0x2 242#define THM_GPIO_PUMPIN_CTRL__SCHMEN__SHIFT 0x3 243#define THM_GPIO_PUMPIN_CTRL__S0__SHIFT 0x4 244#define THM_GPIO_PUMPIN_CTRL__S1__SHIFT 0x5 245#define THM_GPIO_PUMPIN_CTRL__RXEN__SHIFT 0x6 246#define THM_GPIO_PUMPIN_CTRL__RXSEL0__SHIFT 0x7 247#define THM_GPIO_PUMPIN_CTRL__RXSEL1__SHIFT 0x8 248#define THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE__SHIFT 0x10 249#define THM_GPIO_PUMPIN_CTRL__OE__SHIFT 0x11 250#define THM_GPIO_PUMPIN_CTRL__A_OVERRIDE__SHIFT 0x12 251#define THM_GPIO_PUMPIN_CTRL__A__SHIFT 0x13 252#define THM_GPIO_PUMPIN_CTRL__Y__SHIFT 0x1f 253#define THM_GPIO_PUMPIN_CTRL__TXIMPSEL_MASK 0x00000001L 254#define THM_GPIO_PUMPIN_CTRL__PD_MASK 0x00000002L 255#define THM_GPIO_PUMPIN_CTRL__PU_MASK 0x00000004L 256#define THM_GPIO_PUMPIN_CTRL__SCHMEN_MASK 0x00000008L 257#define THM_GPIO_PUMPIN_CTRL__S0_MASK 0x00000010L 258#define THM_GPIO_PUMPIN_CTRL__S1_MASK 0x00000020L 259#define THM_GPIO_PUMPIN_CTRL__RXEN_MASK 0x00000040L 260#define THM_GPIO_PUMPIN_CTRL__RXSEL0_MASK 0x00000080L 261#define THM_GPIO_PUMPIN_CTRL__RXSEL1_MASK 0x00000100L 262#define THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE_MASK 0x00010000L 263#define THM_GPIO_PUMPIN_CTRL__OE_MASK 0x00020000L 264#define THM_GPIO_PUMPIN_CTRL__A_OVERRIDE_MASK 0x00040000L 265#define THM_GPIO_PUMPIN_CTRL__A_MASK 0x00080000L 266#define THM_GPIO_PUMPIN_CTRL__Y_MASK 0x80000000L 267//THM_THERMAL_INT_ENA 268#define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 269#define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 270#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 271#define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 272#define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 273#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 274#define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x00000001L 275#define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x00000002L 276#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x00000004L 277#define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x00000008L 278#define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x00000010L 279#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x00000020L 280//THM_THERMAL_INT_CTRL 281#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 282#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 283#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD__SHIFT 0x10 284#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 285#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 286#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a 287#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK__SHIFT 0x1b 288#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT 0x1c 289#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT 0x1d 290#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0x000000FFL 291#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0x0000FF00L 292#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD_MASK 0x00FF0000L 293#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x01000000L 294#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x02000000L 295#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x04000000L 296#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK_MASK 0x08000000L 297#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK 0x10000000L 298#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK 0xE0000000L 299//THM_THERMAL_INT_STATUS 300#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 301#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 302#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 303#define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT__SHIFT 0x3 304#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x00000001L 305#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x00000002L 306#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x00000004L 307#define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT_MASK 0x00000008L 308//THM_TMON0_RDIL0_DATA 309#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0 310#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb 311#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc 312#define THM_TMON0_RDIL0_DATA__Z_MASK 0x000007FFL 313#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x00000800L 314#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0x00FFF000L 315//THM_TMON0_RDIL1_DATA 316#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0 317#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb 318#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc 319#define THM_TMON0_RDIL1_DATA__Z_MASK 0x000007FFL 320#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x00000800L 321#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0x00FFF000L 322//THM_TMON0_RDIL2_DATA 323#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0 324#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb 325#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc 326#define THM_TMON0_RDIL2_DATA__Z_MASK 0x000007FFL 327#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x00000800L 328#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0x00FFF000L 329//THM_TMON0_RDIL3_DATA 330#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0 331#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb 332#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc 333#define THM_TMON0_RDIL3_DATA__Z_MASK 0x000007FFL 334#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x00000800L 335#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0x00FFF000L 336//THM_TMON0_RDIL4_DATA 337#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0 338#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb 339#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc 340#define THM_TMON0_RDIL4_DATA__Z_MASK 0x000007FFL 341#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x00000800L 342#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0x00FFF000L 343//THM_TMON0_RDIL5_DATA 344#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0 345#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb 346#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc 347#define THM_TMON0_RDIL5_DATA__Z_MASK 0x000007FFL 348#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x00000800L 349#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0x00FFF000L 350//THM_TMON0_RDIL6_DATA 351#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0 352#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb 353#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc 354#define THM_TMON0_RDIL6_DATA__Z_MASK 0x000007FFL 355#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x00000800L 356#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0x00FFF000L 357//THM_TMON0_RDIL7_DATA 358#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0 359#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb 360#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc 361#define THM_TMON0_RDIL7_DATA__Z_MASK 0x000007FFL 362#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x00000800L 363#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0x00FFF000L 364//THM_TMON0_RDIL8_DATA 365#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0 366#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb 367#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc 368#define THM_TMON0_RDIL8_DATA__Z_MASK 0x000007FFL 369#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x00000800L 370#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0x00FFF000L 371//THM_TMON0_RDIL9_DATA 372#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0 373#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb 374#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc 375#define THM_TMON0_RDIL9_DATA__Z_MASK 0x000007FFL 376#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x00000800L 377#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0x00FFF000L 378//THM_TMON0_RDIL10_DATA 379#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0 380#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb 381#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc 382#define THM_TMON0_RDIL10_DATA__Z_MASK 0x000007FFL 383#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x00000800L 384#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0x00FFF000L 385//THM_TMON0_RDIL11_DATA 386#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0 387#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb 388#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc 389#define THM_TMON0_RDIL11_DATA__Z_MASK 0x000007FFL 390#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x00000800L 391#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0x00FFF000L 392//THM_TMON0_RDIL12_DATA 393#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0 394#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb 395#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc 396#define THM_TMON0_RDIL12_DATA__Z_MASK 0x000007FFL 397#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x00000800L 398#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0x00FFF000L 399//THM_TMON0_RDIL13_DATA 400#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0 401#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb 402#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc 403#define THM_TMON0_RDIL13_DATA__Z_MASK 0x000007FFL 404#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x00000800L 405#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0x00FFF000L 406//THM_TMON0_RDIL14_DATA 407#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0 408#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb 409#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc 410#define THM_TMON0_RDIL14_DATA__Z_MASK 0x000007FFL 411#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x00000800L 412#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0x00FFF000L 413//THM_TMON0_RDIL15_DATA 414#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0 415#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb 416#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc 417#define THM_TMON0_RDIL15_DATA__Z_MASK 0x000007FFL 418#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x00000800L 419#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0x00FFF000L 420//THM_TMON0_RDIR0_DATA 421#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0 422#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb 423#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc 424#define THM_TMON0_RDIR0_DATA__Z_MASK 0x000007FFL 425#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x00000800L 426#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0x00FFF000L 427//THM_TMON0_RDIR1_DATA 428#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0 429#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb 430#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc 431#define THM_TMON0_RDIR1_DATA__Z_MASK 0x000007FFL 432#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x00000800L 433#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0x00FFF000L 434//THM_TMON0_RDIR2_DATA 435#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0 436#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb 437#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc 438#define THM_TMON0_RDIR2_DATA__Z_MASK 0x000007FFL 439#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x00000800L 440#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0x00FFF000L 441//THM_TMON0_RDIR3_DATA 442#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0 443#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb 444#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc 445#define THM_TMON0_RDIR3_DATA__Z_MASK 0x000007FFL 446#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x00000800L 447#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0x00FFF000L 448//THM_TMON0_RDIR4_DATA 449#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0 450#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb 451#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc 452#define THM_TMON0_RDIR4_DATA__Z_MASK 0x000007FFL 453#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x00000800L 454#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0x00FFF000L 455//THM_TMON0_RDIR5_DATA 456#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0 457#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb 458#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc 459#define THM_TMON0_RDIR5_DATA__Z_MASK 0x000007FFL 460#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x00000800L 461#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0x00FFF000L 462//THM_TMON0_RDIR6_DATA 463#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0 464#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb 465#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc 466#define THM_TMON0_RDIR6_DATA__Z_MASK 0x000007FFL 467#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x00000800L 468#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0x00FFF000L 469//THM_TMON0_RDIR7_DATA 470#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0 471#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb 472#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc 473#define THM_TMON0_RDIR7_DATA__Z_MASK 0x000007FFL 474#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x00000800L 475#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0x00FFF000L 476//THM_TMON0_RDIR8_DATA 477#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0 478#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb 479#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc 480#define THM_TMON0_RDIR8_DATA__Z_MASK 0x000007FFL 481#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x00000800L 482#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0x00FFF000L 483//THM_TMON0_RDIR9_DATA 484#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0 485#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb 486#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc 487#define THM_TMON0_RDIR9_DATA__Z_MASK 0x000007FFL 488#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x00000800L 489#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0x00FFF000L 490//THM_TMON0_RDIR10_DATA 491#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0 492#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb 493#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc 494#define THM_TMON0_RDIR10_DATA__Z_MASK 0x000007FFL 495#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x00000800L 496#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0x00FFF000L 497//THM_TMON0_RDIR11_DATA 498#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0 499#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb 500#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc 501#define THM_TMON0_RDIR11_DATA__Z_MASK 0x000007FFL 502#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x00000800L 503#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0x00FFF000L 504//THM_TMON0_RDIR12_DATA 505#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0 506#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb 507#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc 508#define THM_TMON0_RDIR12_DATA__Z_MASK 0x000007FFL 509#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x00000800L 510#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0x00FFF000L 511//THM_TMON0_RDIR13_DATA 512#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0 513#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb 514#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc 515#define THM_TMON0_RDIR13_DATA__Z_MASK 0x000007FFL 516#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x00000800L 517#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0x00FFF000L 518//THM_TMON0_RDIR14_DATA 519#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0 520#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb 521#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc 522#define THM_TMON0_RDIR14_DATA__Z_MASK 0x000007FFL 523#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x00000800L 524#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0x00FFF000L 525//THM_TMON0_RDIR15_DATA 526#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0 527#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb 528#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc 529#define THM_TMON0_RDIR15_DATA__Z_MASK 0x000007FFL 530#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x00000800L 531#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0x00FFF000L 532//THM_TMON0_INT_DATA 533#define THM_TMON0_INT_DATA__Z__SHIFT 0x0 534#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb 535#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc 536#define THM_TMON0_INT_DATA__Z_MASK 0x000007FFL 537#define THM_TMON0_INT_DATA__VALID_MASK 0x00000800L 538#define THM_TMON0_INT_DATA__TEMP_MASK 0x00FFF000L 539//THM_TMON0_DEBUG 540#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0 541#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5 542#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x0000001FL 543#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0x0000FFE0L 544//THM_TMON1_RDIL0_DATA 545#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x0 546#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0xb 547#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0xc 548#define THM_TMON1_RDIL0_DATA__Z_MASK 0x000007FFL 549#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x00000800L 550#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0x00FFF000L 551//THM_TMON1_RDIL1_DATA 552#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x0 553#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0xb 554#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0xc 555#define THM_TMON1_RDIL1_DATA__Z_MASK 0x000007FFL 556#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x00000800L 557#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0x00FFF000L 558//THM_TMON1_RDIL2_DATA 559#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x0 560#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0xb 561#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0xc 562#define THM_TMON1_RDIL2_DATA__Z_MASK 0x000007FFL 563#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x00000800L 564#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0x00FFF000L 565//THM_TMON1_RDIL3_DATA 566#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x0 567#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0xb 568#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0xc 569#define THM_TMON1_RDIL3_DATA__Z_MASK 0x000007FFL 570#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x00000800L 571#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0x00FFF000L 572//THM_TMON1_RDIL4_DATA 573#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x0 574#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0xb 575#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0xc 576#define THM_TMON1_RDIL4_DATA__Z_MASK 0x000007FFL 577#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x00000800L 578#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0x00FFF000L 579//THM_TMON1_RDIL5_DATA 580#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x0 581#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0xb 582#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0xc 583#define THM_TMON1_RDIL5_DATA__Z_MASK 0x000007FFL 584#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x00000800L 585#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0x00FFF000L 586//THM_TMON1_RDIL6_DATA 587#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x0 588#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0xb 589#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0xc 590#define THM_TMON1_RDIL6_DATA__Z_MASK 0x000007FFL 591#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x00000800L 592#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0x00FFF000L 593//THM_TMON1_RDIL7_DATA 594#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x0 595#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0xb 596#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0xc 597#define THM_TMON1_RDIL7_DATA__Z_MASK 0x000007FFL 598#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x00000800L 599#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0x00FFF000L 600//THM_TMON1_RDIL8_DATA 601#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x0 602#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0xb 603#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0xc 604#define THM_TMON1_RDIL8_DATA__Z_MASK 0x000007FFL 605#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x00000800L 606#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0x00FFF000L 607//THM_TMON1_RDIL9_DATA 608#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x0 609#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0xb 610#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0xc 611#define THM_TMON1_RDIL9_DATA__Z_MASK 0x000007FFL 612#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x00000800L 613#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0x00FFF000L 614//THM_TMON1_RDIL10_DATA 615#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x0 616#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0xb 617#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0xc 618#define THM_TMON1_RDIL10_DATA__Z_MASK 0x000007FFL 619#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x00000800L 620#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0x00FFF000L 621//THM_TMON1_RDIL11_DATA 622#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x0 623#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0xb 624#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0xc 625#define THM_TMON1_RDIL11_DATA__Z_MASK 0x000007FFL 626#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x00000800L 627#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0x00FFF000L 628//THM_TMON1_RDIL12_DATA 629#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x0 630#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0xb 631#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0xc 632#define THM_TMON1_RDIL12_DATA__Z_MASK 0x000007FFL 633#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x00000800L 634#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0x00FFF000L 635//THM_TMON1_RDIL13_DATA 636#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x0 637#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0xb 638#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0xc 639#define THM_TMON1_RDIL13_DATA__Z_MASK 0x000007FFL 640#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x00000800L 641#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0x00FFF000L 642//THM_TMON1_RDIL14_DATA 643#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x0 644#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0xb 645#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0xc 646#define THM_TMON1_RDIL14_DATA__Z_MASK 0x000007FFL 647#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x00000800L 648#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0x00FFF000L 649//THM_TMON1_RDIL15_DATA 650#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x0 651#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0xb 652#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0xc 653#define THM_TMON1_RDIL15_DATA__Z_MASK 0x000007FFL 654#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x00000800L 655#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0x00FFF000L 656//THM_TMON1_RDIR0_DATA 657#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x0 658#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0xb 659#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0xc 660#define THM_TMON1_RDIR0_DATA__Z_MASK 0x000007FFL 661#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x00000800L 662#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0x00FFF000L 663//THM_TMON1_RDIR1_DATA 664#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x0 665#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0xb 666#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0xc 667#define THM_TMON1_RDIR1_DATA__Z_MASK 0x000007FFL 668#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x00000800L 669#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0x00FFF000L 670//THM_TMON1_RDIR2_DATA 671#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x0 672#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0xb 673#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0xc 674#define THM_TMON1_RDIR2_DATA__Z_MASK 0x000007FFL 675#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x00000800L 676#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0x00FFF000L 677//THM_TMON1_RDIR3_DATA 678#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x0 679#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0xb 680#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0xc 681#define THM_TMON1_RDIR3_DATA__Z_MASK 0x000007FFL 682#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x00000800L 683#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0x00FFF000L 684//THM_TMON1_RDIR4_DATA 685#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x0 686#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0xb 687#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0xc 688#define THM_TMON1_RDIR4_DATA__Z_MASK 0x000007FFL 689#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x00000800L 690#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0x00FFF000L 691//THM_TMON1_RDIR5_DATA 692#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x0 693#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0xb 694#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0xc 695#define THM_TMON1_RDIR5_DATA__Z_MASK 0x000007FFL 696#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x00000800L 697#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0x00FFF000L 698//THM_TMON1_RDIR6_DATA 699#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x0 700#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0xb 701#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0xc 702#define THM_TMON1_RDIR6_DATA__Z_MASK 0x000007FFL 703#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x00000800L 704#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0x00FFF000L 705//THM_TMON1_RDIR7_DATA 706#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x0 707#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0xb 708#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0xc 709#define THM_TMON1_RDIR7_DATA__Z_MASK 0x000007FFL 710#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x00000800L 711#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0x00FFF000L 712//THM_TMON1_RDIR8_DATA 713#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x0 714#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0xb 715#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0xc 716#define THM_TMON1_RDIR8_DATA__Z_MASK 0x000007FFL 717#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x00000800L 718#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0x00FFF000L 719//THM_TMON1_RDIR9_DATA 720#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x0 721#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0xb 722#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0xc 723#define THM_TMON1_RDIR9_DATA__Z_MASK 0x000007FFL 724#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x00000800L 725#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0x00FFF000L 726//THM_TMON1_RDIR10_DATA 727#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x0 728#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0xb 729#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0xc 730#define THM_TMON1_RDIR10_DATA__Z_MASK 0x000007FFL 731#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x00000800L 732#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0x00FFF000L 733//THM_TMON1_RDIR11_DATA 734#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x0 735#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0xb 736#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0xc 737#define THM_TMON1_RDIR11_DATA__Z_MASK 0x000007FFL 738#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x00000800L 739#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0x00FFF000L 740//THM_TMON1_RDIR12_DATA 741#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x0 742#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0xb 743#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0xc 744#define THM_TMON1_RDIR12_DATA__Z_MASK 0x000007FFL 745#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x00000800L 746#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0x00FFF000L 747//THM_TMON1_RDIR13_DATA 748#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x0 749#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0xb 750#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0xc 751#define THM_TMON1_RDIR13_DATA__Z_MASK 0x000007FFL 752#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x00000800L 753#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0x00FFF000L 754//THM_TMON1_RDIR14_DATA 755#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x0 756#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0xb 757#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0xc 758#define THM_TMON1_RDIR14_DATA__Z_MASK 0x000007FFL 759#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x00000800L 760#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0x00FFF000L 761//THM_TMON1_RDIR15_DATA 762#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x0 763#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0xb 764#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0xc 765#define THM_TMON1_RDIR15_DATA__Z_MASK 0x000007FFL 766#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x00000800L 767#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0x00FFF000L 768//THM_TMON1_INT_DATA 769#define THM_TMON1_INT_DATA__Z__SHIFT 0x0 770#define THM_TMON1_INT_DATA__VALID__SHIFT 0xb 771#define THM_TMON1_INT_DATA__TEMP__SHIFT 0xc 772#define THM_TMON1_INT_DATA__Z_MASK 0x000007FFL 773#define THM_TMON1_INT_DATA__VALID_MASK 0x00000800L 774#define THM_TMON1_INT_DATA__TEMP_MASK 0x00FFF000L 775//THM_TMON1_DEBUG 776#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x0 777#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x5 778#define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x0000001FL 779#define THM_TMON1_DEBUG__DEBUG_Z_MASK 0x0000FFE0L 780//THM_DIE1_TEMP 781#define THM_DIE1_TEMP__TEMP__SHIFT 0x0 782#define THM_DIE1_TEMP__VALID__SHIFT 0xb 783#define THM_DIE1_TEMP__TEMP_MASK 0x000007FFL 784#define THM_DIE1_TEMP__VALID_MASK 0x00000800L 785//THM_DIE2_TEMP 786#define THM_DIE2_TEMP__TEMP__SHIFT 0x0 787#define THM_DIE2_TEMP__VALID__SHIFT 0xb 788#define THM_DIE2_TEMP__TEMP_MASK 0x000007FFL 789#define THM_DIE2_TEMP__VALID_MASK 0x00000800L 790//THM_DIE3_TEMP 791#define THM_DIE3_TEMP__TEMP__SHIFT 0x0 792#define THM_DIE3_TEMP__VALID__SHIFT 0xb 793#define THM_DIE3_TEMP__TEMP_MASK 0x000007FFL 794#define THM_DIE3_TEMP__VALID_MASK 0x00000800L 795//CG_MULT_THERMAL_CTRL 796#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0 797#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 798#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 799#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 800#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0x0000000FL 801#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0x000001F0L 802#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x00000200L 803#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0x0FF00000L 804//CG_MULT_THERMAL_STATUS 805#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 806#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 807#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x000001FFL 808#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x0003FE00L 809//THM_TMON0_COEFF 810#define THM_TMON0_COEFF__C_OFFSET__SHIFT 0x0 811#define THM_TMON0_COEFF__D__SHIFT 0xb 812#define THM_TMON0_COEFF__C_OFFSET_MASK 0x000007FFL 813#define THM_TMON0_COEFF__D_MASK 0x0003F800L 814//THM_TMON1_COEFF 815#define THM_TMON1_COEFF__C_OFFSET__SHIFT 0x0 816#define THM_TMON1_COEFF__D__SHIFT 0xb 817#define THM_TMON1_COEFF__C_OFFSET_MASK 0x000007FFL 818#define THM_TMON1_COEFF__D_MASK 0x0003F800L 819//CG_FDO_CTRL0 820#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0 821#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8 822#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10 823#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11 824#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17 825#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18 826#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0x000000FFL 827#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0x0000FF00L 828#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x00010000L 829#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x007E0000L 830#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x00800000L 831#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xFF000000L 832//CG_FDO_CTRL1 833#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0 834#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8 835#define CG_FDO_CTRL1__M__SHIFT 0x10 836#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18 837#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0x000000FFL 838#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0x0000FF00L 839#define CG_FDO_CTRL1__M_MASK 0x00FF0000L 840#define CG_FDO_CTRL1__RESERVED_MASK 0x3F000000L 841//CG_FDO_CTRL2 842#define CG_FDO_CTRL2__TMIN__SHIFT 0x0 843#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8 844#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb 845#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe 846#define CG_FDO_CTRL2__TMAX__SHIFT 0x11 847#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 848#define CG_FDO_CTRL2__TMIN_MASK 0x000000FFL 849#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x00000700L 850#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x00003800L 851#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x0001C000L 852#define CG_FDO_CTRL2__TMAX_MASK 0x01FE0000L 853#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xFE000000L 854//CG_TACH_CTRL 855#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 856#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 857#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x00000007L 858#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L 859//CG_TACH_STATUS 860#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 861#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL 862//CG_THERMAL_STATUS 863#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9 864#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x0001FE00L 865//CG_PUMP_CTRL0 866#define CG_PUMP_CTRL0__PUMP_STATIC_DUTY__SHIFT 0x0 867#define CG_PUMP_CTRL0__PUMP_SPINUP_DUTY__SHIFT 0x8 868#define CG_PUMP_CTRL0__PUMP_PWM_MANUAL__SHIFT 0x10 869#define CG_PUMP_CTRL0__PUMP_PWM_HYSTER__SHIFT 0x11 870#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_EN__SHIFT 0x17 871#define CG_PUMP_CTRL0__PUMP_PWM_RAMP__SHIFT 0x18 872#define CG_PUMP_CTRL0__PUMP_STATIC_DUTY_MASK 0x000000FFL 873#define CG_PUMP_CTRL0__PUMP_SPINUP_DUTY_MASK 0x0000FF00L 874#define CG_PUMP_CTRL0__PUMP_PWM_MANUAL_MASK 0x00010000L 875#define CG_PUMP_CTRL0__PUMP_PWM_HYSTER_MASK 0x007E0000L 876#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_EN_MASK 0x00800000L 877#define CG_PUMP_CTRL0__PUMP_PWM_RAMP_MASK 0xFF000000L 878//CG_PUMP_CTRL1 879#define CG_PUMP_CTRL1__PMAX_DUTY100__SHIFT 0x0 880#define CG_PUMP_CTRL1__PMIN_DUTY__SHIFT 0x8 881#define CG_PUMP_CTRL1__M__SHIFT 0x10 882#define CG_PUMP_CTRL1__RESERVED__SHIFT 0x18 883#define CG_PUMP_CTRL1__PMAX_DUTY100_MASK 0x000000FFL 884#define CG_PUMP_CTRL1__PMIN_DUTY_MASK 0x0000FF00L 885#define CG_PUMP_CTRL1__M_MASK 0x00FF0000L 886#define CG_PUMP_CTRL1__RESERVED_MASK 0x3F000000L 887//CG_PUMP_CTRL2 888#define CG_PUMP_CTRL2__TMIN__SHIFT 0x0 889#define CG_PUMP_CTRL2__PUMP_SPINUP_TIME__SHIFT 0x8 890#define CG_PUMP_CTRL2__PUMP_PWM_MODE__SHIFT 0xb 891#define CG_PUMP_CTRL2__TMIN_HYSTER__SHIFT 0xe 892#define CG_PUMP_CTRL2__TMAX__SHIFT 0x11 893#define CG_PUMP_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 894#define CG_PUMP_CTRL2__TMIN_MASK 0x000000FFL 895#define CG_PUMP_CTRL2__PUMP_SPINUP_TIME_MASK 0x00000700L 896#define CG_PUMP_CTRL2__PUMP_PWM_MODE_MASK 0x00003800L 897#define CG_PUMP_CTRL2__TMIN_HYSTER_MASK 0x0001C000L 898#define CG_PUMP_CTRL2__TMAX_MASK 0x01FE0000L 899#define CG_PUMP_CTRL2__TACH_PWM_RESP_RATE_MASK 0xFE000000L 900//CG_PUMP_TACH_CTRL 901#define CG_PUMP_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 902#define CG_PUMP_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 903#define CG_PUMP_TACH_CTRL__EDGE_PER_REV_MASK 0x00000007L 904#define CG_PUMP_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L 905//CG_PUMP_TACH_STATUS 906#define CG_PUMP_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 907#define CG_PUMP_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL 908//CG_PUMP_STATUS 909#define CG_PUMP_STATUS__PUMP_PWM_DUTY__SHIFT 0x9 910#define CG_PUMP_STATUS__PUMP_PWM_DUTY_MASK 0x0001FE00L 911//THM_TCON_LOCAL0 912#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis__SHIFT 0x1 913#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis__SHIFT 0x2 914#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis_MASK 0x00000002L 915#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis_MASK 0x00000004L 916//THM_TCON_LOCAL1 917#define THM_TCON_LOCAL1__Turn_Off_TMON0__SHIFT 0x0 918#define THM_TCON_LOCAL1__Turn_Off_TMON1__SHIFT 0x1 919#define THM_TCON_LOCAL1__PowerDownTmon0__SHIFT 0x4 920#define THM_TCON_LOCAL1__PowerDownTmon1__SHIFT 0x5 921#define THM_TCON_LOCAL1__Turn_Off_TMON0_MASK 0x00000001L 922#define THM_TCON_LOCAL1__Turn_Off_TMON1_MASK 0x00000002L 923#define THM_TCON_LOCAL1__PowerDownTmon0_MASK 0x00000010L 924#define THM_TCON_LOCAL1__PowerDownTmon1_MASK 0x00000020L 925//THM_TCON_LOCAL2 926#define THM_TCON_LOCAL2__TMON_init_delay__SHIFT 0x0 927#define THM_TCON_LOCAL2__TMON_pwrup_stagger_time__SHIFT 0x2 928#define THM_TCON_LOCAL2__short_stagger_count__SHIFT 0x5 929#define THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT 0x6 930#define THM_TCON_LOCAL2__temp_read_skip_scale__SHIFT 0xa 931#define THM_TCON_LOCAL2__skip_scale_correction__SHIFT 0xb 932#define THM_TCON_LOCAL2__TMON_init_delay_MASK 0x00000003L 933#define THM_TCON_LOCAL2__TMON_pwrup_stagger_time_MASK 0x0000000CL 934#define THM_TCON_LOCAL2__short_stagger_count_MASK 0x00000020L 935#define THM_TCON_LOCAL2__sbtsi_use_corrected_MASK 0x00000040L 936#define THM_TCON_LOCAL2__temp_read_skip_scale_MASK 0x00000400L 937#define THM_TCON_LOCAL2__skip_scale_correction_MASK 0x00000800L 938//THM_TCON_LOCAL3 939#define THM_TCON_LOCAL3__Global_TMAX__SHIFT 0x0 940#define THM_TCON_LOCAL3__Global_TMAX_MASK 0x000007FFL 941//THM_TCON_LOCAL4 942#define THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT 0x0 943#define THM_TCON_LOCAL4__Global_TMAX_ID_MASK 0x000000FFL 944//THM_TCON_LOCAL5 945#define THM_TCON_LOCAL5__Global_TMIN__SHIFT 0x0 946#define THM_TCON_LOCAL5__Global_TMIN_MASK 0x000007FFL 947//THM_TCON_LOCAL6 948#define THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT 0x0 949#define THM_TCON_LOCAL6__Global_TMIN_ID_MASK 0x000000FFL 950//THM_TCON_LOCAL7 951#define THM_TCON_LOCAL7__THERMID__SHIFT 0x0 952#define THM_TCON_LOCAL7__THERMID_MASK 0x000000FFL 953//THM_TCON_LOCAL8 954#define THM_TCON_LOCAL8__THERMMAX__SHIFT 0x0 955#define THM_TCON_LOCAL8__THERMMAX_MASK 0x000007FFL 956//THM_TCON_LOCAL9 957#define THM_TCON_LOCAL9__Tj_Max_TMON0__SHIFT 0x0 958#define THM_TCON_LOCAL9__Tj_Max_TMON0_MASK 0x000007FFL 959//THM_TCON_LOCAL10 960#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID__SHIFT 0x0 961#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID_MASK 0x000000FFL 962//THM_TCON_LOCAL11 963#define THM_TCON_LOCAL11__Tj_Max_TMON1__SHIFT 0x0 964#define THM_TCON_LOCAL11__Tj_Max_TMON1_MASK 0x000007FFL 965//THM_TCON_LOCAL12 966#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID__SHIFT 0x0 967#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID_MASK 0x000000FFL 968//THM_TCON_LOCAL13 969#define THM_TCON_LOCAL13__boot_done__SHIFT 0x0 970#define THM_TCON_LOCAL13__boot_done_MASK 0x00000001L 971//THM_BACO_CNTL 972#define THM_BACO_CNTL__BACO_MODE__SHIFT 0x0 973#define THM_BACO_CNTL__BACO_ISO_EN__SHIFT 0x1 974#define THM_BACO_CNTL__BACO_PWROKRAW_CNTL__SHIFT 0x2 975#define THM_BACO_CNTL__BACO_RESET_EN__SHIFT 0x3 976#define THM_BACO_CNTL__BACO_SOC_VDCI_RESET__SHIFT 0x4 977#define THM_BACO_CNTL__BACO_SMNCLK_MUX__SHIFT 0x5 978#define THM_BACO_CNTL__BACO_SOC_REFCLK_OFF__SHIFT 0x6 979#define THM_BACO_CNTL__BACO_AEB_ISO_EN__SHIFT 0x7 980#define THM_BACO_CNTL__BACO_EXIT__SHIFT 0x8 981#define THM_BACO_CNTL__BACO_ANA_ISO_EN__SHIFT 0x9 982#define THM_BACO_CNTL__BACO_SB_AXI_FENCE__SHIFT 0x1e 983#define THM_BACO_CNTL__SOC_DOMAIN_IDLE__SHIFT 0x1f 984#define THM_BACO_CNTL__BACO_MODE_MASK 0x00000001L 985#define THM_BACO_CNTL__BACO_ISO_EN_MASK 0x00000002L 986#define THM_BACO_CNTL__BACO_PWROKRAW_CNTL_MASK 0x00000004L 987#define THM_BACO_CNTL__BACO_RESET_EN_MASK 0x00000008L 988#define THM_BACO_CNTL__BACO_SOC_VDCI_RESET_MASK 0x00000010L 989#define THM_BACO_CNTL__BACO_SMNCLK_MUX_MASK 0x00000020L 990#define THM_BACO_CNTL__BACO_SOC_REFCLK_OFF_MASK 0x00000040L 991#define THM_BACO_CNTL__BACO_AEB_ISO_EN_MASK 0x00000080L 992#define THM_BACO_CNTL__BACO_EXIT_MASK 0x00000100L 993#define THM_BACO_CNTL__BACO_ANA_ISO_EN_MASK 0x00000200L 994#define THM_BACO_CNTL__BACO_SB_AXI_FENCE_MASK 0x40000000L 995#define THM_BACO_CNTL__SOC_DOMAIN_IDLE_MASK 0x80000000L 996//THM_BACO_TIMING0 997#define THM_BACO_TIMING0__BACO_ISO_EXIT_CNT__SHIFT 0x0 998#define THM_BACO_TIMING0__BACO_PWROKRAW_EXIT_CNT__SHIFT 0x8 999#define THM_BACO_TIMING0__BACO_RESET_EXIT_CNT__SHIFT 0x10 1000#define THM_BACO_TIMING0__BACO_VDCI_RESET_EXIT_CNT__SHIFT 0x18 1001#define THM_BACO_TIMING0__BACO_ISO_EXIT_CNT_MASK 0x000000FFL 1002#define THM_BACO_TIMING0__BACO_PWROKRAW_EXIT_CNT_MASK 0x0000FF00L 1003#define THM_BACO_TIMING0__BACO_RESET_EXIT_CNT_MASK 0x00FF0000L 1004#define THM_BACO_TIMING0__BACO_VDCI_RESET_EXIT_CNT_MASK 0xFF000000L 1005//THM_BACO_TIMING1 1006#define THM_BACO_TIMING1__BACO_SMNCLK_EXIT_CNT__SHIFT 0x0 1007#define THM_BACO_TIMING1__BACO_FENCE_EXIT_CNT__SHIFT 0x8 1008#define THM_BACO_TIMING1__BACO_REFCLK_EXIT_CNT__SHIFT 0x10 1009#define THM_BACO_TIMING1__BACO_MODE_EXIT_CNT__SHIFT 0x18 1010#define THM_BACO_TIMING1__BACO_SMNCLK_EXIT_CNT_MASK 0x000000FFL 1011#define THM_BACO_TIMING1__BACO_FENCE_EXIT_CNT_MASK 0x0000FF00L 1012#define THM_BACO_TIMING1__BACO_REFCLK_EXIT_CNT_MASK 0x00FF0000L 1013#define THM_BACO_TIMING1__BACO_MODE_EXIT_CNT_MASK 0xFF000000L 1014//XTAL_CNTL 1015#define XTAL_CNTL__PCIE_REFCLK_SWITCH__SHIFT 0x0 1016#define XTAL_CNTL__CORE_XTAL_CLKGEN_CLKEN__SHIFT 0x4 1017#define XTAL_CNTL__CORE_XTAL_PWDN__SHIFT 0x8 1018#define XTAL_CNTL__OSC_GAIN_EN__SHIFT 0xc 1019#define XTAL_CNTL__PCIE_REFCLK_SWITCH_MASK 0x00000001L 1020#define XTAL_CNTL__CORE_XTAL_CLKGEN_CLKEN_MASK 0x00000010L 1021#define XTAL_CNTL__CORE_XTAL_PWDN_MASK 0x00000100L 1022#define XTAL_CNTL__OSC_GAIN_EN_MASK 0x00007000L 1023//SBTSI_REMOTE_TEMP 1024#define SBTSI_REMOTE_TEMP__RemoteTcenSensor__SHIFT 0x0 1025#define SBTSI_REMOTE_TEMP__RemoteTcenSensorId__SHIFT 0xb 1026#define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid__SHIFT 0x13 1027#define SBTSI_REMOTE_TEMP__RemoteTcenSensor_MASK 0x000007FFL 1028#define SBTSI_REMOTE_TEMP__RemoteTcenSensorId_MASK 0x0007F800L 1029#define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid_MASK 0x00080000L 1030//SBRMI_CONTROL 1031#define SBRMI_CONTROL__READ_CMD_INT_DIS__SHIFT 0x0 1032#define SBRMI_CONTROL__DPD__SHIFT 0x1 1033#define SBRMI_CONTROL__DbrdySts__SHIFT 0x2 1034#define SBRMI_CONTROL__READ_CMD_INT_DIS_MASK 0x00000001L 1035#define SBRMI_CONTROL__DPD_MASK 0x00000002L 1036#define SBRMI_CONTROL__DbrdySts_MASK 0x00000004L 1037//SBRMI_COMMAND 1038#define SBRMI_COMMAND__Command__SHIFT 0x0 1039#define SBRMI_COMMAND__WrDataLen__SHIFT 0x8 1040#define SBRMI_COMMAND__RdDataLen__SHIFT 0x10 1041#define SBRMI_COMMAND__CommandSent__SHIFT 0x18 1042#define SBRMI_COMMAND__CommandNotSupported__SHIFT 0x19 1043#define SBRMI_COMMAND__CommandAborted__SHIFT 0x1a 1044#define SBRMI_COMMAND__Status__SHIFT 0x1c 1045#define SBRMI_COMMAND__Command_MASK 0x000000FFL 1046#define SBRMI_COMMAND__WrDataLen_MASK 0x0000FF00L 1047#define SBRMI_COMMAND__RdDataLen_MASK 0x00FF0000L 1048#define SBRMI_COMMAND__CommandSent_MASK 0x01000000L 1049#define SBRMI_COMMAND__CommandNotSupported_MASK 0x02000000L 1050#define SBRMI_COMMAND__CommandAborted_MASK 0x04000000L 1051#define SBRMI_COMMAND__Status_MASK 0xF0000000L 1052//SBRMI_WRITE_DATA0 1053#define SBRMI_WRITE_DATA0__WrByte0__SHIFT 0x0 1054#define SBRMI_WRITE_DATA0__WrByte1__SHIFT 0x8 1055#define SBRMI_WRITE_DATA0__WrByte2__SHIFT 0x10 1056#define SBRMI_WRITE_DATA0__WrByte3__SHIFT 0x18 1057#define SBRMI_WRITE_DATA0__WrByte0_MASK 0x000000FFL 1058#define SBRMI_WRITE_DATA0__WrByte1_MASK 0x0000FF00L 1059#define SBRMI_WRITE_DATA0__WrByte2_MASK 0x00FF0000L 1060#define SBRMI_WRITE_DATA0__WrByte3_MASK 0xFF000000L 1061//SBRMI_WRITE_DATA1 1062#define SBRMI_WRITE_DATA1__WrByte4__SHIFT 0x0 1063#define SBRMI_WRITE_DATA1__WrByte5__SHIFT 0x8 1064#define SBRMI_WRITE_DATA1__WrByte6__SHIFT 0x10 1065#define SBRMI_WRITE_DATA1__WrByte7__SHIFT 0x18 1066#define SBRMI_WRITE_DATA1__WrByte4_MASK 0x000000FFL 1067#define SBRMI_WRITE_DATA1__WrByte5_MASK 0x0000FF00L 1068#define SBRMI_WRITE_DATA1__WrByte6_MASK 0x00FF0000L 1069#define SBRMI_WRITE_DATA1__WrByte7_MASK 0xFF000000L 1070//SBRMI_WRITE_DATA2 1071#define SBRMI_WRITE_DATA2__WrByte8__SHIFT 0x0 1072#define SBRMI_WRITE_DATA2__WrByte9__SHIFT 0x8 1073#define SBRMI_WRITE_DATA2__WrByte10__SHIFT 0x10 1074#define SBRMI_WRITE_DATA2__WrByte11__SHIFT 0x18 1075#define SBRMI_WRITE_DATA2__WrByte8_MASK 0x000000FFL 1076#define SBRMI_WRITE_DATA2__WrByte9_MASK 0x0000FF00L 1077#define SBRMI_WRITE_DATA2__WrByte10_MASK 0x00FF0000L 1078#define SBRMI_WRITE_DATA2__WrByte11_MASK 0xFF000000L 1079//SBRMI_READ_DATA0 1080#define SBRMI_READ_DATA0__RdByte0__SHIFT 0x0 1081#define SBRMI_READ_DATA0__RdByte1__SHIFT 0x8 1082#define SBRMI_READ_DATA0__RdByte2__SHIFT 0x10 1083#define SBRMI_READ_DATA0__RdByte3__SHIFT 0x18 1084#define SBRMI_READ_DATA0__RdByte0_MASK 0x000000FFL 1085#define SBRMI_READ_DATA0__RdByte1_MASK 0x0000FF00L 1086#define SBRMI_READ_DATA0__RdByte2_MASK 0x00FF0000L 1087#define SBRMI_READ_DATA0__RdByte3_MASK 0xFF000000L 1088//SBRMI_READ_DATA1 1089#define SBRMI_READ_DATA1__RdByte4__SHIFT 0x0 1090#define SBRMI_READ_DATA1__RdByte5__SHIFT 0x8 1091#define SBRMI_READ_DATA1__RdByte6__SHIFT 0x10 1092#define SBRMI_READ_DATA1__RdByte7__SHIFT 0x18 1093#define SBRMI_READ_DATA1__RdByte4_MASK 0x000000FFL 1094#define SBRMI_READ_DATA1__RdByte5_MASK 0x0000FF00L 1095#define SBRMI_READ_DATA1__RdByte6_MASK 0x00FF0000L 1096#define SBRMI_READ_DATA1__RdByte7_MASK 0xFF000000L 1097//SBRMI_CORE_EN_NUMBER 1098#define SBRMI_CORE_EN_NUMBER__EnabledCoreNum__SHIFT 0x0 1099#define SBRMI_CORE_EN_NUMBER__EnabledCoreNum_MASK 0x0000007FL 1100//SBRMI_CORE_EN_STATUS0 1101#define SBRMI_CORE_EN_STATUS0__CoreEnStat0__SHIFT 0x0 1102#define SBRMI_CORE_EN_STATUS0__CoreEnStat0_MASK 0xFFFFFFFFL 1103//SBRMI_CORE_EN_STATUS1 1104#define SBRMI_CORE_EN_STATUS1__CoreEnStat1__SHIFT 0x0 1105#define SBRMI_CORE_EN_STATUS1__CoreEnStat1_MASK 0xFFFFFFFFL 1106//SBRMI_APIC_STATUS0 1107#define SBRMI_APIC_STATUS0__APICStat0__SHIFT 0x0 1108#define SBRMI_APIC_STATUS0__APICStat0_MASK 0xFFFFFFFFL 1109//SBRMI_APIC_STATUS1 1110#define SBRMI_APIC_STATUS1__APICStat1__SHIFT 0x0 1111#define SBRMI_APIC_STATUS1__APICStat1_MASK 0xFFFFFFFFL 1112//SBRMI_MCE_STATUS0 1113#define SBRMI_MCE_STATUS0__MceStat0__SHIFT 0x0 1114#define SBRMI_MCE_STATUS0__MceStat0_MASK 0xFFFFFFFFL 1115//SBRMI_MCE_STATUS1 1116#define SBRMI_MCE_STATUS1__MceStat1__SHIFT 0x0 1117#define SBRMI_MCE_STATUS1__MceStat1_MASK 0xFFFFFFFFL 1118//SMBUS_CNTL0 1119#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE__SHIFT 0x0 1120#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR__SHIFT 0x1 1121#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE__SHIFT 0x8 1122#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES__SHIFT 0x10 1123#define SMBUS_CNTL0__THM_READY__SHIFT 0x14 1124#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE_MASK 0x00000001L 1125#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_MASK 0x000000FEL 1126#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE_MASK 0x0000FF00L 1127#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES_MASK 0x00070000L 1128#define SMBUS_CNTL0__THM_READY_MASK 0x00100000L 1129//SMBUS_CNTL1 1130#define SMBUS_CNTL1__SMB_TIMEOUT_EN__SHIFT 0x0 1131#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN__SHIFT 0x1 1132#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN__SHIFT 0x9 1133#define SMBUS_CNTL1__SMB_TIMEOUT_EN_MASK 0x00000001L 1134#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN_MASK 0x000001FEL 1135#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN_MASK 0x0001FE00L 1136//SMBUS_BLKWR_CMD_CTRL0 1137#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0__SHIFT 0x0 1138#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1__SHIFT 0x8 1139#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2__SHIFT 0x10 1140#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3__SHIFT 0x18 1141#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0_MASK 0x000000FFL 1142#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1_MASK 0x0000FF00L 1143#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2_MASK 0x00FF0000L 1144#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3_MASK 0xFF000000L 1145//SMBUS_BLKWR_CMD_CTRL1 1146#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4__SHIFT 0x0 1147#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5__SHIFT 0x8 1148#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6__SHIFT 0x10 1149#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7__SHIFT 0x18 1150#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4_MASK 0x000000FFL 1151#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5_MASK 0x0000FF00L 1152#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6_MASK 0x00FF0000L 1153#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7_MASK 0xFF000000L 1154//SMBUS_BLKRD_CMD_CTRL0 1155#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0__SHIFT 0x0 1156#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1__SHIFT 0x8 1157#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2__SHIFT 0x10 1158#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3__SHIFT 0x18 1159#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0_MASK 0x000000FFL 1160#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1_MASK 0x0000FF00L 1161#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2_MASK 0x00FF0000L 1162#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3_MASK 0xFF000000L 1163//SMBUS_BLKRD_CMD_CTRL1 1164#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4__SHIFT 0x0 1165#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5__SHIFT 0x8 1166#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6__SHIFT 0x10 1167#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7__SHIFT 0x18 1168#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4_MASK 0x000000FFL 1169#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5_MASK 0x0000FF00L 1170#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6_MASK 0x00FF0000L 1171#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7_MASK 0xFF000000L 1172//SMBUS_TIMING_CNTL0 1173#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN__SHIFT 0x0 1174#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN__SHIFT 0x16 1175#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN_MASK 0x003FFFFFL 1176#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN_MASK 0x3FC00000L 1177//SMBUS_TIMING_CNTL1 1178#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN__SHIFT 0x0 1179#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN__SHIFT 0x5 1180#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN__SHIFT 0xb 1181#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN__SHIFT 0x14 1182#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN_MASK 0x0000001FL 1183#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN_MASK 0x000007E0L 1184#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN_MASK 0x000FF800L 1185#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN_MASK 0x3FF00000L 1186//SMBUS_TIMING_CNTL2 1187#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN__SHIFT 0x0 1188#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN__SHIFT 0xd 1189#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN_MASK 0x00001FFFL 1190#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN_MASK 0x07FFE000L 1191//SMBUS_TRIGGER_CNTL 1192#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER__SHIFT 0x0 1193#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER__SHIFT 0x8 1194#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER_MASK 0x00000001L 1195#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER_MASK 0x00000100L 1196//SMBUS_UDID_CNTL0 1197#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED__SHIFT 0x0 1198#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN__SHIFT 0x1f 1199#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED_MASK 0x7FFFFFFFL 1200#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN_MASK 0x80000000L 1201//SMBUS_UDID_CNTL1 1202#define SMBUS_UDID_CNTL1__SMB_UDID_31_0__SHIFT 0x0 1203#define SMBUS_UDID_CNTL1__SMB_UDID_31_0_MASK 0xFFFFFFFFL 1204//SMBUS_UDID_CNTL2 1205#define SMBUS_UDID_CNTL2__PEC_SUPPORTED__SHIFT 0x0 1206#define SMBUS_UDID_CNTL2__UDID_VERSION__SHIFT 0x1 1207#define SMBUS_UDID_CNTL2__SMBUS_VERSION__SHIFT 0x4 1208#define SMBUS_UDID_CNTL2__OEM__SHIFT 0x8 1209#define SMBUS_UDID_CNTL2__ASF__SHIFT 0x9 1210#define SMBUS_UDID_CNTL2__IPMI__SHIFT 0xa 1211#define SMBUS_UDID_CNTL2__PEC_SUPPORTED_MASK 0x00000001L 1212#define SMBUS_UDID_CNTL2__UDID_VERSION_MASK 0x0000000EL 1213#define SMBUS_UDID_CNTL2__SMBUS_VERSION_MASK 0x000000F0L 1214#define SMBUS_UDID_CNTL2__OEM_MASK 0x00000100L 1215#define SMBUS_UDID_CNTL2__ASF_MASK 0x00000200L 1216#define SMBUS_UDID_CNTL2__IPMI_MASK 0x00000400L 1217//SMBUS_BACO_DUMMY 1218#define SMBUS_BACO_DUMMY__BACO_DUMMY_DATA__SHIFT 0x0 1219#define SMBUS_BACO_DUMMY__BACO_DUMMY_DATA_MASK 0xFFFFFFFFL 1220//SMBUS_BACO_ADDR_RANGE0_LOW 1221#define SMBUS_BACO_ADDR_RANGE0_LOW__BACO_ADDR_RANGE0_LOW__SHIFT 0x0 1222#define SMBUS_BACO_ADDR_RANGE0_LOW__BACO_ADDR_RANGE0_LOW_MASK 0x000FFFFFL 1223//SMBUS_BACO_ADDR_RANGE0_HIGH 1224#define SMBUS_BACO_ADDR_RANGE0_HIGH__BACO_ADDR_RANGE0_HIGH__SHIFT 0x0 1225#define SMBUS_BACO_ADDR_RANGE0_HIGH__BACO_ADDR_RANGE0_HIGH_MASK 0x000FFFFFL 1226//SMBUS_BACO_ADDR_RANGE1_LOW 1227#define SMBUS_BACO_ADDR_RANGE1_LOW__BACO_ADDR_RANGE1_LOW__SHIFT 0x0 1228#define SMBUS_BACO_ADDR_RANGE1_LOW__BACO_ADDR_RANGE1_LOW_MASK 0x000FFFFFL 1229//SMBUS_BACO_ADDR_RANGE1_HIGH 1230#define SMBUS_BACO_ADDR_RANGE1_HIGH__BACO_ADDR_RANGE1_HIGH__SHIFT 0x0 1231#define SMBUS_BACO_ADDR_RANGE1_HIGH__BACO_ADDR_RANGE1_HIGH_MASK 0x000FFFFFL 1232//SMBUS_BACO_ADDR_RANGE2_LOW 1233#define SMBUS_BACO_ADDR_RANGE2_LOW__BACO_ADDR_RANGE2_LOW__SHIFT 0x0 1234#define SMBUS_BACO_ADDR_RANGE2_LOW__BACO_ADDR_RANGE2_LOW_MASK 0x000FFFFFL 1235//SMBUS_BACO_ADDR_RANGE2_HIGH 1236#define SMBUS_BACO_ADDR_RANGE2_HIGH__BACO_ADDR_RANGE2_HIGH__SHIFT 0x0 1237#define SMBUS_BACO_ADDR_RANGE2_HIGH__BACO_ADDR_RANGE2_HIGH_MASK 0x000FFFFFL 1238//SMBUS_BACO_ADDR_RANGE3_LOW 1239#define SMBUS_BACO_ADDR_RANGE3_LOW__BACO_ADDR_RANGE3_LOW__SHIFT 0x0 1240#define SMBUS_BACO_ADDR_RANGE3_LOW__BACO_ADDR_RANGE3_LOW_MASK 0x000FFFFFL 1241//SMBUS_BACO_ADDR_RANGE3_HIGH 1242#define SMBUS_BACO_ADDR_RANGE3_HIGH__BACO_ADDR_RANGE3_HIGH__SHIFT 0x0 1243#define SMBUS_BACO_ADDR_RANGE3_HIGH__BACO_ADDR_RANGE3_HIGH_MASK 0x000FFFFFL 1244//SMBUS_BACO_ADDR_RANGE4_LOW 1245#define SMBUS_BACO_ADDR_RANGE4_LOW__BACO_ADDR_RANGE4_LOW__SHIFT 0x0 1246#define SMBUS_BACO_ADDR_RANGE4_LOW__BACO_ADDR_RANGE4_LOW_MASK 0x000FFFFFL 1247//SMBUS_BACO_ADDR_RANGE4_HIGH 1248#define SMBUS_BACO_ADDR_RANGE4_HIGH__BACO_ADDR_RANGE4_HIGH__SHIFT 0x0 1249#define SMBUS_BACO_ADDR_RANGE4_HIGH__BACO_ADDR_RANGE4_HIGH_MASK 0x000FFFFFL 1250//THM_GPIO_MACO_EN_CTRL 1251#define THM_GPIO_MACO_EN_CTRL__MACO_EN_TXIMPSEL__SHIFT 0x0 1252#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PD__SHIFT 0x1 1253#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PU__SHIFT 0x2 1254#define THM_GPIO_MACO_EN_CTRL__MACO_EN_SCHMEN__SHIFT 0x3 1255#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S0__SHIFT 0x4 1256#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S1__SHIFT 0x5 1257#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXEN__SHIFT 0x6 1258#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL0__SHIFT 0x7 1259#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL1__SHIFT 0x8 1260#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_OVERRIDE__SHIFT 0x10 1261#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE__SHIFT 0x11 1262#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_OVERRIDE__SHIFT 0x12 1263#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A__SHIFT 0x13 1264#define THM_GPIO_MACO_EN_CTRL__Y__SHIFT 0x1f 1265#define THM_GPIO_MACO_EN_CTRL__MACO_EN_TXIMPSEL_MASK 0x00000001L 1266#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PD_MASK 0x00000002L 1267#define THM_GPIO_MACO_EN_CTRL__MACO_EN_PU_MASK 0x00000004L 1268#define THM_GPIO_MACO_EN_CTRL__MACO_EN_SCHMEN_MASK 0x00000008L 1269#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S0_MASK 0x00000010L 1270#define THM_GPIO_MACO_EN_CTRL__MACO_EN_S1_MASK 0x00000020L 1271#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXEN_MASK 0x00000040L 1272#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL0_MASK 0x00000080L 1273#define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL1_MASK 0x00000100L 1274#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_OVERRIDE_MASK 0x00010000L 1275#define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_MASK 0x00020000L 1276#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_OVERRIDE_MASK 0x00040000L 1277#define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_MASK 0x00080000L 1278#define THM_GPIO_MACO_EN_CTRL__Y_MASK 0x80000000L 1279//THM_BACO_TIMING2 1280#define THM_BACO_TIMING2__BACO_AEB_ISO_EXIT_CNT__SHIFT 0x0 1281#define THM_BACO_TIMING2__BACO_ANA_ISO_EXIT_CNT__SHIFT 0x8 1282#define THM_BACO_TIMING2__BACO_EXIT_CNT__SHIFT 0x10 1283#define THM_BACO_TIMING2__BACO_AEB_ISO_EXIT_CNT_MASK 0x000000FFL 1284#define THM_BACO_TIMING2__BACO_ANA_ISO_EXIT_CNT_MASK 0x0000FF00L 1285#define THM_BACO_TIMING2__BACO_EXIT_CNT_MASK 0x00FF0000L 1286//THM_BACO_TIMING 1287#define THM_BACO_TIMING__BACO_RESET_DELAY__SHIFT 0x0 1288#define THM_BACO_TIMING__BACO_RESET_DELAY_MASK 0x0000FFFFL 1289//THM_TMON0_REMOTE_START 1290#define THM_TMON0_REMOTE_START__DATA__SHIFT 0x0 1291#define THM_TMON0_REMOTE_START__DATA_MASK 0xFFFFFFFFL 1292//THM_TMON0_REMOTE_END 1293#define THM_TMON0_REMOTE_END__DATA__SHIFT 0x0 1294#define THM_TMON0_REMOTE_END__DATA_MASK 0xFFFFFFFFL 1295//THM_TMON1_REMOTE_START 1296#define THM_TMON1_REMOTE_START__DATA__SHIFT 0x0 1297#define THM_TMON1_REMOTE_START__DATA_MASK 0xFFFFFFFFL 1298//THM_TMON1_REMOTE_END 1299#define THM_TMON1_REMOTE_END__DATA__SHIFT 0x0 1300#define THM_TMON1_REMOTE_END__DATA_MASK 0xFFFFFFFFL 1301//THM_TMON2_REMOTE_START 1302#define THM_TMON2_REMOTE_START__DATA__SHIFT 0x0 1303#define THM_TMON2_REMOTE_START__DATA_MASK 0xFFFFFFFFL 1304//THM_TMON2_REMOTE_END 1305#define THM_TMON2_REMOTE_END__DATA__SHIFT 0x0 1306#define THM_TMON2_REMOTE_END__DATA_MASK 0xFFFFFFFFL 1307//THM_TMON3_REMOTE_START 1308#define THM_TMON3_REMOTE_START__DATA__SHIFT 0x0 1309#define THM_TMON3_REMOTE_START__DATA_MASK 0xFFFFFFFFL 1310//THM_TMON3_REMOTE_END 1311#define THM_TMON3_REMOTE_END__DATA__SHIFT 0x0 1312#define THM_TMON3_REMOTE_END__DATA_MASK 0xFFFFFFFFL 1313 1314#endif
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