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thm_14_0_2_offset.h
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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_offset.h
1/* 2 * Copyright 2024 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24#ifndef _thm_14_0_2_OFFSET_HEADER 25#define _thm_14_0_2_OFFSET_HEADER 26 27 28 29// addressBlock: thm_thm_SmuThmDec 30// base address: 0x59800 31#define regTHM_TCON_CUR_TMP 0x0000 32#define regTHM_TCON_CUR_TMP_BASE_IDX 0 33#define regTHM_TCON_HTC 0x0001 34#define regTHM_TCON_HTC_BASE_IDX 0 35#define regTHM_TCON_THERM_TRIP 0x0002 36#define regTHM_TCON_THERM_TRIP_BASE_IDX 0 37#define regTHM_CTF_DELAY 0x0003 38#define regTHM_CTF_DELAY_BASE_IDX 0 39#define regTHM_GPIO_PROCHOT_CTRL 0x0004 40#define regTHM_GPIO_PROCHOT_CTRL_BASE_IDX 0 41#define regTHM_GPIO_THERMTRIP_CTRL 0x0005 42#define regTHM_GPIO_THERMTRIP_CTRL_BASE_IDX 0 43#define regTHM_GPIO_PWM_CTRL 0x0006 44#define regTHM_GPIO_PWM_CTRL_BASE_IDX 0 45#define regTHM_GPIO_TACHIN_CTRL 0x0007 46#define regTHM_GPIO_TACHIN_CTRL_BASE_IDX 0 47#define regTHM_GPIO_PUMPOUT_CTRL 0x0008 48#define regTHM_GPIO_PUMPOUT_CTRL_BASE_IDX 0 49#define regTHM_GPIO_PUMPIN_CTRL 0x0009 50#define regTHM_GPIO_PUMPIN_CTRL_BASE_IDX 0 51#define regTHM_THERMAL_INT_ENA 0x000a 52#define regTHM_THERMAL_INT_ENA_BASE_IDX 0 53#define regTHM_THERMAL_INT_CTRL 0x000b 54#define regTHM_THERMAL_INT_CTRL_BASE_IDX 0 55#define regTHM_THERMAL_INT_STATUS 0x000c 56#define regTHM_THERMAL_INT_STATUS_BASE_IDX 0 57#define regTHM_SW_TEMP 0x000d 58#define regTHM_SW_TEMP_BASE_IDX 0 59#define regCG_MULT_THERMAL_CTRL 0x000e 60#define regCG_MULT_THERMAL_CTRL_BASE_IDX 0 61#define regCG_MULT_THERMAL_STATUS 0x000f 62#define regCG_MULT_THERMAL_STATUS_BASE_IDX 0 63#define regCG_THERMAL_RANGE 0x0010 64#define regCG_THERMAL_RANGE_BASE_IDX 0 65#define regCG_FDO_CTRL0 0x0011 66#define regCG_FDO_CTRL0_BASE_IDX 0 67#define regCG_FDO_CTRL1 0x0012 68#define regCG_FDO_CTRL1_BASE_IDX 0 69#define regCG_FDO_CTRL2 0x0013 70#define regCG_FDO_CTRL2_BASE_IDX 0 71#define regCG_TACH_CTRL 0x0014 72#define regCG_TACH_CTRL_BASE_IDX 0 73#define regCG_TACH_STATUS 0x0015 74#define regCG_TACH_STATUS_BASE_IDX 0 75#define regCG_THERMAL_STATUS 0x0016 76#define regCG_THERMAL_STATUS_BASE_IDX 0 77#define regCG_PUMP_CTRL0 0x0017 78#define regCG_PUMP_CTRL0_BASE_IDX 0 79#define regCG_PUMP_CTRL1 0x0018 80#define regCG_PUMP_CTRL1_BASE_IDX 0 81#define regCG_PUMP_CTRL2 0x0019 82#define regCG_PUMP_CTRL2_BASE_IDX 0 83#define regCG_PUMP_TACH_CTRL 0x001a 84#define regCG_PUMP_TACH_CTRL_BASE_IDX 0 85#define regCG_PUMP_TACH_STATUS 0x001b 86#define regCG_PUMP_TACH_STATUS_BASE_IDX 0 87#define regCG_PUMP_STATUS 0x001c 88#define regCG_PUMP_STATUS_BASE_IDX 0 89#define regTHM_TCON_LOCAL2 0x001d 90#define regTHM_TCON_LOCAL2_BASE_IDX 0 91#define regTHM_TCON_LOCAL3 0x001e 92#define regTHM_TCON_LOCAL3_BASE_IDX 0 93#define regTHM_TCON_LOCAL4 0x001f 94#define regTHM_TCON_LOCAL4_BASE_IDX 0 95#define regTHM_TCON_LOCAL5 0x0020 96#define regTHM_TCON_LOCAL5_BASE_IDX 0 97#define regTHM_TCON_LOCAL6 0x0021 98#define regTHM_TCON_LOCAL6_BASE_IDX 0 99#define regTHM_TCON_LOCAL7 0x0022 100#define regTHM_TCON_LOCAL7_BASE_IDX 0 101#define regTHM_TCON_LOCAL8 0x0023 102#define regTHM_TCON_LOCAL8_BASE_IDX 0 103#define regTHM_TCON_LOCAL9 0x0024 104#define regTHM_TCON_LOCAL9_BASE_IDX 0 105#define regTHM_TCON_LOCAL10 0x0025 106#define regTHM_TCON_LOCAL10_BASE_IDX 0 107#define regTHM_TCON_LOCAL11 0x0026 108#define regTHM_TCON_LOCAL11_BASE_IDX 0 109#define regTHM_TCON_LOCAL12 0x0027 110#define regTHM_TCON_LOCAL12_BASE_IDX 0 111#define regTHM_TCON_LOCAL13 0x0028 112#define regTHM_TCON_LOCAL13_BASE_IDX 0 113#define regTHM_TCON_LOCAL14 0x0029 114#define regTHM_TCON_LOCAL14_BASE_IDX 0 115#define regTHM_TCON_LOCAL15 0x002a 116#define regTHM_TCON_LOCAL15_BASE_IDX 0 117#define regTHM_BACO_CNTL 0x002d 118#define regTHM_BACO_CNTL_BASE_IDX 0 119#define regTHM_BACO_TIMING0 0x002e 120#define regTHM_BACO_TIMING0_BASE_IDX 0 121#define regTHM_BACO_TIMING1 0x002f 122#define regTHM_BACO_TIMING1_BASE_IDX 0 123#define regTHM_BACO_TIMING2 0x0030 124#define regTHM_BACO_TIMING2_BASE_IDX 0 125#define regTHM_BACO_TIMING 0x0031 126#define regTHM_BACO_TIMING_BASE_IDX 0 127#define regXTAL_CNTL 0x0032 128#define regXTAL_CNTL_BASE_IDX 0 129#define regTHM_PWRMGT 0x0033 130#define regTHM_PWRMGT_BASE_IDX 0 131#define regSMUSBI_SBIREGADDR 0x0158 132#define regSMUSBI_SBIREGADDR_BASE_IDX 0 133#define regSMUSBI_SBIREGDATA 0x0159 134#define regSMUSBI_SBIREGDATA_BASE_IDX 0 135#define regSMUSBI_ERRATA_STAT_REG 0x015d 136#define regSMUSBI_ERRATA_STAT_REG_BASE_IDX 0 137#define regSMUSBI_SBICTRL 0x015e 138#define regSMUSBI_SBICTRL_BASE_IDX 0 139#define regSMUSBI_CKNBIRESET 0x015f 140#define regSMUSBI_CKNBIRESET_BASE_IDX 0 141#define regSMUSBI_TIMING 0x0160 142#define regSMUSBI_TIMING_BASE_IDX 0 143#define regSMUSBI_HS_TIMING 0x0161 144#define regSMUSBI_HS_TIMING_BASE_IDX 0 145#define regSBTSI_REMOTE_TEMP 0x0162 146#define regSBTSI_REMOTE_TEMP_BASE_IDX 0 147#define regSBRMI_CONTROL 0x0163 148#define regSBRMI_CONTROL_BASE_IDX 0 149#define regSBRMI_COMMAND 0x0164 150#define regSBRMI_COMMAND_BASE_IDX 0 151#define regSBRMI_WRITE_DATA0 0x0166 152#define regSBRMI_WRITE_DATA0_BASE_IDX 0 153#define regSBRMI_WRITE_DATA1 0x0167 154#define regSBRMI_WRITE_DATA1_BASE_IDX 0 155#define regSBRMI_WRITE_DATA2 0x0168 156#define regSBRMI_WRITE_DATA2_BASE_IDX 0 157#define regSBRMI_READ_DATA0 0x016a 158#define regSBRMI_READ_DATA0_BASE_IDX 0 159#define regSBRMI_READ_DATA1 0x016b 160#define regSBRMI_READ_DATA1_BASE_IDX 0 161#define regSBRMI_CORE_EN_NUMBER 0x016c 162#define regSBRMI_CORE_EN_NUMBER_BASE_IDX 0 163#define regSBRMI_CORE_EN_STATUS0 0x016d 164#define regSBRMI_CORE_EN_STATUS0_BASE_IDX 0 165#define regSBRMI_CORE_EN_STATUS1 0x016e 166#define regSBRMI_CORE_EN_STATUS1_BASE_IDX 0 167#define regSBRMI_APIC_STATUS0 0x016f 168#define regSBRMI_APIC_STATUS0_BASE_IDX 0 169#define regSBRMI_APIC_STATUS1 0x0170 170#define regSBRMI_APIC_STATUS1_BASE_IDX 0 171#define regSBRMI_MCE_STATUS0 0x0171 172#define regSBRMI_MCE_STATUS0_BASE_IDX 0 173#define regSBRMI_MCE_STATUS1 0x0172 174#define regSBRMI_MCE_STATUS1_BASE_IDX 0 175#define regSMBUS_CNTL0 0x0173 176#define regSMBUS_CNTL0_BASE_IDX 0 177#define regSMBUS_CNTL1 0x0174 178#define regSMBUS_CNTL1_BASE_IDX 0 179#define regSMBUS_BLKWR_CMD_CTRL0 0x0175 180#define regSMBUS_BLKWR_CMD_CTRL0_BASE_IDX 0 181#define regSMBUS_BLKWR_CMD_CTRL1 0x0176 182#define regSMBUS_BLKWR_CMD_CTRL1_BASE_IDX 0 183#define regSMBUS_BLKRD_CMD_CTRL0 0x0177 184#define regSMBUS_BLKRD_CMD_CTRL0_BASE_IDX 0 185#define regSMBUS_BLKRD_CMD_CTRL1 0x0178 186#define regSMBUS_BLKRD_CMD_CTRL1_BASE_IDX 0 187#define regSMBUS_TIMING_CNTL0 0x0179 188#define regSMBUS_TIMING_CNTL0_BASE_IDX 0 189#define regSMBUS_TIMING_CNTL1 0x017a 190#define regSMBUS_TIMING_CNTL1_BASE_IDX 0 191#define regSMBUS_TIMING_CNTL2 0x017b 192#define regSMBUS_TIMING_CNTL2_BASE_IDX 0 193#define regSMBUS_TRIGGER_CNTL 0x017c 194#define regSMBUS_TRIGGER_CNTL_BASE_IDX 0 195#define regSMBUS_UDID_CNTL0 0x017d 196#define regSMBUS_UDID_CNTL0_BASE_IDX 0 197#define regSMBUS_UDID_CNTL1 0x017e 198#define regSMBUS_UDID_CNTL1_BASE_IDX 0 199#define regSMBUS_UDID_CNTL2 0x017f 200#define regSMBUS_UDID_CNTL2_BASE_IDX 0 201#define regSMUSBI_SMBUS 0x0180 202#define regSMUSBI_SMBUS_BASE_IDX 0 203#define regSMUSBI_ALERT 0x0181 204#define regSMUSBI_ALERT_BASE_IDX 0 205#define regSMBUS_BACO_DUMMY 0x0182 206#define regSMBUS_BACO_DUMMY_BASE_IDX 0 207#define regSMBUS_BACO_ADDR_RANGE0_LOW 0x0183 208#define regSMBUS_BACO_ADDR_RANGE0_LOW_BASE_IDX 0 209#define regSMBUS_BACO_ADDR_RANGE0_HIGH 0x0184 210#define regSMBUS_BACO_ADDR_RANGE0_HIGH_BASE_IDX 0 211#define regSMBUS_BACO_ADDR_RANGE1_LOW 0x0185 212#define regSMBUS_BACO_ADDR_RANGE1_LOW_BASE_IDX 0 213#define regSMBUS_BACO_ADDR_RANGE1_HIGH 0x0186 214#define regSMBUS_BACO_ADDR_RANGE1_HIGH_BASE_IDX 0 215#define regSMBUS_BACO_ADDR_RANGE2_LOW 0x0187 216#define regSMBUS_BACO_ADDR_RANGE2_LOW_BASE_IDX 0 217#define regSMBUS_BACO_ADDR_RANGE2_HIGH 0x0188 218#define regSMBUS_BACO_ADDR_RANGE2_HIGH_BASE_IDX 0 219#define regSMBUS_BACO_ADDR_RANGE3_LOW 0x0189 220#define regSMBUS_BACO_ADDR_RANGE3_LOW_BASE_IDX 0 221#define regSMBUS_BACO_ADDR_RANGE3_HIGH 0x018a 222#define regSMBUS_BACO_ADDR_RANGE3_HIGH_BASE_IDX 0 223#define regSMBUS_BACO_ADDR_RANGE4_LOW 0x018b 224#define regSMBUS_BACO_ADDR_RANGE4_LOW_BASE_IDX 0 225#define regSMBUS_BACO_ADDR_RANGE4_HIGH 0x018c 226#define regSMBUS_BACO_ADDR_RANGE4_HIGH_BASE_IDX 0 227 228#endif
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