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thm_13_0_2_offset.h
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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_offset.h
1/* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24#ifndef _thm_13_0_2_OFFSET_HEADER 25#define _thm_13_0_2_OFFSET_HEADER 26 27 28 29// addressBlock: thm_thm_SmuThmDec 30// base address: 0x59800 31#define regTHM_TCON_CUR_TMP 0x0000 32#define regTHM_TCON_CUR_TMP_BASE_IDX 0 33#define regTHM_TCON_HTC 0x0001 34#define regTHM_TCON_HTC_BASE_IDX 0 35#define regTHM_TCON_THERM_TRIP 0x0002 36#define regTHM_TCON_THERM_TRIP_BASE_IDX 0 37#define regTHM_CTF_DELAY 0x0003 38#define regTHM_CTF_DELAY_BASE_IDX 0 39#define regTHM_GPIO_PROCHOT_CTRL 0x0004 40#define regTHM_GPIO_PROCHOT_CTRL_BASE_IDX 0 41#define regTHM_GPIO_THERMTRIP_CTRL 0x0005 42#define regTHM_GPIO_THERMTRIP_CTRL_BASE_IDX 0 43#define regTHM_GPIO_PWM_CTRL 0x0006 44#define regTHM_GPIO_PWM_CTRL_BASE_IDX 0 45#define regTHM_GPIO_TACHIN_CTRL 0x0007 46#define regTHM_GPIO_TACHIN_CTRL_BASE_IDX 0 47#define regTHM_GPIO_PUMPOUT_CTRL 0x0008 48#define regTHM_GPIO_PUMPOUT_CTRL_BASE_IDX 0 49#define regTHM_GPIO_PUMPIN_CTRL 0x0009 50#define regTHM_GPIO_PUMPIN_CTRL_BASE_IDX 0 51#define regTHM_THERMAL_INT_ENA 0x000a 52#define regTHM_THERMAL_INT_ENA_BASE_IDX 0 53#define regTHM_THERMAL_INT_CTRL 0x000b 54#define regTHM_THERMAL_INT_CTRL_BASE_IDX 0 55#define regTHM_THERMAL_INT_STATUS 0x000c 56#define regTHM_THERMAL_INT_STATUS_BASE_IDX 0 57#define regTHM_TMON0_RDIL0_DATA 0x000d 58#define regTHM_TMON0_RDIL0_DATA_BASE_IDX 0 59#define regTHM_TMON0_RDIL1_DATA 0x000e 60#define regTHM_TMON0_RDIL1_DATA_BASE_IDX 0 61#define regTHM_TMON0_RDIL2_DATA 0x000f 62#define regTHM_TMON0_RDIL2_DATA_BASE_IDX 0 63#define regTHM_TMON0_RDIL3_DATA 0x0010 64#define regTHM_TMON0_RDIL3_DATA_BASE_IDX 0 65#define regTHM_TMON0_RDIL4_DATA 0x0011 66#define regTHM_TMON0_RDIL4_DATA_BASE_IDX 0 67#define regTHM_TMON0_RDIL5_DATA 0x0012 68#define regTHM_TMON0_RDIL5_DATA_BASE_IDX 0 69#define regTHM_TMON0_RDIL6_DATA 0x0013 70#define regTHM_TMON0_RDIL6_DATA_BASE_IDX 0 71#define regTHM_TMON0_RDIL7_DATA 0x0014 72#define regTHM_TMON0_RDIL7_DATA_BASE_IDX 0 73#define regTHM_TMON0_RDIL8_DATA 0x0015 74#define regTHM_TMON0_RDIL8_DATA_BASE_IDX 0 75#define regTHM_TMON0_RDIL9_DATA 0x0016 76#define regTHM_TMON0_RDIL9_DATA_BASE_IDX 0 77#define regTHM_TMON0_RDIL10_DATA 0x0017 78#define regTHM_TMON0_RDIL10_DATA_BASE_IDX 0 79#define regTHM_TMON0_RDIL11_DATA 0x0018 80#define regTHM_TMON0_RDIL11_DATA_BASE_IDX 0 81#define regTHM_TMON0_RDIL12_DATA 0x0019 82#define regTHM_TMON0_RDIL12_DATA_BASE_IDX 0 83#define regTHM_TMON0_RDIL13_DATA 0x001a 84#define regTHM_TMON0_RDIL13_DATA_BASE_IDX 0 85#define regTHM_TMON0_RDIL14_DATA 0x001b 86#define regTHM_TMON0_RDIL14_DATA_BASE_IDX 0 87#define regTHM_TMON0_RDIL15_DATA 0x001c 88#define regTHM_TMON0_RDIL15_DATA_BASE_IDX 0 89#define regTHM_TMON0_RDIR0_DATA 0x001d 90#define regTHM_TMON0_RDIR0_DATA_BASE_IDX 0 91#define regTHM_TMON0_RDIR1_DATA 0x001e 92#define regTHM_TMON0_RDIR1_DATA_BASE_IDX 0 93#define regTHM_TMON0_RDIR2_DATA 0x001f 94#define regTHM_TMON0_RDIR2_DATA_BASE_IDX 0 95#define regTHM_TMON0_RDIR3_DATA 0x0020 96#define regTHM_TMON0_RDIR3_DATA_BASE_IDX 0 97#define regTHM_TMON0_RDIR4_DATA 0x0021 98#define regTHM_TMON0_RDIR4_DATA_BASE_IDX 0 99#define regTHM_TMON0_RDIR5_DATA 0x0022 100#define regTHM_TMON0_RDIR5_DATA_BASE_IDX 0 101#define regTHM_TMON0_RDIR6_DATA 0x0023 102#define regTHM_TMON0_RDIR6_DATA_BASE_IDX 0 103#define regTHM_TMON0_RDIR7_DATA 0x0024 104#define regTHM_TMON0_RDIR7_DATA_BASE_IDX 0 105#define regTHM_TMON0_RDIR8_DATA 0x0025 106#define regTHM_TMON0_RDIR8_DATA_BASE_IDX 0 107#define regTHM_TMON0_RDIR9_DATA 0x0026 108#define regTHM_TMON0_RDIR9_DATA_BASE_IDX 0 109#define regTHM_TMON0_RDIR10_DATA 0x0027 110#define regTHM_TMON0_RDIR10_DATA_BASE_IDX 0 111#define regTHM_TMON0_RDIR11_DATA 0x0028 112#define regTHM_TMON0_RDIR11_DATA_BASE_IDX 0 113#define regTHM_TMON0_RDIR12_DATA 0x0029 114#define regTHM_TMON0_RDIR12_DATA_BASE_IDX 0 115#define regTHM_TMON0_RDIR13_DATA 0x002a 116#define regTHM_TMON0_RDIR13_DATA_BASE_IDX 0 117#define regTHM_TMON0_RDIR14_DATA 0x002b 118#define regTHM_TMON0_RDIR14_DATA_BASE_IDX 0 119#define regTHM_TMON0_RDIR15_DATA 0x002c 120#define regTHM_TMON0_RDIR15_DATA_BASE_IDX 0 121#define regTHM_TMON0_INT_DATA 0x002d 122#define regTHM_TMON0_INT_DATA_BASE_IDX 0 123#define regTHM_TMON0_CTRL 0x002e 124#define regTHM_TMON0_CTRL_BASE_IDX 0 125#define regTHM_TMON0_CTRL2 0x002f 126#define regTHM_TMON0_CTRL2_BASE_IDX 0 127#define regTHM_TMON1_RDIL0_DATA 0x0031 128#define regTHM_TMON1_RDIL0_DATA_BASE_IDX 0 129#define regTHM_TMON1_RDIL1_DATA 0x0032 130#define regTHM_TMON1_RDIL1_DATA_BASE_IDX 0 131#define regTHM_TMON1_RDIL2_DATA 0x0033 132#define regTHM_TMON1_RDIL2_DATA_BASE_IDX 0 133#define regTHM_TMON1_RDIL3_DATA 0x0034 134#define regTHM_TMON1_RDIL3_DATA_BASE_IDX 0 135#define regTHM_TMON1_RDIL4_DATA 0x0035 136#define regTHM_TMON1_RDIL4_DATA_BASE_IDX 0 137#define regTHM_TMON1_RDIL5_DATA 0x0036 138#define regTHM_TMON1_RDIL5_DATA_BASE_IDX 0 139#define regTHM_TMON1_RDIL6_DATA 0x0037 140#define regTHM_TMON1_RDIL6_DATA_BASE_IDX 0 141#define regTHM_TMON1_RDIL7_DATA 0x0038 142#define regTHM_TMON1_RDIL7_DATA_BASE_IDX 0 143#define regTHM_TMON1_RDIL8_DATA 0x0039 144#define regTHM_TMON1_RDIL8_DATA_BASE_IDX 0 145#define regTHM_TMON1_RDIL9_DATA 0x003a 146#define regTHM_TMON1_RDIL9_DATA_BASE_IDX 0 147#define regTHM_TMON1_RDIL10_DATA 0x003b 148#define regTHM_TMON1_RDIL10_DATA_BASE_IDX 0 149#define regTHM_TMON1_RDIL11_DATA 0x003c 150#define regTHM_TMON1_RDIL11_DATA_BASE_IDX 0 151#define regTHM_TMON1_RDIL12_DATA 0x003d 152#define regTHM_TMON1_RDIL12_DATA_BASE_IDX 0 153#define regTHM_TMON1_RDIL13_DATA 0x003e 154#define regTHM_TMON1_RDIL13_DATA_BASE_IDX 0 155#define regTHM_TMON1_RDIL14_DATA 0x003f 156#define regTHM_TMON1_RDIL14_DATA_BASE_IDX 0 157#define regTHM_TMON1_RDIL15_DATA 0x0040 158#define regTHM_TMON1_RDIL15_DATA_BASE_IDX 0 159#define regTHM_TMON1_RDIR0_DATA 0x0041 160#define regTHM_TMON1_RDIR0_DATA_BASE_IDX 0 161#define regTHM_TMON1_RDIR1_DATA 0x0042 162#define regTHM_TMON1_RDIR1_DATA_BASE_IDX 0 163#define regTHM_TMON1_RDIR2_DATA 0x0043 164#define regTHM_TMON1_RDIR2_DATA_BASE_IDX 0 165#define regTHM_TMON1_RDIR3_DATA 0x0044 166#define regTHM_TMON1_RDIR3_DATA_BASE_IDX 0 167#define regTHM_TMON1_RDIR4_DATA 0x0045 168#define regTHM_TMON1_RDIR4_DATA_BASE_IDX 0 169#define regTHM_TMON1_RDIR5_DATA 0x0046 170#define regTHM_TMON1_RDIR5_DATA_BASE_IDX 0 171#define regTHM_TMON1_RDIR6_DATA 0x0047 172#define regTHM_TMON1_RDIR6_DATA_BASE_IDX 0 173#define regTHM_TMON1_RDIR7_DATA 0x0048 174#define regTHM_TMON1_RDIR7_DATA_BASE_IDX 0 175#define regTHM_TMON1_RDIR8_DATA 0x0049 176#define regTHM_TMON1_RDIR8_DATA_BASE_IDX 0 177#define regTHM_TMON1_RDIR9_DATA 0x004a 178#define regTHM_TMON1_RDIR9_DATA_BASE_IDX 0 179#define regTHM_TMON1_RDIR10_DATA 0x004b 180#define regTHM_TMON1_RDIR10_DATA_BASE_IDX 0 181#define regTHM_TMON1_RDIR11_DATA 0x004c 182#define regTHM_TMON1_RDIR11_DATA_BASE_IDX 0 183#define regTHM_TMON1_RDIR12_DATA 0x004d 184#define regTHM_TMON1_RDIR12_DATA_BASE_IDX 0 185#define regTHM_TMON1_RDIR13_DATA 0x004e 186#define regTHM_TMON1_RDIR13_DATA_BASE_IDX 0 187#define regTHM_TMON1_RDIR14_DATA 0x004f 188#define regTHM_TMON1_RDIR14_DATA_BASE_IDX 0 189#define regTHM_TMON1_RDIR15_DATA 0x0050 190#define regTHM_TMON1_RDIR15_DATA_BASE_IDX 0 191#define regTHM_TMON1_INT_DATA 0x0051 192#define regTHM_TMON1_INT_DATA_BASE_IDX 0 193#define regTHM_DIE1_TEMP 0x0079 194#define regTHM_DIE1_TEMP_BASE_IDX 0 195#define regTHM_DIE2_TEMP 0x007a 196#define regTHM_DIE2_TEMP_BASE_IDX 0 197#define regTHM_DIE3_TEMP 0x007b 198#define regTHM_DIE3_TEMP_BASE_IDX 0 199#define regTHM_SW_TEMP 0x0081 200#define regTHM_SW_TEMP_BASE_IDX 0 201#define regCG_MULT_THERMAL_CTRL 0x0082 202#define regCG_MULT_THERMAL_CTRL_BASE_IDX 0 203#define regCG_MULT_THERMAL_STATUS 0x0083 204#define regCG_MULT_THERMAL_STATUS_BASE_IDX 0 205#define regCG_THERMAL_RANGE 0x0084 206#define regCG_THERMAL_RANGE_BASE_IDX 0 207#define regTHM_TMON_CONFIG 0x0085 208#define regTHM_TMON_CONFIG_BASE_IDX 0 209#define regTHM_TMON_CONFIG2 0x0086 210#define regTHM_TMON_CONFIG2_BASE_IDX 0 211#define regTHM_TMON0_COEFF 0x0087 212#define regTHM_TMON0_COEFF_BASE_IDX 0 213#define regTHM_TMON1_COEFF 0x0088 214#define regTHM_TMON1_COEFF_BASE_IDX 0 215#define regCG_FDO_CTRL0 0x008b 216#define regCG_FDO_CTRL0_BASE_IDX 0 217#define regCG_FDO_CTRL1 0x008c 218#define regCG_FDO_CTRL1_BASE_IDX 0 219#define regCG_FDO_CTRL2 0x008d 220#define regCG_FDO_CTRL2_BASE_IDX 0 221#define regCG_TACH_CTRL 0x008e 222#define regCG_TACH_CTRL_BASE_IDX 0 223#define regCG_TACH_STATUS 0x008f 224#define regCG_TACH_STATUS_BASE_IDX 0 225#define regCG_THERMAL_STATUS 0x0090 226#define regCG_THERMAL_STATUS_BASE_IDX 0 227#define regCG_PUMP_CTRL0 0x0091 228#define regCG_PUMP_CTRL0_BASE_IDX 0 229#define regCG_PUMP_CTRL1 0x0092 230#define regCG_PUMP_CTRL1_BASE_IDX 0 231#define regCG_PUMP_CTRL2 0x0093 232#define regCG_PUMP_CTRL2_BASE_IDX 0 233#define regCG_PUMP_TACH_CTRL 0x0094 234#define regCG_PUMP_TACH_CTRL_BASE_IDX 0 235#define regCG_PUMP_TACH_STATUS 0x0095 236#define regCG_PUMP_TACH_STATUS_BASE_IDX 0 237#define regCG_PUMP_STATUS 0x0096 238#define regCG_PUMP_STATUS_BASE_IDX 0 239#define regTHM_TCON_LOCAL0 0x0097 240#define regTHM_TCON_LOCAL0_BASE_IDX 0 241#define regTHM_TCON_LOCAL1 0x0098 242#define regTHM_TCON_LOCAL1_BASE_IDX 0 243#define regTHM_TCON_LOCAL2 0x0099 244#define regTHM_TCON_LOCAL2_BASE_IDX 0 245#define regTHM_TCON_LOCAL3 0x009a 246#define regTHM_TCON_LOCAL3_BASE_IDX 0 247#define regTHM_TCON_LOCAL4 0x009b 248#define regTHM_TCON_LOCAL4_BASE_IDX 0 249#define regTHM_TCON_LOCAL5 0x009c 250#define regTHM_TCON_LOCAL5_BASE_IDX 0 251#define regTHM_TCON_LOCAL6 0x009d 252#define regTHM_TCON_LOCAL6_BASE_IDX 0 253#define regTHM_TCON_LOCAL7 0x009e 254#define regTHM_TCON_LOCAL7_BASE_IDX 0 255#define regTHM_TCON_LOCAL8 0x009f 256#define regTHM_TCON_LOCAL8_BASE_IDX 0 257#define regTHM_TCON_LOCAL9 0x00a0 258#define regTHM_TCON_LOCAL9_BASE_IDX 0 259#define regTHM_TCON_LOCAL10 0x00a1 260#define regTHM_TCON_LOCAL10_BASE_IDX 0 261#define regTHM_TCON_LOCAL11 0x00a2 262#define regTHM_TCON_LOCAL11_BASE_IDX 0 263#define regTHM_TCON_LOCAL12 0x00a3 264#define regTHM_TCON_LOCAL12_BASE_IDX 0 265#define regTHM_TCON_LOCAL14 0x00a4 266#define regTHM_TCON_LOCAL14_BASE_IDX 0 267#define regTHM_TCON_LOCAL15 0x00a5 268#define regTHM_TCON_LOCAL15_BASE_IDX 0 269#define regTHM_TCON_LOCAL13 0x00a6 270#define regTHM_TCON_LOCAL13_BASE_IDX 0 271#define regXTAL_CNTL 0x00ac 272#define regXTAL_CNTL_BASE_IDX 0 273#define regTHM_PWRMGT 0x00ad 274#define regTHM_PWRMGT_BASE_IDX 0 275#define regTHM_GPIO_MACO_EN_CTRL 0x00ae 276#define regTHM_GPIO_MACO_EN_CTRL_BASE_IDX 0 277#define regSBTSI_REMOTE_TEMP 0x00ca 278#define regSBTSI_REMOTE_TEMP_BASE_IDX 0 279#define regSBRMI_CONTROL 0x00cb 280#define regSBRMI_CONTROL_BASE_IDX 0 281#define regSBRMI_COMMAND 0x00cc 282#define regSBRMI_COMMAND_BASE_IDX 0 283#define regSBRMI_WRITE_DATA0 0x00cd 284#define regSBRMI_WRITE_DATA0_BASE_IDX 0 285#define regSBRMI_WRITE_DATA1 0x00ce 286#define regSBRMI_WRITE_DATA1_BASE_IDX 0 287#define regSBRMI_WRITE_DATA2 0x00cf 288#define regSBRMI_WRITE_DATA2_BASE_IDX 0 289#define regSBRMI_READ_DATA0 0x00d0 290#define regSBRMI_READ_DATA0_BASE_IDX 0 291#define regSBRMI_READ_DATA1 0x00d1 292#define regSBRMI_READ_DATA1_BASE_IDX 0 293#define regSBRMI_CORE_EN_NUMBER 0x00d2 294#define regSBRMI_CORE_EN_NUMBER_BASE_IDX 0 295#define regSBRMI_CORE_EN_STATUS0 0x00d3 296#define regSBRMI_CORE_EN_STATUS0_BASE_IDX 0 297#define regSBRMI_CORE_EN_STATUS1 0x00d4 298#define regSBRMI_CORE_EN_STATUS1_BASE_IDX 0 299#define regSBRMI_APIC_STATUS0 0x00d5 300#define regSBRMI_APIC_STATUS0_BASE_IDX 0 301#define regSBRMI_APIC_STATUS1 0x00d6 302#define regSBRMI_APIC_STATUS1_BASE_IDX 0 303#define regSBRMI_MCE_STATUS0 0x00db 304#define regSBRMI_MCE_STATUS0_BASE_IDX 0 305#define regSBRMI_MCE_STATUS1 0x00dc 306#define regSBRMI_MCE_STATUS1_BASE_IDX 0 307#define regSMBUS_CNTL0 0x00df 308#define regSMBUS_CNTL0_BASE_IDX 0 309#define regSMBUS_CNTL1 0x00e0 310#define regSMBUS_CNTL1_BASE_IDX 0 311#define regSMBUS_BLKWR_CMD_CTRL0 0x00e1 312#define regSMBUS_BLKWR_CMD_CTRL0_BASE_IDX 0 313#define regSMBUS_BLKWR_CMD_CTRL1 0x00e2 314#define regSMBUS_BLKWR_CMD_CTRL1_BASE_IDX 0 315#define regSMBUS_BLKRD_CMD_CTRL0 0x00e3 316#define regSMBUS_BLKRD_CMD_CTRL0_BASE_IDX 0 317#define regSMBUS_BLKRD_CMD_CTRL1 0x00e4 318#define regSMBUS_BLKRD_CMD_CTRL1_BASE_IDX 0 319#define regSMBUS_TIMING_CNTL0 0x00e5 320#define regSMBUS_TIMING_CNTL0_BASE_IDX 0 321#define regSMBUS_TIMING_CNTL1 0x00e6 322#define regSMBUS_TIMING_CNTL1_BASE_IDX 0 323#define regSMBUS_TIMING_CNTL2 0x00e7 324#define regSMBUS_TIMING_CNTL2_BASE_IDX 0 325#define regSMBUS_TRIGGER_CNTL 0x00e8 326#define regSMBUS_TRIGGER_CNTL_BASE_IDX 0 327#define regSMBUS_UDID_CNTL0 0x00e9 328#define regSMBUS_UDID_CNTL0_BASE_IDX 0 329#define regSMBUS_UDID_CNTL1 0x00ea 330#define regSMBUS_UDID_CNTL1_BASE_IDX 0 331#define regSMBUS_UDID_CNTL2 0x00eb 332#define regSMBUS_UDID_CNTL2_BASE_IDX 0 333#define regTHM_TMON0_REMOTE_START 0x0100 334#define regTHM_TMON0_REMOTE_START_BASE_IDX 0 335#define regTHM_TMON0_REMOTE_END 0x013f 336#define regTHM_TMON0_REMOTE_END_BASE_IDX 0 337#define regTHM_TMON1_REMOTE_START 0x0140 338#define regTHM_TMON1_REMOTE_START_BASE_IDX 0 339#define regTHM_TMON1_REMOTE_END 0x017f 340#define regTHM_TMON1_REMOTE_END_BASE_IDX 0 341#define regTHM_TMON2_REMOTE_START 0x0180 342#define regTHM_TMON2_REMOTE_START_BASE_IDX 0 343#define regTHM_TMON2_REMOTE_END 0x01bf 344#define regTHM_TMON2_REMOTE_END_BASE_IDX 0 345 346#endif
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