FILE
smuio_13_0_3_offset.h
File preview with syntax highlighting.
linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_13_0_3_offset.h
1/* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef _smuio_13_0_3_OFFSET_HEADER 24#define _smuio_13_0_3_OFFSET_HEADER 25 26 27 28// addressBlock: aid_smuio_smuio_reset_SmuSmuioDec 29// base address: 0x5a300 30#define regSMUIO_MP_RESET_INTR 0x00c1 31#define regSMUIO_MP_RESET_INTR_BASE_IDX 1 32#define regSMUIO_SOC_HALT 0x00c2 33#define regSMUIO_SOC_HALT_BASE_IDX 1 34 35 36// addressBlock: aid_smuio_smuio_tsc_SmuSmuioDec 37// base address: 0x5a8a0 38#define regPWROK_REFCLK_GAP_CYCLES 0x0028 39#define regPWROK_REFCLK_GAP_CYCLES_BASE_IDX 2 40#define regGOLDEN_TSC_INCREMENT_UPPER 0x002b 41#define regGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX 2 42#define regGOLDEN_TSC_INCREMENT_LOWER 0x002c 43#define regGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX 2 44#define regGOLDEN_TSC_COUNT_UPPER 0x002d 45#define regGOLDEN_TSC_COUNT_UPPER_BASE_IDX 2 46#define regGOLDEN_TSC_COUNT_LOWER 0x002e 47#define regGOLDEN_TSC_COUNT_LOWER_BASE_IDX 2 48#define regSOC_GOLDEN_TSC_SHADOW_UPPER 0x002f 49#define regSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 2 50#define regSOC_GOLDEN_TSC_SHADOW_LOWER 0x0030 51#define regSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 2 52#define regSOC_GAP_PWROK 0x0031 53#define regSOC_GAP_PWROK_BASE_IDX 2 54 55 56// addressBlock: aid_smuio_smuio_swtimer_SmuSmuioDec 57// base address: 0x5ac70 58#define regPWR_VIRT_RESET_REQ 0x011c 59#define regPWR_VIRT_RESET_REQ_BASE_IDX 2 60#define regPWR_DISP_TIMER_CONTROL 0x011d 61#define regPWR_DISP_TIMER_CONTROL_BASE_IDX 2 62#define regPWR_DISP_TIMER_DEBUG 0x011e 63#define regPWR_DISP_TIMER_DEBUG_BASE_IDX 2 64#define regPWR_DISP_TIMER2_CONTROL 0x011f 65#define regPWR_DISP_TIMER2_CONTROL_BASE_IDX 2 66#define regPWR_DISP_TIMER2_DEBUG 0x0120 67#define regPWR_DISP_TIMER2_DEBUG_BASE_IDX 2 68#define regPWR_DISP_TIMER_GLOBAL_CONTROL 0x0121 69#define regPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX 2 70#define regPWR_IH_CONTROL 0x0122 71#define regPWR_IH_CONTROL_BASE_IDX 2 72 73 74// addressBlock: aid_smuio_smuio_misc_SmuSmuioDec 75// base address: 0x5a000 76#define regSMUIO_MCM_CONFIG 0x0023 77#define regSMUIO_MCM_CONFIG_BASE_IDX 1 78#define regIP_DISCOVERY_VERSION 0x0000 79#define regIP_DISCOVERY_VERSION_BASE_IDX 2 80#define regSCRATCH_REGISTER0 0x01bd 81#define regSCRATCH_REGISTER0_BASE_IDX 2 82#define regSCRATCH_REGISTER1 0x01be 83#define regSCRATCH_REGISTER1_BASE_IDX 2 84#define regSCRATCH_REGISTER2 0x01bf 85#define regSCRATCH_REGISTER2_BASE_IDX 2 86#define regSCRATCH_REGISTER3 0x01c0 87#define regSCRATCH_REGISTER3_BASE_IDX 2 88#define regSCRATCH_REGISTER4 0x01c1 89#define regSCRATCH_REGISTER4_BASE_IDX 2 90#define regSCRATCH_REGISTER5 0x01c2 91#define regSCRATCH_REGISTER5_BASE_IDX 2 92#define regSCRATCH_REGISTER6 0x01c3 93#define regSCRATCH_REGISTER6_BASE_IDX 2 94#define regSCRATCH_REGISTER7 0x01c4 95#define regSCRATCH_REGISTER7_BASE_IDX 2 96 97 98// addressBlock: aid_smuio_smuio_gpio_SmuSmuioDec 99// base address: 0x5a500 100#define regSMU_GPIOPAD_SW_INT_STAT 0x0140 101#define regSMU_GPIOPAD_SW_INT_STAT_BASE_IDX 1 102#define regSMU_GPIOPAD_MASK 0x0141 103#define regSMU_GPIOPAD_MASK_BASE_IDX 1 104#define regSMU_GPIOPAD_A 0x0142 105#define regSMU_GPIOPAD_A_BASE_IDX 1 106#define regSMU_GPIOPAD_TXIMPSEL 0x0143 107#define regSMU_GPIOPAD_TXIMPSEL_BASE_IDX 1 108#define regSMU_GPIOPAD_EN 0x0144 109#define regSMU_GPIOPAD_EN_BASE_IDX 1 110#define regSMU_GPIOPAD_Y 0x0145 111#define regSMU_GPIOPAD_Y_BASE_IDX 1 112#define regSMU_GPIOPAD_RXEN 0x0146 113#define regSMU_GPIOPAD_RXEN_BASE_IDX 1 114#define regSMU_GPIOPAD_RCVR_SEL0 0x0147 115#define regSMU_GPIOPAD_RCVR_SEL0_BASE_IDX 1 116#define regSMU_GPIOPAD_RCVR_SEL1 0x0148 117#define regSMU_GPIOPAD_RCVR_SEL1_BASE_IDX 1 118#define regSMU_GPIOPAD_PU_EN 0x0149 119#define regSMU_GPIOPAD_PU_EN_BASE_IDX 1 120#define regSMU_GPIOPAD_PD_EN 0x014a 121#define regSMU_GPIOPAD_PD_EN_BASE_IDX 1 122#define regSMU_GPIOPAD_PINSTRAPS 0x014b 123#define regSMU_GPIOPAD_PINSTRAPS_BASE_IDX 1 124#define regDFT_PINSTRAPS 0x014c 125#define regDFT_PINSTRAPS_BASE_IDX 1 126#define regSMU_GPIOPAD_INT_STAT_EN 0x014d 127#define regSMU_GPIOPAD_INT_STAT_EN_BASE_IDX 1 128#define regSMU_GPIOPAD_INT_STAT 0x014e 129#define regSMU_GPIOPAD_INT_STAT_BASE_IDX 1 130#define regSMU_GPIOPAD_INT_STAT_AK 0x014f 131#define regSMU_GPIOPAD_INT_STAT_AK_BASE_IDX 1 132#define regSMU_GPIOPAD_INT_EN 0x0150 133#define regSMU_GPIOPAD_INT_EN_BASE_IDX 1 134#define regSMU_GPIOPAD_INT_TYPE 0x0151 135#define regSMU_GPIOPAD_INT_TYPE_BASE_IDX 1 136#define regSMU_GPIOPAD_INT_POLARITY 0x0152 137#define regSMU_GPIOPAD_INT_POLARITY_BASE_IDX 1 138#define regSMUIO_PCC_GPIO_SELECT 0x0155 139#define regSMUIO_PCC_GPIO_SELECT_BASE_IDX 1 140#define regSMU_GPIOPAD_S0 0x0156 141#define regSMU_GPIOPAD_S0_BASE_IDX 1 142#define regSMU_GPIOPAD_S1 0x0157 143#define regSMU_GPIOPAD_S1_BASE_IDX 1 144#define regSMU_GPIOPAD_SCHMEN 0x0158 145#define regSMU_GPIOPAD_SCHMEN_BASE_IDX 1 146#define regSMU_GPIOPAD_SCL_EN 0x0159 147#define regSMU_GPIOPAD_SCL_EN_BASE_IDX 1 148#define regSMU_GPIOPAD_SDA_EN 0x015a 149#define regSMU_GPIOPAD_SDA_EN_BASE_IDX 1 150#define regSMUIO_GPIO_INT0_SELECT 0x015b 151#define regSMUIO_GPIO_INT0_SELECT_BASE_IDX 1 152#define regSMUIO_GPIO_INT1_SELECT 0x015c 153#define regSMUIO_GPIO_INT1_SELECT_BASE_IDX 1 154#define regSMUIO_GPIO_INT2_SELECT 0x015d 155#define regSMUIO_GPIO_INT2_SELECT_BASE_IDX 1 156#define regSMUIO_GPIO_INT3_SELECT 0x015e 157#define regSMUIO_GPIO_INT3_SELECT_BASE_IDX 1 158#define regSMU_GPIOPAD_MP_INT0_STAT 0x015f 159#define regSMU_GPIOPAD_MP_INT0_STAT_BASE_IDX 1 160#define regSMU_GPIOPAD_MP_INT1_STAT 0x0160 161#define regSMU_GPIOPAD_MP_INT1_STAT_BASE_IDX 1 162#define regSMU_GPIOPAD_MP_INT2_STAT 0x0161 163#define regSMU_GPIOPAD_MP_INT2_STAT_BASE_IDX 1 164#define regSMU_GPIOPAD_MP_INT3_STAT 0x0162 165#define regSMU_GPIOPAD_MP_INT3_STAT_BASE_IDX 1 166#define regSMIO_INDEX 0x0163 167#define regSMIO_INDEX_BASE_IDX 1 168#define regS0_VID_SMIO_CNTL 0x0164 169#define regS0_VID_SMIO_CNTL_BASE_IDX 1 170#define regS1_VID_SMIO_CNTL 0x0165 171#define regS1_VID_SMIO_CNTL_BASE_IDX 1 172#define regOPEN_DRAIN_SELECT 0x0166 173#define regOPEN_DRAIN_SELECT_BASE_IDX 1 174#define regSMIO_ENABLE 0x0167 175#define regSMIO_ENABLE_BASE_IDX 1 176 177#endif
~/
Read-only file preview.