FILE
smu_8_0_sh_mask.h
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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h
1/* 2 * SMU_8_0 Register documentation 3 * 4 * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24#ifndef SMU_8_0_SH_MASK_H 25#define SMU_8_0_SH_MASK_H 26 27#define THM_TCON_CSR_CONFIG__TCC_ADDR_MASK 0x3ff 28#define THM_TCON_CSR_CONFIG__TCC_ADDR__SHIFT 0x0 29#define THM_TCON_CSR_CONFIG__TCC_READ_OP_MASK 0x400 30#define THM_TCON_CSR_CONFIG__TCC_READ_OP__SHIFT 0xa 31#define THM_TCON_CSR_DATA__TCC_DATA_MASK 0xfff 32#define THM_TCON_CSR_DATA__TCC_DATA__SHIFT 0x0 33#define THM_TCON_CSR_DATA__TCC_REQ_DONE_MASK 0x1000 34#define THM_TCON_CSR_DATA__TCC_REQ_DONE__SHIFT 0xc 35#define THM_TCON_HTC__HTC_EN_MASK 0x1 36#define THM_TCON_HTC__HTC_EN__SHIFT 0x0 37#define THM_TCON_HTC__RSVD0_MASK 0x2 38#define THM_TCON_HTC__RSVD0__SHIFT 0x1 39#define THM_TCON_HTC__HTC_P_STATE_EN_MASK 0x4 40#define THM_TCON_HTC__HTC_P_STATE_EN__SHIFT 0x2 41#define THM_TCON_HTC__RSVD1_MASK 0x8 42#define THM_TCON_HTC__RSVD1__SHIFT 0x3 43#define THM_TCON_HTC__HTC_ACTIVE_MASK 0x10 44#define THM_TCON_HTC__HTC_ACTIVE__SHIFT 0x4 45#define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK 0x20 46#define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT 0x5 47#define THM_TCON_HTC__HTC_APIC_HI_EN_MASK 0x40 48#define THM_TCON_HTC__HTC_APIC_HI_EN__SHIFT 0x6 49#define THM_TCON_HTC__HTC_APIC_LO_EN_MASK 0x80 50#define THM_TCON_HTC__HTC_APIC_LO_EN__SHIFT 0x7 51#define THM_TCON_HTC__HTC_DIAG_MASK 0x100 52#define THM_TCON_HTC__HTC_DIAG__SHIFT 0x8 53#define THM_TCON_HTC__DIS_PROCHOT_PIN_MASK 0x200 54#define THM_TCON_HTC__DIS_PROCHOT_PIN__SHIFT 0x9 55#define THM_TCON_HTC__HTC_TO_GNB_EN_MASK 0x400 56#define THM_TCON_HTC__HTC_TO_GNB_EN__SHIFT 0xa 57#define THM_TCON_HTC__PROCHOT_TO_GNB_EN_MASK 0x800 58#define THM_TCON_HTC__PROCHOT_TO_GNB_EN__SHIFT 0xb 59#define THM_TCON_HTC__RSVD2_MASK 0xf000 60#define THM_TCON_HTC__RSVD2__SHIFT 0xc 61#define THM_TCON_HTC__HTC_TMP_LMT_MASK 0x7f0000 62#define THM_TCON_HTC__HTC_TMP_LMT__SHIFT 0x10 63#define THM_TCON_HTC__HTC_SLEW_SEL_MASK 0x800000 64#define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT 0x17 65#define THM_TCON_HTC__HTC_HYST_LMT_MASK 0xf000000 66#define THM_TCON_HTC__HTC_HYST_LMT__SHIFT 0x18 67#define THM_TCON_HTC__HTC_PSTATE_LIMIT_MASK 0x70000000 68#define THM_TCON_HTC__HTC_PSTATE_LIMIT__SHIFT 0x1c 69#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK 0x1f 70#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0 71#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK 0x60 72#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5 73#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK 0x80 74#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7 75#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK 0x1f00 76#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8 77#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK 0x30000 78#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10 79#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK 0x40000 80#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12 81#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK 0x80000 82#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13 83#define THM_TCON_CUR_TMP__CUR_TEMP_MASK 0xffe00000 84#define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT 0x15 85#define THM_TCON_THERM_TRIP__RSVD0_MASK 0x1 86#define THM_TCON_THERM_TRIP__RSVD0__SHIFT 0x0 87#define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x2 88#define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1 89#define THM_TCON_THERM_TRIP__RSVD1_MASK 0x4 90#define THM_TCON_THERM_TRIP__RSVD1__SHIFT 0x2 91#define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x8 92#define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3 93#define THM_TCON_THERM_TRIP__RSVD2_MASK 0x10 94#define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4 95#define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x20 96#define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5 97#define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7fffffc0 98#define THM_TCON_THERM_TRIP__RSVD3__SHIFT 0x6 99#define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000 100#define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f 101#define THM_GPIO_PROCHOT_CTRL__TX12_EN_MASK 0x1 102#define THM_GPIO_PROCHOT_CTRL__TX12_EN__SHIFT 0x0 103#define THM_GPIO_PROCHOT_CTRL__PD_MASK 0x2 104#define THM_GPIO_PROCHOT_CTRL__PD__SHIFT 0x1 105#define THM_GPIO_PROCHOT_CTRL__PU_MASK 0x4 106#define THM_GPIO_PROCHOT_CTRL__PU__SHIFT 0x2 107#define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK 0x8 108#define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT 0x3 109#define THM_GPIO_PROCHOT_CTRL__SN_MASK 0x10 110#define THM_GPIO_PROCHOT_CTRL__SN__SHIFT 0x4 111#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK 0x100 112#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT 0x8 113#define THM_GPIO_PROCHOT_CTRL__OE_MASK 0x200 114#define THM_GPIO_PROCHOT_CTRL__OE__SHIFT 0x9 115#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK 0x400 116#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT 0xa 117#define THM_GPIO_PROCHOT_CTRL__A_MASK 0x800 118#define THM_GPIO_PROCHOT_CTRL__A__SHIFT 0xb 119#define THM_GPIO_PROCHOT_CTRL__Y_MASK 0x1000 120#define THM_GPIO_PROCHOT_CTRL__Y__SHIFT 0xc 121#define THM_GPIO_THERMTRIP_CTRL__TX12_EN_MASK 0x1 122#define THM_GPIO_THERMTRIP_CTRL__TX12_EN__SHIFT 0x0 123#define THM_GPIO_THERMTRIP_CTRL__PD_MASK 0x2 124#define THM_GPIO_THERMTRIP_CTRL__PD__SHIFT 0x1 125#define THM_GPIO_THERMTRIP_CTRL__PU_MASK 0x4 126#define THM_GPIO_THERMTRIP_CTRL__PU__SHIFT 0x2 127#define THM_GPIO_THERMTRIP_CTRL__SCHMEN_MASK 0x8 128#define THM_GPIO_THERMTRIP_CTRL__SCHMEN__SHIFT 0x3 129#define THM_GPIO_THERMTRIP_CTRL__SN_MASK 0x10 130#define THM_GPIO_THERMTRIP_CTRL__SN__SHIFT 0x4 131#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE_MASK 0x100 132#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE__SHIFT 0x8 133#define THM_GPIO_THERMTRIP_CTRL__OE_MASK 0x200 134#define THM_GPIO_THERMTRIP_CTRL__OE__SHIFT 0x9 135#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE_MASK 0x400 136#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE__SHIFT 0xa 137#define THM_GPIO_THERMTRIP_CTRL__A_MASK 0x800 138#define THM_GPIO_THERMTRIP_CTRL__A__SHIFT 0xb 139#define THM_GPIO_THERMTRIP_CTRL__Y_MASK 0x1000 140#define THM_GPIO_THERMTRIP_CTRL__Y__SHIFT 0xc 141#define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1 142#define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 143#define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2 144#define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 145#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4 146#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 147#define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8 148#define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 149#define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10 150#define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 151#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20 152#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 153#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff 154#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 155#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00 156#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 157#define THM_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000 158#define THM_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10 159#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000 160#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 161#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000 162#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 163#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000 164#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a 165#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000 166#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b 167#define THM_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000 168#define THM_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c 169#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1 170#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 171#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2 172#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 173#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4 174#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 175#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8 176#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3 177#define TMON0_RDIL0_DATA__TEMP_Z_DATA_MASK 0xfff 178#define TMON0_RDIL0_DATA__TEMP_Z_DATA__SHIFT 0x0 179#define TMON0_RDIL1_DATA__TEMP_Z_DATA_MASK 0xfff 180#define TMON0_RDIL1_DATA__TEMP_Z_DATA__SHIFT 0x0 181#define TMON0_RDIL2_DATA__TEMP_Z_DATA_MASK 0xfff 182#define TMON0_RDIL2_DATA__TEMP_Z_DATA__SHIFT 0x0 183#define TMON0_RDIL3_DATA__TEMP_Z_DATA_MASK 0xfff 184#define TMON0_RDIL3_DATA__TEMP_Z_DATA__SHIFT 0x0 185#define TMON0_RDIL4_DATA__TEMP_Z_DATA_MASK 0xfff 186#define TMON0_RDIL4_DATA__TEMP_Z_DATA__SHIFT 0x0 187#define TMON0_RDIL5_DATA__TEMP_Z_DATA_MASK 0xfff 188#define TMON0_RDIL5_DATA__TEMP_Z_DATA__SHIFT 0x0 189#define TMON0_RDIL6_DATA__TEMP_Z_DATA_MASK 0xfff 190#define TMON0_RDIL6_DATA__TEMP_Z_DATA__SHIFT 0x0 191#define TMON0_RDIL7_DATA__TEMP_Z_DATA_MASK 0xfff 192#define TMON0_RDIL7_DATA__TEMP_Z_DATA__SHIFT 0x0 193#define TMON0_RDIL8_DATA__TEMP_Z_DATA_MASK 0xfff 194#define TMON0_RDIL8_DATA__TEMP_Z_DATA__SHIFT 0x0 195#define TMON0_RDIL9_DATA__TEMP_Z_DATA_MASK 0xfff 196#define TMON0_RDIL9_DATA__TEMP_Z_DATA__SHIFT 0x0 197#define TMON0_RDIL10_DATA__TEMP_Z_DATA_MASK 0xfff 198#define TMON0_RDIL10_DATA__TEMP_Z_DATA__SHIFT 0x0 199#define TMON0_RDIL11_DATA__TEMP_Z_DATA_MASK 0xfff 200#define TMON0_RDIL11_DATA__TEMP_Z_DATA__SHIFT 0x0 201#define TMON0_RDIL12_DATA__TEMP_Z_DATA_MASK 0xfff 202#define TMON0_RDIL12_DATA__TEMP_Z_DATA__SHIFT 0x0 203#define TMON0_RDIL13_DATA__TEMP_Z_DATA_MASK 0xfff 204#define TMON0_RDIL13_DATA__TEMP_Z_DATA__SHIFT 0x0 205#define TMON0_RDIL14_DATA__TEMP_Z_DATA_MASK 0xfff 206#define TMON0_RDIL14_DATA__TEMP_Z_DATA__SHIFT 0x0 207#define TMON0_RDIL15_DATA__TEMP_Z_DATA_MASK 0xfff 208#define TMON0_RDIL15_DATA__TEMP_Z_DATA__SHIFT 0x0 209#define TMON0_RDIR0_DATA__TEMP_Z_DATA_MASK 0xfff 210#define TMON0_RDIR0_DATA__TEMP_Z_DATA__SHIFT 0x0 211#define TMON0_RDIR1_DATA__TEMP_Z_DATA_MASK 0xfff 212#define TMON0_RDIR1_DATA__TEMP_Z_DATA__SHIFT 0x0 213#define TMON0_RDIR2_DATA__TEMP_Z_DATA_MASK 0xfff 214#define TMON0_RDIR2_DATA__TEMP_Z_DATA__SHIFT 0x0 215#define TMON0_RDIR3_DATA__TEMP_Z_DATA_MASK 0xfff 216#define TMON0_RDIR3_DATA__TEMP_Z_DATA__SHIFT 0x0 217#define TMON0_RDIR4_DATA__TEMP_Z_DATA_MASK 0xfff 218#define TMON0_RDIR4_DATA__TEMP_Z_DATA__SHIFT 0x0 219#define TMON0_RDIR5_DATA__TEMP_Z_DATA_MASK 0xfff 220#define TMON0_RDIR5_DATA__TEMP_Z_DATA__SHIFT 0x0 221#define TMON0_RDIR6_DATA__TEMP_Z_DATA_MASK 0xfff 222#define TMON0_RDIR6_DATA__TEMP_Z_DATA__SHIFT 0x0 223#define TMON0_RDIR7_DATA__TEMP_Z_DATA_MASK 0xfff 224#define TMON0_RDIR7_DATA__TEMP_Z_DATA__SHIFT 0x0 225#define TMON0_RDIR8_DATA__TEMP_Z_DATA_MASK 0xfff 226#define TMON0_RDIR8_DATA__TEMP_Z_DATA__SHIFT 0x0 227#define TMON0_RDIR9_DATA__TEMP_Z_DATA_MASK 0xfff 228#define TMON0_RDIR9_DATA__TEMP_Z_DATA__SHIFT 0x0 229#define TMON0_RDIR10_DATA__TEMP_Z_DATA_MASK 0xfff 230#define TMON0_RDIR10_DATA__TEMP_Z_DATA__SHIFT 0x0 231#define TMON0_RDIR11_DATA__TEMP_Z_DATA_MASK 0xfff 232#define TMON0_RDIR11_DATA__TEMP_Z_DATA__SHIFT 0x0 233#define TMON0_RDIR12_DATA__TEMP_Z_DATA_MASK 0xfff 234#define TMON0_RDIR12_DATA__TEMP_Z_DATA__SHIFT 0x0 235#define TMON0_RDIR13_DATA__TEMP_Z_DATA_MASK 0xfff 236#define TMON0_RDIR13_DATA__TEMP_Z_DATA__SHIFT 0x0 237#define TMON0_RDIR14_DATA__TEMP_Z_DATA_MASK 0xfff 238#define TMON0_RDIR14_DATA__TEMP_Z_DATA__SHIFT 0x0 239#define TMON0_RDIR15_DATA__TEMP_Z_DATA_MASK 0xfff 240#define TMON0_RDIR15_DATA__TEMP_Z_DATA__SHIFT 0x0 241#define TMON0_INT_DATA__TEMP_Z_DATA_MASK 0xfff 242#define TMON0_INT_DATA__TEMP_Z_DATA__SHIFT 0x0 243#define TMON0_RDIL_PRESENT0__RDIL_PRESENT_7_0_MASK 0xff 244#define TMON0_RDIL_PRESENT0__RDIL_PRESENT_7_0__SHIFT 0x0 245#define TMON0_RDIL_PRESENT1__RDIL_PRESENT_15_8_MASK 0xff 246#define TMON0_RDIL_PRESENT1__RDIL_PRESENT_15_8__SHIFT 0x0 247#define TMON0_RDIR_PRESENT0__RDIR_PRESENT_7_0_MASK 0xff 248#define TMON0_RDIR_PRESENT0__RDIR_PRESENT_7_0__SHIFT 0x0 249#define TMON0_RDIR_PRESENT1__RDIR_PRESENT_15_8_MASK 0xff 250#define TMON0_RDIR_PRESENT1__RDIR_PRESENT_15_8__SHIFT 0x0 251#define TMON0_CONFIG__NUM_ACQ_MASK 0x7 252#define TMON0_CONFIG__NUM_ACQ__SHIFT 0x0 253#define TMON0_CONFIG__FORCE_MAX_ACQ_MASK 0x8 254#define TMON0_CONFIG__FORCE_MAX_ACQ__SHIFT 0x3 255#define TMON0_CONFIG__RDI_INTERLEAVE_MASK 0x10 256#define TMON0_CONFIG__RDI_INTERLEAVE__SHIFT 0x4 257#define TMON0_CONFIG__RE_CALIB_EN_MASK 0x40 258#define TMON0_CONFIG__RE_CALIB_EN__SHIFT 0x6 259#define TMON0_TEMP_CALC_COEFF0__Z_MASK 0x7ff 260#define TMON0_TEMP_CALC_COEFF0__Z__SHIFT 0x0 261#define TMON0_TEMP_CALC_COEFF1__A_MASK 0xfff 262#define TMON0_TEMP_CALC_COEFF1__A__SHIFT 0x0 263#define TMON0_TEMP_CALC_COEFF2__B_MASK 0x3f 264#define TMON0_TEMP_CALC_COEFF2__B__SHIFT 0x0 265#define TMON0_TEMP_CALC_COEFF3__C_MASK 0x7ff 266#define TMON0_TEMP_CALC_COEFF3__C__SHIFT 0x0 267#define TMON0_TEMP_CALC_COEFF4__K_MASK 0x1 268#define TMON0_TEMP_CALC_COEFF4__K__SHIFT 0x0 269#define TMON0_DEBUG0__DEBUG_Z_MASK 0x7ff 270#define TMON0_DEBUG0__DEBUG_Z__SHIFT 0x0 271#define TMON0_DEBUG0__DEBUG_Z_EN_MASK 0x800 272#define TMON0_DEBUG0__DEBUG_Z_EN__SHIFT 0xb 273#define TMON0_DEBUG1__DEBUG_RDI_MASK 0x1f 274#define TMON0_DEBUG1__DEBUG_RDI__SHIFT 0x0 275#define TMON1_RDIL0_DATA__TEMP_Z_DATA_MASK 0xfff 276#define TMON1_RDIL0_DATA__TEMP_Z_DATA__SHIFT 0x0 277#define TMON1_RDIL1_DATA__TEMP_Z_DATA_MASK 0xfff 278#define TMON1_RDIL1_DATA__TEMP_Z_DATA__SHIFT 0x0 279#define TMON1_RDIL2_DATA__TEMP_Z_DATA_MASK 0xfff 280#define TMON1_RDIL2_DATA__TEMP_Z_DATA__SHIFT 0x0 281#define TMON1_RDIL3_DATA__TEMP_Z_DATA_MASK 0xfff 282#define TMON1_RDIL3_DATA__TEMP_Z_DATA__SHIFT 0x0 283#define TMON1_RDIL4_DATA__TEMP_Z_DATA_MASK 0xfff 284#define TMON1_RDIL4_DATA__TEMP_Z_DATA__SHIFT 0x0 285#define TMON1_RDIL5_DATA__TEMP_Z_DATA_MASK 0xfff 286#define TMON1_RDIL5_DATA__TEMP_Z_DATA__SHIFT 0x0 287#define TMON1_RDIL6_DATA__TEMP_Z_DATA_MASK 0xfff 288#define TMON1_RDIL6_DATA__TEMP_Z_DATA__SHIFT 0x0 289#define TMON1_RDIL7_DATA__TEMP_Z_DATA_MASK 0xfff 290#define TMON1_RDIL7_DATA__TEMP_Z_DATA__SHIFT 0x0 291#define TMON1_RDIL8_DATA__TEMP_Z_DATA_MASK 0xfff 292#define TMON1_RDIL8_DATA__TEMP_Z_DATA__SHIFT 0x0 293#define TMON1_RDIL9_DATA__TEMP_Z_DATA_MASK 0xfff 294#define TMON1_RDIL9_DATA__TEMP_Z_DATA__SHIFT 0x0 295#define TMON1_RDIL10_DATA__TEMP_Z_DATA_MASK 0xfff 296#define TMON1_RDIL10_DATA__TEMP_Z_DATA__SHIFT 0x0 297#define TMON1_RDIL11_DATA__TEMP_Z_DATA_MASK 0xfff 298#define TMON1_RDIL11_DATA__TEMP_Z_DATA__SHIFT 0x0 299#define TMON1_RDIL12_DATA__TEMP_Z_DATA_MASK 0xfff 300#define TMON1_RDIL12_DATA__TEMP_Z_DATA__SHIFT 0x0 301#define TMON1_RDIL13_DATA__TEMP_Z_DATA_MASK 0xfff 302#define TMON1_RDIL13_DATA__TEMP_Z_DATA__SHIFT 0x0 303#define TMON1_RDIL14_DATA__TEMP_Z_DATA_MASK 0xfff 304#define TMON1_RDIL14_DATA__TEMP_Z_DATA__SHIFT 0x0 305#define TMON1_RDIL15_DATA__TEMP_Z_DATA_MASK 0xfff 306#define TMON1_RDIL15_DATA__TEMP_Z_DATA__SHIFT 0x0 307#define TMON1_RDIR0_DATA__TEMP_Z_DATA_MASK 0xfff 308#define TMON1_RDIR0_DATA__TEMP_Z_DATA__SHIFT 0x0 309#define TMON1_RDIR1_DATA__TEMP_Z_DATA_MASK 0xfff 310#define TMON1_RDIR1_DATA__TEMP_Z_DATA__SHIFT 0x0 311#define TMON1_RDIR2_DATA__TEMP_Z_DATA_MASK 0xfff 312#define TMON1_RDIR2_DATA__TEMP_Z_DATA__SHIFT 0x0 313#define TMON1_RDIR3_DATA__TEMP_Z_DATA_MASK 0xfff 314#define TMON1_RDIR3_DATA__TEMP_Z_DATA__SHIFT 0x0 315#define TMON1_RDIR4_DATA__TEMP_Z_DATA_MASK 0xfff 316#define TMON1_RDIR4_DATA__TEMP_Z_DATA__SHIFT 0x0 317#define TMON1_RDIR5_DATA__TEMP_Z_DATA_MASK 0xfff 318#define TMON1_RDIR5_DATA__TEMP_Z_DATA__SHIFT 0x0 319#define TMON1_RDIR6_DATA__TEMP_Z_DATA_MASK 0xfff 320#define TMON1_RDIR6_DATA__TEMP_Z_DATA__SHIFT 0x0 321#define TMON1_RDIR7_DATA__TEMP_Z_DATA_MASK 0xfff 322#define TMON1_RDIR7_DATA__TEMP_Z_DATA__SHIFT 0x0 323#define TMON1_RDIR8_DATA__TEMP_Z_DATA_MASK 0xfff 324#define TMON1_RDIR8_DATA__TEMP_Z_DATA__SHIFT 0x0 325#define TMON1_RDIR9_DATA__TEMP_Z_DATA_MASK 0xfff 326#define TMON1_RDIR9_DATA__TEMP_Z_DATA__SHIFT 0x0 327#define TMON1_RDIR10_DATA__TEMP_Z_DATA_MASK 0xfff 328#define TMON1_RDIR10_DATA__TEMP_Z_DATA__SHIFT 0x0 329#define TMON1_RDIR11_DATA__TEMP_Z_DATA_MASK 0xfff 330#define TMON1_RDIR11_DATA__TEMP_Z_DATA__SHIFT 0x0 331#define TMON1_RDIR12_DATA__TEMP_Z_DATA_MASK 0xfff 332#define TMON1_RDIR12_DATA__TEMP_Z_DATA__SHIFT 0x0 333#define TMON1_RDIR13_DATA__TEMP_Z_DATA_MASK 0xfff 334#define TMON1_RDIR13_DATA__TEMP_Z_DATA__SHIFT 0x0 335#define TMON1_RDIR14_DATA__TEMP_Z_DATA_MASK 0xfff 336#define TMON1_RDIR14_DATA__TEMP_Z_DATA__SHIFT 0x0 337#define TMON1_RDIR15_DATA__TEMP_Z_DATA_MASK 0xfff 338#define TMON1_RDIR15_DATA__TEMP_Z_DATA__SHIFT 0x0 339#define TMON1_INT_DATA__TEMP_Z_DATA_MASK 0xfff 340#define TMON1_INT_DATA__TEMP_Z_DATA__SHIFT 0x0 341#define TMON1_RDIL_PRESENT0__RDIL_PRESENT_7_0_MASK 0xff 342#define TMON1_RDIL_PRESENT0__RDIL_PRESENT_7_0__SHIFT 0x0 343#define TMON1_RDIL_PRESENT1__RDIL_PRESENT_15_8_MASK 0xff 344#define TMON1_RDIL_PRESENT1__RDIL_PRESENT_15_8__SHIFT 0x0 345#define TMON1_RDIR_PRESENT0__RDIR_PRESENT_7_0_MASK 0xff 346#define TMON1_RDIR_PRESENT0__RDIR_PRESENT_7_0__SHIFT 0x0 347#define TMON1_RDIR_PRESENT1__RDIR_PRESENT_15_8_MASK 0xff 348#define TMON1_RDIR_PRESENT1__RDIR_PRESENT_15_8__SHIFT 0x0 349#define TMON1_CONFIG__NUM_ACQ_MASK 0x7 350#define TMON1_CONFIG__NUM_ACQ__SHIFT 0x0 351#define TMON1_CONFIG__FORCE_MAX_ACQ_MASK 0x8 352#define TMON1_CONFIG__FORCE_MAX_ACQ__SHIFT 0x3 353#define TMON1_CONFIG__RDI_INTERLEAVE_MASK 0x10 354#define TMON1_CONFIG__RDI_INTERLEAVE__SHIFT 0x4 355#define TMON1_CONFIG__RE_CALIB_EN_MASK 0x40 356#define TMON1_CONFIG__RE_CALIB_EN__SHIFT 0x6 357#define TMON1_TEMP_CALC_COEFF0__Z_MASK 0x7ff 358#define TMON1_TEMP_CALC_COEFF0__Z__SHIFT 0x0 359#define TMON1_TEMP_CALC_COEFF1__A_MASK 0xfff 360#define TMON1_TEMP_CALC_COEFF1__A__SHIFT 0x0 361#define TMON1_TEMP_CALC_COEFF2__B_MASK 0x3f 362#define TMON1_TEMP_CALC_COEFF2__B__SHIFT 0x0 363#define TMON1_TEMP_CALC_COEFF3__C_MASK 0x7ff 364#define TMON1_TEMP_CALC_COEFF3__C__SHIFT 0x0 365#define TMON1_TEMP_CALC_COEFF4__K_MASK 0x1 366#define TMON1_TEMP_CALC_COEFF4__K__SHIFT 0x0 367#define TMON1_DEBUG0__DEBUG_Z_MASK 0x7ff 368#define TMON1_DEBUG0__DEBUG_Z__SHIFT 0x0 369#define TMON1_DEBUG0__DEBUG_Z_EN_MASK 0x800 370#define TMON1_DEBUG0__DEBUG_Z_EN__SHIFT 0xb 371#define TMON1_DEBUG1__DEBUG_RDI_MASK 0x1f 372#define TMON1_DEBUG1__DEBUG_RDI__SHIFT 0x0 373#define THM_TMON0_REMOTE_START__DATA_MASK 0xffffffff 374#define THM_TMON0_REMOTE_START__DATA__SHIFT 0x0 375#define THM_TMON0_REMOTE_END__DATA_MASK 0xffffffff 376#define THM_TMON0_REMOTE_END__DATA__SHIFT 0x0 377#define THM_TMON1_REMOTE_START__DATA_MASK 0xffffffff 378#define THM_TMON1_REMOTE_START__DATA__SHIFT 0x0 379#define THM_TMON1_REMOTE_END__DATA_MASK 0xffffffff 380#define THM_TMON1_REMOTE_END__DATA__SHIFT 0x0 381#define THM_TCON_LOCAL0__HaltPolling_MASK 0x1 382#define THM_TCON_LOCAL0__HaltPolling__SHIFT 0x0 383#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis_MASK 0x2 384#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis__SHIFT 0x1 385#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis_MASK 0x4 386#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis__SHIFT 0x2 387#define THM_TCON_LOCAL1__PwrDn_Limit_Temp_MASK 0x7 388#define THM_TCON_LOCAL1__PwrDn_Limit_Temp__SHIFT 0x0 389#define THM_TCON_LOCAL1__PwrDn_DelaySlope_MASK 0x38 390#define THM_TCON_LOCAL1__PwrDn_DelaySlope__SHIFT 0x3 391#define THM_TCON_LOCAL1__PwrDn_MinDelay_MASK 0x1c0 392#define THM_TCON_LOCAL1__PwrDn_MinDelay__SHIFT 0x6 393#define THM_TCON_LOCAL2__PwrDn_MaxDlyMult_MASK 0x3 394#define THM_TCON_LOCAL2__PwrDn_MaxDlyMult__SHIFT 0x0 395#define THM_TCON_LOCAL2__PwrDn_NumSensors_MASK 0xc 396#define THM_TCON_LOCAL2__PwrDn_NumSensors__SHIFT 0x2 397#define THM_TCON_LOCAL2__start_mission_polling_MASK 0x10 398#define THM_TCON_LOCAL2__start_mission_polling__SHIFT 0x4 399#define THM_TCON_LOCAL2__short_stagger_count_MASK 0x20 400#define THM_TCON_LOCAL2__short_stagger_count__SHIFT 0x5 401#define THM_TCON_LOCAL2__sbtsi_use_corrected_MASK 0x40 402#define THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT 0x6 403#define THM_TCON_LOCAL2__csrslave_use_corrected_MASK 0x80 404#define THM_TCON_LOCAL2__csrslave_use_corrected__SHIFT 0x7 405#define THM_TCON_LOCAL2__smu_use_corrected_MASK 0x100 406#define THM_TCON_LOCAL2__smu_use_corrected__SHIFT 0x8 407#define THM_TCON_LOCAL2__skip_scale_correction_MASK 0x800 408#define THM_TCON_LOCAL2__skip_scale_correction__SHIFT 0xb 409#define THM_TCON_LOCAL3__Global_TMAX_MASK 0x7ff 410#define THM_TCON_LOCAL3__Global_TMAX__SHIFT 0x0 411#define THM_TCON_LOCAL4__Global_TMAX_ID_MASK 0xff 412#define THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT 0x0 413#define THM_TCON_LOCAL5__Global_TMIN_MASK 0x7ff 414#define THM_TCON_LOCAL5__Global_TMIN__SHIFT 0x0 415#define THM_TCON_LOCAL6__Global_TMIN_ID_MASK 0xff 416#define THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT 0x0 417#define THM_TCON_LOCAL7__THERMID_MASK 0xff 418#define THM_TCON_LOCAL7__THERMID__SHIFT 0x0 419#define THM_TCON_LOCAL8__THERMMAX_MASK 0x7ff 420#define THM_TCON_LOCAL8__THERMMAX__SHIFT 0x0 421#define THM_TCON_LOCAL9__Tj_Max_TMON0_MASK 0x7ff 422#define THM_TCON_LOCAL9__Tj_Max_TMON0__SHIFT 0x0 423#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID_MASK 0xf 424#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID__SHIFT 0x0 425#define THM_TCON_LOCAL11__Tj_Max_TMON1_MASK 0x7ff 426#define THM_TCON_LOCAL11__Tj_Max_TMON1__SHIFT 0x0 427#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID_MASK 0xf 428#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID__SHIFT 0x0 429#define THM_TCON_LOCAL13__PowerDownTmon0_MASK 0x1 430#define THM_TCON_LOCAL13__PowerDownTmon0__SHIFT 0x0 431#define THM_TCON_LOCAL13__PowerDownTmon1_MASK 0x2 432#define THM_TCON_LOCAL13__PowerDownTmon1__SHIFT 0x1 433#define THM_TCON_LOCAL14__boot_done_MASK 0x1 434#define THM_TCON_LOCAL14__boot_done__SHIFT 0x0 435#define THM_FUSE0__FUSE_TmonRsInterleave_MASK 0x1 436#define THM_FUSE0__FUSE_TmonRsInterleave__SHIFT 0x0 437#define THM_FUSE0__FUSE_TmonNumAcq_MASK 0xe 438#define THM_FUSE0__FUSE_TmonNumAcq__SHIFT 0x1 439#define THM_FUSE0__FUSE_TmonForceMaxAcq_MASK 0x10 440#define THM_FUSE0__FUSE_TmonForceMaxAcq__SHIFT 0x4 441#define THM_FUSE0__FUSE_TmonClkDiv_MASK 0x60 442#define THM_FUSE0__FUSE_TmonClkDiv__SHIFT 0x5 443#define THM_FUSE0__FUSE_TmonBGAdj1_MASK 0x7f80 444#define THM_FUSE0__FUSE_TmonBGAdj1__SHIFT 0x7 445#define THM_FUSE0__FUSE_TmonBGAdj0_MASK 0x7f8000 446#define THM_FUSE0__FUSE_TmonBGAdj0__SHIFT 0xf 447#define THM_FUSE0__FUSE_TconZtValue_MASK 0xff800000 448#define THM_FUSE0__FUSE_TconZtValue__SHIFT 0x17 449#define THM_FUSE1__FUSE_TconZtValue_MASK 0x3 450#define THM_FUSE1__FUSE_TconZtValue__SHIFT 0x0 451#define THM_FUSE1__FUSE_TconUseSecondary_MASK 0xc 452#define THM_FUSE1__FUSE_TconUseSecondary__SHIFT 0x2 453#define THM_FUSE1__FUSE_TconTmpAdjLoRes_MASK 0x10 454#define THM_FUSE1__FUSE_TconTmpAdjLoRes__SHIFT 0x4 455#define THM_FUSE1__FUSE_TconPwrUpStaggerTime_MASK 0x60 456#define THM_FUSE1__FUSE_TconPwrUpStaggerTime__SHIFT 0x5 457#define THM_FUSE1__FUSE_TconPwrDnTmpLmt_MASK 0x380 458#define THM_FUSE1__FUSE_TconPwrDnTmpLmt__SHIFT 0x7 459#define THM_FUSE1__FUSE_TconPwrDnNumSensors_MASK 0xc00 460#define THM_FUSE1__FUSE_TconPwrDnNumSensors__SHIFT 0xa 461#define THM_FUSE1__FUSE_TconPwrDnMinDelay_MASK 0x7000 462#define THM_FUSE1__FUSE_TconPwrDnMinDelay__SHIFT 0xc 463#define THM_FUSE1__FUSE_TconPwrDnMaxDelayMult_MASK 0x18000 464#define THM_FUSE1__FUSE_TconPwrDnMaxDelayMult__SHIFT 0xf 465#define THM_FUSE1__FUSE_TconPwrDnDelaySlope_MASK 0xe0000 466#define THM_FUSE1__FUSE_TconPwrDnDelaySlope__SHIFT 0x11 467#define THM_FUSE1__FUSE_TconKValue_MASK 0x100000 468#define THM_FUSE1__FUSE_TconKValue__SHIFT 0x14 469#define THM_FUSE1__FUSE_TconDtValue31_MASK 0x7e00000 470#define THM_FUSE1__FUSE_TconDtValue31__SHIFT 0x15 471#define THM_FUSE1__FUSE_TconDtValue30_MASK 0xf8000000 472#define THM_FUSE1__FUSE_TconDtValue30__SHIFT 0x1b 473#define THM_FUSE2__FUSE_TconDtValue30_MASK 0x1 474#define THM_FUSE2__FUSE_TconDtValue30__SHIFT 0x0 475#define THM_FUSE2__FUSE_TconDtValue29_MASK 0x7e 476#define THM_FUSE2__FUSE_TconDtValue29__SHIFT 0x1 477#define THM_FUSE2__FUSE_TconDtValue28_MASK 0x1f80 478#define THM_FUSE2__FUSE_TconDtValue28__SHIFT 0x7 479#define THM_FUSE2__FUSE_TconDtValue27_MASK 0x7e000 480#define THM_FUSE2__FUSE_TconDtValue27__SHIFT 0xd 481#define THM_FUSE2__FUSE_TconDtValue26_MASK 0x1f80000 482#define THM_FUSE2__FUSE_TconDtValue26__SHIFT 0x13 483#define THM_FUSE2__FUSE_TconDtValue25_MASK 0x7e000000 484#define THM_FUSE2__FUSE_TconDtValue25__SHIFT 0x19 485#define THM_FUSE2__FUSE_TconDtValue24_MASK 0x80000000 486#define THM_FUSE2__FUSE_TconDtValue24__SHIFT 0x1f 487#define THM_FUSE3__FUSE_TconDtValue24_MASK 0x1f 488#define THM_FUSE3__FUSE_TconDtValue24__SHIFT 0x0 489#define THM_FUSE3__FUSE_TconDtValue23_MASK 0x7e0 490#define THM_FUSE3__FUSE_TconDtValue23__SHIFT 0x5 491#define THM_FUSE3__FUSE_TconDtValue22_MASK 0x1f800 492#define THM_FUSE3__FUSE_TconDtValue22__SHIFT 0xb 493#define THM_FUSE3__FUSE_TconDtValue21_MASK 0x7e0000 494#define THM_FUSE3__FUSE_TconDtValue21__SHIFT 0x11 495#define THM_FUSE3__FUSE_TconDtValue20_MASK 0x1f800000 496#define THM_FUSE3__FUSE_TconDtValue20__SHIFT 0x17 497#define THM_FUSE3__FUSE_TconDtValue19_MASK 0xe0000000 498#define THM_FUSE3__FUSE_TconDtValue19__SHIFT 0x1d 499#define THM_FUSE4__FUSE_TconDtValue19_MASK 0x7 500#define THM_FUSE4__FUSE_TconDtValue19__SHIFT 0x0 501#define THM_FUSE4__FUSE_TconDtValue18_MASK 0x1f8 502#define THM_FUSE4__FUSE_TconDtValue18__SHIFT 0x3 503#define THM_FUSE4__FUSE_TconDtValue17_MASK 0x7e00 504#define THM_FUSE4__FUSE_TconDtValue17__SHIFT 0x9 505#define THM_FUSE4__FUSE_TconDtValue16_MASK 0x1f8000 506#define THM_FUSE4__FUSE_TconDtValue16__SHIFT 0xf 507#define THM_FUSE4__FUSE_TconDtValue15_MASK 0x7e00000 508#define THM_FUSE4__FUSE_TconDtValue15__SHIFT 0x15 509#define THM_FUSE4__FUSE_TconDtValue14_MASK 0xf8000000 510#define THM_FUSE4__FUSE_TconDtValue14__SHIFT 0x1b 511#define THM_FUSE5__FUSE_TconDtValue14_MASK 0x1 512#define THM_FUSE5__FUSE_TconDtValue14__SHIFT 0x0 513#define THM_FUSE5__FUSE_TconDtValue13_MASK 0x7e 514#define THM_FUSE5__FUSE_TconDtValue13__SHIFT 0x1 515#define THM_FUSE5__FUSE_TconDtValue12_MASK 0x1f80 516#define THM_FUSE5__FUSE_TconDtValue12__SHIFT 0x7 517#define THM_FUSE5__FUSE_TconDtValue11_MASK 0x7e000 518#define THM_FUSE5__FUSE_TconDtValue11__SHIFT 0xd 519#define THM_FUSE5__FUSE_TconDtValue10_MASK 0x1f80000 520#define THM_FUSE5__FUSE_TconDtValue10__SHIFT 0x13 521#define THM_FUSE5__FUSE_TconDtValue9_MASK 0x7e000000 522#define THM_FUSE5__FUSE_TconDtValue9__SHIFT 0x19 523#define THM_FUSE5__FUSE_TconDtValue8_MASK 0x80000000 524#define THM_FUSE5__FUSE_TconDtValue8__SHIFT 0x1f 525#define THM_FUSE6__FUSE_TconDtValue8_MASK 0x1f 526#define THM_FUSE6__FUSE_TconDtValue8__SHIFT 0x0 527#define THM_FUSE6__FUSE_TconDtValue7_MASK 0x7e0 528#define THM_FUSE6__FUSE_TconDtValue7__SHIFT 0x5 529#define THM_FUSE6__FUSE_TconDtValue6_MASK 0x1f800 530#define THM_FUSE6__FUSE_TconDtValue6__SHIFT 0xb 531#define THM_FUSE6__FUSE_TconDtValue5_MASK 0x7e0000 532#define THM_FUSE6__FUSE_TconDtValue5__SHIFT 0x11 533#define THM_FUSE6__FUSE_TconDtValue4_MASK 0x1f800000 534#define THM_FUSE6__FUSE_TconDtValue4__SHIFT 0x17 535#define THM_FUSE6__FUSE_TconDtValue3_MASK 0xe0000000 536#define THM_FUSE6__FUSE_TconDtValue3__SHIFT 0x1d 537#define THM_FUSE7__FUSE_TconDtValue3_MASK 0x7 538#define THM_FUSE7__FUSE_TconDtValue3__SHIFT 0x0 539#define THM_FUSE7__FUSE_TconDtValue2_MASK 0x1f8 540#define THM_FUSE7__FUSE_TconDtValue2__SHIFT 0x3 541#define THM_FUSE7__FUSE_TconDtValue1_MASK 0x7e00 542#define THM_FUSE7__FUSE_TconDtValue1__SHIFT 0x9 543#define THM_FUSE7__FUSE_TconDtValue0_MASK 0x1f8000 544#define THM_FUSE7__FUSE_TconDtValue0__SHIFT 0xf 545#define THM_FUSE7__FUSE_TconCtValue1_MASK 0xffe00000 546#define THM_FUSE7__FUSE_TconCtValue1__SHIFT 0x15 547#define THM_FUSE8__FUSE_TconCtValue0_MASK 0x7ff 548#define THM_FUSE8__FUSE_TconCtValue0__SHIFT 0x0 549#define THM_FUSE8__FUSE_TconBtValue_MASK 0x1f800 550#define THM_FUSE8__FUSE_TconBtValue__SHIFT 0xb 551#define THM_FUSE8__FUSE_TconBootDelay_MASK 0x60000 552#define THM_FUSE8__FUSE_TconBootDelay__SHIFT 0x11 553#define THM_FUSE8__FUSE_TconAtValue1_MASK 0x7ff80000 554#define THM_FUSE8__FUSE_TconAtValue1__SHIFT 0x13 555#define THM_FUSE8__FUSE_TconAtValue0_MASK 0x80000000 556#define THM_FUSE8__FUSE_TconAtValue0__SHIFT 0x1f 557#define THM_FUSE9__FUSE_TconAtValue0_MASK 0x7ff 558#define THM_FUSE9__FUSE_TconAtValue0__SHIFT 0x0 559#define THM_FUSE9__FUSE_ThermTripLimit_MASK 0x7f800 560#define THM_FUSE9__FUSE_ThermTripLimit__SHIFT 0xb 561#define THM_FUSE9__FUSE_ThermTripEn_MASK 0x80000 562#define THM_FUSE9__FUSE_ThermTripEn__SHIFT 0x13 563#define THM_FUSE9__FUSE_HtcTmpLmt_MASK 0x7f00000 564#define THM_FUSE9__FUSE_HtcTmpLmt__SHIFT 0x14 565#define THM_FUSE9__FUSE_HtcMsrLock_MASK 0x8000000 566#define THM_FUSE9__FUSE_HtcMsrLock__SHIFT 0x1b 567#define THM_FUSE9__FUSE_HtcHystLmt_MASK 0xf0000000 568#define THM_FUSE9__FUSE_HtcHystLmt__SHIFT 0x1c 569#define THM_FUSE10__FUSE_HtcDis_MASK 0x1 570#define THM_FUSE10__FUSE_HtcDis__SHIFT 0x0 571#define THM_FUSE10__FUSE_HtcClkInact_MASK 0xe 572#define THM_FUSE10__FUSE_HtcClkInact__SHIFT 0x1 573#define THM_FUSE10__FUSE_HtcClkAct_MASK 0x70 574#define THM_FUSE10__FUSE_HtcClkAct__SHIFT 0x4 575#define THM_FUSE10__FUSE_UnusedBits_MASK 0xffffff80 576#define THM_FUSE10__FUSE_UnusedBits__SHIFT 0x7 577#define THM_FUSE11__PA_SPARE_MASK 0xff 578#define THM_FUSE11__PA_SPARE__SHIFT 0x0 579#define THM_FUSE12__FusesValid_MASK 0x1 580#define THM_FUSE12__FusesValid__SHIFT 0x0 581#define MP0PUB_IND_INDEX__MP0PUB_IND_ADDR_MASK 0xffffffff 582#define MP0PUB_IND_INDEX__MP0PUB_IND_ADDR__SHIFT 0x0 583#define MP0PUB_IND_DATA__MP0PUB_IND_DATA_MASK 0xffffffff 584#define MP0PUB_IND_DATA__MP0PUB_IND_DATA__SHIFT 0x0 585#define MP0PUB_IND_INDEX_0__MP0PUB_IND_ADDR_MASK 0xffffffff 586#define MP0PUB_IND_INDEX_0__MP0PUB_IND_ADDR__SHIFT 0x0 587#define MP0PUB_IND_DATA_0__MP0PUB_IND_DATA_MASK 0xffffffff 588#define MP0PUB_IND_DATA_0__MP0PUB_IND_DATA__SHIFT 0x0 589#define MP0PUB_IND_INDEX_1__MP0PUB_IND_ADDR_MASK 0xffffffff 590#define MP0PUB_IND_INDEX_1__MP0PUB_IND_ADDR__SHIFT 0x0 591#define MP0PUB_IND_DATA_1__MP0PUB_IND_DATA_MASK 0xffffffff 592#define MP0PUB_IND_DATA_1__MP0PUB_IND_DATA__SHIFT 0x0 593#define MP0PUB_IND_INDEX_2__MP0PUB_IND_ADDR_MASK 0xffffffff 594#define MP0PUB_IND_INDEX_2__MP0PUB_IND_ADDR__SHIFT 0x0 595#define MP0PUB_IND_DATA_2__MP0PUB_IND_DATA_MASK 0xffffffff 596#define MP0PUB_IND_DATA_2__MP0PUB_IND_DATA__SHIFT 0x0 597#define MP0PUB_IND_INDEX_3__MP0PUB_IND_ADDR_MASK 0xffffffff 598#define MP0PUB_IND_INDEX_3__MP0PUB_IND_ADDR__SHIFT 0x0 599#define MP0PUB_IND_DATA_3__MP0PUB_IND_DATA_MASK 0xffffffff 600#define MP0PUB_IND_DATA_3__MP0PUB_IND_DATA__SHIFT 0x0 601#define MP0PUB_IND_INDEX_4__MP0PUB_IND_ADDR_MASK 0xffffffff 602#define MP0PUB_IND_INDEX_4__MP0PUB_IND_ADDR__SHIFT 0x0 603#define MP0PUB_IND_DATA_4__MP0PUB_IND_DATA_MASK 0xffffffff 604#define MP0PUB_IND_DATA_4__MP0PUB_IND_DATA__SHIFT 0x0 605#define MP0PUB_IND_INDEX_5__MP0PUB_IND_ADDR_MASK 0xffffffff 606#define MP0PUB_IND_INDEX_5__MP0PUB_IND_ADDR__SHIFT 0x0 607#define MP0PUB_IND_DATA_5__MP0PUB_IND_DATA_MASK 0xffffffff 608#define MP0PUB_IND_DATA_5__MP0PUB_IND_DATA__SHIFT 0x0 609#define MP0PUB_IND_INDEX_6__MP0PUB_IND_ADDR_MASK 0xffffffff 610#define MP0PUB_IND_INDEX_6__MP0PUB_IND_ADDR__SHIFT 0x0 611#define MP0PUB_IND_DATA_6__MP0PUB_IND_DATA_MASK 0xffffffff 612#define MP0PUB_IND_DATA_6__MP0PUB_IND_DATA__SHIFT 0x0 613#define MP0PUB_IND_INDEX_7__MP0PUB_IND_ADDR_MASK 0xffffffff 614#define MP0PUB_IND_INDEX_7__MP0PUB_IND_ADDR__SHIFT 0x0 615#define MP0PUB_IND_DATA_7__MP0PUB_IND_DATA_MASK 0xffffffff 616#define MP0PUB_IND_DATA_7__MP0PUB_IND_DATA__SHIFT 0x0 617#define MP0PUB_IND_INDEX_8__MP0PUB_IND_ADDR_MASK 0xffffffff 618#define MP0PUB_IND_INDEX_8__MP0PUB_IND_ADDR__SHIFT 0x0 619#define MP0PUB_IND_DATA_8__MP0PUB_IND_DATA_MASK 0xffffffff 620#define MP0PUB_IND_DATA_8__MP0PUB_IND_DATA__SHIFT 0x0 621#define MP0PUB_IND_INDEX_9__MP0PUB_IND_ADDR_MASK 0xffffffff 622#define MP0PUB_IND_INDEX_9__MP0PUB_IND_ADDR__SHIFT 0x0 623#define MP0PUB_IND_DATA_9__MP0PUB_IND_DATA_MASK 0xffffffff 624#define MP0PUB_IND_DATA_9__MP0PUB_IND_DATA__SHIFT 0x0 625#define MP0PUB_IND_INDEX_10__MP0PUB_IND_ADDR_MASK 0xffffffff 626#define MP0PUB_IND_INDEX_10__MP0PUB_IND_ADDR__SHIFT 0x0 627#define MP0PUB_IND_DATA_10__MP0PUB_IND_DATA_MASK 0xffffffff 628#define MP0PUB_IND_DATA_10__MP0PUB_IND_DATA__SHIFT 0x0 629#define MP0PUB_IND_INDEX_11__MP0PUB_IND_ADDR_MASK 0xffffffff 630#define MP0PUB_IND_INDEX_11__MP0PUB_IND_ADDR__SHIFT 0x0 631#define MP0PUB_IND_DATA_11__MP0PUB_IND_DATA_MASK 0xffffffff 632#define MP0PUB_IND_DATA_11__MP0PUB_IND_DATA__SHIFT 0x0 633#define MP0PUB_IND_INDEX_12__MP0PUB_IND_ADDR_MASK 0xffffffff 634#define MP0PUB_IND_INDEX_12__MP0PUB_IND_ADDR__SHIFT 0x0 635#define MP0PUB_IND_DATA_12__MP0PUB_IND_DATA_MASK 0xffffffff 636#define MP0PUB_IND_DATA_12__MP0PUB_IND_DATA__SHIFT 0x0 637#define MP0PUB_IND_INDEX_13__MP0PUB_IND_ADDR_MASK 0xffffffff 638#define MP0PUB_IND_INDEX_13__MP0PUB_IND_ADDR__SHIFT 0x0 639#define MP0PUB_IND_DATA_13__MP0PUB_IND_DATA_MASK 0xffffffff 640#define MP0PUB_IND_DATA_13__MP0PUB_IND_DATA__SHIFT 0x0 641#define MP0PUB_IND_INDEX_14__MP0PUB_IND_ADDR_MASK 0xffffffff 642#define MP0PUB_IND_INDEX_14__MP0PUB_IND_ADDR__SHIFT 0x0 643#define MP0PUB_IND_DATA_14__MP0PUB_IND_DATA_MASK 0xffffffff 644#define MP0PUB_IND_DATA_14__MP0PUB_IND_DATA__SHIFT 0x0 645#define MP0PUB_IND_INDEX_15__MP0PUB_IND_ADDR_MASK 0xffffffff 646#define MP0PUB_IND_INDEX_15__MP0PUB_IND_ADDR__SHIFT 0x0 647#define MP0PUB_IND_DATA_15__MP0PUB_IND_DATA_MASK 0xffffffff 648#define MP0PUB_IND_DATA_15__MP0PUB_IND_DATA__SHIFT 0x0 649#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1 650#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0 651#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2 652#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1 653#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4 654#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2 655#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8 656#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3 657#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10 658#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4 659#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20 660#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5 661#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40 662#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6 663#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80 664#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7 665#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100 666#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT 0x8 667#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK 0x200 668#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT 0x9 669#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK 0x400 670#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT 0xa 671#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800 672#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT 0xb 673#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK 0x1000 674#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT 0xc 675#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK 0x2000 676#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT 0xd 677#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK 0x4000 678#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT 0xe 679#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK 0x8000 680#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT 0xf 681#define MP0_MSP_MESSAGE_0__MP0_MSP_MSG_MASK 0xffffffff 682#define MP0_MSP_MESSAGE_0__MP0_MSP_MSG__SHIFT 0x0 683#define MP0_MSP_MESSAGE_1__MP0_MSP_MSG_MASK 0xffffffff 684#define MP0_MSP_MESSAGE_1__MP0_MSP_MSG__SHIFT 0x0 685#define MP0_MSP_MESSAGE_2__MP0_MSP_MSG_MASK 0xffffffff 686#define MP0_MSP_MESSAGE_2__MP0_MSP_MSG__SHIFT 0x0 687#define MP0_MSP_MESSAGE_3__MP0_MSP_MSG_MASK 0xffffffff 688#define MP0_MSP_MESSAGE_3__MP0_MSP_MSG__SHIFT 0x0 689#define MP0_MSP_MESSAGE_4__MP0_MSP_MSG_MASK 0xffffffff 690#define MP0_MSP_MESSAGE_4__MP0_MSP_MSG__SHIFT 0x0 691#define MP0_MSP_MESSAGE_5__MP0_MSP_MSG_MASK 0xffffffff 692#define MP0_MSP_MESSAGE_5__MP0_MSP_MSG__SHIFT 0x0 693#define MP0_MSP_MESSAGE_6__MP0_MSP_MSG_MASK 0xffffffff 694#define MP0_MSP_MESSAGE_6__MP0_MSP_MSG__SHIFT 0x0 695#define MP0_MSP_MESSAGE_7__MP0_MSP_MSG_MASK 0xffffffff 696#define MP0_MSP_MESSAGE_7__MP0_MSP_MSG__SHIFT 0x0 697#define SAM_IH_EXT_ERR_INTR__UVD_MASK 0x1 698#define SAM_IH_EXT_ERR_INTR__UVD__SHIFT 0x0 699#define SAM_IH_EXT_ERR_INTR__VCE_MASK 0x2 700#define SAM_IH_EXT_ERR_INTR__VCE__SHIFT 0x1 701#define SAM_IH_EXT_ERR_INTR__ISP_MASK 0x4 702#define SAM_IH_EXT_ERR_INTR__ISP__SHIFT 0x2 703#define SAM_IH_EXT_ERR_INTR__RESERVED_MASK 0xfffffff8 704#define SAM_IH_EXT_ERR_INTR__RESERVED__SHIFT 0x3 705#define SAM_IH_EXT_ERR_INTR_STATUS__UVD_MASK 0x1 706#define SAM_IH_EXT_ERR_INTR_STATUS__UVD__SHIFT 0x0 707#define SAM_IH_EXT_ERR_INTR_STATUS__VCE_MASK 0x2 708#define SAM_IH_EXT_ERR_INTR_STATUS__VCE__SHIFT 0x1 709#define SAM_IH_EXT_ERR_INTR_STATUS__ISP_MASK 0x4 710#define SAM_IH_EXT_ERR_INTR_STATUS__ISP__SHIFT 0x2 711#define SAM_IH_EXT_ERR_INTR_STATUS__RESERVED_MASK 0xfffffff8 712#define SAM_IH_EXT_ERR_INTR_STATUS__RESERVED__SHIFT 0x3 713#define MP0_DISP_TIMER0_CTRL0__START_MASK 0x1 714#define MP0_DISP_TIMER0_CTRL0__START__SHIFT 0x0 715#define MP0_DISP_TIMER0_CTRL0__CLEAR_MASK 0x100 716#define MP0_DISP_TIMER0_CTRL0__CLEAR__SHIFT 0x8 717#define MP0_DISP_TIMER0_CTRL0__DEC_MASK 0x10000 718#define MP0_DISP_TIMER0_CTRL0__DEC__SHIFT 0x10 719#define MP0_DISP_TIMER0_CTRL0__PULSE_COUNT_MODE_MASK 0x1000000 720#define MP0_DISP_TIMER0_CTRL0__PULSE_COUNT_MODE__SHIFT 0x18 721#define MP0_DISP_TIMER0_CTRL1__PWM_OUTPUT_EN_MASK 0x1 722#define MP0_DISP_TIMER0_CTRL1__PWM_OUTPUT_EN__SHIFT 0x0 723#define MP0_DISP_TIMER0_CTRL1__TIME_SLICE_MODE_EN_MASK 0x100 724#define MP0_DISP_TIMER0_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x8 725#define MP0_DISP_TIMER0_CTRL1__TIMER_SATURATION_EN_MASK 0x10000 726#define MP0_DISP_TIMER0_CTRL1__TIMER_SATURATION_EN__SHIFT 0x10 727#define MP0_DISP_TIMER0_CTRL1__RESERVED_MASK 0xff000000 728#define MP0_DISP_TIMER0_CTRL1__RESERVED__SHIFT 0x18 729#define MP0_DISP_TIMER0_CMP_AUTOINC__AUTOINC_MASK 0xf 730#define MP0_DISP_TIMER0_CMP_AUTOINC__AUTOINC__SHIFT 0x0 731#define MP0_DISP_TIMER0_CMP_AUTOINC__RESERVED_MASK 0xfffffff0 732#define MP0_DISP_TIMER0_CMP_AUTOINC__RESERVED__SHIFT 0x4 733#define MP0_DISP_TIMER0_INTEN__INTEN_MASK 0xf 734#define MP0_DISP_TIMER0_INTEN__INTEN__SHIFT 0x0 735#define MP0_DISP_TIMER0_INTEN__RESERVED_MASK 0xfffffff0 736#define MP0_DISP_TIMER0_INTEN__RESERVED__SHIFT 0x4 737#define MP0_DISP_TIMER0_OCMP_0_0__OCMP_MASK 0xffffffff 738#define MP0_DISP_TIMER0_OCMP_0_0__OCMP__SHIFT 0x0 739#define MP0_DISP_TIMER0_OCMP_0_1__OCMP_MASK 0xffffffff 740#define MP0_DISP_TIMER0_OCMP_0_1__OCMP__SHIFT 0x0 741#define MP0_DISP_TIMER0_CNT__COUNT_MASK 0xffffffff 742#define MP0_DISP_TIMER0_CNT__COUNT__SHIFT 0x0 743#define MP0_DISP_TIMER1_CTRL0__START_MASK 0x1 744#define MP0_DISP_TIMER1_CTRL0__START__SHIFT 0x0 745#define MP0_DISP_TIMER1_CTRL0__CLEAR_MASK 0x100 746#define MP0_DISP_TIMER1_CTRL0__CLEAR__SHIFT 0x8 747#define MP0_DISP_TIMER1_CTRL0__DEC_MASK 0x10000 748#define MP0_DISP_TIMER1_CTRL0__DEC__SHIFT 0x10 749#define MP0_DISP_TIMER1_CTRL0__PULSE_COUNT_MODE_MASK 0x1000000 750#define MP0_DISP_TIMER1_CTRL0__PULSE_COUNT_MODE__SHIFT 0x18 751#define MP0_DISP_TIMER1_CTRL1__PWM_OUTPUT_EN_MASK 0x1 752#define MP0_DISP_TIMER1_CTRL1__PWM_OUTPUT_EN__SHIFT 0x0 753#define MP0_DISP_TIMER1_CTRL1__TIME_SLICE_MODE_EN_MASK 0x100 754#define MP0_DISP_TIMER1_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x8 755#define MP0_DISP_TIMER1_CTRL1__TIMER_SATURATION_EN_MASK 0x10000 756#define MP0_DISP_TIMER1_CTRL1__TIMER_SATURATION_EN__SHIFT 0x10 757#define MP0_DISP_TIMER1_CTRL1__RESERVED_MASK 0xff000000 758#define MP0_DISP_TIMER1_CTRL1__RESERVED__SHIFT 0x18 759#define MP0_DISP_TIMER1_CMP_AUTOINC__AUTOINC_MASK 0xf 760#define MP0_DISP_TIMER1_CMP_AUTOINC__AUTOINC__SHIFT 0x0 761#define MP0_DISP_TIMER1_CMP_AUTOINC__RESERVED_MASK 0xfffffff0 762#define MP0_DISP_TIMER1_CMP_AUTOINC__RESERVED__SHIFT 0x4 763#define MP0_DISP_TIMER1_INTEN__INTEN_MASK 0xf 764#define MP0_DISP_TIMER1_INTEN__INTEN__SHIFT 0x0 765#define MP0_DISP_TIMER1_INTEN__RESERVED_MASK 0xfffffff0 766#define MP0_DISP_TIMER1_INTEN__RESERVED__SHIFT 0x4 767#define MP0_DISP_TIMER1_OCMP_0_0__OCMP_MASK 0xffffffff 768#define MP0_DISP_TIMER1_OCMP_0_0__OCMP__SHIFT 0x0 769#define MP0_DISP_TIMER1_OCMP_0_1__OCMP_MASK 0xffffffff 770#define MP0_DISP_TIMER1_OCMP_0_1__OCMP__SHIFT 0x0 771#define MP0_DISP_TIMER1_CNT__COUNT_MASK 0xffffffff 772#define MP0_DISP_TIMER1_CNT__COUNT__SHIFT 0x0 773#define SMU_MP1_SRBM2P_MSG_0__CONTENT_MASK 0xffffffff 774#define SMU_MP1_SRBM2P_MSG_0__CONTENT__SHIFT 0x0 775#define SMU_MP1_SRBM2P_MSG_1__CONTENT_MASK 0xffffffff 776#define SMU_MP1_SRBM2P_MSG_1__CONTENT__SHIFT 0x0 777#define SMU_MP1_SRBM2P_MSG_2__CONTENT_MASK 0xffffffff 778#define SMU_MP1_SRBM2P_MSG_2__CONTENT__SHIFT 0x0 779#define SMU_MP1_SRBM2P_MSG_3__CONTENT_MASK 0xffffffff 780#define SMU_MP1_SRBM2P_MSG_3__CONTENT__SHIFT 0x0 781#define SMU_MP1_SRBM2P_MSG_4__CONTENT_MASK 0xffffffff 782#define SMU_MP1_SRBM2P_MSG_4__CONTENT__SHIFT 0x0 783#define SMU_MP1_SRBM2P_MSG_5__CONTENT_MASK 0xffffffff 784#define SMU_MP1_SRBM2P_MSG_5__CONTENT__SHIFT 0x0 785#define SMU_MP1_SRBM2P_MSG_6__CONTENT_MASK 0xffffffff 786#define SMU_MP1_SRBM2P_MSG_6__CONTENT__SHIFT 0x0 787#define SMU_MP1_SRBM2P_MSG_7__CONTENT_MASK 0xffffffff 788#define SMU_MP1_SRBM2P_MSG_7__CONTENT__SHIFT 0x0 789#define SMU_MP1_SRBM2P_MSG_8__CONTENT_MASK 0xffffffff 790#define SMU_MP1_SRBM2P_MSG_8__CONTENT__SHIFT 0x0 791#define SMU_MP1_SRBM2P_MSG_9__CONTENT_MASK 0xffffffff 792#define SMU_MP1_SRBM2P_MSG_9__CONTENT__SHIFT 0x0 793#define SMU_MP1_SRBM2P_MSG_10__CONTENT_MASK 0xffffffff 794#define SMU_MP1_SRBM2P_MSG_10__CONTENT__SHIFT 0x0 795#define SMU_MP1_SRBM2P_MSG_11__CONTENT_MASK 0xffffffff 796#define SMU_MP1_SRBM2P_MSG_11__CONTENT__SHIFT 0x0 797#define SMU_MP1_SRBM2P_MSG_12__CONTENT_MASK 0xffffffff 798#define SMU_MP1_SRBM2P_MSG_12__CONTENT__SHIFT 0x0 799#define SMU_MP1_SRBM2P_MSG_13__CONTENT_MASK 0xffffffff 800#define SMU_MP1_SRBM2P_MSG_13__CONTENT__SHIFT 0x0 801#define SMU_MP1_SRBM2P_MSG_14__CONTENT_MASK 0xffffffff 802#define SMU_MP1_SRBM2P_MSG_14__CONTENT__SHIFT 0x0 803#define SMU_MP1_SRBM2P_MSG_15__CONTENT_MASK 0xffffffff 804#define SMU_MP1_SRBM2P_MSG_15__CONTENT__SHIFT 0x0 805#define SMU_MP1_SRBM2P_RESP_0__CONTENT_MASK 0xffffffff 806#define SMU_MP1_SRBM2P_RESP_0__CONTENT__SHIFT 0x0 807#define SMU_MP1_SRBM2P_RESP_1__CONTENT_MASK 0xffffffff 808#define SMU_MP1_SRBM2P_RESP_1__CONTENT__SHIFT 0x0 809#define SMU_MP1_SRBM2P_RESP_2__CONTENT_MASK 0xffffffff 810#define SMU_MP1_SRBM2P_RESP_2__CONTENT__SHIFT 0x0 811#define SMU_MP1_SRBM2P_RESP_3__CONTENT_MASK 0xffffffff 812#define SMU_MP1_SRBM2P_RESP_3__CONTENT__SHIFT 0x0 813#define SMU_MP1_SRBM2P_RESP_4__CONTENT_MASK 0xffffffff 814#define SMU_MP1_SRBM2P_RESP_4__CONTENT__SHIFT 0x0 815#define SMU_MP1_SRBM2P_RESP_5__CONTENT_MASK 0xffffffff 816#define SMU_MP1_SRBM2P_RESP_5__CONTENT__SHIFT 0x0 817#define SMU_MP1_SRBM2P_RESP_6__CONTENT_MASK 0xffffffff 818#define SMU_MP1_SRBM2P_RESP_6__CONTENT__SHIFT 0x0 819#define SMU_MP1_SRBM2P_RESP_7__CONTENT_MASK 0xffffffff 820#define SMU_MP1_SRBM2P_RESP_7__CONTENT__SHIFT 0x0 821#define SMU_MP1_SRBM2P_RESP_8__CONTENT_MASK 0xffffffff 822#define SMU_MP1_SRBM2P_RESP_8__CONTENT__SHIFT 0x0 823#define SMU_MP1_SRBM2P_RESP_9__CONTENT_MASK 0xffffffff 824#define SMU_MP1_SRBM2P_RESP_9__CONTENT__SHIFT 0x0 825#define SMU_MP1_SRBM2P_RESP_10__CONTENT_MASK 0xffffffff 826#define SMU_MP1_SRBM2P_RESP_10__CONTENT__SHIFT 0x0 827#define SMU_MP1_SRBM2P_RESP_11__CONTENT_MASK 0xffffffff 828#define SMU_MP1_SRBM2P_RESP_11__CONTENT__SHIFT 0x0 829#define SMU_MP1_SRBM2P_RESP_12__CONTENT_MASK 0xffffffff 830#define SMU_MP1_SRBM2P_RESP_12__CONTENT__SHIFT 0x0 831#define SMU_MP1_SRBM2P_RESP_13__CONTENT_MASK 0xffffffff 832#define SMU_MP1_SRBM2P_RESP_13__CONTENT__SHIFT 0x0 833#define SMU_MP1_SRBM2P_RESP_14__CONTENT_MASK 0xffffffff 834#define SMU_MP1_SRBM2P_RESP_14__CONTENT__SHIFT 0x0 835#define SMU_MP1_SRBM2P_RESP_15__CONTENT_MASK 0xffffffff 836#define SMU_MP1_SRBM2P_RESP_15__CONTENT__SHIFT 0x0 837#define SMU_MP1_SRBM2P_ARG_0__CONTENT_MASK 0xffffffff 838#define SMU_MP1_SRBM2P_ARG_0__CONTENT__SHIFT 0x0 839#define SMU_MP1_SRBM2P_ARG_1__CONTENT_MASK 0xffffffff 840#define SMU_MP1_SRBM2P_ARG_1__CONTENT__SHIFT 0x0 841#define SMU_MP1_SRBM2P_ARG_2__CONTENT_MASK 0xffffffff 842#define SMU_MP1_SRBM2P_ARG_2__CONTENT__SHIFT 0x0 843#define SMU_MP1_SRBM2P_ARG_3__CONTENT_MASK 0xffffffff 844#define SMU_MP1_SRBM2P_ARG_3__CONTENT__SHIFT 0x0 845#define SMU_MP1_SRBM2P_ARG_4__CONTENT_MASK 0xffffffff 846#define SMU_MP1_SRBM2P_ARG_4__CONTENT__SHIFT 0x0 847#define SMU_MP1_SRBM2P_ARG_5__CONTENT_MASK 0xffffffff 848#define SMU_MP1_SRBM2P_ARG_5__CONTENT__SHIFT 0x0 849#define SMU_MP1_SRBM2P_ARG_6__CONTENT_MASK 0xffffffff 850#define SMU_MP1_SRBM2P_ARG_6__CONTENT__SHIFT 0x0 851#define SMU_MP1_SRBM2P_ARG_7__CONTENT_MASK 0xffffffff 852#define SMU_MP1_SRBM2P_ARG_7__CONTENT__SHIFT 0x0 853#define SMU_MP1_SRBM2P_ARG_8__CONTENT_MASK 0xffffffff 854#define SMU_MP1_SRBM2P_ARG_8__CONTENT__SHIFT 0x0 855#define SMU_MP1_SRBM2P_ARG_9__CONTENT_MASK 0xffffffff 856#define SMU_MP1_SRBM2P_ARG_9__CONTENT__SHIFT 0x0 857#define SMU_MP1_SRBM2P_ARG_10__CONTENT_MASK 0xffffffff 858#define SMU_MP1_SRBM2P_ARG_10__CONTENT__SHIFT 0x0 859#define SMU_MP1_SRBM2P_ARG_11__CONTENT_MASK 0xffffffff 860#define SMU_MP1_SRBM2P_ARG_11__CONTENT__SHIFT 0x0 861#define SMU_MP1_SRBM2P_ARG_12__CONTENT_MASK 0xffffffff 862#define SMU_MP1_SRBM2P_ARG_12__CONTENT__SHIFT 0x0 863#define SMU_MP1_SRBM2P_ARG_13__CONTENT_MASK 0xffffffff 864#define SMU_MP1_SRBM2P_ARG_13__CONTENT__SHIFT 0x0 865#define SMU_MP1_SRBM2P_ARG_14__CONTENT_MASK 0xffffffff 866#define SMU_MP1_SRBM2P_ARG_14__CONTENT__SHIFT 0x0 867#define SMU_MP1_SRBM2P_ARG_15__CONTENT_MASK 0xffffffff 868#define SMU_MP1_SRBM2P_ARG_15__CONTENT__SHIFT 0x0 869#define SMU_MP1_ACP2MP_RESP__CONTENT_MASK 0xffffffff 870#define SMU_MP1_ACP2MP_RESP__CONTENT__SHIFT 0x0 871#define SMU_MP1_DC2MP_RESP__CONTENT_MASK 0xffffffff 872#define SMU_MP1_DC2MP_RESP__CONTENT__SHIFT 0x0 873#define SMU_MP1_UVD2MP_RESP__CONTENT_MASK 0xffffffff 874#define SMU_MP1_UVD2MP_RESP__CONTENT__SHIFT 0x0 875#define SMU_MP1_VCE2MP_RESP__CONTENT_MASK 0xffffffff 876#define SMU_MP1_VCE2MP_RESP__CONTENT__SHIFT 0x0 877#define SMU_MP1_RLC2MP_RESP__CONTENT_MASK 0xffffffff 878#define SMU_MP1_RLC2MP_RESP__CONTENT__SHIFT 0x0 879#define MP_FPS_CNT__FPS_CNT_MASK 0xffffffff 880#define MP_FPS_CNT__FPS_CNT__SHIFT 0x0 881#define SMU_DISP0_TIMER_INT_CONTROL__INT_STAT_MASK 0x1 882#define SMU_DISP0_TIMER_INT_CONTROL__INT_STAT__SHIFT 0x0 883#define SMU_DISP0_TIMER_INT_CONTROL__INT_UNMASK_MASK 0x2 884#define SMU_DISP0_TIMER_INT_CONTROL__INT_UNMASK__SHIFT 0x1 885#define SMU_DISP0_TIMER_INT_CONTROL__INT_TYPE_MASK 0x4 886#define SMU_DISP0_TIMER_INT_CONTROL__INT_TYPE__SHIFT 0x2 887#define SMU_DISP0_TIMER_INT_CONTROL__INT_ACK_MASK 0x8 888#define SMU_DISP0_TIMER_INT_CONTROL__INT_ACK__SHIFT 0x3 889#define SMU_DISP0_TIMER_INT_CONTROL__MASK_MASK 0x10 890#define SMU_DISP0_TIMER_INT_CONTROL__MASK__SHIFT 0x4 891#define SMU_DISP1_TIMER_INT_CONTROL__INT_STAT_MASK 0x1 892#define SMU_DISP1_TIMER_INT_CONTROL__INT_STAT__SHIFT 0x0 893#define SMU_DISP1_TIMER_INT_CONTROL__INT_UNMASK_MASK 0x2 894#define SMU_DISP1_TIMER_INT_CONTROL__INT_UNMASK__SHIFT 0x1 895#define SMU_DISP1_TIMER_INT_CONTROL__INT_TYPE_MASK 0x4 896#define SMU_DISP1_TIMER_INT_CONTROL__INT_TYPE__SHIFT 0x2 897#define SMU_DISP1_TIMER_INT_CONTROL__INT_ACK_MASK 0x8 898#define SMU_DISP1_TIMER_INT_CONTROL__INT_ACK__SHIFT 0x3 899#define SMU_DISP1_TIMER_INT_CONTROL__MASK_MASK 0x10 900#define SMU_DISP1_TIMER_INT_CONTROL__MASK__SHIFT 0x4 901#define SMU_SRBM_CONFIG__MSTR_CREDITS_MASK 0x1f 902#define SMU_SRBM_CONFIG__MSTR_CREDITS__SHIFT 0x0 903#define MP_FPS_CNT_XBAR__FPS_CNT_MASK 0xffffffff 904#define MP_FPS_CNT_XBAR__FPS_CNT__SHIFT 0x0 905#define MP_SRBM_CONFIG_XBAR__MSTR_CREDITS_MASK 0x1f 906#define MP_SRBM_CONFIG_XBAR__MSTR_CREDITS__SHIFT 0x0 907#define MP_SRBM_CONTROL__ACC_VIO_EN_MASK 0x1 908#define MP_SRBM_CONTROL__ACC_VIO_EN__SHIFT 0x0 909#define MP_SRBM_CONTROL__ALLOW_NS_ACC_MASK 0x2 910#define MP_SRBM_CONTROL__ALLOW_NS_ACC__SHIFT 0x1 911#define MP_SRBM_CONTROL__SOFT_RST_MASK_MASK 0x4 912#define MP_SRBM_CONTROL__SOFT_RST_MASK__SHIFT 0x2 913#define MP_SRBM_CONTROL__SOFT_RST_STS_MASK 0x8 914#define MP_SRBM_CONTROL__SOFT_RST_STS__SHIFT 0x3 915#define MP_SRBM_ACCVIO_LOG__ACC_VIO_OP_MASK 0x1 916#define MP_SRBM_ACCVIO_LOG__ACC_VIO_OP__SHIFT 0x0 917#define MP_SRBM_ACCVIO_LOG__ACC_VIO_SRCID_MASK 0xe 918#define MP_SRBM_ACCVIO_LOG__ACC_VIO_SRCID__SHIFT 0x1 919#define MP_SRBM_ACCVIO_LOG__ACC_VIO_VALID_MASK 0x80000000 920#define MP_SRBM_ACCVIO_LOG__ACC_VIO_VALID__SHIFT 0x1f 921#define MP_SRBM_ACCVIO_ADDR__ACC_VIO_ADDR_MASK 0xffffffff 922#define MP_SRBM_ACCVIO_ADDR__ACC_VIO_ADDR__SHIFT 0x0 923#define MP_CRBBM_CONTROL__ACC_VIO_EN_MASK 0x1 924#define MP_CRBBM_CONTROL__ACC_VIO_EN__SHIFT 0x0 925#define MP_CRBBM_CONTROL__MP0_ACCESS_MASK 0x2 926#define MP_CRBBM_CONTROL__MP0_ACCESS__SHIFT 0x1 927#define MP_CRBBM_CONTROL__ALLOW_NS_ACC_MASK 0x4 928#define MP_CRBBM_CONTROL__ALLOW_NS_ACC__SHIFT 0x2 929#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_OP_MASK 0x1 930#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_OP__SHIFT 0x0 931#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_INTF_MASK 0x2 932#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_INTF__SHIFT 0x1 933#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_VALID_MASK 0x80000000 934#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_VALID__SHIFT 0x1f 935#define MP_CRBBM_ACCVIO_ADDR__ACC_VIO_ADDR_MASK 0xffffffff 936#define MP_CRBBM_ACCVIO_ADDR__ACC_VIO_ADDR__SHIFT 0x0 937#define MP_DRAM_CNTL_WRREQ_CNTL__tag_MASK 0x1ffff 938#define MP_DRAM_CNTL_WRREQ_CNTL__tag__SHIFT 0x0 939#define MP_DRAM_CNTL_WRREQ_CNTL__urg_MASK 0x1e0000 940#define MP_DRAM_CNTL_WRREQ_CNTL__urg__SHIFT 0x11 941#define MP_DRAM_CNTL_WRREQ_CNTL__stall_MASK 0x200000 942#define MP_DRAM_CNTL_WRREQ_CNTL__stall__SHIFT 0x15 943#define MP_DRAM_CNTL_WRREQ_CNTL__priv_MASK 0x400000 944#define MP_DRAM_CNTL_WRREQ_CNTL__priv__SHIFT 0x16 945#define MP_DRAM_CNTL_WRREQ_CNTL__cid_MASK 0xff800000 946#define MP_DRAM_CNTL_WRREQ_CNTL__cid__SHIFT 0x17 947#define MP_DRAM_CNTL_WRREQ_CNTL_1__vf_MASK 0x1 948#define MP_DRAM_CNTL_WRREQ_CNTL_1__vf__SHIFT 0x0 949#define MP_DRAM_CNTL_WRREQ_CNTL_1__vfid_MASK 0xfe 950#define MP_DRAM_CNTL_WRREQ_CNTL_1__vfid__SHIFT 0x1 951#define MP_DRAM_CNTL_WRREQ_CNTL_1__physical_MASK 0x100 952#define MP_DRAM_CNTL_WRREQ_CNTL_1__physical__SHIFT 0x8 953#define MP_DRAM_CNTL_WRREQ_CNTL_1__snoop_MASK 0x200 954#define MP_DRAM_CNTL_WRREQ_CNTL_1__snoop__SHIFT 0x9 955#define MP_DRAM_CNTL_WRREQ_CNTL_1__inval_MASK 0x400 956#define MP_DRAM_CNTL_WRREQ_CNTL_1__inval__SHIFT 0xa 957#define MP_DRAM_CNTL_WRREQ_CNTL_1__op_MASK 0x3f800 958#define MP_DRAM_CNTL_WRREQ_CNTL_1__op__SHIFT 0xb 959#define MP_DRAM_CNTL_WRREQ_CNTL_1__swap_MASK 0x300000 960#define MP_DRAM_CNTL_WRREQ_CNTL_1__swap__SHIFT 0x14 961#define MP_DRAM_CNTL_WRREQ_CNTL_1__vmid_MASK 0x3c00000 962#define MP_DRAM_CNTL_WRREQ_CNTL_1__vmid__SHIFT 0x16 963#define MP_DRAM_CNTL_WRREQ_CNTL_1__atc_MASK 0x4000000 964#define MP_DRAM_CNTL_WRREQ_CNTL_1__atc__SHIFT 0x1a 965#define MP_DRAM_CNTL_WRREQ_CNTL_1__fed_MASK 0x8000000 966#define MP_DRAM_CNTL_WRREQ_CNTL_1__fed__SHIFT 0x1b 967#define MP_DRAM_CNTL_WRREQ_LOW_ADDR__addr_MASK 0xffffffff 968#define MP_DRAM_CNTL_WRREQ_LOW_ADDR__addr__SHIFT 0x0 969#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__addr_47_37_MASK 0x7ff 970#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__addr_47_37__SHIFT 0x0 971#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__reserved_MASK 0xfffff800 972#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__reserved__SHIFT 0xb 973#define MP_DRAM_CNTL_WRREQ_MASK__mask_MASK 0xffffffff 974#define MP_DRAM_CNTL_WRREQ_MASK__mask__SHIFT 0x0 975#define MP_DRAM_CNTL_WRREQ_DATA_0__data_MASK 0xffffffff 976#define MP_DRAM_CNTL_WRREQ_DATA_0__data__SHIFT 0x0 977#define MP_DRAM_CNTL_WRREQ_DATA_1__data_MASK 0xffffffff 978#define MP_DRAM_CNTL_WRREQ_DATA_1__data__SHIFT 0x0 979#define MP_DRAM_CNTL_WRREQ_DATA_2__data_MASK 0xffffffff 980#define MP_DRAM_CNTL_WRREQ_DATA_2__data__SHIFT 0x0 981#define MP_DRAM_CNTL_WRREQ_DATA_3__data_MASK 0xffffffff 982#define MP_DRAM_CNTL_WRREQ_DATA_3__data__SHIFT 0x0 983#define MP_DRAM_CNTL_WRREQ_DATA_4__data_MASK 0xffffffff 984#define MP_DRAM_CNTL_WRREQ_DATA_4__data__SHIFT 0x0 985#define MP_DRAM_CNTL_WRREQ_DATA_5__data_MASK 0xffffffff 986#define MP_DRAM_CNTL_WRREQ_DATA_5__data__SHIFT 0x0 987#define MP_DRAM_CNTL_WRREQ_DATA_6__data_MASK 0xffffffff 988#define MP_DRAM_CNTL_WRREQ_DATA_6__data__SHIFT 0x0 989#define MP_DRAM_CNTL_WRREQ_DATA_7__data_MASK 0xffffffff 990#define MP_DRAM_CNTL_WRREQ_DATA_7__data__SHIFT 0x0 991#define MP_DRAM_CNTL_WRREQ_STATUS__credit_counter_MASK 0x1f 992#define MP_DRAM_CNTL_WRREQ_STATUS__credit_counter__SHIFT 0x0 993#define MP_DRAM_CNTL_WRREQ_STATUS__reserved0_MASK 0xe0 994#define MP_DRAM_CNTL_WRREQ_STATUS__reserved0__SHIFT 0x5 995#define MP_DRAM_CNTL_WRREQ_STATUS__fifo_not_empty_MASK 0x100 996#define MP_DRAM_CNTL_WRREQ_STATUS__fifo_not_empty__SHIFT 0x8 997#define MP_DRAM_CNTL_WRREQ_STATUS__reserved1_MASK 0xfe00 998#define MP_DRAM_CNTL_WRREQ_STATUS__reserved1__SHIFT 0x9 999#define MP_DRAM_CNTL_WRREQ_STATUS__tag_pointer_MASK 0xf0000 1000#define MP_DRAM_CNTL_WRREQ_STATUS__tag_pointer__SHIFT 0x10 1001#define MP_DRAM_CNTL_WRREQ_STATUS__reserved2_MASK 0xfff00000 1002#define MP_DRAM_CNTL_WRREQ_STATUS__reserved2__SHIFT 0x14 1003#define MP_DRAM_CNTL_WRRET_STATUS_0__valid_MASK 0x1 1004#define MP_DRAM_CNTL_WRRET_STATUS_0__valid__SHIFT 0x0 1005#define MP_DRAM_CNTL_WRRET_STATUS_0__nack_MASK 0x6 1006#define MP_DRAM_CNTL_WRRET_STATUS_0__nack__SHIFT 0x1 1007#define MP_DRAM_CNTL_WRRET_STATUS_0__reserved_MASK 0xfff8 1008#define MP_DRAM_CNTL_WRRET_STATUS_0__reserved__SHIFT 0x3 1009#define MP_DRAM_CNTL_WRRET_STATUS_0__tag_MASK 0xffff0000 1010#define MP_DRAM_CNTL_WRRET_STATUS_0__tag__SHIFT 0x10 1011#define MP_DRAM_CNTL_RDREQ_ADDR__addr_MASK 0xffffffff 1012#define MP_DRAM_CNTL_RDREQ_ADDR__addr__SHIFT 0x0 1013#define MP_DRAM_CNTL_RDREQ_CNTL__tag_MASK 0xffff 1014#define MP_DRAM_CNTL_RDREQ_CNTL__tag__SHIFT 0x0 1015#define MP_DRAM_CNTL_RDREQ_CNTL__mask_MASK 0xff0000 1016#define MP_DRAM_CNTL_RDREQ_CNTL__mask__SHIFT 0x10 1017#define MP_DRAM_CNTL_RDREQ_CNTL__addr_47_40_MASK 0xff000000 1018#define MP_DRAM_CNTL_RDREQ_CNTL__addr_47_40__SHIFT 0x18 1019#define MP_DRAM_CNTL_RDREQ_CNTL_1__urg_MASK 0xf 1020#define MP_DRAM_CNTL_RDREQ_CNTL_1__urg__SHIFT 0x0 1021#define MP_DRAM_CNTL_RDREQ_CNTL_1__stall_MASK 0x10 1022#define MP_DRAM_CNTL_RDREQ_CNTL_1__stall__SHIFT 0x4 1023#define MP_DRAM_CNTL_RDREQ_CNTL_1__priv_MASK 0x20 1024#define MP_DRAM_CNTL_RDREQ_CNTL_1__priv__SHIFT 0x5 1025#define MP_DRAM_CNTL_RDREQ_CNTL_1__swap_MASK 0xc0 1026#define MP_DRAM_CNTL_RDREQ_CNTL_1__swap__SHIFT 0x6 1027#define MP_DRAM_CNTL_RDREQ_CNTL_1__cid_MASK 0x1ff00 1028#define MP_DRAM_CNTL_RDREQ_CNTL_1__cid__SHIFT 0x8 1029#define MP_DRAM_CNTL_RDREQ_CNTL_1__vmid_MASK 0x1e0000 1030#define MP_DRAM_CNTL_RDREQ_CNTL_1__vmid__SHIFT 0x11 1031#define MP_DRAM_CNTL_RDREQ_CNTL_1__atc_MASK 0x200000 1032#define MP_DRAM_CNTL_RDREQ_CNTL_1__atc__SHIFT 0x15 1033#define MP_DRAM_CNTL_RDREQ_CNTL_1__physical_MASK 0x400000 1034#define MP_DRAM_CNTL_RDREQ_CNTL_1__physical__SHIFT 0x16 1035#define MP_DRAM_CNTL_RDREQ_CNTL_1__exe_MASK 0x800000 1036#define MP_DRAM_CNTL_RDREQ_CNTL_1__exe__SHIFT 0x17 1037#define MP_DRAM_CNTL_RDREQ_CNTL_1__snoop_MASK 0x1000000 1038#define MP_DRAM_CNTL_RDREQ_CNTL_1__snoop__SHIFT 0x18 1039#define MP_DRAM_CNTL_RDREQ_CNTL_1__shared_MASK 0x2000000 1040#define MP_DRAM_CNTL_RDREQ_CNTL_1__shared__SHIFT 0x19 1041#define MP_DRAM_CNTL_RDREQ_CNTL_1__vf_MASK 0x4000000 1042#define MP_DRAM_CNTL_RDREQ_CNTL_1__vf__SHIFT 0x1a 1043#define MP_DRAM_CNTL_RDREQ_CNTL_1__vfid_MASK 0xf8000000 1044#define MP_DRAM_CNTL_RDREQ_CNTL_1__vfid__SHIFT 0x1b 1045#define MP_DRAM_CNTL_RDRET_VALID__vld_0_MASK 0x1 1046#define MP_DRAM_CNTL_RDRET_VALID__vld_0__SHIFT 0x0 1047#define MP_DRAM_CNTL_RDRET_VALID__vld_1_MASK 0x2 1048#define MP_DRAM_CNTL_RDRET_VALID__vld_1__SHIFT 0x1 1049#define MP_DRAM_CNTL_RDRET_VALID__vld_2_MASK 0x4 1050#define MP_DRAM_CNTL_RDRET_VALID__vld_2__SHIFT 0x2 1051#define MP_DRAM_CNTL_RDRET_VALID__vld_3_MASK 0x8 1052#define MP_DRAM_CNTL_RDRET_VALID__vld_3__SHIFT 0x3 1053#define MP_DRAM_CNTL_RDRET_VALID__vld_4_MASK 0x10 1054#define MP_DRAM_CNTL_RDRET_VALID__vld_4__SHIFT 0x4 1055#define MP_DRAM_CNTL_RDRET_VALID__vld_5_MASK 0x20 1056#define MP_DRAM_CNTL_RDRET_VALID__vld_5__SHIFT 0x5 1057#define MP_DRAM_CNTL_RDRET_VALID__vld_6_MASK 0x40 1058#define MP_DRAM_CNTL_RDRET_VALID__vld_6__SHIFT 0x6 1059#define MP_DRAM_CNTL_RDRET_VALID__vld_7_MASK 0x80 1060#define MP_DRAM_CNTL_RDRET_VALID__vld_7__SHIFT 0x7 1061#define MP_DRAM_CNTL_RDRET_VALID__reserved_MASK 0xffff00 1062#define MP_DRAM_CNTL_RDRET_VALID__reserved__SHIFT 0x8 1063#define MP_DRAM_CNTL_RDRET_VALID__atomic_MASK 0xff000000 1064#define MP_DRAM_CNTL_RDRET_VALID__atomic__SHIFT 0x18 1065#define MP_DRAM_CNTL_RDRET_NACK__nack_0_MASK 0x3 1066#define MP_DRAM_CNTL_RDRET_NACK__nack_0__SHIFT 0x0 1067#define MP_DRAM_CNTL_RDRET_NACK__nack_1_MASK 0xc 1068#define MP_DRAM_CNTL_RDRET_NACK__nack_1__SHIFT 0x2 1069#define MP_DRAM_CNTL_RDRET_NACK__nack_2_MASK 0x30 1070#define MP_DRAM_CNTL_RDRET_NACK__nack_2__SHIFT 0x4 1071#define MP_DRAM_CNTL_RDRET_NACK__nack_3_MASK 0xc0 1072#define MP_DRAM_CNTL_RDRET_NACK__nack_3__SHIFT 0x6 1073#define MP_DRAM_CNTL_RDRET_NACK__nack_4_MASK 0x300 1074#define MP_DRAM_CNTL_RDRET_NACK__nack_4__SHIFT 0x8 1075#define MP_DRAM_CNTL_RDRET_NACK__nack_5_MASK 0xc00 1076#define MP_DRAM_CNTL_RDRET_NACK__nack_5__SHIFT 0xa 1077#define MP_DRAM_CNTL_RDRET_NACK__nack_6_MASK 0x3000 1078#define MP_DRAM_CNTL_RDRET_NACK__nack_6__SHIFT 0xc 1079#define MP_DRAM_CNTL_RDRET_NACK__nack_7_MASK 0xc000 1080#define MP_DRAM_CNTL_RDRET_NACK__nack_7__SHIFT 0xe 1081#define MP_DRAM_CNTL_RDRET_NACK__reserved_MASK 0xffff0000 1082#define MP_DRAM_CNTL_RDRET_NACK__reserved__SHIFT 0x10 1083#define MP_DRAM_CNTL_RDRET_DATA_0__DATA_MASK 0xffffffff 1084#define MP_DRAM_CNTL_RDRET_DATA_0__DATA__SHIFT 0x0 1085#define MP_DRAM_CNTL_RDRET_DATA_1__DATA_MASK 0xffffffff 1086#define MP_DRAM_CNTL_RDRET_DATA_1__DATA__SHIFT 0x0 1087#define MP_DRAM_CNTL_RDRET_DATA_2__DATA_MASK 0xffffffff 1088#define MP_DRAM_CNTL_RDRET_DATA_2__DATA__SHIFT 0x0 1089#define MP_DRAM_CNTL_RDRET_DATA_3__DATA_MASK 0xffffffff 1090#define MP_DRAM_CNTL_RDRET_DATA_3__DATA__SHIFT 0x0 1091#define MP_DRAM_CNTL_RDRET_DATA_4__DATA_MASK 0xffffffff 1092#define MP_DRAM_CNTL_RDRET_DATA_4__DATA__SHIFT 0x0 1093#define MP_DRAM_CNTL_RDRET_DATA_5__DATA_MASK 0xffffffff 1094#define MP_DRAM_CNTL_RDRET_DATA_5__DATA__SHIFT 0x0 1095#define MP_DRAM_CNTL_RDRET_DATA_6__DATA_MASK 0xffffffff 1096#define MP_DRAM_CNTL_RDRET_DATA_6__DATA__SHIFT 0x0 1097#define MP_DRAM_CNTL_RDRET_DATA_7__DATA_MASK 0xffffffff 1098#define MP_DRAM_CNTL_RDRET_DATA_7__DATA__SHIFT 0x0 1099#define MP_DRAM_CNTL_RDRET_DATA_8__DATA_MASK 0xffffffff 1100#define MP_DRAM_CNTL_RDRET_DATA_8__DATA__SHIFT 0x0 1101#define MP_DRAM_CNTL_RDRET_DATA_9__DATA_MASK 0xffffffff 1102#define MP_DRAM_CNTL_RDRET_DATA_9__DATA__SHIFT 0x0 1103#define MP_DRAM_CNTL_RDRET_DATA_10__DATA_MASK 0xffffffff 1104#define MP_DRAM_CNTL_RDRET_DATA_10__DATA__SHIFT 0x0 1105#define MP_DRAM_CNTL_RDRET_DATA_11__DATA_MASK 0xffffffff 1106#define MP_DRAM_CNTL_RDRET_DATA_11__DATA__SHIFT 0x0 1107#define MP_DRAM_CNTL_RDRET_DATA_12__DATA_MASK 0xffffffff 1108#define MP_DRAM_CNTL_RDRET_DATA_12__DATA__SHIFT 0x0 1109#define MP_DRAM_CNTL_RDRET_DATA_13__DATA_MASK 0xffffffff 1110#define MP_DRAM_CNTL_RDRET_DATA_13__DATA__SHIFT 0x0 1111#define MP_DRAM_CNTL_RDRET_DATA_14__DATA_MASK 0xffffffff 1112#define MP_DRAM_CNTL_RDRET_DATA_14__DATA__SHIFT 0x0 1113#define MP_DRAM_CNTL_RDRET_DATA_15__DATA_MASK 0xffffffff 1114#define MP_DRAM_CNTL_RDRET_DATA_15__DATA__SHIFT 0x0 1115#define MP_DRAM_CNTL_RDRET_DATA_16__DATA_MASK 0xffffffff 1116#define MP_DRAM_CNTL_RDRET_DATA_16__DATA__SHIFT 0x0 1117#define MP_DRAM_CNTL_RDRET_DATA_17__DATA_MASK 0xffffffff 1118#define MP_DRAM_CNTL_RDRET_DATA_17__DATA__SHIFT 0x0 1119#define MP_DRAM_CNTL_RDRET_DATA_18__DATA_MASK 0xffffffff 1120#define MP_DRAM_CNTL_RDRET_DATA_18__DATA__SHIFT 0x0 1121#define MP_DRAM_CNTL_RDRET_DATA_19__DATA_MASK 0xffffffff 1122#define MP_DRAM_CNTL_RDRET_DATA_19__DATA__SHIFT 0x0 1123#define MP_DRAM_CNTL_RDRET_DATA_20__DATA_MASK 0xffffffff 1124#define MP_DRAM_CNTL_RDRET_DATA_20__DATA__SHIFT 0x0 1125#define MP_DRAM_CNTL_RDRET_DATA_21__DATA_MASK 0xffffffff 1126#define MP_DRAM_CNTL_RDRET_DATA_21__DATA__SHIFT 0x0 1127#define MP_DRAM_CNTL_RDRET_DATA_22__DATA_MASK 0xffffffff 1128#define MP_DRAM_CNTL_RDRET_DATA_22__DATA__SHIFT 0x0 1129#define MP_DRAM_CNTL_RDRET_DATA_23__DATA_MASK 0xffffffff 1130#define MP_DRAM_CNTL_RDRET_DATA_23__DATA__SHIFT 0x0 1131#define MP_DRAM_CNTL_RDRET_DATA_24__DATA_MASK 0xffffffff 1132#define MP_DRAM_CNTL_RDRET_DATA_24__DATA__SHIFT 0x0 1133#define MP_DRAM_CNTL_RDRET_DATA_25__DATA_MASK 0xffffffff 1134#define MP_DRAM_CNTL_RDRET_DATA_25__DATA__SHIFT 0x0 1135#define MP_DRAM_CNTL_RDRET_DATA_26__DATA_MASK 0xffffffff 1136#define MP_DRAM_CNTL_RDRET_DATA_26__DATA__SHIFT 0x0 1137#define MP_DRAM_CNTL_RDRET_DATA_27__DATA_MASK 0xffffffff 1138#define MP_DRAM_CNTL_RDRET_DATA_27__DATA__SHIFT 0x0 1139#define MP_DRAM_CNTL_RDRET_DATA_28__DATA_MASK 0xffffffff 1140#define MP_DRAM_CNTL_RDRET_DATA_28__DATA__SHIFT 0x0 1141#define MP_DRAM_CNTL_RDRET_DATA_29__DATA_MASK 0xffffffff 1142#define MP_DRAM_CNTL_RDRET_DATA_29__DATA__SHIFT 0x0 1143#define MP_DRAM_CNTL_RDRET_DATA_30__DATA_MASK 0xffffffff 1144#define MP_DRAM_CNTL_RDRET_DATA_30__DATA__SHIFT 0x0 1145#define MP_DRAM_CNTL_RDRET_DATA_31__DATA_MASK 0xffffffff 1146#define MP_DRAM_CNTL_RDRET_DATA_31__DATA__SHIFT 0x0 1147#define MP_DRAM_CNTL_RDRET_DATA_32__DATA_MASK 0xffffffff 1148#define MP_DRAM_CNTL_RDRET_DATA_32__DATA__SHIFT 0x0 1149#define MP_DRAM_CNTL_RDRET_DATA_33__DATA_MASK 0xffffffff 1150#define MP_DRAM_CNTL_RDRET_DATA_33__DATA__SHIFT 0x0 1151#define MP_DRAM_CNTL_RDRET_DATA_34__DATA_MASK 0xffffffff 1152#define MP_DRAM_CNTL_RDRET_DATA_34__DATA__SHIFT 0x0 1153#define MP_DRAM_CNTL_RDRET_DATA_35__DATA_MASK 0xffffffff 1154#define MP_DRAM_CNTL_RDRET_DATA_35__DATA__SHIFT 0x0 1155#define MP_DRAM_CNTL_RDRET_DATA_36__DATA_MASK 0xffffffff 1156#define MP_DRAM_CNTL_RDRET_DATA_36__DATA__SHIFT 0x0 1157#define MP_DRAM_CNTL_RDRET_DATA_37__DATA_MASK 0xffffffff 1158#define MP_DRAM_CNTL_RDRET_DATA_37__DATA__SHIFT 0x0 1159#define MP_DRAM_CNTL_RDRET_DATA_38__DATA_MASK 0xffffffff 1160#define MP_DRAM_CNTL_RDRET_DATA_38__DATA__SHIFT 0x0 1161#define MP_DRAM_CNTL_RDRET_DATA_39__DATA_MASK 0xffffffff 1162#define MP_DRAM_CNTL_RDRET_DATA_39__DATA__SHIFT 0x0 1163#define MP_DRAM_CNTL_RDRET_DATA_40__DATA_MASK 0xffffffff 1164#define MP_DRAM_CNTL_RDRET_DATA_40__DATA__SHIFT 0x0 1165#define MP_DRAM_CNTL_RDRET_DATA_41__DATA_MASK 0xffffffff 1166#define MP_DRAM_CNTL_RDRET_DATA_41__DATA__SHIFT 0x0 1167#define MP_DRAM_CNTL_RDRET_DATA_42__DATA_MASK 0xffffffff 1168#define MP_DRAM_CNTL_RDRET_DATA_42__DATA__SHIFT 0x0 1169#define MP_DRAM_CNTL_RDRET_DATA_43__DATA_MASK 0xffffffff 1170#define MP_DRAM_CNTL_RDRET_DATA_43__DATA__SHIFT 0x0 1171#define MP_DRAM_CNTL_RDRET_DATA_44__DATA_MASK 0xffffffff 1172#define MP_DRAM_CNTL_RDRET_DATA_44__DATA__SHIFT 0x0 1173#define MP_DRAM_CNTL_RDRET_DATA_45__DATA_MASK 0xffffffff 1174#define MP_DRAM_CNTL_RDRET_DATA_45__DATA__SHIFT 0x0 1175#define MP_DRAM_CNTL_RDRET_DATA_46__DATA_MASK 0xffffffff 1176#define MP_DRAM_CNTL_RDRET_DATA_46__DATA__SHIFT 0x0 1177#define MP_DRAM_CNTL_RDRET_DATA_47__DATA_MASK 0xffffffff 1178#define MP_DRAM_CNTL_RDRET_DATA_47__DATA__SHIFT 0x0 1179#define MP_DRAM_CNTL_RDRET_DATA_48__DATA_MASK 0xffffffff 1180#define MP_DRAM_CNTL_RDRET_DATA_48__DATA__SHIFT 0x0 1181#define MP_DRAM_CNTL_RDRET_DATA_49__DATA_MASK 0xffffffff 1182#define MP_DRAM_CNTL_RDRET_DATA_49__DATA__SHIFT 0x0 1183#define MP_DRAM_CNTL_RDRET_DATA_50__DATA_MASK 0xffffffff 1184#define MP_DRAM_CNTL_RDRET_DATA_50__DATA__SHIFT 0x0 1185#define MP_DRAM_CNTL_RDRET_DATA_51__DATA_MASK 0xffffffff 1186#define MP_DRAM_CNTL_RDRET_DATA_51__DATA__SHIFT 0x0 1187#define MP_DRAM_CNTL_RDRET_DATA_52__DATA_MASK 0xffffffff 1188#define MP_DRAM_CNTL_RDRET_DATA_52__DATA__SHIFT 0x0 1189#define MP_DRAM_CNTL_RDRET_DATA_53__DATA_MASK 0xffffffff 1190#define MP_DRAM_CNTL_RDRET_DATA_53__DATA__SHIFT 0x0 1191#define MP_DRAM_CNTL_RDRET_DATA_54__DATA_MASK 0xffffffff 1192#define MP_DRAM_CNTL_RDRET_DATA_54__DATA__SHIFT 0x0 1193#define MP_DRAM_CNTL_RDRET_DATA_55__DATA_MASK 0xffffffff 1194#define MP_DRAM_CNTL_RDRET_DATA_55__DATA__SHIFT 0x0 1195#define MP_DRAM_CNTL_RDRET_DATA_56__DATA_MASK 0xffffffff 1196#define MP_DRAM_CNTL_RDRET_DATA_56__DATA__SHIFT 0x0 1197#define MP_DRAM_CNTL_RDRET_DATA_57__DATA_MASK 0xffffffff 1198#define MP_DRAM_CNTL_RDRET_DATA_57__DATA__SHIFT 0x0 1199#define MP_DRAM_CNTL_RDRET_DATA_58__DATA_MASK 0xffffffff 1200#define MP_DRAM_CNTL_RDRET_DATA_58__DATA__SHIFT 0x0 1201#define MP_DRAM_CNTL_RDRET_DATA_59__DATA_MASK 0xffffffff 1202#define MP_DRAM_CNTL_RDRET_DATA_59__DATA__SHIFT 0x0 1203#define MP_DRAM_CNTL_RDRET_DATA_60__DATA_MASK 0xffffffff 1204#define MP_DRAM_CNTL_RDRET_DATA_60__DATA__SHIFT 0x0 1205#define MP_DRAM_CNTL_RDRET_DATA_61__DATA_MASK 0xffffffff 1206#define MP_DRAM_CNTL_RDRET_DATA_61__DATA__SHIFT 0x0 1207#define MP_DRAM_CNTL_RDRET_DATA_62__DATA_MASK 0xffffffff 1208#define MP_DRAM_CNTL_RDRET_DATA_62__DATA__SHIFT 0x0 1209#define MP_DRAM_CNTL_RDRET_DATA_63__DATA_MASK 0xffffffff 1210#define MP_DRAM_CNTL_RDRET_DATA_63__DATA__SHIFT 0x0 1211#define MP_IOC_CTRL__IOC_mst_send_MASK 0x1 1212#define MP_IOC_CTRL__IOC_mst_send__SHIFT 0x0 1213#define MP_IOC_CTRL__IOC_mst_stop_MASK 0x2 1214#define MP_IOC_CTRL__IOC_mst_stop__SHIFT 0x1 1215#define MP_IOC_CTRL__IOC_mst_force_active_MASK 0x4 1216#define MP_IOC_CTRL__IOC_mst_force_active__SHIFT 0x2 1217#define MP_IOC_CTRL__IOC_mst_rdValid_MASK 0x8 1218#define MP_IOC_CTRL__IOC_mst_rdValid__SHIFT 0x3 1219#define MP_IOC_CTRL__IOC_mst_busy_MASK 0x10 1220#define MP_IOC_CTRL__IOC_mst_busy__SHIFT 0x4 1221#define MP_IOC_CTRL__IOC_mst_disabled_MASK 0x20 1222#define MP_IOC_CTRL__IOC_mst_disabled__SHIFT 0x5 1223#define MP_IOC_CTRL__IOC_mst_debug_rst_MASK 0x40 1224#define MP_IOC_CTRL__IOC_mst_debug_rst__SHIFT 0x6 1225#define MP_IOC_CTRL__IOC_mst_stop_ack_MASK 0x80 1226#define MP_IOC_CTRL__IOC_mst_stop_ack__SHIFT 0x7 1227#define MP_IOC_CTRL__IOC_mst_rderr_MASK 0x300 1228#define MP_IOC_CTRL__IOC_mst_rderr__SHIFT 0x8 1229#define MP_IOC_RDDATA__IOC_mst_rdData_MASK 0xffffffff 1230#define MP_IOC_RDDATA__IOC_mst_rdData__SHIFT 0x0 1231#define MP_IOC_PHASE1__BiuCqfC_AwqReqCommit_MASK 0x2 1232#define MP_IOC_PHASE1__BiuCqfC_AwqReqCommit__SHIFT 0x1 1233#define MP_IOC_PHASE1__BiuCqfC_AltReqRdCmd_MASK 0x4 1234#define MP_IOC_PHASE1__BiuCqfC_AltReqRdCmd__SHIFT 0x2 1235#define MP_IOC_PHASE1__BiuCqfC_AltReqAddrLo_MASK 0xfffffff8 1236#define MP_IOC_PHASE1__BiuCqfC_AltReqAddrLo__SHIFT 0x3 1237#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrMid_MASK 0xff 1238#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrMid__SHIFT 0x0 1239#define MP_IOC_PHASE2__BiuCqfC_AltReqMask_MASK 0xff00 1240#define MP_IOC_PHASE2__BiuCqfC_AltReqMask__SHIFT 0x8 1241#define MP_IOC_PHASE2__BiuCqfC_AltReqSize_MASK 0x30000 1242#define MP_IOC_PHASE2__BiuCqfC_AltReqSize__SHIFT 0x10 1243#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrHi_MASK 0xff000000 1244#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrHi__SHIFT 0x18 1245#define MP_IOC_PHASE3__BiuDbfC_C2aDataOut_MASK 0xffffffff 1246#define MP_IOC_PHASE3__BiuDbfC_C2aDataOut__SHIFT 0x0 1247#define MP_IOC_READ_0__data_MASK 0xffffffff 1248#define MP_IOC_READ_0__data__SHIFT 0x0 1249#define MP_IOC_READ_1__data_MASK 0xffffffff 1250#define MP_IOC_READ_1__data__SHIFT 0x0 1251#define MP_IOC_READ_2__data_MASK 0xffffffff 1252#define MP_IOC_READ_2__data__SHIFT 0x0 1253#define MP_IOC_READ_3__data_MASK 0xffffffff 1254#define MP_IOC_READ_3__data__SHIFT 0x0 1255#define MP_IOC_READ_4__data_MASK 0xffffffff 1256#define MP_IOC_READ_4__data__SHIFT 0x0 1257#define MP_IOC_READ_5__data_MASK 0xffffffff 1258#define MP_IOC_READ_5__data__SHIFT 0x0 1259#define MP_IOC_READ_6__data_MASK 0xffffffff 1260#define MP_IOC_READ_6__data__SHIFT 0x0 1261#define MP_IOC_READ_7__data_MASK 0xffffffff 1262#define MP_IOC_READ_7__data__SHIFT 0x0 1263#define MP_IOC_READ_8__data_MASK 0xffffffff 1264#define MP_IOC_READ_8__data__SHIFT 0x0 1265#define MP_IOC_READ_9__data_MASK 0xffffffff 1266#define MP_IOC_READ_9__data__SHIFT 0x0 1267#define MP_IOC_READ_10__data_MASK 0xffffffff 1268#define MP_IOC_READ_10__data__SHIFT 0x0 1269#define MP_IOC_READ_11__data_MASK 0xffffffff 1270#define MP_IOC_READ_11__data__SHIFT 0x0 1271#define MP_IOC_READ_12__data_MASK 0xffffffff 1272#define MP_IOC_READ_12__data__SHIFT 0x0 1273#define MP_IOC_READ_13__data_MASK 0xffffffff 1274#define MP_IOC_READ_13__data__SHIFT 0x0 1275#define MP_IOC_READ_14__data_MASK 0xffffffff 1276#define MP_IOC_READ_14__data__SHIFT 0x0 1277#define MP_IOC_READ_15__data_MASK 0xffffffff 1278#define MP_IOC_READ_15__data__SHIFT 0x0 1279#define MP_IOC_WRITE_0__data_MASK 0xffffffff 1280#define MP_IOC_WRITE_0__data__SHIFT 0x0 1281#define MP_IOC_WRITE_1__data_MASK 0xffffffff 1282#define MP_IOC_WRITE_1__data__SHIFT 0x0 1283#define MP_IOC_WRITE_2__data_MASK 0xffffffff 1284#define MP_IOC_WRITE_2__data__SHIFT 0x0 1285#define MP_IOC_WRITE_3__data_MASK 0xffffffff 1286#define MP_IOC_WRITE_3__data__SHIFT 0x0 1287#define MP_IOC_WRITE_4__data_MASK 0xffffffff 1288#define MP_IOC_WRITE_4__data__SHIFT 0x0 1289#define MP_IOC_WRITE_5__data_MASK 0xffffffff 1290#define MP_IOC_WRITE_5__data__SHIFT 0x0 1291#define MP_IOC_WRITE_6__data_MASK 0xffffffff 1292#define MP_IOC_WRITE_6__data__SHIFT 0x0 1293#define MP_IOC_WRITE_7__data_MASK 0xffffffff 1294#define MP_IOC_WRITE_7__data__SHIFT 0x0 1295#define MP_IOC_WRITE_8__data_MASK 0xffffffff 1296#define MP_IOC_WRITE_8__data__SHIFT 0x0 1297#define MP_IOC_WRITE_9__data_MASK 0xffffffff 1298#define MP_IOC_WRITE_9__data__SHIFT 0x0 1299#define MP_IOC_WRITE_10__data_MASK 0xffffffff 1300#define MP_IOC_WRITE_10__data__SHIFT 0x0 1301#define MP_IOC_WRITE_11__data_MASK 0xffffffff 1302#define MP_IOC_WRITE_11__data__SHIFT 0x0 1303#define MP_IOC_WRITE_12__data_MASK 0xffffffff 1304#define MP_IOC_WRITE_12__data__SHIFT 0x0 1305#define MP_IOC_WRITE_13__data_MASK 0xffffffff 1306#define MP_IOC_WRITE_13__data__SHIFT 0x0 1307#define MP_IOC_WRITE_14__data_MASK 0xffffffff 1308#define MP_IOC_WRITE_14__data__SHIFT 0x0 1309#define MP_IOC_WRITE_15__data_MASK 0xffffffff 1310#define MP_IOC_WRITE_15__data__SHIFT 0x0 1311#define MP_INTERRUPT_CONTROL__MAX_CREDIT_VALUE_MASK 0x1f 1312#define MP_INTERRUPT_CONTROL__MAX_CREDIT_VALUE__SHIFT 0x0 1313#define MP_INTERRUPT_CONTROL__MP0_SW_TRIG_MASK_MASK 0x20 1314#define MP_INTERRUPT_CONTROL__MP0_SW_TRIG_MASK__SHIFT 0x5 1315#define MP_INTERRUPT_CONTROL__MP0_SW_INT_ACK_MASK 0x40 1316#define MP_INTERRUPT_CONTROL__MP0_SW_INT_ACK__SHIFT 0x6 1317#define MP_INTERRUPT_CONTROL__MP1_SW_TRIG_MASK_MASK 0x80 1318#define MP_INTERRUPT_CONTROL__MP1_SW_TRIG_MASK__SHIFT 0x7 1319#define MP_INTERRUPT_CONTROL__MP1_SW_INT_ACK_MASK 0x100 1320#define MP_INTERRUPT_CONTROL__MP1_SW_INT_ACK__SHIFT 0x8 1321#define MP0_SW_INT__VALID_MASK 0x1 1322#define MP0_SW_INT__VALID__SHIFT 0x0 1323#define MP0_SW_INT__INT_ID_MASK 0x1fe 1324#define MP0_SW_INT__INT_ID__SHIFT 0x1 1325#define MP0_SW_INT_CTXID__CTXID_MASK 0xfffffff 1326#define MP0_SW_INT_CTXID__CTXID__SHIFT 0x0 1327#define MP1_SW_INT__VALID_MASK 0x1 1328#define MP1_SW_INT__VALID__SHIFT 0x0 1329#define MP1_SW_INT__INT_ID_MASK 0x1fe 1330#define MP1_SW_INT__INT_ID__SHIFT 0x1 1331#define MP1_SW_INT_CTXID__CTXID_MASK 0xfffffff 1332#define MP1_SW_INT_CTXID__CTXID__SHIFT 0x0 1333#define DISP_TIMER_ID__DISP_T0_INT_ID_MASK 0xff 1334#define DISP_TIMER_ID__DISP_T0_INT_ID__SHIFT 0x0 1335#define DISP_TIMER_ID__DISP_T1_INT_ID_MASK 0xff00 1336#define DISP_TIMER_ID__DISP_T1_INT_ID__SHIFT 0x8 1337#define PWRHW_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 1338#define PWRHW_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 1339#define PWRHW_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 1340#define PWRHW_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 1341#define CURRENT_STATE_CPU0__CURRENT_PSTATE_ID_MASK 0x7 1342#define CURRENT_STATE_CPU0__CURRENT_PSTATE_ID__SHIFT 0x0 1343#define CURRENT_STATE_CPU0__CURRENT_DID_MASK 0x38 1344#define CURRENT_STATE_CPU0__CURRENT_DID__SHIFT 0x3 1345#define CURRENT_STATE_CPU0__CURRENT_FID_MASK 0xfc0 1346#define CURRENT_STATE_CPU0__CURRENT_FID__SHIFT 0x6 1347#define CURRENT_STATE_CPU0__CPU_COF_MASK 0xfff000 1348#define CURRENT_STATE_CPU0__CPU_COF__SHIFT 0xc 1349#define CURRENT_STATE_CPU0__CPU_COF_IND_PROG_MASK 0x7f000000 1350#define CURRENT_STATE_CPU0__CPU_COF_IND_PROG__SHIFT 0x18 1351#define CURRENT_STATE_CPU1__CURRENT_PSTATE_ID_MASK 0x7 1352#define CURRENT_STATE_CPU1__CURRENT_PSTATE_ID__SHIFT 0x0 1353#define CURRENT_STATE_CPU1__CURRENT_DID_MASK 0x38 1354#define CURRENT_STATE_CPU1__CURRENT_DID__SHIFT 0x3 1355#define CURRENT_STATE_CPU1__CURRENT_FID_MASK 0xfc0 1356#define CURRENT_STATE_CPU1__CURRENT_FID__SHIFT 0x6 1357#define CURRENT_STATE_CPU1__CPU_COF_MASK 0xfff000 1358#define CURRENT_STATE_CPU1__CPU_COF__SHIFT 0xc 1359#define CURRENT_STATE_CPU1__CPU_COF_IND_PROG_MASK 0x7f000000 1360#define CURRENT_STATE_CPU1__CPU_COF_IND_PROG__SHIFT 0x18 1361#define CPU_REDUN_DONE0__CPU_REDUN_DONE_MASK 0x1 1362#define CPU_REDUN_DONE0__CPU_REDUN_DONE__SHIFT 0x0 1363#define CPU_REDUN_DONE1__CPU_REDUN_DONE_MASK 0x1 1364#define CPU_REDUN_DONE1__CPU_REDUN_DONE__SHIFT 0x0 1365#define CURRENT_VID_CPU0__CURRENT_VID_MASK 0xff 1366#define CURRENT_VID_CPU0__CURRENT_VID__SHIFT 0x0 1367#define CURRENT_VID_CPU1__CURRENT_VID_MASK 0xff 1368#define CURRENT_VID_CPU1__CURRENT_VID__SHIFT 0x0 1369#define UNBPM_PWRMGT_ACK__REQUESTOR_CODE_MASK 0x1f 1370#define UNBPM_PWRMGT_ACK__REQUESTOR_CODE__SHIFT 0x0 1371#define UNBPM_PWRMGT_ACK__REQUEST_ACK_MASK 0x100 1372#define UNBPM_PWRMGT_ACK__REQUEST_ACK__SHIFT 0x8 1373#define UNBPM_PWRMGT_ACK__REQUEST_NACK_MASK 0x10000 1374#define UNBPM_PWRMGT_ACK__REQUEST_NACK__SHIFT 0x10 1375#define UNBPM_PWRMGT_ACK__ERROR_CODE_MASK 0xff000000 1376#define UNBPM_PWRMGT_ACK__ERROR_CODE__SHIFT 0x18 1377#define CURRENT_FREQ_STATE_NB__CURRENT_FID_MASK 0xff 1378#define CURRENT_FREQ_STATE_NB__CURRENT_FID__SHIFT 0x0 1379#define CURRENT_FREQ_STATE_NB__CURRENT_DID_MASK 0xff00 1380#define CURRENT_FREQ_STATE_NB__CURRENT_DID__SHIFT 0x8 1381#define CURRENT_FREQ_STATE_NB__NB_LOW_POWER_MASK 0xff0000 1382#define CURRENT_FREQ_STATE_NB__NB_LOW_POWER__SHIFT 0x10 1383#define CURRENT_FREQ_STATE_NB__NB_STUTTER_MODE_MASK 0xff000000 1384#define CURRENT_FREQ_STATE_NB__NB_STUTTER_MODE__SHIFT 0x18 1385#define CURRENT_PSTATE_NB__CURRENT_PSTATE_ID_MASK 0xff 1386#define CURRENT_PSTATE_NB__CURRENT_PSTATE_ID__SHIFT 0x0 1387#define CURRENT_PSTATE_NB__CURRENT_PSTATE_LO_MASK 0x100 1388#define CURRENT_PSTATE_NB__CURRENT_PSTATE_LO__SHIFT 0x8 1389#define CURRENT_PSTATE_NB__CURRENT_MEM_PSTATE_ID_MASK 0x200 1390#define CURRENT_PSTATE_NB__CURRENT_MEM_PSTATE_ID__SHIFT 0x9 1391#define UNBPM_MSG_INT_CONFIG__MSG_REG_TARGET_ADDR_MASK 0xffffffff 1392#define UNBPM_MSG_INT_CONFIG__MSG_REG_TARGET_ADDR__SHIFT 0x0 1393#define UNBPM_NBPWRMGT_CMD__TARGET_BLOCK_MASK 0x3 1394#define UNBPM_NBPWRMGT_CMD__TARGET_BLOCK__SHIFT 0x0 1395#define UNBPM_NBPWRMGT_CMD__TARGET_CMD_MASK 0x100 1396#define UNBPM_NBPWRMGT_CMD__TARGET_CMD__SHIFT 0x8 1397#define UNBPM_NBPWRMGT_CMD__DCT_SR_MAP_MASK 0xff0000 1398#define UNBPM_NBPWRMGT_CMD__DCT_SR_MAP__SHIFT 0x10 1399#define UNBPM_NBPWRMGT_CMD__RETURN_NB_ACK_MASK 0x1000000 1400#define UNBPM_NBPWRMGT_CMD__RETURN_NB_ACK__SHIFT 0x18 1401#define UNBPM_NBPWRMGT_CMD__OVERRIDE_PARAMS_MASK 0x2000000 1402#define UNBPM_NBPWRMGT_CMD__OVERRIDE_PARAMS__SHIFT 0x19 1403#define UNBPM_NBPWRMGT_CMD__SET_NB_LOW_POWER_MASK 0x4000000 1404#define UNBPM_NBPWRMGT_CMD__SET_NB_LOW_POWER__SHIFT 0x1a 1405#define UNBPM_NBPWRMGT_CMD__SET_NB_STUTTER_MODE_MASK 0x8000000 1406#define UNBPM_NBPWRMGT_CMD__SET_NB_STUTTER_MODE__SHIFT 0x1b 1407#define UNBPM_NBPWRMGT_FSM_CFG__DIS_AUTO_PWRGATE_ON_EXIT_MASK 0x2 1408#define UNBPM_NBPWRMGT_FSM_CFG__DIS_AUTO_PWRGATE_ON_EXIT__SHIFT 0x1 1409#define DDR0_FUSE_SSB_XFER__START_STATUS_XFER_MASK 0x1 1410#define DDR0_FUSE_SSB_XFER__START_STATUS_XFER__SHIFT 0x0 1411#define DDR0_FUSE_SSB_XFER_CFG__FUSE_DDR0_LAST_ADDR_MASK 0x7ff 1412#define DDR0_FUSE_SSB_XFER_CFG__FUSE_DDR0_LAST_ADDR__SHIFT 0x0 1413#define DDR1_FUSE_SSB_XFER__START_STATUS_XFER_MASK 0x1 1414#define DDR1_FUSE_SSB_XFER__START_STATUS_XFER__SHIFT 0x0 1415#define DDR1_FUSE_SSB_XFER_CFG__FUSE_DDR1_LAST_ADDR_MASK 0x7ff 1416#define DDR1_FUSE_SSB_XFER_CFG__FUSE_DDR1_LAST_ADDR__SHIFT 0x0 1417#define UNBPM_FUSES_VAL_PWROK__CK_FUSES_VAL_PWROK_MASK 0x1 1418#define UNBPM_FUSES_VAL_PWROK__CK_FUSES_VAL_PWROK__SHIFT 0x0 1419#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER0_MASK 0x1 1420#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER0__SHIFT 0x0 1421#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER1_MASK 0x2 1422#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER1__SHIFT 0x1 1423#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER0_MASK 0x4 1424#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER0__SHIFT 0x2 1425#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER1_MASK 0x8 1426#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER1__SHIFT 0x3 1427#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN0_MASK 0x10 1428#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN0__SHIFT 0x4 1429#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN1_MASK 0x20 1430#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN1__SHIFT 0x5 1431#define MISC_SMU_PWRMGT_CFG0__TARGET_ADDR_MASK 0xffffffff 1432#define MISC_SMU_PWRMGT_CFG0__TARGET_ADDR__SHIFT 0x0 1433#define MISC_GNB_PWRMGT_CFG1__TIMER_EN_MASK 0x1 1434#define MISC_GNB_PWRMGT_CFG1__TIMER_EN__SHIFT 0x0 1435#define MISC_GNB_PWRMGT_CFG1__TIMER_INTERVAL_MASK 0x1fffe 1436#define MISC_GNB_PWRMGT_CFG1__TIMER_INTERVAL__SHIFT 0x1 1437#define MISC_GNB_PWRMGT_CFG1__INT_GEN_EN_MASK 0x20000 1438#define MISC_GNB_PWRMGT_CFG1__INT_GEN_EN__SHIFT 0x11 1439#define MISC_SMU_PWRMGT_CFG1__TIMER_EN_MASK 0x1 1440#define MISC_SMU_PWRMGT_CFG1__TIMER_EN__SHIFT 0x0 1441#define MISC_SMU_PWRMGT_CFG1__TIMER_INTERVAL_MASK 0x1fffe 1442#define MISC_SMU_PWRMGT_CFG1__TIMER_INTERVAL__SHIFT 0x1 1443#define MISC_SMU_PWRMGT_CFG1__INT_GEN_EN_MASK 0x20000 1444#define MISC_SMU_PWRMGT_CFG1__INT_GEN_EN__SHIFT 0x11 1445#define MISC_GNB_PWRMGT_DATA__GN_ON_INB_WAKE_MASK 0x1 1446#define MISC_GNB_PWRMGT_DATA__GN_ON_INB_WAKE__SHIFT 0x0 1447#define MISC_GNB_PWRMGT_DATA__GN_ALLOW_NB_PSTATES_MASK 0x2 1448#define MISC_GNB_PWRMGT_DATA__GN_ALLOW_NB_PSTATES__SHIFT 0x1 1449#define MISC_GNB_PWRMGT_DATA__GN_FLUSH_REQ_TOGGLE_MASK 0x4 1450#define MISC_GNB_PWRMGT_DATA__GN_FLUSH_REQ_TOGGLE__SHIFT 0x2 1451#define MISC_GNB_PWRMGT_DATA__GN_CROSS_TRIGGER_MASK 0x78 1452#define MISC_GNB_PWRMGT_DATA__GN_CROSS_TRIGGER__SHIFT 0x3 1453#define MISC_GNB_PWRMGT_DATA__GN_STOP_CLOCKS_MASK 0x80 1454#define MISC_GNB_PWRMGT_DATA__GN_STOP_CLOCKS__SHIFT 0x7 1455#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH0LINK_WAKE_MASK 0x100 1456#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH0LINK_WAKE__SHIFT 0x8 1457#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH1LINK_WAKE_MASK 0x200 1458#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH1LINK_WAKE__SHIFT 0x9 1459#define GN_GNB_SLOW__GN_GNB_SLOW_DATA_MASK 0x1 1460#define GN_GNB_SLOW__GN_GNB_SLOW_DATA__SHIFT 0x0 1461#define GN_FORCE_NBPS1__GN_FORCE_NBPS1_DATA_MASK 0x1 1462#define GN_FORCE_NBPS1__GN_FORCE_NBPS1_DATA__SHIFT 0x0 1463#define MISC_SMU_PWRMGT_DATA__NB_NBPS_MASK 0x1 1464#define MISC_SMU_PWRMGT_DATA__NB_NBPS__SHIFT 0x0 1465#define MISC_SMU_PWRMGT_DATA__NB_MEMPS_MASK 0x2 1466#define MISC_SMU_PWRMGT_DATA__NB_MEMPS__SHIFT 0x1 1467#define NB_COF__NB_COF_MASK 0xffff 1468#define NB_COF__NB_COF__SHIFT 0x0 1469#define UNBPM_CK_IRESET__CK_IRESET_LOCAL_MASK 0x1 1470#define UNBPM_CK_IRESET__CK_IRESET_LOCAL__SHIFT 0x0 1471#define CURRENT_VID_NB__CURRENT_VID_MASK 0xff 1472#define CURRENT_VID_NB__CURRENT_VID__SHIFT 0x0 1473#define SPR_FUSE_PSTATEPWR1__PwrValue0_MASK 0xff 1474#define SPR_FUSE_PSTATEPWR1__PwrValue0__SHIFT 0x0 1475#define SPR_FUSE_PSTATEPWR1__PwrValue1_MASK 0xff00 1476#define SPR_FUSE_PSTATEPWR1__PwrValue1__SHIFT 0x8 1477#define SPR_FUSE_PSTATEPWR1__PwrValue2_MASK 0xff0000 1478#define SPR_FUSE_PSTATEPWR1__PwrValue2__SHIFT 0x10 1479#define SPR_FUSE_PSTATEPWR1__PwrValue3_MASK 0xff000000 1480#define SPR_FUSE_PSTATEPWR1__PwrValue3__SHIFT 0x18 1481#define SPR_FUSE_PSTATEPWR2__PwrValue4_MASK 0xff 1482#define SPR_FUSE_PSTATEPWR2__PwrValue4__SHIFT 0x0 1483#define SPR_FUSE_PSTATEPWR2__PwrDiv0_MASK 0x300 1484#define SPR_FUSE_PSTATEPWR2__PwrDiv0__SHIFT 0x8 1485#define SPR_FUSE_PSTATEPWR2__PwrDiv1_MASK 0xc00 1486#define SPR_FUSE_PSTATEPWR2__PwrDiv1__SHIFT 0xa 1487#define SPR_FUSE_PSTATEPWR2__PwrDiv2_MASK 0x3000 1488#define SPR_FUSE_PSTATEPWR2__PwrDiv2__SHIFT 0xc 1489#define SPR_FUSE_PSTATEPWR2__PwrDiv3_MASK 0xc000 1490#define SPR_FUSE_PSTATEPWR2__PwrDiv3__SHIFT 0xe 1491#define SPR_FUSE_PSTATEPWR2__PwrDiv4_MASK 0x30000 1492#define SPR_FUSE_PSTATEPWR2__PwrDiv4__SHIFT 0x10 1493#define SPR_FUSE_PSTATEPWR2__PwrDiv5_MASK 0xc0000 1494#define SPR_FUSE_PSTATEPWR2__PwrDiv5__SHIFT 0x12 1495#define SPR_FUSE_PSTATEPWR2__PwrDiv6_MASK 0x300000 1496#define SPR_FUSE_PSTATEPWR2__PwrDiv6__SHIFT 0x14 1497#define SPR_FUSE_PSTATEPWR2__PwrDiv7_MASK 0xc00000 1498#define SPR_FUSE_PSTATEPWR2__PwrDiv7__SHIFT 0x16 1499#define SPR_FUSE_PSTATEPWR2__Reserved_MASK 0xff000000 1500#define SPR_FUSE_PSTATEPWR2__Reserved__SHIFT 0x18 1501#define SPR_FUSE_PSTATEPWR3__PwrValue5_MASK 0xff 1502#define SPR_FUSE_PSTATEPWR3__PwrValue5__SHIFT 0x0 1503#define SPR_FUSE_PSTATEPWR3__PwrValue6_MASK 0xff00 1504#define SPR_FUSE_PSTATEPWR3__PwrValue6__SHIFT 0x8 1505#define SPR_FUSE_PSTATEPWR3__PwrValue7_MASK 0xff0000 1506#define SPR_FUSE_PSTATEPWR3__PwrValue7__SHIFT 0x10 1507#define SPR_FUSE_PSTATEPWR3__Reserved_MASK 0xff000000 1508#define SPR_FUSE_PSTATEPWR3__Reserved__SHIFT 0x18 1509#define SPR_FUSE_THERMAL_SCRATCH__ThermalScratch_MASK 0xffffffff 1510#define SPR_FUSE_THERMAL_SCRATCH__ThermalScratch__SHIFT 0x0 1511#define SPR_PRODUCT_INFO0__BrandId_MASK 0xffff 1512#define SPR_PRODUCT_INFO0__BrandId__SHIFT 0x0 1513#define SPR_PRODUCT_INFO0__Reserved0_MASK 0x70000 1514#define SPR_PRODUCT_INFO0__Reserved0__SHIFT 0x10 1515#define SPR_PRODUCT_INFO0__SerialNumRdDis_MASK 0x80000 1516#define SPR_PRODUCT_INFO0__SerialNumRdDis__SHIFT 0x13 1517#define SPR_PRODUCT_INFO0__Reserved1_MASK 0xfff00000 1518#define SPR_PRODUCT_INFO0__Reserved1__SHIFT 0x14 1519#define SPR_SERIALNUM_REG1__SPR_SERIALNUM_REG1_MASK 0xffffffff 1520#define SPR_SERIALNUM_REG1__SPR_SERIALNUM_REG1__SHIFT 0x0 1521#define SPR_SERIALNUM_REG2__SPR_SERIALNUM_REG2_MASK 0xffffffff 1522#define SPR_SERIALNUM_REG2__SPR_SERIALNUM_REG2__SHIFT 0x0 1523#define SPR_PRODUCT_INFO1__DiDtMode_MASK 0x1 1524#define SPR_PRODUCT_INFO1__DiDtMode__SHIFT 0x0 1525#define SPR_PRODUCT_INFO1__DiDtCfg0_MASK 0x3e 1526#define SPR_PRODUCT_INFO1__DiDtCfg0__SHIFT 0x1 1527#define SPR_PRODUCT_INFO1__DiDtCfg1_MASK 0x3fc0 1528#define SPR_PRODUCT_INFO1__DiDtCfg1__SHIFT 0x6 1529#define SPR_PRODUCT_INFO1__DiDtCfg2_MASK 0xc000 1530#define SPR_PRODUCT_INFO1__DiDtCfg2__SHIFT 0xe 1531#define SPR_PRODUCT_INFO1__DiDtCfg3_MASK 0x10000 1532#define SPR_PRODUCT_INFO1__DiDtCfg3__SHIFT 0x10 1533#define SPR_PRODUCT_INFO1__DiDtCfg4_MASK 0x1e0000 1534#define SPR_PRODUCT_INFO1__DiDtCfg4__SHIFT 0x11 1535#define SPR_PRODUCT_INFO1__Reserved_MASK 0xffe00000 1536#define SPR_PRODUCT_INFO1__Reserved__SHIFT 0x15 1537#define SPR_EXT_PRODUCT_INFO__Reserved_MASK 0xffffffff 1538#define SPR_EXT_PRODUCT_INFO__Reserved__SHIFT 0x0 1539#define SPR_MSIDFUSE__MSID_MASK 0xffffff 1540#define SPR_MSIDFUSE__MSID__SHIFT 0x0 1541#define SPR_MSIDFUSE__Reserved_MASK 0xff000000 1542#define SPR_MSIDFUSE__Reserved__SHIFT 0x18 1543#define SPR_LINK_PRODUCT_INFO__Reserved_MASK 0xffffffff 1544#define SPR_LINK_PRODUCT_INFO__Reserved__SHIFT 0x0 1545#define SPR_BRAND_NAME_ADDR__Index_MASK 0xf 1546#define SPR_BRAND_NAME_ADDR__Index__SHIFT 0x0 1547#define SPR_BRAND_NAME_ADDR__Reserved_MASK 0xfffffff0 1548#define SPR_BRAND_NAME_ADDR__Reserved__SHIFT 0x4 1549#define SPR_BRAND_NAME_DATA__DATA_MASK 0xffffffff 1550#define SPR_BRAND_NAME_DATA__DATA__SHIFT 0x0 1551#define SPR_COMBO_PHY_PRODUCT_INFO__SPR_COMBO_PHY_PRODUCT_INFO_MASK 0xffffffff 1552#define SPR_COMBO_PHY_PRODUCT_INFO__SPR_COMBO_PHY_PRODUCT_INFO__SHIFT 0x0 1553#define MISC_GNB_PWRMGT_CFG0__TARGET_ADDR_MASK 0xffffffff 1554#define MISC_GNB_PWRMGT_CFG0__TARGET_ADDR__SHIFT 0x0 1555#define UNBPM_EXIT_TO_PSTATE__EXIT_TO_PSTATE_MASK 0x1 1556#define UNBPM_EXIT_TO_PSTATE__EXIT_TO_PSTATE__SHIFT 0x0 1557#define UNBPM_WARM_RESET_HS_STATUS__NB_CSTATE_ACTIVE_MASK 0x1 1558#define UNBPM_WARM_RESET_HS_STATUS__NB_CSTATE_ACTIVE__SHIFT 0x0 1559#define UNBPM_WARM_RESET_HS_STATUS__WARM_RESET_HS_DONE_MASK 0x2 1560#define UNBPM_WARM_RESET_HS_STATUS__WARM_RESET_HS_DONE__SHIFT 0x1 1561#define UNBPM_VOLTAGE_CNTL__VOLTAGE_EN_MASK 0x1 1562#define UNBPM_VOLTAGE_CNTL__VOLTAGE_EN__SHIFT 0x0 1563#define UNBPM_VOLTAGE_CNTL__VOLTAGE_LEVEL_MASK 0x1fe 1564#define UNBPM_VOLTAGE_CNTL__VOLTAGE_LEVEL__SHIFT 0x1 1565#define UNBPM_VOLTAGE_STATUS__VOLTAGE_STATUS_MASK 0x1 1566#define UNBPM_VOLTAGE_STATUS__VOLTAGE_STATUS__SHIFT 0x0 1567#define UNBPM_VOLTAGE_STATUS__VOLTAGE_CURRENT_LEVEL_MASK 0x1fe 1568#define UNBPM_VOLTAGE_STATUS__VOLTAGE_CURRENT_LEVEL__SHIFT 0x1 1569#define NUM_BOOST_STATES__NUM_BOOST_STATES_MASK 0x7 1570#define NUM_BOOST_STATES__NUM_BOOST_STATES__SHIFT 0x0 1571#define WARM_RESET_NB_CONTROL__WARM_RESET_CPU_VID_MASK 0xff 1572#define WARM_RESET_NB_CONTROL__WARM_RESET_CPU_VID__SHIFT 0x0 1573#define WARM_RESET_NB_CONTROL__NB_DISABLE_CORE_MASK 0xff00 1574#define WARM_RESET_NB_CONTROL__NB_DISABLE_CORE__SHIFT 0x8 1575#define ONION_NO_STREAMS_PEND__ONION_NO_STREAMS_PEND_MASK 0x1 1576#define ONION_NO_STREAMS_PEND__ONION_NO_STREAMS_PEND__SHIFT 0x0 1577#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_0_MASK 0x2 1578#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_0__SHIFT 0x1 1579#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_1_MASK 0x4 1580#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_1__SHIFT 0x2 1581#define SPR_PROGRAMMABLE_CTRL__PllRegUpTime_MASK 0x3 1582#define SPR_PROGRAMMABLE_CTRL__PllRegUpTime__SHIFT 0x0 1583#define SPR_PROGRAMMABLE_CTRL__PllVddOutUpTime_MASK 0xc 1584#define SPR_PROGRAMMABLE_CTRL__PllVddOutUpTime__SHIFT 0x2 1585#define SPR_PROGRAMMABLE_CTRL__ResonanceTime_MASK 0x30 1586#define SPR_PROGRAMMABLE_CTRL__ResonanceTime__SHIFT 0x4 1587#define SPR_PROGRAMMABLE_CTRL__C6PLLPwrDnReg_MASK 0x40 1588#define SPR_PROGRAMMABLE_CTRL__C6PLLPwrDnReg__SHIFT 0x6 1589#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnVCO_MASK 0x80 1590#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnVCO__SHIFT 0x7 1591#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnReg_MASK 0x100 1592#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnReg__SHIFT 0x8 1593#define SPR_PROGRAMMABLE_CTRL__NbPLLPwrDnReg_MASK 0x200 1594#define SPR_PROGRAMMABLE_CTRL__NbPLLPwrDnReg__SHIFT 0x9 1595#define SPR_PROGRAMMABLE_CTRL__SOIWait_MASK 0x3c00 1596#define SPR_PROGRAMMABLE_CTRL__SOIWait__SHIFT 0xa 1597#define PHN_FUSERX_MISC_FUSES__Spare_MASK 0xff 1598#define PHN_FUSERX_MISC_FUSES__Spare__SHIFT 0x0 1599#define PHN_FUSERX_MISC_FUSES__OverClockRefClkDis_MASK 0x100 1600#define PHN_FUSERX_MISC_FUSES__OverClockRefClkDis__SHIFT 0x8 1601#define PHN_FUSERX_MISC_FUSES__MemPstate_MASK 0x1e00 1602#define PHN_FUSERX_MISC_FUSES__MemPstate__SHIFT 0x9 1603#define PHN_FUSERX_MISC_FUSES__NbPstateHi_MASK 0x6000 1604#define PHN_FUSERX_MISC_FUSES__NbPstateHi__SHIFT 0xd 1605#define PHN_FUSERX_MISC_FUSES__NbPstateLo_MASK 0x18000 1606#define PHN_FUSERX_MISC_FUSES__NbPstateLo__SHIFT 0xf 1607#define PHN_FUSERX_MISC_FUSES__ScanCLK400MHz_MASK 0x20000 1608#define PHN_FUSERX_MISC_FUSES__ScanCLK400MHz__SHIFT 0x11 1609#define PHN_FUSERX_MISC_FUSES__CoreDis_MASK 0x3c0000 1610#define PHN_FUSERX_MISC_FUSES__CoreDis__SHIFT 0x12 1611#define PHN_FUSERX_MISC_FUSES__PHN_FusesValid_MASK 0x80000000 1612#define PHN_FUSERX_MISC_FUSES__PHN_FusesValid__SHIFT 0x1f 1613#define UNBPM_PWRCTRL_MISC__PWRGATEMASTERDIS_MASK 0x1 1614#define UNBPM_PWRCTRL_MISC__PWRGATEMASTERDIS__SHIFT 0x0 1615#define CSTATE_ACTIVE_SAMPLER__SAMPLE_TIME_MASK 0x1f 1616#define CSTATE_ACTIVE_SAMPLER__SAMPLE_TIME__SHIFT 0x0 1617#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_QOS_MASK 0xf 1618#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_QOS__SHIFT 0x0 1619#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_BUFF_FLUSH_MASK 0x10 1620#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_BUFF_FLUSH__SHIFT 0x4 1621#define UNBPM_DEBUG_CONFIG_STATUS__MASTER_DEBUG_EN_MASK 0x20 1622#define UNBPM_DEBUG_CONFIG_STATUS__MASTER_DEBUG_EN__SHIFT 0x5 1623#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_ACTIVE_MASK 0x100 1624#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_ACTIVE__SHIFT 0x8 1625#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_BUSY_MASK 0x200 1626#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_BUSY__SHIFT 0x9 1627#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_DATA_COUNT_MASK 0x3c00 1628#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_DATA_COUNT__SHIFT 0xa 1629#define UNBPM_DEBUG_CONFIG_STATUS__MST_OUTSTANDING_TRANS_MASK 0xff0000 1630#define UNBPM_DEBUG_CONFIG_STATUS__MST_OUTSTANDING_TRANS__SHIFT 0x10 1631#define UNBPM_AXIMST_LAST_CMD__AXI_MASTER_LAST_CMD_MASK 0xffffffff 1632#define UNBPM_AXIMST_LAST_CMD__AXI_MASTER_LAST_CMD__SHIFT 0x0 1633#define UNB_IF_INTRGEN_LAST_SENT__GNBPM_LAST_DATA_SENT_MASK 0xffff 1634#define UNB_IF_INTRGEN_LAST_SENT__GNBPM_LAST_DATA_SENT__SHIFT 0x0 1635#define UNB_IF_INTRGEN_LAST_SENT__SMUPM_LAST_DATA_SENT_MASK 0xffff0000 1636#define UNB_IF_INTRGEN_LAST_SENT__SMUPM_LAST_DATA_SENT__SHIFT 0x10 1637#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_LOGGING_EN_MASK 0x1 1638#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_LOGGING_EN__SHIFT 0x0 1639#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_CYCLE_NUM_MASK 0x1fe 1640#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_CYCLE_NUM__SHIFT 0x1 1641#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNb_MASK 0x1 1642#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNb__SHIFT 0x0 1643#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDct_MASK 0x6 1644#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDct__SHIFT 0x1 1645#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpu_MASK 0x38 1646#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpu__SHIFT 0x3 1647#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPwrTog_MASK 0x40 1648#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPwrTog__SHIFT 0x6 1649#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbPstateLo_MASK 0x80 1650#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbPstateLo__SHIFT 0x7 1651#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbMemPstate_MASK 0x100 1652#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbMemPstate__SHIFT 0x8 1653#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuNbFid_MASK 0x7e00 1654#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuNbFid__SHIFT 0x9 1655#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDid_MASK 0x38000 1656#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDid__SHIFT 0xf 1657#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstate_MASK 0x40000 1658#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstate__SHIFT 0x12 1659#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstateId_MASK 0x380000 1660#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstateId__SHIFT 0x13 1661#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqGateEn_MASK 0x400000 1662#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqGateEn__SHIFT 0x16 1663#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPrbEn_MASK 0x800000 1664#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPrbEn__SHIFT 0x17 1665#define UNBPM_PWRMGT_REQ_DBG_STATUS__NbPwrMgtReqOutstanding_MASK 0x7000000 1666#define UNBPM_PWRMGT_REQ_DBG_STATUS__NbPwrMgtReqOutstanding__SHIFT 0x18 1667#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgZeroVid_MASK 0x1 1668#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgZeroVid__SHIFT 0x0 1669#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidPlane_MASK 0x6 1670#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidPlane__SHIFT 0x1 1671#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgRamp_MASK 0x8 1672#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgRamp__SHIFT 0x3 1673#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_Vid_MASK 0xff0 1674#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_Vid__SHIFT 0x4 1675#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VSTime_MASK 0x7000 1676#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VSTime__SHIFT 0xc 1677#define UNBPM_VIDCHG_REQ_DBG_STATUS__CK_VidChgBusy_MASK 0x10000 1678#define UNBPM_VIDCHG_REQ_DBG_STATUS__CK_VidChgBusy__SHIFT 0x10 1679#define UNBPM_SCRATCH_0__DATA_MASK 0xffffffff 1680#define UNBPM_SCRATCH_0__DATA__SHIFT 0x0 1681#define UNBPM_SCRATCH_1__DATA_MASK 0xffffffff 1682#define UNBPM_SCRATCH_1__DATA__SHIFT 0x0 1683#define POWERON_CPU_0__POWERON_MASK 0x1 1684#define POWERON_CPU_0__POWERON__SHIFT 0x0 1685#define POWERREADY_CPU_0__POWERREADY_MASK 0x1 1686#define POWERREADY_CPU_0__POWERREADY__SHIFT 0x0 1687#define PGRUNFEEDBACK_CPU_0__PG_RUNFEEDBACK_MASK 0x1 1688#define PGRUNFEEDBACK_CPU_0__PG_RUNFEEDBACK__SHIFT 0x0 1689#define RCC3ON_CPU_0__CK_RCC3ON_MASK 0x1 1690#define RCC3ON_CPU_0__CK_RCC3ON__SHIFT 0x0 1691#define RCC3ON_CPU_0__RCC3_PSM_EN_MASK 0x2 1692#define RCC3ON_CPU_0__RCC3_PSM_EN__SHIFT 0x1 1693#define RCC3ON_CPU_0__RCC3_PSM_CLK_DIV_MASK 0xc 1694#define RCC3ON_CPU_0__RCC3_PSM_CLK_DIV__SHIFT 0x2 1695#define RCC3ON_CPU_0__RCC3_AVG_EN_MASK 0x10 1696#define RCC3ON_CPU_0__RCC3_AVG_EN__SHIFT 0x4 1697#define RCC3ON_CPU_0__RCC3_AVG_DIV_MASK 0x7e0 1698#define RCC3ON_CPU_0__RCC3_AVG_DIV__SHIFT 0x5 1699#define RCC3ON_CPU_0__RCC3_DIDT_TIMER_MASK 0x1f800 1700#define RCC3ON_CPU_0__RCC3_DIDT_TIMER__SHIFT 0xb 1701#define RCC3ON_CPU_0__RCC3_WAKE_MIN_14_0_MASK 0xfffe0000 1702#define RCC3ON_CPU_0__RCC3_WAKE_MIN_14_0__SHIFT 0x11 1703#define RCC3EXITDONE_CPU_0__RCC3EXITDONE_MASK 0x1 1704#define RCC3EXITDONE_CPU_0__RCC3EXITDONE__SHIFT 0x0 1705#define CORE_FUNC_LATE_SSB_XFER_0__START_STATUS_XFER_MASK 0x1 1706#define CORE_FUNC_LATE_SSB_XFER_0__START_STATUS_XFER__SHIFT 0x0 1707#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_FUNC_LAST_ADDR_MASK 0x7ff 1708#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_FUNC_LAST_ADDR__SHIFT 0x0 1709#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_LATE_LAST_ADDR_MASK 0x7ff0000 1710#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_LATE_LAST_ADDR__SHIFT 0x10 1711#define CORE_REDUN_SSB_XFER_0__START_STATUS_XFER_MASK 0x1 1712#define CORE_REDUN_SSB_XFER_0__START_STATUS_XFER__SHIFT 0x0 1713#define CORE_REDUN_SSB_XFER_CFG_0__FUSE_REDUN_LAST_ADDR_MASK 0x7ff 1714#define CORE_REDUN_SSB_XFER_CFG_0__FUSE_REDUN_LAST_ADDR__SHIFT 0x0 1715#define CORE_APM_SSB_XFER_0__START_STATUS_XFER_MASK 0x1 1716#define CORE_APM_SSB_XFER_0__START_STATUS_XFER__SHIFT 0x0 1717#define CORE_APM_SSB_XFER_CFG_0__FUSE_APM_LAST_ADDR_MASK 0x7ff 1718#define CORE_APM_SSB_XFER_CFG_0__FUSE_APM_LAST_ADDR__SHIFT 0x0 1719#define COREPM_PWRCTRL_MISC_0__PWRGATEMASTERDIS_MASK 0x1 1720#define COREPM_PWRCTRL_MISC_0__PWRGATEMASTERDIS__SHIFT 0x0 1721#define LDOIVRON_CPU_0__CK_LDOIVRON_MASK 0x1 1722#define LDOIVRON_CPU_0__CK_LDOIVRON__SHIFT 0x0 1723#define LDOIVREXITDONE_CPU_0__LDOIVREXITDONE_MASK 0x1 1724#define LDOIVREXITDONE_CPU_0__LDOIVREXITDONE__SHIFT 0x0 1725#define RCC3_TARGETPSMREF_CPU_0__RCC3_TARGETPSMREF_MASK 0x3fff 1726#define RCC3_TARGETPSMREF_CPU_0__RCC3_TARGETPSMREF__SHIFT 0x0 1727#define IVR_TARGETPSMREF_CPU_0__IVR_TARGETPSMREF_MASK 0x3fff 1728#define IVR_TARGETPSMREF_CPU_0__IVR_TARGETPSMREF__SHIFT 0x0 1729#define CK_JTCOOLRESET_LATCHED_CPU_0__CK_JTCOOLRESET_LATCHED_MASK 0x1 1730#define CK_JTCOOLRESET_LATCHED_CPU_0__CK_JTCOOLRESET_LATCHED__SHIFT 0x0 1731#define CK_DISABLECORE_CPU_0__CK_DISABLECORE_MASK 0x1 1732#define CK_DISABLECORE_CPU_0__CK_DISABLECORE__SHIFT 0x0 1733#define COREPM_ID_0__COREPM_INDEX_MASK 0x1 1734#define COREPM_ID_0__COREPM_INDEX__SHIFT 0x0 1735#define COREPM_SCRATCH_0__SCRATCH_DATA_MASK 0xffffffff 1736#define COREPM_SCRATCH_0__SCRATCH_DATA__SHIFT 0x0 1737#define RCC3_WAKEMIN_CPU_0__RCC3_WAKE_MIN_46_15_MASK 0xffffffff 1738#define RCC3_WAKEMIN_CPU_0__RCC3_WAKE_MIN_46_15__SHIFT 0x0 1739#define SPMI_CONFIG0_0__SPMI_ENABLE_MASK 0x1 1740#define SPMI_CONFIG0_0__SPMI_ENABLE__SHIFT 0x0 1741#define SPMI_CONFIG0_0__SPMI_PATH_NUM_TIMING_FLOPS_MASK 0x7c 1742#define SPMI_CONFIG0_0__SPMI_PATH_NUM_TIMING_FLOPS__SHIFT 0x2 1743#define SPMI_CONFIG0_0__SPMI_SIGNALING_DELAY_CYCLES_MASK 0xf80 1744#define SPMI_CONFIG0_0__SPMI_SIGNALING_DELAY_CYCLES__SHIFT 0x7 1745#define SPMI_CONFIG0_0__SPMI_SIGNALING_HOLD_CYCLES_MASK 0x1f000 1746#define SPMI_CONFIG0_0__SPMI_SIGNALING_HOLD_CYCLES__SHIFT 0xc 1747#define SPMI_CONFIG0_0__SPMI_PATH_ENABLE_DELAY_CYCLES_MASK 0x3e0000 1748#define SPMI_CONFIG0_0__SPMI_PATH_ENABLE_DELAY_CYCLES__SHIFT 0x11 1749#define SPMI_CONFIG0_0__SPMI_PATH_DISABLE_DELAY_CYCLES_MASK 0x7c00000 1750#define SPMI_CONFIG0_0__SPMI_PATH_DISABLE_DELAY_CYCLES__SHIFT 0x16 1751#define SPMI_CONFIG1_0__SPMI_SIGNALING_RESET_HOLD_CYCLES_MASK 0x1f 1752#define SPMI_CONFIG1_0__SPMI_SIGNALING_RESET_HOLD_CYCLES__SHIFT 0x0 1753#define SPMI_CONFIG1_0__SPMI_CHAIN_SIZE_MASK 0xffe0 1754#define SPMI_CONFIG1_0__SPMI_CHAIN_SIZE__SHIFT 0x5 1755#define SPMI_FSM_READ_TRIGGER_0__FSM_READ_TRIGGER_MASK 0x1 1756#define SPMI_FSM_READ_TRIGGER_0__FSM_READ_TRIGGER__SHIFT 0x0 1757#define SPMI_FSM_WRITE_TRIGGER_0__FSM_WRITE_TRIGGER_MASK 0x1 1758#define SPMI_FSM_WRITE_TRIGGER_0__FSM_WRITE_TRIGGER__SHIFT 0x0 1759#define SPMI_FSM_RESET_TRIGGER_0__FSM_RESET_TRIGGER_MASK 0x1 1760#define SPMI_FSM_RESET_TRIGGER_0__FSM_RESET_TRIGGER__SHIFT 0x0 1761#define SPMI_FSM_BUSY_0__FSM_BUSY_MASK 0x1 1762#define SPMI_FSM_BUSY_0__FSM_BUSY__SHIFT 0x0 1763#define SPMI_PATH_0__PATH_ENABLE_REQ_MASK 0x1 1764#define SPMI_PATH_0__PATH_ENABLE_REQ__SHIFT 0x0 1765#define SPMI_PATH_0__PATH_ENABLE_ACK_MASK 0x2 1766#define SPMI_PATH_0__PATH_ENABLE_ACK__SHIFT 0x1 1767#define SPMI_PATH_0__PATH_ENABLE_REQ_auto_clear_MASK 0x10 1768#define SPMI_PATH_0__PATH_ENABLE_REQ_auto_clear__SHIFT 0x4 1769#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED_MASK 0x1 1770#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED__SHIFT 0x0 1771#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY_MASK 0x2 1772#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY__SHIFT 0x1 1773#define SPMI_C6_STATE_0__SPMI_IF_COUNTER_ADDRESS_C6_MASK 0xfffc 1774#define SPMI_C6_STATE_0__SPMI_IF_COUNTER_ADDRESS_C6__SHIFT 0x2 1775#define SPMI_JTAG_OVER_0__SPMI_IF_JTAG_OVER_HAPPENED_MASK 0x1 1776#define SPMI_JTAG_OVER_0__SPMI_IF_JTAG_OVER_HAPPENED__SHIFT 0x0 1777#define SPMI_SRAM_ADDRESS_0__SRAM_ADDRESS_MASK 0xffffffff 1778#define SPMI_SRAM_ADDRESS_0__SRAM_ADDRESS__SHIFT 0x0 1779#define SPMI_SRAM_DATA_0__SRAM_DATA_MASK 0xffffffff 1780#define SPMI_SRAM_DATA_0__SRAM_DATA__SHIFT 0x0 1781#define SPMI_RESET_0__ASYNC_RESET_0_MASK 0x1 1782#define SPMI_RESET_0__ASYNC_RESET_0__SHIFT 0x0 1783#define SPMI_RESET_0__SYNC_RESET_MASK 0x80000000 1784#define SPMI_RESET_0__SYNC_RESET__SHIFT 0x1f 1785#define SPMI_FORCE_CLOCK_GATERS_0__CLOCK_GATER_0_FORCE_MASK 0x1 1786#define SPMI_FORCE_CLOCK_GATERS_0__CLOCK_GATER_0_FORCE__SHIFT 0x0 1787#define SPMI_FORCE_CLOCK_GATERS_0__SRAM_CLOCK_GATER_FORCE_MASK 0x100 1788#define SPMI_FORCE_CLOCK_GATERS_0__SRAM_CLOCK_GATER_FORCE__SHIFT 0x8 1789#define SPMI_SPARE_0__SPARE_DATA_MASK 0xffffffff 1790#define SPMI_SPARE_0__SPARE_DATA__SHIFT 0x0 1791#define SPMI_SPARE_EX_0__SPARE_DATA_EX_MASK 0xffffffff 1792#define SPMI_SPARE_EX_0__SPARE_DATA_EX__SHIFT 0x0 1793#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_EN_MASK 0x1 1794#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_EN__SHIFT 0x0 1795#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_TIMER_MASK 0x7fe 1796#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_TIMER__SHIFT 0x1 1797#define POWERON_CPU_1__POWERON_MASK 0x1 1798#define POWERON_CPU_1__POWERON__SHIFT 0x0 1799#define POWERREADY_CPU_1__POWERREADY_MASK 0x1 1800#define POWERREADY_CPU_1__POWERREADY__SHIFT 0x0 1801#define PGRUNFEEDBACK_CPU_1__PG_RUNFEEDBACK_MASK 0x1 1802#define PGRUNFEEDBACK_CPU_1__PG_RUNFEEDBACK__SHIFT 0x0 1803#define RCC3ON_CPU_1__CK_RCC3ON_MASK 0x1 1804#define RCC3ON_CPU_1__CK_RCC3ON__SHIFT 0x0 1805#define RCC3ON_CPU_1__RCC3_PSM_EN_MASK 0x2 1806#define RCC3ON_CPU_1__RCC3_PSM_EN__SHIFT 0x1 1807#define RCC3ON_CPU_1__RCC3_PSM_CLK_DIV_MASK 0xc 1808#define RCC3ON_CPU_1__RCC3_PSM_CLK_DIV__SHIFT 0x2 1809#define RCC3ON_CPU_1__RCC3_AVG_EN_MASK 0x10 1810#define RCC3ON_CPU_1__RCC3_AVG_EN__SHIFT 0x4 1811#define RCC3ON_CPU_1__RCC3_AVG_DIV_MASK 0x7e0 1812#define RCC3ON_CPU_1__RCC3_AVG_DIV__SHIFT 0x5 1813#define RCC3ON_CPU_1__RCC3_DIDT_TIMER_MASK 0x1f800 1814#define RCC3ON_CPU_1__RCC3_DIDT_TIMER__SHIFT 0xb 1815#define RCC3ON_CPU_1__RCC3_WAKE_MIN_14_0_MASK 0xfffe0000 1816#define RCC3ON_CPU_1__RCC3_WAKE_MIN_14_0__SHIFT 0x11 1817#define RCC3EXITDONE_CPU_1__RCC3EXITDONE_MASK 0x1 1818#define RCC3EXITDONE_CPU_1__RCC3EXITDONE__SHIFT 0x0 1819#define CORE_FUNC_LATE_SSB_XFER_1__START_STATUS_XFER_MASK 0x1 1820#define CORE_FUNC_LATE_SSB_XFER_1__START_STATUS_XFER__SHIFT 0x0 1821#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_FUNC_LAST_ADDR_MASK 0x7ff 1822#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_FUNC_LAST_ADDR__SHIFT 0x0 1823#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_LATE_LAST_ADDR_MASK 0x7ff0000 1824#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_LATE_LAST_ADDR__SHIFT 0x10 1825#define CORE_REDUN_SSB_XFER_1__START_STATUS_XFER_MASK 0x1 1826#define CORE_REDUN_SSB_XFER_1__START_STATUS_XFER__SHIFT 0x0 1827#define CORE_REDUN_SSB_XFER_CFG_1__FUSE_REDUN_LAST_ADDR_MASK 0x7ff 1828#define CORE_REDUN_SSB_XFER_CFG_1__FUSE_REDUN_LAST_ADDR__SHIFT 0x0 1829#define CORE_APM_SSB_XFER_1__START_STATUS_XFER_MASK 0x1 1830#define CORE_APM_SSB_XFER_1__START_STATUS_XFER__SHIFT 0x0 1831#define CORE_APM_SSB_XFER_CFG_1__FUSE_APM_LAST_ADDR_MASK 0x7ff 1832#define CORE_APM_SSB_XFER_CFG_1__FUSE_APM_LAST_ADDR__SHIFT 0x0 1833#define COREPM_PWRCTRL_MISC_1__PWRGATEMASTERDIS_MASK 0x1 1834#define COREPM_PWRCTRL_MISC_1__PWRGATEMASTERDIS__SHIFT 0x0 1835#define LDOIVRON_CPU_1__CK_LDOIVRON_MASK 0x1 1836#define LDOIVRON_CPU_1__CK_LDOIVRON__SHIFT 0x0 1837#define LDOIVREXITDONE_CPU_1__LDOIVREXITDONE_MASK 0x1 1838#define LDOIVREXITDONE_CPU_1__LDOIVREXITDONE__SHIFT 0x0 1839#define RCC3_TARGETPSMREF_CPU_1__RCC3_TARGETPSMREF_MASK 0x3fff 1840#define RCC3_TARGETPSMREF_CPU_1__RCC3_TARGETPSMREF__SHIFT 0x0 1841#define IVR_TARGETPSMREF_CPU_1__IVR_TARGETPSMREF_MASK 0x3fff 1842#define IVR_TARGETPSMREF_CPU_1__IVR_TARGETPSMREF__SHIFT 0x0 1843#define CK_JTCOOLRESET_LATCHED_CPU_1__CK_JTCOOLRESET_LATCHED_MASK 0x1 1844#define CK_JTCOOLRESET_LATCHED_CPU_1__CK_JTCOOLRESET_LATCHED__SHIFT 0x0 1845#define CK_DISABLECORE_CPU_1__CK_DISABLECORE_MASK 0x1 1846#define CK_DISABLECORE_CPU_1__CK_DISABLECORE__SHIFT 0x0 1847#define COREPM_ID_1__COREPM_INDEX_MASK 0x1 1848#define COREPM_ID_1__COREPM_INDEX__SHIFT 0x0 1849#define COREPM_SCRATCH_1__SCRATCH_DATA_MASK 0xffffffff 1850#define COREPM_SCRATCH_1__SCRATCH_DATA__SHIFT 0x0 1851#define RCC3_WAKEMIN_CPU_1__RCC3_WAKE_MIN_46_15_MASK 0xffffffff 1852#define RCC3_WAKEMIN_CPU_1__RCC3_WAKE_MIN_46_15__SHIFT 0x0 1853#define SPMI_CONFIG0_1__SPMI_ENABLE_MASK 0x1 1854#define SPMI_CONFIG0_1__SPMI_ENABLE__SHIFT 0x0 1855#define SPMI_CONFIG0_1__SPMI_PATH_NUM_TIMING_FLOPS_MASK 0x7c 1856#define SPMI_CONFIG0_1__SPMI_PATH_NUM_TIMING_FLOPS__SHIFT 0x2 1857#define SPMI_CONFIG0_1__SPMI_SIGNALING_DELAY_CYCLES_MASK 0xf80 1858#define SPMI_CONFIG0_1__SPMI_SIGNALING_DELAY_CYCLES__SHIFT 0x7 1859#define SPMI_CONFIG0_1__SPMI_SIGNALING_HOLD_CYCLES_MASK 0x1f000 1860#define SPMI_CONFIG0_1__SPMI_SIGNALING_HOLD_CYCLES__SHIFT 0xc 1861#define SPMI_CONFIG0_1__SPMI_PATH_ENABLE_DELAY_CYCLES_MASK 0x3e0000 1862#define SPMI_CONFIG0_1__SPMI_PATH_ENABLE_DELAY_CYCLES__SHIFT 0x11 1863#define SPMI_CONFIG0_1__SPMI_PATH_DISABLE_DELAY_CYCLES_MASK 0x7c00000 1864#define SPMI_CONFIG0_1__SPMI_PATH_DISABLE_DELAY_CYCLES__SHIFT 0x16 1865#define SPMI_CONFIG1_1__SPMI_SIGNALING_RESET_HOLD_CYCLES_MASK 0x1f 1866#define SPMI_CONFIG1_1__SPMI_SIGNALING_RESET_HOLD_CYCLES__SHIFT 0x0 1867#define SPMI_CONFIG1_1__SPMI_CHAIN_SIZE_MASK 0xffe0 1868#define SPMI_CONFIG1_1__SPMI_CHAIN_SIZE__SHIFT 0x5 1869#define SPMI_FSM_READ_TRIGGER_1__FSM_READ_TRIGGER_MASK 0x1 1870#define SPMI_FSM_READ_TRIGGER_1__FSM_READ_TRIGGER__SHIFT 0x0 1871#define SPMI_FSM_WRITE_TRIGGER_1__FSM_WRITE_TRIGGER_MASK 0x1 1872#define SPMI_FSM_WRITE_TRIGGER_1__FSM_WRITE_TRIGGER__SHIFT 0x0 1873#define SPMI_FSM_RESET_TRIGGER_1__FSM_RESET_TRIGGER_MASK 0x1 1874#define SPMI_FSM_RESET_TRIGGER_1__FSM_RESET_TRIGGER__SHIFT 0x0 1875#define SPMI_FSM_BUSY_1__FSM_BUSY_MASK 0x1 1876#define SPMI_FSM_BUSY_1__FSM_BUSY__SHIFT 0x0 1877#define SPMI_PATH_1__PATH_ENABLE_REQ_MASK 0x1 1878#define SPMI_PATH_1__PATH_ENABLE_REQ__SHIFT 0x0 1879#define SPMI_PATH_1__PATH_ENABLE_ACK_MASK 0x2 1880#define SPMI_PATH_1__PATH_ENABLE_ACK__SHIFT 0x1 1881#define SPMI_PATH_1__PATH_ENABLE_REQ_auto_clear_MASK 0x10 1882#define SPMI_PATH_1__PATH_ENABLE_REQ_auto_clear__SHIFT 0x4 1883#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED_MASK 0x1 1884#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED__SHIFT 0x0 1885#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY_MASK 0x2 1886#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY__SHIFT 0x1 1887#define SPMI_C6_STATE_1__SPMI_IF_COUNTER_ADDRESS_C6_MASK 0xfffc 1888#define SPMI_C6_STATE_1__SPMI_IF_COUNTER_ADDRESS_C6__SHIFT 0x2 1889#define SPMI_JTAG_OVER_1__SPMI_IF_JTAG_OVER_HAPPENED_MASK 0x1 1890#define SPMI_JTAG_OVER_1__SPMI_IF_JTAG_OVER_HAPPENED__SHIFT 0x0 1891#define SPMI_SRAM_ADDRESS_1__SRAM_ADDRESS_MASK 0xffffffff 1892#define SPMI_SRAM_ADDRESS_1__SRAM_ADDRESS__SHIFT 0x0 1893#define SPMI_SRAM_DATA_1__SRAM_DATA_MASK 0xffffffff 1894#define SPMI_SRAM_DATA_1__SRAM_DATA__SHIFT 0x0 1895#define SPMI_RESET_1__ASYNC_RESET_0_MASK 0x1 1896#define SPMI_RESET_1__ASYNC_RESET_0__SHIFT 0x0 1897#define SPMI_RESET_1__SYNC_RESET_MASK 0x80000000 1898#define SPMI_RESET_1__SYNC_RESET__SHIFT 0x1f 1899#define SPMI_FORCE_CLOCK_GATERS_1__CLOCK_GATER_0_FORCE_MASK 0x1 1900#define SPMI_FORCE_CLOCK_GATERS_1__CLOCK_GATER_0_FORCE__SHIFT 0x0 1901#define SPMI_FORCE_CLOCK_GATERS_1__SRAM_CLOCK_GATER_FORCE_MASK 0x100 1902#define SPMI_FORCE_CLOCK_GATERS_1__SRAM_CLOCK_GATER_FORCE__SHIFT 0x8 1903#define SPMI_SPARE_1__SPARE_DATA_MASK 0xffffffff 1904#define SPMI_SPARE_1__SPARE_DATA__SHIFT 0x0 1905#define SPMI_SPARE_EX_1__SPARE_DATA_EX_MASK 0xffffffff 1906#define SPMI_SPARE_EX_1__SPARE_DATA_EX__SHIFT 0x0 1907#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_EN_MASK 0x1 1908#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_EN__SHIFT 0x0 1909#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_TIMER_MASK 0x7fe 1910#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_TIMER__SHIFT 0x1 1911#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1 1912#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0 1913#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2 1914#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1 1915#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4 1916#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2 1917#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8 1918#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3 1919#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40 1920#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6 1921#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100 1922#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8 1923#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200 1924#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9 1925#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400 1926#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa 1927#define GENERAL_PWRMGT__SPARE11_MASK 0x800 1928#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb 1929#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000 1930#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe 1931#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000 1932#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf 1933#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000 1934#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10 1935#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000 1936#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11 1937#define GENERAL_PWRMGT__SPARE18_MASK 0x40000 1938#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12 1939#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000 1940#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13 1941#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000 1942#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17 1943#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000 1944#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b 1945#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000 1946#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c 1947#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3 1948#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0 1949#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 1950#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2 1951#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8 1952#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 1953#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10 1954#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4 1955#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0 1956#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5 1957#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10 1958#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4 1959#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20 1960#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5 1961#define SCLK_PWRMGT_CNTL__RESERVED_0_MASK 0x40 1962#define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT 0x6 1963#define SCLK_PWRMGT_CNTL__RESERVED_3_MASK 0x1000000 1964#define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT 0x18 1965#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_ACPI_INDEX_MASK 0xf 1966#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_ACPI_INDEX__SHIFT 0x0 1967#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_ACPI_INDEX_MASK 0xf0 1968#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_ACPI_INDEX__SHIFT 0x4 1969#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00 1970#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8 1971#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000 1972#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc 1973#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000 1974#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10 1975#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000 1976#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15 1977#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000 1978#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a 1979#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000 1980#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d 1981#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf 1982#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0 1983#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0 1984#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4 1985#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00 1986#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8 1987#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000 1988#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc 1989#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000 1990#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10 1991#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000 1992#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14 1993#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000 1994#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18 1995#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000 1996#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c 1997#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_UVD_INDEX_MASK 0xf 1998#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_UVD_INDEX__SHIFT 0x0 1999#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_UVD_INDEX_MASK 0xf0 2000#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_UVD_INDEX__SHIFT 0x4 2001#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_VCE_INDEX_MASK 0xf00 2002#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_VCE_INDEX__SHIFT 0x8 2003#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_VCE_INDEX_MASK 0xf000 2004#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_VCE_INDEX__SHIFT 0xc 2005#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_ACP_INDEX_MASK 0xf0000 2006#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_ACP_INDEX__SHIFT 0x10 2007#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_ACP_INDEX_MASK 0xf00000 2008#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_ACP_INDEX__SHIFT 0x14 2009#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_SAMU_INDEX_MASK 0xf000000 2010#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_SAMU_INDEX__SHIFT 0x18 2011#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_SAMU_INDEX_MASK 0xf0000000 2012#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_SAMU_INDEX__SHIFT 0x1c 2013#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 2014#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 2015#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 2016#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 2017#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 2018#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 2019#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 2020#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 2021#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 2022#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 2023#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 2024#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 2025#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 2026#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 2027#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 2028#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 2029#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 2030#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 2031#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 2032#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 2033#define CG_FREQ_TRAN_VOTING_0__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 2034#define CG_FREQ_TRAN_VOTING_0__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 2035#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 2036#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 2037#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 2038#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 2039#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 2040#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 2041#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 2042#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 2043#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 2044#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 2045#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 2046#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 2047#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 2048#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 2049#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 2050#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 2051#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 2052#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 2053#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 2054#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 2055#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 2056#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 2057#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 2058#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 2059#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 2060#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 2061#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 2062#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 2063#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 2064#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 2065#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 2066#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 2067#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 2068#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 2069#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 2070#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 2071#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 2072#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 2073#define CG_FREQ_TRAN_VOTING_0__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 2074#define CG_FREQ_TRAN_VOTING_0__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f 2075#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 2076#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 2077#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 2078#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 2079#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 2080#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 2081#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 2082#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 2083#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 2084#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 2085#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 2086#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 2087#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 2088#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 2089#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 2090#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 2091#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 2092#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 2093#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 2094#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 2095#define CG_FREQ_TRAN_VOTING_1__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 2096#define CG_FREQ_TRAN_VOTING_1__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 2097#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 2098#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 2099#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 2100#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 2101#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 2102#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 2103#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 2104#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 2105#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 2106#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 2107#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 2108#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 2109#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 2110#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 2111#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 2112#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 2113#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 2114#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 2115#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 2116#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 2117#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 2118#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 2119#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 2120#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 2121#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 2122#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 2123#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 2124#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 2125#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 2126#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 2127#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 2128#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 2129#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 2130#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 2131#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 2132#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 2133#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 2134#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 2135#define CG_FREQ_TRAN_VOTING_1__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 2136#define CG_FREQ_TRAN_VOTING_1__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f 2137#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 2138#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 2139#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 2140#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 2141#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 2142#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 2143#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 2144#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 2145#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 2146#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 2147#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 2148#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 2149#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 2150#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 2151#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 2152#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 2153#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 2154#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 2155#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 2156#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 2157#define CG_FREQ_TRAN_VOTING_2__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 2158#define CG_FREQ_TRAN_VOTING_2__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 2159#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 2160#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 2161#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 2162#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 2163#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 2164#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 2165#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 2166#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 2167#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 2168#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 2169#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 2170#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 2171#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 2172#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 2173#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 2174#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 2175#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 2176#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 2177#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 2178#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 2179#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 2180#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 2181#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 2182#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 2183#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 2184#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 2185#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 2186#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 2187#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 2188#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 2189#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 2190#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 2191#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 2192#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 2193#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 2194#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 2195#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 2196#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 2197#define CG_FREQ_TRAN_VOTING_2__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 2198#define CG_FREQ_TRAN_VOTING_2__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f 2199#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 2200#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 2201#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 2202#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 2203#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 2204#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 2205#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 2206#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 2207#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 2208#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 2209#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 2210#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 2211#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 2212#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 2213#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 2214#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 2215#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 2216#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 2217#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 2218#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 2219#define CG_FREQ_TRAN_VOTING_3__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 2220#define CG_FREQ_TRAN_VOTING_3__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 2221#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 2222#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 2223#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 2224#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 2225#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 2226#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 2227#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 2228#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 2229#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 2230#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 2231#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 2232#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 2233#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 2234#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 2235#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 2236#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 2237#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 2238#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 2239#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 2240#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 2241#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 2242#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 2243#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 2244#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 2245#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 2246#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 2247#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 2248#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 2249#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 2250#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 2251#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 2252#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 2253#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 2254#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 2255#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 2256#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 2257#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 2258#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 2259#define CG_FREQ_TRAN_VOTING_3__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 2260#define CG_FREQ_TRAN_VOTING_3__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f 2261#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 2262#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 2263#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 2264#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 2265#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 2266#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 2267#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 2268#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 2269#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 2270#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 2271#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 2272#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 2273#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 2274#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 2275#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 2276#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 2277#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 2278#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 2279#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 2280#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 2281#define CG_FREQ_TRAN_VOTING_4__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 2282#define CG_FREQ_TRAN_VOTING_4__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 2283#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 2284#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 2285#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 2286#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 2287#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 2288#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 2289#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 2290#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 2291#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 2292#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 2293#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 2294#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 2295#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 2296#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 2297#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 2298#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 2299#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 2300#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 2301#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 2302#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 2303#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 2304#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 2305#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 2306#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 2307#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 2308#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 2309#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 2310#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 2311#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 2312#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 2313#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 2314#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 2315#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 2316#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 2317#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 2318#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 2319#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 2320#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 2321#define CG_FREQ_TRAN_VOTING_4__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 2322#define CG_FREQ_TRAN_VOTING_4__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f 2323#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 2324#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 2325#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 2326#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 2327#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 2328#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 2329#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 2330#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 2331#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 2332#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 2333#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 2334#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 2335#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 2336#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 2337#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 2338#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 2339#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 2340#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 2341#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 2342#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 2343#define CG_FREQ_TRAN_VOTING_5__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 2344#define CG_FREQ_TRAN_VOTING_5__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 2345#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 2346#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 2347#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 2348#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 2349#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 2350#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 2351#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 2352#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 2353#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 2354#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 2355#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 2356#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 2357#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 2358#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 2359#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 2360#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 2361#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 2362#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 2363#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 2364#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 2365#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 2366#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 2367#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 2368#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 2369#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 2370#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 2371#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 2372#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 2373#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 2374#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 2375#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 2376#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 2377#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 2378#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 2379#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 2380#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 2381#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 2382#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 2383#define CG_FREQ_TRAN_VOTING_5__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 2384#define CG_FREQ_TRAN_VOTING_5__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f 2385#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 2386#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 2387#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 2388#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 2389#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 2390#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 2391#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 2392#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 2393#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 2394#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 2395#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 2396#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 2397#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 2398#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 2399#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 2400#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 2401#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 2402#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 2403#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 2404#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 2405#define CG_FREQ_TRAN_VOTING_6__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 2406#define CG_FREQ_TRAN_VOTING_6__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 2407#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 2408#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 2409#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 2410#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 2411#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 2412#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 2413#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 2414#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 2415#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 2416#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 2417#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 2418#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 2419#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 2420#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 2421#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 2422#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 2423#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 2424#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 2425#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 2426#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 2427#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 2428#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 2429#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 2430#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 2431#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 2432#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 2433#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 2434#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 2435#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 2436#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 2437#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 2438#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 2439#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 2440#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 2441#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 2442#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 2443#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 2444#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 2445#define CG_FREQ_TRAN_VOTING_6__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 2446#define CG_FREQ_TRAN_VOTING_6__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f 2447#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 2448#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 2449#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 2450#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 2451#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 2452#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 2453#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 2454#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 2455#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 2456#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 2457#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 2458#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 2459#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 2460#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 2461#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 2462#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 2463#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 2464#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 2465#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 2466#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 2467#define CG_FREQ_TRAN_VOTING_7__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 2468#define CG_FREQ_TRAN_VOTING_7__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 2469#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 2470#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 2471#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 2472#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 2473#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 2474#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 2475#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 2476#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 2477#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 2478#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 2479#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 2480#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 2481#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 2482#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 2483#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 2484#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 2485#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 2486#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 2487#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 2488#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 2489#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 2490#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 2491#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 2492#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 2493#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 2494#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 2495#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 2496#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 2497#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 2498#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 2499#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 2500#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 2501#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 2502#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 2503#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 2504#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 2505#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 2506#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 2507#define CG_FREQ_TRAN_VOTING_7__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 2508#define CG_FREQ_TRAN_VOTING_7__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f 2509#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff 2510#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0 2511#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000 2512#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10 2513#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f 2514#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0 2515#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80 2516#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7 2517#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 2518#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 2519#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 2520#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 2521#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 2522#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 2523#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000 2524#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10 2525#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000 2526#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11 2527#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000 2528#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12 2529#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000 2530#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13 2531#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000 2532#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14 2533#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000 2534#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15 2535#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000 2536#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16 2537#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000 2538#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17 2539#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000 2540#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18 2541#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000 2542#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19 2543#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000 2544#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a 2545#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000 2546#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b 2547#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000 2548#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c 2549#define SCLK_DEEP_SLEEP_CNTL__VCE_0_BUSY_MASK_MASK 0x20000000 2550#define SCLK_DEEP_SLEEP_CNTL__VCE_0_BUSY_MASK__SHIFT 0x1d 2551#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000 2552#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e 2553#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 2554#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f 2555#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1 2556#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0 2557#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2 2558#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1 2559#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4 2560#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2 2561#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8 2562#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3 2563#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10 2564#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4 2565#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40 2566#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6 2567#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80 2568#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7 2569#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100 2570#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8 2571#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200 2572#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9 2573#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400 2574#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa 2575#define SCLK_DEEP_SLEEP_CNTL2__VCE_0_CG_MC_STAT_BUSY_MASK_MASK 0x800 2576#define SCLK_DEEP_SLEEP_CNTL2__VCE_0_CG_MC_STAT_BUSY_MASK__SHIFT 0xb 2577#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_BUSY_MASK_MASK 0x200000 2578#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_BUSY_MASK__SHIFT 0x15 2579#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_CG_MC_STAT_BUSY_MASK_MASK 0x400000 2580#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_CG_MC_STAT_BUSY_MASK__SHIFT 0x16 2581#define SCLK_DEEP_SLEEP_CNTL2__REG_SCLK_DEEP_SLEEP_MASK_MASK 0x800000 2582#define SCLK_DEEP_SLEEP_CNTL2__REG_SCLK_DEEP_SLEEP_MASK__SHIFT 0x17 2583#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000 2584#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18 2585#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1 2586#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0 2587#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2 2588#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1 2589#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4 2590#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2 2591#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8 2592#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3 2593#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10 2594#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4 2595#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20 2596#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5 2597#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40 2598#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6 2599#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80 2600#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7 2601#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100 2602#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8 2603#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200 2604#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9 2605#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400 2606#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa 2607#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800 2608#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb 2609#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000 2610#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc 2611#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000 2612#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd 2613#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000 2614#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe 2615#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000 2616#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf 2617#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_SLAVE_SCLK_BUSY_MASK_MASK 0x10000 2618#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_SLAVE_SCLK_BUSY_MASK__SHIFT 0x10 2619#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_MASTER_SCLK_BUSY_MASK_MASK 0x20000 2620#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_MASTER_SCLK_BUSY_MASK__SHIFT 0x11 2621#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7 2622#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0 2623#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38 2624#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3 2625#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000 2626#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10 2627#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000 2628#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11 2629#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000 2630#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14 2631#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 2632#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 2633#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 2634#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 2635#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 2636#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 2637#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000 2638#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10 2639#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 2640#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f 2641#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1 2642#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0 2643#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2 2644#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1 2645#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4 2646#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2 2647#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8 2648#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3 2649#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10 2650#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4 2651#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20 2652#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5 2653#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40 2654#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6 2655#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80 2656#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7 2657#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100 2658#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8 2659#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200 2660#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9 2661#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400 2662#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa 2663#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800 2664#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb 2665#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000 2666#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc 2667#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000 2668#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd 2669#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000 2670#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe 2671#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000 2672#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf 2673#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000 2674#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10 2675#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000 2676#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11 2677#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000 2678#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12 2679#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000 2680#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13 2681#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000 2682#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14 2683#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE0_IDLE_MASK_MASK 0x200000 2684#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE0_IDLE_MASK__SHIFT 0x15 2685#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE1_IDLE_MASK_MASK 0x400000 2686#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE1_IDLE_MASK__SHIFT 0x16 2687#define LCLK_DEEP_SLEEP_CNTL2__L1IMUIOAGR_IDLE_MASK_MASK 0x800000 2688#define LCLK_DEEP_SLEEP_CNTL2__L1IMUIOAGR_IDLE_MASK__SHIFT 0x17 2689#define LCLK_DEEP_SLEEP_CNTL2__SPG_SMU_IDLE_MASK_MASK 0x1000000 2690#define LCLK_DEEP_SLEEP_CNTL2__SPG_SMU_IDLE_MASK__SHIFT 0x18 2691#define LCLK_DEEP_SLEEP_CNTL2__APG_SMU_IDLE_MASK_MASK 0x2000000 2692#define LCLK_DEEP_SLEEP_CNTL2__APG_SMU_IDLE_MASK__SHIFT 0x19 2693#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE0_MASK_MASK 0x4000000 2694#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE0_MASK__SHIFT 0x1a 2695#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE1_MASK_MASK 0x8000000 2696#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE1_MASK__SHIFT 0x1b 2697#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE2_MASK_MASK 0x10000000 2698#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE2_MASK__SHIFT 0x1c 2699#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE3_MASK_MASK 0x20000000 2700#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE3_MASK__SHIFT 0x1d 2701#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xc0000000 2702#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x1e 2703#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS_MASK 0x1 2704#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS__SHIFT 0x0 2705#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK 0x1fe 2706#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT 0x1 2707#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff 2708#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0 2709#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000 2710#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10 2711#define PWR_DC_RESP__RESPONSE_MASK 0x1 2712#define PWR_DC_RESP__RESPONSE__SHIFT 0x0 2713#define PWR_VCE_RESP__RESPONSE_MASK 0xffffffff 2714#define PWR_VCE_RESP__RESPONSE__SHIFT 0x0 2715#define PWR_UVD_RESP__RESPONSE_MASK 0xffffffff 2716#define PWR_UVD_RESP__RESPONSE__SHIFT 0x0 2717#define PWR_ACP_RESP__RESPONSE_MASK 0xffffffff 2718#define PWR_ACP_RESP__RESPONSE__SHIFT 0x0 2719#define PWR_DC_REQ__REQUEST_MASK 0x1 2720#define PWR_DC_REQ__REQUEST__SHIFT 0x0 2721#define SCLK_MIN_DIV__FRACV_MASK 0xfff 2722#define SCLK_MIN_DIV__FRACV__SHIFT 0x0 2723#define SCLK_MIN_DIV__INTV_MASK 0x7f000 2724#define SCLK_MIN_DIV__INTV__SHIFT 0xc 2725#define PCIE_PGFSM_CONFIG__FSM_ADDR_MASK 0xff 2726#define PCIE_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 2727#define PCIE_PGFSM_CONFIG__Power_Down_MASK 0x100 2728#define PCIE_PGFSM_CONFIG__Power_Down__SHIFT 0x8 2729#define PCIE_PGFSM_CONFIG__Power_Up_MASK 0x200 2730#define PCIE_PGFSM_CONFIG__Power_Up__SHIFT 0x9 2731#define PCIE_PGFSM_CONFIG__P1_Select_MASK 0x400 2732#define PCIE_PGFSM_CONFIG__P1_Select__SHIFT 0xa 2733#define PCIE_PGFSM_CONFIG__P2_Select_MASK 0x800 2734#define PCIE_PGFSM_CONFIG__P2_Select__SHIFT 0xb 2735#define PCIE_PGFSM_CONFIG__Write_Op_MASK 0x1000 2736#define PCIE_PGFSM_CONFIG__Write_Op__SHIFT 0xc 2737#define PCIE_PGFSM_CONFIG__Read_Op_MASK 0x2000 2738#define PCIE_PGFSM_CONFIG__Read_Op__SHIFT 0xd 2739#define PCIE_PGFSM_CONFIG__Reserved_MASK 0xfffc000 2740#define PCIE_PGFSM_CONFIG__Reserved__SHIFT 0xe 2741#define PCIE_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000 2742#define PCIE_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 2743#define PCIE_PGFSM_WRITE__Write_value_MASK 0xffffffff 2744#define PCIE_PGFSM_WRITE__Write_value__SHIFT 0x0 2745#define SERDES_BUSY__PCIE_SERDES_BUSY_MASK 0x1 2746#define SERDES_BUSY__PCIE_SERDES_BUSY__SHIFT 0x0 2747#define PCIE_PGFSM2_CONFIG__FSM_ADDR_MASK 0xff 2748#define PCIE_PGFSM2_CONFIG__FSM_ADDR__SHIFT 0x0 2749#define PCIE_PGFSM2_CONFIG__Power_Down_MASK 0x100 2750#define PCIE_PGFSM2_CONFIG__Power_Down__SHIFT 0x8 2751#define PCIE_PGFSM2_CONFIG__Power_Up_MASK 0x200 2752#define PCIE_PGFSM2_CONFIG__Power_Up__SHIFT 0x9 2753#define PCIE_PGFSM2_CONFIG__P1_Select_MASK 0x400 2754#define PCIE_PGFSM2_CONFIG__P1_Select__SHIFT 0xa 2755#define PCIE_PGFSM2_CONFIG__P2_Select_MASK 0x800 2756#define PCIE_PGFSM2_CONFIG__P2_Select__SHIFT 0xb 2757#define PCIE_PGFSM2_CONFIG__Write_Op_MASK 0x1000 2758#define PCIE_PGFSM2_CONFIG__Write_Op__SHIFT 0xc 2759#define PCIE_PGFSM2_CONFIG__Read_Op_MASK 0x2000 2760#define PCIE_PGFSM2_CONFIG__Read_Op__SHIFT 0xd 2761#define PCIE_PGFSM2_CONFIG__Reserved_MASK 0xfffc000 2762#define PCIE_PGFSM2_CONFIG__Reserved__SHIFT 0xe 2763#define PCIE_PGFSM2_CONFIG__REG_ADDR_MASK 0xf0000000 2764#define PCIE_PGFSM2_CONFIG__REG_ADDR__SHIFT 0x1c 2765#define PCIE_PGFSM2_WRITE__Write_value_MASK 0xffffffff 2766#define PCIE_PGFSM2_WRITE__Write_value__SHIFT 0x0 2767#define SERDES2_BUSY__PCIE_SERDES_BUSY_MASK 0x1 2768#define SERDES2_BUSY__PCIE_SERDES_BUSY__SHIFT 0x0 2769#define PCIE_PGFSM_0_READ__Read_value_MASK 0xffffff 2770#define PCIE_PGFSM_0_READ__Read_value__SHIFT 0x0 2771#define PCIE_PGFSM_0_READ__Read_valid_MASK 0x1000000 2772#define PCIE_PGFSM_0_READ__Read_valid__SHIFT 0x18 2773#define PCIE_PGFSM_1_READ__Read_value_MASK 0xffffff 2774#define PCIE_PGFSM_1_READ__Read_value__SHIFT 0x0 2775#define PCIE_PGFSM_1_READ__Read_valid_MASK 0x1000000 2776#define PCIE_PGFSM_1_READ__Read_valid__SHIFT 0x18 2777#define PWR_ACPI_INTERRUPT__BIF_CG_req_MASK 0x1 2778#define PWR_ACPI_INTERRUPT__BIF_CG_req__SHIFT 0x0 2779#define PWR_ACPI_INTERRUPT__AZ_CG_req_MASK 0x2 2780#define PWR_ACPI_INTERRUPT__AZ_CG_req__SHIFT 0x1 2781#define PWR_ACPI_INTERRUPT__AZ_CG_resp_MASK 0x4 2782#define PWR_ACPI_INTERRUPT__AZ_CG_resp__SHIFT 0x2 2783#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_MASK 0xffff 2784#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD__SHIFT 0x0 2785#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT_MASK 0xf0000 2786#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT__SHIFT 0x10 2787#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN_MASK 0x1 2788#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN__SHIFT 0x0 2789#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT_MASK 0x2 2790#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT__SHIFT 0x1 2791#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT_MASK 0x4 2792#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT__SHIFT 0x2 2793#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE_MASK 0x8 2794#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE__SHIFT 0x3 2795#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ_MASK 0x1 2796#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ__SHIFT 0x0 2797#define REG_SCLK_DEEP_SLEEP_EXIT__REG_sclk_deep_sleep_exit_MASK 0x1 2798#define REG_SCLK_DEEP_SLEEP_EXIT__REG_sclk_deep_sleep_exit__SHIFT 0x0 2799#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG4_MASK 0xffff 2800#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG4__SHIFT 0x0 2801#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG5_MASK 0xffff0000 2802#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG5__SHIFT 0x10 2803#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1 2804#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0 2805#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe 2806#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1 2807#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000 2808#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11 2809#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000 2810#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16 2811#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff 2812#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0 2813#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff 2814#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0 2815#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1 2816#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0 2817#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe 2818#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1 2819#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000 2820#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11 2821#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000 2822#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16 2823#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff 2824#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0 2825#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff 2826#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0 2827#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1 2828#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0 2829#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe 2830#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1 2831#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000 2832#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11 2833#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000 2834#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16 2835#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff 2836#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0 2837#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff 2838#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0 2839#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1 2840#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0 2841#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe 2842#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1 2843#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000 2844#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11 2845#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000 2846#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16 2847#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff 2848#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0 2849#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff 2850#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0 2851#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1 2852#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0 2853#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe 2854#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1 2855#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000 2856#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11 2857#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000 2858#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16 2859#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff 2860#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0 2861#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff 2862#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0 2863#define MISC_UNB_PWRMGT_CFG0__TARGET_ADDR_MASK 0xffffffff 2864#define MISC_UNB_PWRMGT_CFG0__TARGET_ADDR__SHIFT 0x0 2865#define MISC_UNB_PWRMGT_CFG1__TIMER_EN_MASK 0x1 2866#define MISC_UNB_PWRMGT_CFG1__TIMER_EN__SHIFT 0x0 2867#define MISC_UNB_PWRMGT_CFG1__TIMER_INTERVAL_MASK 0x1fffe 2868#define MISC_UNB_PWRMGT_CFG1__TIMER_INTERVAL__SHIFT 0x1 2869#define MISC_UNB_PWRMGT_CFG1__INT_GEN_EN_MASK 0x20000 2870#define MISC_UNB_PWRMGT_CFG1__INT_GEN_EN__SHIFT 0x11 2871#define MISC_UNB_PWRMGT_DATA__NB_CROSS_TRIGGER_MASK 0xf 2872#define MISC_UNB_PWRMGT_DATA__NB_CROSS_TRIGGER__SHIFT 0x0 2873#define MISC_UNB_PWRMGT_DATA__NB_PRE_SELF_REFRESH_MASK 0x10 2874#define MISC_UNB_PWRMGT_DATA__NB_PRE_SELF_REFRESH__SHIFT 0x4 2875#define MISC_UNB_PWRMGT_DATA__NB_REQ_NB_PSTATE_MASK 0x20 2876#define MISC_UNB_PWRMGT_DATA__NB_REQ_NB_PSTATE__SHIFT 0x5 2877#define MISC_UNB_PWRMGT_DATA__NB_FLUSH_ACK_TOGGLE_MASK 0x40 2878#define MISC_UNB_PWRMGT_DATA__NB_FLUSH_ACK_TOGGLE__SHIFT 0x6 2879#define MISC_UNB_PWRMGT_DATA__NB_ON_INB_WAKE_ACK_MASK 0x80 2880#define MISC_UNB_PWRMGT_DATA__NB_ON_INB_WAKE_ACK__SHIFT 0x7 2881#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH0LINK_WAKE_ACK_MASK 0x100 2882#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH0LINK_WAKE_ACK__SHIFT 0x8 2883#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH1LINK_WAKE_ACK_MASK 0x200 2884#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH1LINK_WAKE_ACK__SHIFT 0x9 2885#define GNBPM_SMU_PWRMGT_DATA__UNBPM_AllCpusInCC6_MASK 0x1 2886#define GNBPM_SMU_PWRMGT_DATA__UNBPM_AllCpusInCC6__SHIFT 0x0 2887#define GNBPM_SMU_PWRMGT_DATA__UNBPM_HtcActive_MASK 0x2 2888#define GNBPM_SMU_PWRMGT_DATA__UNBPM_HtcActive__SHIFT 0x1 2889#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SmuInt_MASK 0x4 2890#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SmuInt__SHIFT 0x2 2891#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SPARE_MASK 0xf8 2892#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SPARE__SHIFT 0x3 2893#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_EN_MASK 0x1 2894#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_EN__SHIFT 0x0 2895#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_PERIOD_MASK 0x1fffe 2896#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_PERIOD__SHIFT 0x1 2897#define DMA_ACTIVE_SAMPLER_CFG__DMA_ACTIVE_TRANS_CNT_MASK 0x60000 2898#define DMA_ACTIVE_SAMPLER_CFG__DMA_ACTIVE_TRANS_CNT__SHIFT 0x11 2899#define SOUTHBRIDGE_TYPE__DISCRETE_SB_MASK 0x1 2900#define SOUTHBRIDGE_TYPE__DISCRETE_SB__SHIFT 0x0 2901#define GNBPM_SMU_PWRMGT_STATUS__PM_AllCpusInCC6_MASK 0x1 2902#define GNBPM_SMU_PWRMGT_STATUS__PM_AllCpusInCC6__SHIFT 0x0 2903#define GNBPM_SMU_PWRMGT_STATUS__PM_HtcActive_MASK 0x2 2904#define GNBPM_SMU_PWRMGT_STATUS__PM_HtcActive__SHIFT 0x1 2905#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuInt_MASK 0x4 2906#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuInt__SHIFT 0x2 2907#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuIntSuperVminExit_MASK 0x8 2908#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuIntSuperVminExit__SHIFT 0x3 2909#define GNBPM_SMU_PWRMGT_STATUS__PM_PreSelfRefresh_MASK 0x10 2910#define GNBPM_SMU_PWRMGT_STATUS__PM_PreSelfRefresh__SHIFT 0x4 2911#define GNBPM_SMU_PWRMGT_STATUS__PM_ReqNbPstate_MASK 0x20 2912#define GNBPM_SMU_PWRMGT_STATUS__PM_ReqNbPstate__SHIFT 0x5 2913#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowNbPstate_MASK 0x40 2914#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowNbPstate__SHIFT 0x6 2915#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowSelfRefresh_MASK 0x80 2916#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowSelfRefresh__SHIFT 0x7 2917#define GNBPM_SMU_PWRMGT_STATUS__PM_IntrWake_MASK 0x100 2918#define GNBPM_SMU_PWRMGT_STATUS__PM_IntrWake__SHIFT 0x8 2919#define GNBPM_SMU_PWRMGT_STATUS__SPARE_MASK 0xfe00 2920#define GNBPM_SMU_PWRMGT_STATUS__SPARE__SHIFT 0x9 2921#define ALLOW_SR_INTR_CTRL__ALLOW_SR_INTR_CTRL_MASK 0x3 2922#define ALLOW_SR_INTR_CTRL__ALLOW_SR_INTR_CTRL__SHIFT 0x0 2923#define GC_CAC_LKG_AGGR_LOWER__LKG_AGGR_31_0_MASK 0xffffffff 2924#define GC_CAC_LKG_AGGR_LOWER__LKG_AGGR_31_0__SHIFT 0x0 2925#define GC_CAC_LKG_AGGR_UPPER__LKG_AGGR_63_32_MASK 0xffffffff 2926#define GC_CAC_LKG_AGGR_UPPER__LKG_AGGR_63_32__SHIFT 0x0 2927#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0xffff 2928#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0 2929#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1_MASK 0xffff0000 2930#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1__SHIFT 0x10 2931#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2_MASK 0xffff 2932#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2__SHIFT 0x0 2933#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3_MASK 0xffff0000 2934#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3__SHIFT 0x10 2935#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4_MASK 0xffff 2936#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4__SHIFT 0x0 2937#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5_MASK 0xffff0000 2938#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5__SHIFT 0x10 2939#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6_MASK 0xffff 2940#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6__SHIFT 0x0 2941#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7_MASK 0xffff0000 2942#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7__SHIFT 0x10 2943#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xffffffff 2944#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0 2945#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xffffffff 2946#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x0 2947#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xffffffff 2948#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x0 2949#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xffffffff 2950#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x0 2951#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xffffffff 2952#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x0 2953#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK 0xffffffff 2954#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT 0x0 2955#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK 0xffffffff 2956#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT 0x0 2957#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK 0xffffffff 2958#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT 0x0 2959#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0xffff 2960#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0 2961#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0xffff0000 2962#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x10 2963 2964#endif /* SMU_8_0_SH_MASK_H */
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