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smu_8_0_d.h
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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_d.h
1/* 2 * SMU_8_0 Register documentation 3 * 4 * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24#ifndef SMU_8_0_D_H 25#define SMU_8_0_D_H 26 27#define ixTHM_TCON_CSR_CONFIG 0xd82014a4 28#define ixTHM_TCON_CSR_DATA 0xd82014a8 29#define ixTHM_TCON_HTC 0xd8200c64 30#define ixTHM_TCON_CUR_TMP 0xd8200ca4 31#define ixTHM_TCON_THERM_TRIP 0xd8200ce4 32#define ixTHM_GPIO_PROCHOT_CTRL 0xd8200d00 33#define ixTHM_GPIO_THERMTRIP_CTRL 0xd8200d04 34#define ixTHM_THERMAL_INT_ENA 0xd8200d10 35#define ixTHM_THERMAL_INT_CTRL 0xd8200d14 36#define ixTHM_THERMAL_INT_STATUS 0xd8200d18 37#define ixTMON0_RDIL0_DATA 0xd8202000 38#define ixTMON0_RDIL1_DATA 0xd8202004 39#define ixTMON0_RDIL2_DATA 0xd8202008 40#define ixTMON0_RDIL3_DATA 0xd820200c 41#define ixTMON0_RDIL4_DATA 0xd8202010 42#define ixTMON0_RDIL5_DATA 0xd8202014 43#define ixTMON0_RDIL6_DATA 0xd8202018 44#define ixTMON0_RDIL7_DATA 0xd820201c 45#define ixTMON0_RDIL8_DATA 0xd8202020 46#define ixTMON0_RDIL9_DATA 0xd8202024 47#define ixTMON0_RDIL10_DATA 0xd8202028 48#define ixTMON0_RDIL11_DATA 0xd820202c 49#define ixTMON0_RDIL12_DATA 0xd8202030 50#define ixTMON0_RDIL13_DATA 0xd8202034 51#define ixTMON0_RDIL14_DATA 0xd8202038 52#define ixTMON0_RDIL15_DATA 0xd820203c 53#define ixTMON0_RDIR0_DATA 0xd8202040 54#define ixTMON0_RDIR1_DATA 0xd8202044 55#define ixTMON0_RDIR2_DATA 0xd8202048 56#define ixTMON0_RDIR3_DATA 0xd820204c 57#define ixTMON0_RDIR4_DATA 0xd8202050 58#define ixTMON0_RDIR5_DATA 0xd8202054 59#define ixTMON0_RDIR6_DATA 0xd8202058 60#define ixTMON0_RDIR7_DATA 0xd820205c 61#define ixTMON0_RDIR8_DATA 0xd8202060 62#define ixTMON0_RDIR9_DATA 0xd8202064 63#define ixTMON0_RDIR10_DATA 0xd8202068 64#define ixTMON0_RDIR11_DATA 0xd820206c 65#define ixTMON0_RDIR12_DATA 0xd8202070 66#define ixTMON0_RDIR13_DATA 0xd8202074 67#define ixTMON0_RDIR14_DATA 0xd8202078 68#define ixTMON0_RDIR15_DATA 0xd820207c 69#define ixTMON0_INT_DATA 0xd8202080 70#define ixTMON0_RDIL_PRESENT0 0xd8202084 71#define ixTMON0_RDIL_PRESENT1 0xd8202088 72#define ixTMON0_RDIR_PRESENT0 0xd820208c 73#define ixTMON0_RDIR_PRESENT1 0xd8202090 74#define ixTMON0_CONFIG 0xd8202098 75#define ixTMON0_TEMP_CALC_COEFF0 0xd82020a0 76#define ixTMON0_TEMP_CALC_COEFF1 0xd82020a4 77#define ixTMON0_TEMP_CALC_COEFF2 0xd82020a8 78#define ixTMON0_TEMP_CALC_COEFF3 0xd82020ac 79#define ixTMON0_TEMP_CALC_COEFF4 0xd82020b0 80#define ixTMON0_DEBUG0 0xd82020b4 81#define ixTMON0_DEBUG1 0xd82020b8 82#define ixTMON1_RDIL0_DATA 0xd8202100 83#define ixTMON1_RDIL1_DATA 0xd8202104 84#define ixTMON1_RDIL2_DATA 0xd8202108 85#define ixTMON1_RDIL3_DATA 0xd820210c 86#define ixTMON1_RDIL4_DATA 0xd8202110 87#define ixTMON1_RDIL5_DATA 0xd8202114 88#define ixTMON1_RDIL6_DATA 0xd8202118 89#define ixTMON1_RDIL7_DATA 0xd820211c 90#define ixTMON1_RDIL8_DATA 0xd8202120 91#define ixTMON1_RDIL9_DATA 0xd8202124 92#define ixTMON1_RDIL10_DATA 0xd8202128 93#define ixTMON1_RDIL11_DATA 0xd820212c 94#define ixTMON1_RDIL12_DATA 0xd8202130 95#define ixTMON1_RDIL13_DATA 0xd8202134 96#define ixTMON1_RDIL14_DATA 0xd8202138 97#define ixTMON1_RDIL15_DATA 0xd820213c 98#define ixTMON1_RDIR0_DATA 0xd8202140 99#define ixTMON1_RDIR1_DATA 0xd8202144 100#define ixTMON1_RDIR2_DATA 0xd8202148 101#define ixTMON1_RDIR3_DATA 0xd820214c 102#define ixTMON1_RDIR4_DATA 0xd8202150 103#define ixTMON1_RDIR5_DATA 0xd8202154 104#define ixTMON1_RDIR6_DATA 0xd8202158 105#define ixTMON1_RDIR7_DATA 0xd820215c 106#define ixTMON1_RDIR8_DATA 0xd8202160 107#define ixTMON1_RDIR9_DATA 0xd8202164 108#define ixTMON1_RDIR10_DATA 0xd8202168 109#define ixTMON1_RDIR11_DATA 0xd820216c 110#define ixTMON1_RDIR12_DATA 0xd8202170 111#define ixTMON1_RDIR13_DATA 0xd8202174 112#define ixTMON1_RDIR14_DATA 0xd8202178 113#define ixTMON1_RDIR15_DATA 0xd820217c 114#define ixTMON1_INT_DATA 0xd8202180 115#define ixTMON1_RDIL_PRESENT0 0xd8202184 116#define ixTMON1_RDIL_PRESENT1 0xd8202188 117#define ixTMON1_RDIR_PRESENT0 0xd820218c 118#define ixTMON1_RDIR_PRESENT1 0xd8202190 119#define ixTMON1_CONFIG 0xd8202198 120#define ixTMON1_TEMP_CALC_COEFF0 0xd82021a0 121#define ixTMON1_TEMP_CALC_COEFF1 0xd82021a4 122#define ixTMON1_TEMP_CALC_COEFF2 0xd82021a8 123#define ixTMON1_TEMP_CALC_COEFF3 0xd82021ac 124#define ixTMON1_TEMP_CALC_COEFF4 0xd82021b0 125#define ixTMON1_DEBUG0 0xd82021b4 126#define ixTMON1_DEBUG1 0xd82021b8 127#define ixTHM_TMON0_REMOTE_START 0xd8202800 128#define ixTHM_TMON0_REMOTE_END 0xd82028fc 129#define ixTHM_TMON1_REMOTE_START 0xd8202900 130#define ixTHM_TMON1_REMOTE_END 0xd82029fc 131#define ixTHM_TCON_LOCAL0 0xd8202e00 132#define ixTHM_TCON_LOCAL1 0xd8202e04 133#define ixTHM_TCON_LOCAL2 0xd8202e08 134#define ixTHM_TCON_LOCAL3 0xd8202e0c 135#define ixTHM_TCON_LOCAL4 0xd8202e10 136#define ixTHM_TCON_LOCAL5 0xd8202e14 137#define ixTHM_TCON_LOCAL6 0xd8202e18 138#define ixTHM_TCON_LOCAL7 0xd8202e1c 139#define ixTHM_TCON_LOCAL8 0xd8202e20 140#define ixTHM_TCON_LOCAL9 0xd8202e24 141#define ixTHM_TCON_LOCAL10 0xd8202e28 142#define ixTHM_TCON_LOCAL11 0xd8202e2c 143#define ixTHM_TCON_LOCAL12 0xd8202e30 144#define ixTHM_TCON_LOCAL13 0xd8202ef8 145#define ixTHM_TCON_LOCAL14 0xd8202efc 146#define ixTHM_FUSE0 0xd8210000 147#define ixTHM_FUSE1 0xd8210004 148#define ixTHM_FUSE2 0xd8210008 149#define ixTHM_FUSE3 0xd821000c 150#define ixTHM_FUSE4 0xd8210010 151#define ixTHM_FUSE5 0xd8210014 152#define ixTHM_FUSE6 0xd8210018 153#define ixTHM_FUSE7 0xd821001c 154#define ixTHM_FUSE8 0xd8210020 155#define ixTHM_FUSE9 0xd8210024 156#define ixTHM_FUSE10 0xd8210028 157#define ixTHM_FUSE11 0xd821002c 158#define ixTHM_FUSE12 0xd8210030 159#define mmMP0PUB_IND_INDEX 0x180 160#define mmMP_SMUIF0_MP0PUB_IND_INDEX 0x180 161#define mmMP_SMUIF1_MP0PUB_IND_INDEX 0x182 162#define mmMP_SMUIF2_MP0PUB_IND_INDEX 0x184 163#define mmMP_SMUIF3_MP0PUB_IND_INDEX 0x186 164#define mmMP_SMUIF4_MP0PUB_IND_INDEX 0x188 165#define mmMP_SMUIF5_MP0PUB_IND_INDEX 0x18a 166#define mmMP_SMUIF6_MP0PUB_IND_INDEX 0x18c 167#define mmMP_SMUIF7_MP0PUB_IND_INDEX 0x18e 168#define mmMP_SMUIF8_MP0PUB_IND_INDEX 0x190 169#define mmMP_SMUIF9_MP0PUB_IND_INDEX 0x192 170#define mmMP_SMUIF10_MP0PUB_IND_INDEX 0x194 171#define mmMP_SMUIF11_MP0PUB_IND_INDEX 0x196 172#define mmMP_SMUIF12_MP0PUB_IND_INDEX 0x198 173#define mmMP_SMUIF13_MP0PUB_IND_INDEX 0x19a 174#define mmMP_SMUIF14_MP0PUB_IND_INDEX 0x19c 175#define mmMP_SMUIF15_MP0PUB_IND_INDEX 0x19e 176#define mmMP0PUB_IND_DATA 0x181 177#define mmMP_SMUIF0_MP0PUB_IND_DATA 0x181 178#define mmMP_SMUIF1_MP0PUB_IND_DATA 0x183 179#define mmMP_SMUIF2_MP0PUB_IND_DATA 0x185 180#define mmMP_SMUIF3_MP0PUB_IND_DATA 0x187 181#define mmMP_SMUIF4_MP0PUB_IND_DATA 0x189 182#define mmMP_SMUIF5_MP0PUB_IND_DATA 0x18b 183#define mmMP_SMUIF6_MP0PUB_IND_DATA 0x18d 184#define mmMP_SMUIF7_MP0PUB_IND_DATA 0x18f 185#define mmMP_SMUIF8_MP0PUB_IND_DATA 0x191 186#define mmMP_SMUIF9_MP0PUB_IND_DATA 0x193 187#define mmMP_SMUIF10_MP0PUB_IND_DATA 0x195 188#define mmMP_SMUIF11_MP0PUB_IND_DATA 0x197 189#define mmMP_SMUIF12_MP0PUB_IND_DATA 0x199 190#define mmMP_SMUIF13_MP0PUB_IND_DATA 0x19b 191#define mmMP_SMUIF14_MP0PUB_IND_DATA 0x19d 192#define mmMP_SMUIF15_MP0PUB_IND_DATA 0x19f 193#define mmMP0PUB_IND_INDEX_0 0x180 194#define mmMP0PUB_IND_DATA_0 0x181 195#define mmMP0PUB_IND_INDEX_1 0x182 196#define mmMP0PUB_IND_DATA_1 0x183 197#define mmMP0PUB_IND_INDEX_2 0x184 198#define mmMP0PUB_IND_DATA_2 0x185 199#define mmMP0PUB_IND_INDEX_3 0x186 200#define mmMP0PUB_IND_DATA_3 0x187 201#define mmMP0PUB_IND_INDEX_4 0x188 202#define mmMP0PUB_IND_DATA_4 0x189 203#define mmMP0PUB_IND_INDEX_5 0x18a 204#define mmMP0PUB_IND_DATA_5 0x18b 205#define mmMP0PUB_IND_INDEX_6 0x18c 206#define mmMP0PUB_IND_DATA_6 0x18d 207#define mmMP0PUB_IND_INDEX_7 0x18e 208#define mmMP0PUB_IND_DATA_7 0x18f 209#define mmMP0PUB_IND_INDEX_8 0x190 210#define mmMP0PUB_IND_DATA_8 0x191 211#define mmMP0PUB_IND_INDEX_9 0x192 212#define mmMP0PUB_IND_DATA_9 0x193 213#define mmMP0PUB_IND_INDEX_10 0x194 214#define mmMP0PUB_IND_DATA_10 0x195 215#define mmMP0PUB_IND_INDEX_11 0x196 216#define mmMP0PUB_IND_DATA_11 0x197 217#define mmMP0PUB_IND_INDEX_12 0x198 218#define mmMP0PUB_IND_DATA_12 0x199 219#define mmMP0PUB_IND_INDEX_13 0x19a 220#define mmMP0PUB_IND_DATA_13 0x19b 221#define mmMP0PUB_IND_INDEX_14 0x19c 222#define mmMP0PUB_IND_DATA_14 0x19d 223#define mmMP0PUB_IND_INDEX_15 0x19e 224#define mmMP0PUB_IND_DATA_15 0x19f 225#define mmMP0_IND_ACCESS_CNTL 0x1a0 226#define mmMP0_MSP_MESSAGE_0 0x1a1 227#define mmMP0_MSP_MESSAGE_1 0x1a2 228#define mmMP0_MSP_MESSAGE_2 0x1a3 229#define mmMP0_MSP_MESSAGE_3 0x1a4 230#define mmMP0_MSP_MESSAGE_4 0x1a5 231#define mmMP0_MSP_MESSAGE_5 0x1a6 232#define mmMP0_MSP_MESSAGE_6 0x1a7 233#define mmMP0_MSP_MESSAGE_7 0x1a8 234#define mmSAM_IH_EXT_ERR_INTR 0x1a9 235#define mmSAM_IH_EXT_ERR_INTR_STATUS 0x1aa 236#define mmMP0_DISP_TIMER0_CTRL0 0x1ab 237#define mmMP0_DISP_TIMER0_CTRL1 0x1ac 238#define mmMP0_DISP_TIMER0_CMP_AUTOINC 0x1ad 239#define mmMP0_DISP_TIMER0_INTEN 0x1ae 240#define mmMP0_DISP_TIMER0_OCMP_0_0 0x1af 241#define mmMP0_DISP_TIMER0_OCMP_0_1 0x1b0 242#define mmMP0_DISP_TIMER0_CNT 0x1b1 243#define mmMP0_DISP_TIMER1_CTRL0 0x1b2 244#define mmMP0_DISP_TIMER1_CTRL1 0x1b3 245#define mmMP0_DISP_TIMER1_CMP_AUTOINC 0x1b4 246#define mmMP0_DISP_TIMER1_INTEN 0x1b5 247#define mmMP0_DISP_TIMER1_OCMP_0_0 0x1b6 248#define mmMP0_DISP_TIMER1_OCMP_0_1 0x1b7 249#define mmMP0_DISP_TIMER1_CNT 0x1b8 250#define mmSMU_MP1_SRBM2P_MSG_0 0x1c0 251#define mmSMU_MP1_SRBM2P_MSG_1 0x1c1 252#define mmSMU_MP1_SRBM2P_MSG_2 0x1c2 253#define mmSMU_MP1_SRBM2P_MSG_3 0x1c3 254#define mmSMU_MP1_SRBM2P_MSG_4 0x1c4 255#define mmSMU_MP1_SRBM2P_MSG_5 0x1c5 256#define mmSMU_MP1_SRBM2P_MSG_6 0x1c6 257#define mmSMU_MP1_SRBM2P_MSG_7 0x1c7 258#define mmSMU_MP1_SRBM2P_MSG_8 0x1c8 259#define mmSMU_MP1_SRBM2P_MSG_9 0x1c9 260#define mmSMU_MP1_SRBM2P_MSG_10 0x1ca 261#define mmSMU_MP1_SRBM2P_MSG_11 0x1cb 262#define mmSMU_MP1_SRBM2P_MSG_12 0x1cc 263#define mmSMU_MP1_SRBM2P_MSG_13 0x1cd 264#define mmSMU_MP1_SRBM2P_MSG_14 0x1ce 265#define mmSMU_MP1_SRBM2P_MSG_15 0x1cf 266#define mmSMU_MP1_SRBM2P_RESP_0 0x1d0 267#define mmSMU_MP1_SRBM2P_RESP_1 0x1d1 268#define mmSMU_MP1_SRBM2P_RESP_2 0x1d2 269#define mmSMU_MP1_SRBM2P_RESP_3 0x1d3 270#define mmSMU_MP1_SRBM2P_RESP_4 0x1d4 271#define mmSMU_MP1_SRBM2P_RESP_5 0x1d5 272#define mmSMU_MP1_SRBM2P_RESP_6 0x1d6 273#define mmSMU_MP1_SRBM2P_RESP_7 0x1d7 274#define mmSMU_MP1_SRBM2P_RESP_8 0x1d8 275#define mmSMU_MP1_SRBM2P_RESP_9 0x1d9 276#define mmSMU_MP1_SRBM2P_RESP_10 0x1da 277#define mmSMU_MP1_SRBM2P_RESP_11 0x1db 278#define mmSMU_MP1_SRBM2P_RESP_12 0x1dc 279#define mmSMU_MP1_SRBM2P_RESP_13 0x1dd 280#define mmSMU_MP1_SRBM2P_RESP_14 0x1de 281#define mmSMU_MP1_SRBM2P_RESP_15 0x1df 282#define mmSMU_MP1_SRBM2P_ARG_0 0x1e0 283#define mmSMU_MP1_SRBM2P_ARG_1 0x1e1 284#define mmSMU_MP1_SRBM2P_ARG_2 0x1e2 285#define mmSMU_MP1_SRBM2P_ARG_3 0x1e3 286#define mmSMU_MP1_SRBM2P_ARG_4 0x1e4 287#define mmSMU_MP1_SRBM2P_ARG_5 0x1e5 288#define mmSMU_MP1_SRBM2P_ARG_6 0x1e6 289#define mmSMU_MP1_SRBM2P_ARG_7 0x1e7 290#define mmSMU_MP1_SRBM2P_ARG_8 0x1e8 291#define mmSMU_MP1_SRBM2P_ARG_9 0x1e9 292#define mmSMU_MP1_SRBM2P_ARG_10 0x1ea 293#define mmSMU_MP1_SRBM2P_ARG_11 0x1eb 294#define mmSMU_MP1_SRBM2P_ARG_12 0x1ec 295#define mmSMU_MP1_SRBM2P_ARG_13 0x1ed 296#define mmSMU_MP1_SRBM2P_ARG_14 0x1ee 297#define mmSMU_MP1_SRBM2P_ARG_15 0x1ef 298#define mmSMU_MP1_ACP2MP_RESP 0x1f0 299#define mmSMU_MP1_DC2MP_RESP 0x1f1 300#define mmSMU_MP1_UVD2MP_RESP 0x1f2 301#define mmSMU_MP1_VCE2MP_RESP 0x1f3 302#define mmSMU_MP1_RLC2MP_RESP 0x1f4 303#define mmMP_FPS_CNT 0x1f5 304#define mmSMU_DISP0_TIMER_INT_CONTROL 0x1f6 305#define mmSMU_DISP1_TIMER_INT_CONTROL 0x1f7 306#define mmSMU_SRBM_CONFIG 0x1f8 307#define ixMP_FPS_CNT_XBAR 0xcf200800 308#define ixMP_SRBM_CONFIG_XBAR 0xcf200804 309#define ixMP_SRBM_CONTROL 0xcf200c00 310#define ixMP_SRBM_ACCVIO_LOG 0xcf200c04 311#define ixMP_SRBM_ACCVIO_ADDR 0xcf200c08 312#define ixMP_CRBBM_CONTROL 0xcf200c0c 313#define ixMP_CRBBM_ACCVIO_LOG 0xcf200c10 314#define ixMP_CRBBM_ACCVIO_ADDR 0xcf200c14 315#define ixMP_DRAM_CNTL_WRREQ_CNTL 0xcf200000 316#define ixMP_DRAM_CNTL_WRREQ_CNTL_1 0xcf200004 317#define ixMP_DRAM_CNTL_WRREQ_LOW_ADDR 0xcf200008 318#define ixMP_DRAM_CNTL_WRREQ_HIGH_ADDR 0xcf20000c 319#define ixMP_DRAM_CNTL_WRREQ_MASK 0xcf200010 320#define ixMP_DRAM_CNTL_WRREQ_DATA_0 0xcf200014 321#define ixMP_DRAM_CNTL_WRREQ_DATA_1 0xcf200018 322#define ixMP_DRAM_CNTL_WRREQ_DATA_2 0xcf20001c 323#define ixMP_DRAM_CNTL_WRREQ_DATA_3 0xcf200020 324#define ixMP_DRAM_CNTL_WRREQ_DATA_4 0xcf200024 325#define ixMP_DRAM_CNTL_WRREQ_DATA_5 0xcf200028 326#define ixMP_DRAM_CNTL_WRREQ_DATA_6 0xcf20002c 327#define ixMP_DRAM_CNTL_WRREQ_DATA_7 0xcf200030 328#define ixMP_DRAM_CNTL_WRREQ_STATUS 0xcf200038 329#define ixMP_DRAM_CNTL_WRRET_STATUS_0 0xcf20003c 330#define ixMP_DRAM_CNTL_RDREQ_ADDR 0xcf200040 331#define ixMP_DRAM_CNTL_RDREQ_CNTL 0xcf200044 332#define ixMP_DRAM_CNTL_RDREQ_CNTL_1 0xcf200048 333#define ixMP_DRAM_CNTL_RDRET_VALID 0xcf20004c 334#define ixMP_DRAM_CNTL_RDRET_NACK 0xcf200050 335#define ixMP_DRAM_CNTL_RDRET_DATA_0 0xcf200054 336#define ixMP_DRAM_CNTL_RDRET_DATA_1 0xcf200058 337#define ixMP_DRAM_CNTL_RDRET_DATA_2 0xcf20005c 338#define ixMP_DRAM_CNTL_RDRET_DATA_3 0xcf200060 339#define ixMP_DRAM_CNTL_RDRET_DATA_4 0xcf200064 340#define ixMP_DRAM_CNTL_RDRET_DATA_5 0xcf200068 341#define ixMP_DRAM_CNTL_RDRET_DATA_6 0xcf20006c 342#define ixMP_DRAM_CNTL_RDRET_DATA_7 0xcf200070 343#define ixMP_DRAM_CNTL_RDRET_DATA_8 0xcf200074 344#define ixMP_DRAM_CNTL_RDRET_DATA_9 0xcf200078 345#define ixMP_DRAM_CNTL_RDRET_DATA_10 0xcf20007c 346#define ixMP_DRAM_CNTL_RDRET_DATA_11 0xcf200080 347#define ixMP_DRAM_CNTL_RDRET_DATA_12 0xcf200084 348#define ixMP_DRAM_CNTL_RDRET_DATA_13 0xcf200088 349#define ixMP_DRAM_CNTL_RDRET_DATA_14 0xcf20008c 350#define ixMP_DRAM_CNTL_RDRET_DATA_15 0xcf200090 351#define ixMP_DRAM_CNTL_RDRET_DATA_16 0xcf200094 352#define ixMP_DRAM_CNTL_RDRET_DATA_17 0xcf200098 353#define ixMP_DRAM_CNTL_RDRET_DATA_18 0xcf20009c 354#define ixMP_DRAM_CNTL_RDRET_DATA_19 0xcf2000a0 355#define ixMP_DRAM_CNTL_RDRET_DATA_20 0xcf2000a4 356#define ixMP_DRAM_CNTL_RDRET_DATA_21 0xcf2000a8 357#define ixMP_DRAM_CNTL_RDRET_DATA_22 0xcf2000ac 358#define ixMP_DRAM_CNTL_RDRET_DATA_23 0xcf2000b0 359#define ixMP_DRAM_CNTL_RDRET_DATA_24 0xcf2000b4 360#define ixMP_DRAM_CNTL_RDRET_DATA_25 0xcf2000b8 361#define ixMP_DRAM_CNTL_RDRET_DATA_26 0xcf2000bc 362#define ixMP_DRAM_CNTL_RDRET_DATA_27 0xcf2000c0 363#define ixMP_DRAM_CNTL_RDRET_DATA_28 0xcf2000c4 364#define ixMP_DRAM_CNTL_RDRET_DATA_29 0xcf2000c8 365#define ixMP_DRAM_CNTL_RDRET_DATA_30 0xcf2000cc 366#define ixMP_DRAM_CNTL_RDRET_DATA_31 0xcf2000d0 367#define ixMP_DRAM_CNTL_RDRET_DATA_32 0xcf2000d4 368#define ixMP_DRAM_CNTL_RDRET_DATA_33 0xcf2000d8 369#define ixMP_DRAM_CNTL_RDRET_DATA_34 0xcf2000dc 370#define ixMP_DRAM_CNTL_RDRET_DATA_35 0xcf2000e0 371#define ixMP_DRAM_CNTL_RDRET_DATA_36 0xcf2000e4 372#define ixMP_DRAM_CNTL_RDRET_DATA_37 0xcf2000e8 373#define ixMP_DRAM_CNTL_RDRET_DATA_38 0xcf2000ec 374#define ixMP_DRAM_CNTL_RDRET_DATA_39 0xcf2000f0 375#define ixMP_DRAM_CNTL_RDRET_DATA_40 0xcf2000f4 376#define ixMP_DRAM_CNTL_RDRET_DATA_41 0xcf2000f8 377#define ixMP_DRAM_CNTL_RDRET_DATA_42 0xcf2000fc 378#define ixMP_DRAM_CNTL_RDRET_DATA_43 0xcf200100 379#define ixMP_DRAM_CNTL_RDRET_DATA_44 0xcf200104 380#define ixMP_DRAM_CNTL_RDRET_DATA_45 0xcf200108 381#define ixMP_DRAM_CNTL_RDRET_DATA_46 0xcf20010c 382#define ixMP_DRAM_CNTL_RDRET_DATA_47 0xcf200110 383#define ixMP_DRAM_CNTL_RDRET_DATA_48 0xcf200114 384#define ixMP_DRAM_CNTL_RDRET_DATA_49 0xcf200118 385#define ixMP_DRAM_CNTL_RDRET_DATA_50 0xcf20011c 386#define ixMP_DRAM_CNTL_RDRET_DATA_51 0xcf200120 387#define ixMP_DRAM_CNTL_RDRET_DATA_52 0xcf200124 388#define ixMP_DRAM_CNTL_RDRET_DATA_53 0xcf200128 389#define ixMP_DRAM_CNTL_RDRET_DATA_54 0xcf20012c 390#define ixMP_DRAM_CNTL_RDRET_DATA_55 0xcf200130 391#define ixMP_DRAM_CNTL_RDRET_DATA_56 0xcf200134 392#define ixMP_DRAM_CNTL_RDRET_DATA_57 0xcf200138 393#define ixMP_DRAM_CNTL_RDRET_DATA_58 0xcf20013c 394#define ixMP_DRAM_CNTL_RDRET_DATA_59 0xcf200140 395#define ixMP_DRAM_CNTL_RDRET_DATA_60 0xcf200144 396#define ixMP_DRAM_CNTL_RDRET_DATA_61 0xcf200148 397#define ixMP_DRAM_CNTL_RDRET_DATA_62 0xcf20014c 398#define ixMP_DRAM_CNTL_RDRET_DATA_63 0xcf200150 399#define ixMP_IOC_CTRL 0xcf100000 400#define ixMP_IOC_RDDATA 0xcf100004 401#define ixMP_IOC_PHASE1 0xcf100008 402#define ixMP_IOC_PHASE2 0xcf10000c 403#define ixMP_IOC_PHASE3 0xcf100010 404#define ixMP_IOC_READ_0 0xcf100024 405#define ixMP_IOC_READ_1 0xcf100028 406#define ixMP_IOC_READ_2 0xcf10002c 407#define ixMP_IOC_READ_3 0xcf100030 408#define ixMP_IOC_READ_4 0xcf100034 409#define ixMP_IOC_READ_5 0xcf100038 410#define ixMP_IOC_READ_6 0xcf10003c 411#define ixMP_IOC_READ_7 0xcf100040 412#define ixMP_IOC_READ_8 0xcf100044 413#define ixMP_IOC_READ_9 0xcf100048 414#define ixMP_IOC_READ_10 0xcf10004c 415#define ixMP_IOC_READ_11 0xcf100050 416#define ixMP_IOC_READ_12 0xcf100054 417#define ixMP_IOC_READ_13 0xcf100058 418#define ixMP_IOC_READ_14 0xcf10005c 419#define ixMP_IOC_READ_15 0xcf100060 420#define ixMP_IOC_WRITE_0 0xcf100064 421#define ixMP_IOC_WRITE_1 0xcf100068 422#define ixMP_IOC_WRITE_2 0xcf10006c 423#define ixMP_IOC_WRITE_3 0xcf100070 424#define ixMP_IOC_WRITE_4 0xcf100074 425#define ixMP_IOC_WRITE_5 0xcf100078 426#define ixMP_IOC_WRITE_6 0xcf10007c 427#define ixMP_IOC_WRITE_7 0xcf100080 428#define ixMP_IOC_WRITE_8 0xcf100084 429#define ixMP_IOC_WRITE_9 0xcf100088 430#define ixMP_IOC_WRITE_10 0xcf10008c 431#define ixMP_IOC_WRITE_11 0xcf100090 432#define ixMP_IOC_WRITE_12 0xcf100094 433#define ixMP_IOC_WRITE_13 0xcf100098 434#define ixMP_IOC_WRITE_14 0xcf10009c 435#define ixMP_IOC_WRITE_15 0xcf1000a0 436#define ixMP_INTERRUPT_CONTROL 0xcf200400 437#define ixMP0_SW_INT 0xcf200404 438#define ixMP0_SW_INT_CTXID 0xcf200408 439#define ixMP1_SW_INT 0xcf20040c 440#define ixMP1_SW_INT_CTXID 0xcf200410 441#define ixDISP_TIMER_ID 0xcf200414 442#define mmPWRHW_SMC_IND_INDEX 0x180 443#define mmPWRHW0_PWRHW_SMC_IND_INDEX 0x180 444#define mmPWRHW1_PWRHW_SMC_IND_INDEX 0x182 445#define mmPWRHW2_PWRHW_SMC_IND_INDEX 0x184 446#define mmPWRHW3_PWRHW_SMC_IND_INDEX 0x186 447#define mmPWRHW_SMC_IND_DATA 0x181 448#define mmPWRHW0_PWRHW_SMC_IND_DATA 0x181 449#define mmPWRHW1_PWRHW_SMC_IND_DATA 0x183 450#define mmPWRHW2_PWRHW_SMC_IND_DATA 0x185 451#define mmPWRHW3_PWRHW_SMC_IND_DATA 0x187 452#define ixCURRENT_STATE_CPU0 0xd0210000 453#define ixCURRENT_STATE_CPU1 0xd0210010 454#define ixCPU_REDUN_DONE0 0xd0210004 455#define ixCPU_REDUN_DONE1 0xd0210014 456#define ixCURRENT_VID_CPU0 0xd0210008 457#define ixCURRENT_VID_CPU1 0xd0210018 458#define ixUNBPM_PWRMGT_ACK 0xd0211000 459#define ixCURRENT_FREQ_STATE_NB 0xd0211004 460#define ixCURRENT_PSTATE_NB 0xd0211008 461#define ixUNBPM_MSG_INT_CONFIG 0xd021100c 462#define ixUNBPM_NBPWRMGT_CMD 0xd0211010 463#define ixUNBPM_NBPWRMGT_FSM_CFG 0xd0211014 464#define ixDDR0_FUSE_SSB_XFER 0xd0211018 465#define ixDDR0_FUSE_SSB_XFER_CFG 0xd021101c 466#define ixDDR1_FUSE_SSB_XFER 0xd0211020 467#define ixDDR1_FUSE_SSB_XFER_CFG 0xd0211024 468#define ixUNBPM_FUSES_VAL_PWROK 0xd0211028 469#define ixSYNFIFO_CLK_RATIO 0xd021102c 470#define ixMISC_SMU_PWRMGT_CFG0 0xd0211030 471#define ixMISC_GNB_PWRMGT_CFG1 0xd0211034 472#define ixMISC_SMU_PWRMGT_CFG1 0xd0211038 473#define ixMISC_GNB_PWRMGT_DATA 0xd021103c 474#define ixGN_GNB_SLOW 0xd0211040 475#define ixGN_FORCE_NBPS1 0xd0211044 476#define ixMISC_SMU_PWRMGT_DATA 0xd0211048 477#define ixNB_COF 0xd021104c 478#define ixUNBPM_CK_IRESET 0xd0211050 479#define ixCURRENT_VID_NB 0xd0211054 480#define ixSPR_FUSE_PSTATEPWR1 0xd0211058 481#define ixSPR_FUSE_PSTATEPWR2 0xd021105c 482#define ixSPR_FUSE_PSTATEPWR3 0xd0211060 483#define ixSPR_FUSE_THERMAL_SCRATCH 0xd0211064 484#define ixSPR_PRODUCT_INFO0 0xd0211068 485#define ixSPR_SERIALNUM_REG1 0xd021106c 486#define ixSPR_SERIALNUM_REG2 0xd0211070 487#define ixSPR_PRODUCT_INFO1 0xd0211074 488#define ixSPR_EXT_PRODUCT_INFO 0xd021107c 489#define ixSPR_MSIDFUSE 0xd0211080 490#define ixSPR_LINK_PRODUCT_INFO 0xd0211084 491#define ixSPR_BRAND_NAME_ADDR 0xd0211088 492#define ixSPR_BRAND_NAME_DATA 0xd021108c 493#define ixSPR_COMBO_PHY_PRODUCT_INFO 0xd0211090 494#define ixMISC_GNB_PWRMGT_CFG0 0xd0211094 495#define ixUNBPM_EXIT_TO_PSTATE 0xd0211098 496#define ixUNBPM_WARM_RESET_HS_STATUS 0xd021109c 497#define ixUNBPM_VOLTAGE_CNTL 0xd02110a0 498#define ixUNBPM_VOLTAGE_STATUS 0xd02110a4 499#define ixNUM_BOOST_STATES 0xd02110a8 500#define ixWARM_RESET_NB_CONTROL 0xd02110ac 501#define ixONION_NO_STREAMS_PEND 0xd02110b0 502#define ixSPR_PROGRAMMABLE_CTRL 0xd02110b4 503#define ixPHN_FUSERX_MISC_FUSES 0xd02110b8 504#define ixUNBPM_PWRCTRL_MISC 0xd02110bc 505#define ixCSTATE_ACTIVE_SAMPLER 0xd02110c0 506#define ixUNBPM_DEBUG_CONFIG_STATUS 0xd02110c4 507#define ixUNBPM_AXIMST_LAST_CMD 0xd02110c8 508#define ixUNB_IF_INTRGEN_LAST_SENT 0xd02110cc 509#define ixUNBPM_DEBUG_BUS_CNTL 0xd02110d0 510#define ixUNBPM_PWRMGT_REQ_DBG_STATUS 0xd02110d4 511#define ixUNBPM_VIDCHG_REQ_DBG_STATUS 0xd02110d8 512#define ixUNBPM_SCRATCH_0 0xd021e000 513#define ixUNBPM_SCRATCH_1 0xd021e004 514#define ixPOWERON_CPU_0 0xd0220000 515#define ixPOWERREADY_CPU_0 0xd0220004 516#define ixPGRUNFEEDBACK_CPU_0 0xd0220008 517#define ixRCC3ON_CPU_0 0xd022000c 518#define ixRCC3EXITDONE_CPU_0 0xd0220010 519#define ixCORE_FUNC_LATE_SSB_XFER_0 0xd0220014 520#define ixCORE_FUNC_LATE_SSB_XFER_CFG_0 0xd0220018 521#define ixCORE_REDUN_SSB_XFER_0 0xd022001c 522#define ixCORE_REDUN_SSB_XFER_CFG_0 0xd0220020 523#define ixCORE_APM_SSB_XFER_0 0xd0220024 524#define ixCORE_APM_SSB_XFER_CFG_0 0xd0220028 525#define ixCOREPM_PWRCTRL_MISC_0 0xd022002c 526#define ixLDOIVRON_CPU_0 0xd0220030 527#define ixLDOIVREXITDONE_CPU_0 0xd0220034 528#define ixRCC3_TARGETPSMREF_CPU_0 0xd0220038 529#define ixIVR_TARGETPSMREF_CPU_0 0xd022003c 530#define ixCK_JTCOOLRESET_LATCHED_CPU_0 0xd0220044 531#define ixCK_DISABLECORE_CPU_0 0xd0220048 532#define ixCOREPM_ID_0 0xd022004c 533#define ixCOREPM_SCRATCH_0 0xd0220050 534#define ixRCC3_WAKEMIN_CPU_0 0xd0220054 535#define ixSPMI_CONFIG0_0 0xd0221000 536#define ixSPMI_CONFIG1_0 0xd0221004 537#define ixSPMI_FSM_READ_TRIGGER_0 0xd0221008 538#define ixSPMI_FSM_WRITE_TRIGGER_0 0xd022100c 539#define ixSPMI_FSM_RESET_TRIGGER_0 0xd0221010 540#define ixSPMI_FSM_BUSY_0 0xd0221014 541#define ixSPMI_PATH_0 0xd0221018 542#define ixSPMI_C6_STATE_0 0xd022101c 543#define ixSPMI_JTAG_OVER_0 0xd0221020 544#define ixSPMI_SRAM_ADDRESS_0 0xd0221024 545#define ixSPMI_SRAM_DATA_0 0xd0221028 546#define ixSPMI_RESET_0 0xd022102c 547#define ixSPMI_FORCE_CLOCK_GATERS_0 0xd0221030 548#define ixSPMI_SPARE_0 0xd0221034 549#define ixSPMI_SPARE_EX_0 0xd0221038 550#define ixSPMI_SRAM_CLK_GATER_0 0xd022103c 551#define ixPOWERON_CPU_1 0xd0230000 552#define ixPOWERREADY_CPU_1 0xd0230004 553#define ixPGRUNFEEDBACK_CPU_1 0xd0230008 554#define ixRCC3ON_CPU_1 0xd023000c 555#define ixRCC3EXITDONE_CPU_1 0xd0230010 556#define ixCORE_FUNC_LATE_SSB_XFER_1 0xd0230014 557#define ixCORE_FUNC_LATE_SSB_XFER_CFG_1 0xd0230018 558#define ixCORE_REDUN_SSB_XFER_1 0xd023001c 559#define ixCORE_REDUN_SSB_XFER_CFG_1 0xd0230020 560#define ixCORE_APM_SSB_XFER_1 0xd0230024 561#define ixCORE_APM_SSB_XFER_CFG_1 0xd0230028 562#define ixCOREPM_PWRCTRL_MISC_1 0xd023002c 563#define ixLDOIVRON_CPU_1 0xd0230030 564#define ixLDOIVREXITDONE_CPU_1 0xd0230034 565#define ixRCC3_TARGETPSMREF_CPU_1 0xd0230038 566#define ixIVR_TARGETPSMREF_CPU_1 0xd023003c 567#define ixCK_JTCOOLRESET_LATCHED_CPU_1 0xd0230044 568#define ixCK_DISABLECORE_CPU_1 0xd0230048 569#define ixCOREPM_ID_1 0xd023004c 570#define ixCOREPM_SCRATCH_1 0xd0230050 571#define ixRCC3_WAKEMIN_CPU_1 0xd0230054 572#define ixSPMI_CONFIG0_1 0xd0231000 573#define ixSPMI_CONFIG1_1 0xd0231004 574#define ixSPMI_FSM_READ_TRIGGER_1 0xd0231008 575#define ixSPMI_FSM_WRITE_TRIGGER_1 0xd023100c 576#define ixSPMI_FSM_RESET_TRIGGER_1 0xd0231010 577#define ixSPMI_FSM_BUSY_1 0xd0231014 578#define ixSPMI_PATH_1 0xd0231018 579#define ixSPMI_C6_STATE_1 0xd023101c 580#define ixSPMI_JTAG_OVER_1 0xd0231020 581#define ixSPMI_SRAM_ADDRESS_1 0xd0231024 582#define ixSPMI_SRAM_DATA_1 0xd0231028 583#define ixSPMI_RESET_1 0xd023102c 584#define ixSPMI_FORCE_CLOCK_GATERS_1 0xd0231030 585#define ixSPMI_SPARE_1 0xd0231034 586#define ixSPMI_SPARE_EX_1 0xd0231038 587#define ixSPMI_SRAM_CLK_GATER_1 0xd023103c 588#define ixGENERAL_PWRMGT 0xd0200000 589#define ixCNB_PWRMGT_CNTL 0xd0200004 590#define ixSCLK_PWRMGT_CNTL 0xd0200008 591#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xd0200014 592#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xd02000f0 593#define ixTARGET_AND_CURRENT_PROFILE_INDEX_2 0xd02000f4 594#define ixCG_FREQ_TRAN_VOTING_0 0xd02001a8 595#define ixCG_FREQ_TRAN_VOTING_1 0xd02001ac 596#define ixCG_FREQ_TRAN_VOTING_2 0xd02001b0 597#define ixCG_FREQ_TRAN_VOTING_3 0xd02001b4 598#define ixCG_FREQ_TRAN_VOTING_4 0xd02001b8 599#define ixCG_FREQ_TRAN_VOTING_5 0xd02001bc 600#define ixCG_FREQ_TRAN_VOTING_6 0xd02001c0 601#define ixCG_FREQ_TRAN_VOTING_7 0xd02001c4 602#define ixCG_STATIC_SCREEN_PARAMETER 0xd0200044 603#define ixCG_ACPI_CNTL 0xd0200064 604#define ixSCLK_DEEP_SLEEP_CNTL 0xd0200080 605#define ixSCLK_DEEP_SLEEP_CNTL2 0xd0200084 606#define ixSCLK_DEEP_SLEEP_CNTL3 0xd020009c 607#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xd0200088 608#define ixLCLK_DEEP_SLEEP_CNTL 0xd020008c 609#define ixLCLK_DEEP_SLEEP_CNTL2 0xd0200310 610#define ixSMU_VOLTAGE_STATUS 0xd0200094 611#define ixCG_ULV_PARAMETER 0xd020015c 612#define ixPWR_DC_RESP 0xd0200300 613#define ixPWR_VCE_RESP 0xd0200304 614#define ixPWR_UVD_RESP 0xd0200308 615#define ixPWR_ACP_RESP 0xd020030c 616#define ixPWR_DC_REQ 0xd020031c 617#define ixSCLK_MIN_DIV 0xd02003ac 618#define ixPCIE_PGFSM_CONFIG 0xd02002d0 619#define ixPCIE_PGFSM_WRITE 0xd02002d4 620#define ixSERDES_BUSY 0xd02002d8 621#define ixPCIE_PGFSM2_CONFIG 0xd02002dc 622#define ixPCIE_PGFSM2_WRITE 0xd02002e0 623#define ixSERDES2_BUSY 0xd02002e4 624#define ixPCIE_PGFSM_0_READ 0xd02002e8 625#define ixPCIE_PGFSM_1_READ 0xd02002ec 626#define ixPWR_ACPI_INTERRUPT 0xd0200318 627#define ixVDDGFX_IDLE_PARAMETER 0xd020036c 628#define ixVDDGFX_IDLE_CONTROL 0xd0200370 629#define ixVDDGFX_IDLE_EXIT 0xd0200374 630#define ixREG_SCLK_DEEP_SLEEP_EXIT 0xd0200378 631#define ixCAC_WEIGHT_LKG_DC_3 0xd020803c 632#define ixLCAC_MC0_CNTL 0xd0208130 633#define ixLCAC_MC0_OVR_SEL 0xd0208134 634#define ixLCAC_MC0_OVR_VAL 0xd0208138 635#define ixLCAC_MC1_CNTL 0xd020813c 636#define ixLCAC_MC1_OVR_SEL 0xd0208140 637#define ixLCAC_MC1_OVR_VAL 0xd0208144 638#define ixLCAC_MC2_CNTL 0xd0208148 639#define ixLCAC_MC2_OVR_SEL 0xd020814c 640#define ixLCAC_MC2_OVR_VAL 0xd0208150 641#define ixLCAC_MC3_CNTL 0xd0208154 642#define ixLCAC_MC3_OVR_SEL 0xd0208158 643#define ixLCAC_MC3_OVR_VAL 0xd020815c 644#define ixLCAC_CPL_CNTL 0xd0208160 645#define ixLCAC_CPL_OVR_SEL 0xd0208164 646#define ixLCAC_CPL_OVR_VAL 0xd0208168 647#define ixMISC_UNB_PWRMGT_CFG0 0xd020c000 648#define ixMISC_UNB_PWRMGT_CFG1 0xd020c004 649#define ixMISC_UNB_PWRMGT_DATA 0xd020c00c 650#define ixGNBPM_SMU_PWRMGT_DATA 0xd020c010 651#define ixDMA_ACTIVE_SAMPLER_CFG 0xd020c014 652#define ixSOUTHBRIDGE_TYPE 0xd020c01c 653#define ixGNBPM_SMU_PWRMGT_STATUS 0xd020c020 654#define ixALLOW_SR_INTR_CTRL 0xd020c024 655#define mmGC_CAC_LKG_AGGR_LOWER 0x3294 656#define mmGC_CAC_LKG_AGGR_UPPER 0x3295 657#define ixGC_CAC_WEIGHT_CU_0 0x32 658#define ixGC_CAC_WEIGHT_CU_1 0x33 659#define ixGC_CAC_WEIGHT_CU_2 0x34 660#define ixGC_CAC_WEIGHT_CU_3 0x35 661#define ixGC_CAC_ACC_CU0 0xba 662#define ixGC_CAC_ACC_CU1 0xbb 663#define ixGC_CAC_ACC_CU2 0xbc 664#define ixGC_CAC_ACC_CU3 0xbd 665#define ixGC_CAC_ACC_CU4 0xbe 666#define ixGC_CAC_ACC_CU5 0xbf 667#define ixGC_CAC_ACC_CU6 0xc0 668#define ixGC_CAC_ACC_CU7 0xc1 669#define ixGC_CAC_OVRD_CU 0xe7 670 671#endif /* SMU_8_0_D_H */
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