FILE
smu_7_1_2_enum.h
File preview with syntax highlighting.
linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h
1/* 2 * SMU_7_1_2 Register documentation 3 * 4 * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24#ifndef SMU_7_1_2_ENUM_H 25#define SMU_7_1_2_ENUM_H 26 27#define CG_SRBM_START_ADDR 0x600 28#define CG_SRBM_END_ADDR 0x8ff 29#define RCU_CCF_DWORDS0 0xa0 30#define RCU_CCF_BITS0 0x1400 31#define RCU_CCF_DWORDS1 0x0 32#define RCU_CCF_BITS1 0x0 33#define RCU_SAM_BYTES 0x2c 34#define RCU_SAM_RTL_BYTES 0x2c 35#define RCU_SMU_BYTES 0x14 36#define RCU_SMU_RTL_BYTES 0x14 37#define SFP_CHAIN_ADDR 0x0 38#define SFP_BYTES 0x140 39#define SFP_SADR 0xc0 40#define SFP_EADR 0x1ff 41#define SAMU_KEY_CHAIN_ADR 0x0 42#define SAMU_KEY_SADR 0x2a0 43#define SAMU_KEY_EADR 0x2cb 44#define SMU_KEY_CHAIN_ADR 0x0 45#define SMU_KEY_SADR 0x2cc 46#define SMU_KEY_EADR 0x2df 47#define SMC_MSG_TEST 0x1 48#define SMC_MSG_PHY_LN_OFF 0x2 49#define SMC_MSG_PHY_LN_ON 0x3 50#define SMC_MSG_DDI_PHY_OFF 0x4 51#define SMC_MSG_DDI_PHY_ON 0x5 52#define SMC_MSG_CASCADE_PLL_OFF 0x6 53#define SMC_MSG_CASCADE_PLL_ON 0x7 54#define SMC_MSG_PWR_OFF_x16 0x8 55#define SMC_MSG_CONFIG_LCLK_DPM 0x9 56#define SMC_MSG_FLUSH_DATA_CACHE 0xa 57#define SMC_MSG_FLUSH_INSTRUCTION_CACHE 0xb 58#define SMC_MSG_CONFIG_VPC_ACCUMULATOR 0xc 59#define SMC_MSG_CONFIG_BAPM 0xd 60#define SMC_MSG_CONFIG_TDC_LIMIT 0xe 61#define SMC_MSG_CONFIG_LPMx 0xf 62#define SMC_MSG_CONFIG_HTC_LIMIT 0x10 63#define SMC_MSG_CONFIG_THERMAL_CNTL 0x11 64#define SMC_MSG_CONFIG_VOLTAGE_CNTL 0x12 65#define SMC_MSG_CONFIG_TDP_CNTL 0x13 66#define SMC_MSG_EN_PM_CNTL 0x14 67#define SMC_MSG_DIS_PM_CNTL 0x15 68#define SMC_MSG_CONFIG_NBDPM 0x16 69#define SMC_MSG_CONFIG_LOADLINE 0x17 70#define SMC_MSG_ADJUST_LOADLINE 0x18 71#define SMC_MSG_RESET 0x20 72#define SMC_MSG_VOLTAGE 0x25 73#define SMC_VERSION_MAJOR 0x7 74#define SMC_VERSION_MINOR 0x0 75#define SMC_HEADER_SIZE 0x40 76#define ROM_SIGNATURE 0xaa55 77typedef enum SurfaceEndian { 78 ENDIAN_NONE = 0x0, 79 ENDIAN_8IN16 = 0x1, 80 ENDIAN_8IN32 = 0x2, 81 ENDIAN_8IN64 = 0x3, 82} SurfaceEndian; 83typedef enum ArrayMode { 84 ARRAY_LINEAR_GENERAL = 0x0, 85 ARRAY_LINEAR_ALIGNED = 0x1, 86 ARRAY_1D_TILED_THIN1 = 0x2, 87 ARRAY_1D_TILED_THICK = 0x3, 88 ARRAY_2D_TILED_THIN1 = 0x4, 89 ARRAY_PRT_TILED_THIN1 = 0x5, 90 ARRAY_PRT_2D_TILED_THIN1 = 0x6, 91 ARRAY_2D_TILED_THICK = 0x7, 92 ARRAY_2D_TILED_XTHICK = 0x8, 93 ARRAY_PRT_TILED_THICK = 0x9, 94 ARRAY_PRT_2D_TILED_THICK = 0xa, 95 ARRAY_PRT_3D_TILED_THIN1 = 0xb, 96 ARRAY_3D_TILED_THIN1 = 0xc, 97 ARRAY_3D_TILED_THICK = 0xd, 98 ARRAY_3D_TILED_XTHICK = 0xe, 99 ARRAY_PRT_3D_TILED_THICK = 0xf, 100} ArrayMode; 101typedef enum PipeTiling { 102 CONFIG_1_PIPE = 0x0, 103 CONFIG_2_PIPE = 0x1, 104 CONFIG_4_PIPE = 0x2, 105 CONFIG_8_PIPE = 0x3, 106} PipeTiling; 107typedef enum BankTiling { 108 CONFIG_4_BANK = 0x0, 109 CONFIG_8_BANK = 0x1, 110} BankTiling; 111typedef enum GroupInterleave { 112 CONFIG_256B_GROUP = 0x0, 113 CONFIG_512B_GROUP = 0x1, 114} GroupInterleave; 115typedef enum RowTiling { 116 CONFIG_1KB_ROW = 0x0, 117 CONFIG_2KB_ROW = 0x1, 118 CONFIG_4KB_ROW = 0x2, 119 CONFIG_8KB_ROW = 0x3, 120 CONFIG_1KB_ROW_OPT = 0x4, 121 CONFIG_2KB_ROW_OPT = 0x5, 122 CONFIG_4KB_ROW_OPT = 0x6, 123 CONFIG_8KB_ROW_OPT = 0x7, 124} RowTiling; 125typedef enum BankSwapBytes { 126 CONFIG_128B_SWAPS = 0x0, 127 CONFIG_256B_SWAPS = 0x1, 128 CONFIG_512B_SWAPS = 0x2, 129 CONFIG_1KB_SWAPS = 0x3, 130} BankSwapBytes; 131typedef enum SampleSplitBytes { 132 CONFIG_1KB_SPLIT = 0x0, 133 CONFIG_2KB_SPLIT = 0x1, 134 CONFIG_4KB_SPLIT = 0x2, 135 CONFIG_8KB_SPLIT = 0x3, 136} SampleSplitBytes; 137typedef enum NumPipes { 138 ADDR_CONFIG_1_PIPE = 0x0, 139 ADDR_CONFIG_2_PIPE = 0x1, 140 ADDR_CONFIG_4_PIPE = 0x2, 141 ADDR_CONFIG_8_PIPE = 0x3, 142} NumPipes; 143typedef enum PipeInterleaveSize { 144 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, 145 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, 146} PipeInterleaveSize; 147typedef enum BankInterleaveSize { 148 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, 149 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, 150 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, 151 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, 152} BankInterleaveSize; 153typedef enum NumShaderEngines { 154 ADDR_CONFIG_1_SHADER_ENGINE = 0x0, 155 ADDR_CONFIG_2_SHADER_ENGINE = 0x1, 156} NumShaderEngines; 157typedef enum ShaderEngineTileSize { 158 ADDR_CONFIG_SE_TILE_16 = 0x0, 159 ADDR_CONFIG_SE_TILE_32 = 0x1, 160} ShaderEngineTileSize; 161typedef enum NumGPUs { 162 ADDR_CONFIG_1_GPU = 0x0, 163 ADDR_CONFIG_2_GPU = 0x1, 164 ADDR_CONFIG_4_GPU = 0x2, 165} NumGPUs; 166typedef enum MultiGPUTileSize { 167 ADDR_CONFIG_GPU_TILE_16 = 0x0, 168 ADDR_CONFIG_GPU_TILE_32 = 0x1, 169 ADDR_CONFIG_GPU_TILE_64 = 0x2, 170 ADDR_CONFIG_GPU_TILE_128 = 0x3, 171} MultiGPUTileSize; 172typedef enum RowSize { 173 ADDR_CONFIG_1KB_ROW = 0x0, 174 ADDR_CONFIG_2KB_ROW = 0x1, 175 ADDR_CONFIG_4KB_ROW = 0x2, 176} RowSize; 177typedef enum NumLowerPipes { 178 ADDR_CONFIG_1_LOWER_PIPES = 0x0, 179 ADDR_CONFIG_2_LOWER_PIPES = 0x1, 180} NumLowerPipes; 181typedef enum DebugBlockId { 182 DBG_CLIENT_BLKID_RESERVED = 0x0, 183 DBG_CLIENT_BLKID_dbg = 0x1, 184 DBG_CLIENT_BLKID_scf2 = 0x2, 185 DBG_CLIENT_BLKID_mcd5 = 0x3, 186 DBG_CLIENT_BLKID_vmc = 0x4, 187 DBG_CLIENT_BLKID_sx30 = 0x5, 188 DBG_CLIENT_BLKID_mcd2 = 0x6, 189 DBG_CLIENT_BLKID_bci1 = 0x7, 190 DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8, 191 DBG_CLIENT_BLKID_mcc0 = 0x9, 192 DBG_CLIENT_BLKID_uvdf_0 = 0xa, 193 DBG_CLIENT_BLKID_uvdf_1 = 0xb, 194 DBG_CLIENT_BLKID_bci0 = 0xc, 195 DBG_CLIENT_BLKID_vcec0_0 = 0xd, 196 DBG_CLIENT_BLKID_cb100 = 0xe, 197 DBG_CLIENT_BLKID_cb001 = 0xf, 198 DBG_CLIENT_BLKID_mcd4 = 0x10, 199 DBG_CLIENT_BLKID_tmonw00 = 0x11, 200 DBG_CLIENT_BLKID_cb101 = 0x12, 201 DBG_CLIENT_BLKID_sx10 = 0x13, 202 DBG_CLIENT_BLKID_cb301 = 0x14, 203 DBG_CLIENT_BLKID_tmonw01 = 0x15, 204 DBG_CLIENT_BLKID_vcea0_0 = 0x16, 205 DBG_CLIENT_BLKID_vcea0_1 = 0x17, 206 DBG_CLIENT_BLKID_vcea0_2 = 0x18, 207 DBG_CLIENT_BLKID_vcea0_3 = 0x19, 208 DBG_CLIENT_BLKID_scf1 = 0x1a, 209 DBG_CLIENT_BLKID_sx20 = 0x1b, 210 DBG_CLIENT_BLKID_spim1 = 0x1c, 211 DBG_CLIENT_BLKID_pa10 = 0x1d, 212 DBG_CLIENT_BLKID_pa00 = 0x1e, 213 DBG_CLIENT_BLKID_gmcon = 0x1f, 214 DBG_CLIENT_BLKID_mcb = 0x20, 215 DBG_CLIENT_BLKID_vgt0 = 0x21, 216 DBG_CLIENT_BLKID_pc0 = 0x22, 217 DBG_CLIENT_BLKID_bci2 = 0x23, 218 DBG_CLIENT_BLKID_uvdb_0 = 0x24, 219 DBG_CLIENT_BLKID_spim3 = 0x25, 220 DBG_CLIENT_BLKID_cpc_0 = 0x26, 221 DBG_CLIENT_BLKID_cpc_1 = 0x27, 222 DBG_CLIENT_BLKID_uvdm_0 = 0x28, 223 DBG_CLIENT_BLKID_uvdm_1 = 0x29, 224 DBG_CLIENT_BLKID_uvdm_2 = 0x2a, 225 DBG_CLIENT_BLKID_uvdm_3 = 0x2b, 226 DBG_CLIENT_BLKID_cb000 = 0x2c, 227 DBG_CLIENT_BLKID_spim0 = 0x2d, 228 DBG_CLIENT_BLKID_mcc2 = 0x2e, 229 DBG_CLIENT_BLKID_ds0 = 0x2f, 230 DBG_CLIENT_BLKID_srbm = 0x30, 231 DBG_CLIENT_BLKID_ih = 0x31, 232 DBG_CLIENT_BLKID_sem = 0x32, 233 DBG_CLIENT_BLKID_sdma_0 = 0x33, 234 DBG_CLIENT_BLKID_sdma_1 = 0x34, 235 DBG_CLIENT_BLKID_hdp = 0x35, 236 DBG_CLIENT_BLKID_acp_0 = 0x36, 237 DBG_CLIENT_BLKID_acp_1 = 0x37, 238 DBG_CLIENT_BLKID_cb200 = 0x38, 239 DBG_CLIENT_BLKID_scf3 = 0x39, 240 DBG_CLIENT_BLKID_vceb1_0 = 0x3a, 241 DBG_CLIENT_BLKID_vcea1_0 = 0x3b, 242 DBG_CLIENT_BLKID_vcea1_1 = 0x3c, 243 DBG_CLIENT_BLKID_vcea1_2 = 0x3d, 244 DBG_CLIENT_BLKID_vcea1_3 = 0x3e, 245 DBG_CLIENT_BLKID_bci3 = 0x3f, 246 DBG_CLIENT_BLKID_mcd0 = 0x40, 247 DBG_CLIENT_BLKID_pa11 = 0x41, 248 DBG_CLIENT_BLKID_pa01 = 0x42, 249 DBG_CLIENT_BLKID_cb201 = 0x43, 250 DBG_CLIENT_BLKID_spim2 = 0x44, 251 DBG_CLIENT_BLKID_vgt2 = 0x45, 252 DBG_CLIENT_BLKID_pc2 = 0x46, 253 DBG_CLIENT_BLKID_smu_0 = 0x47, 254 DBG_CLIENT_BLKID_smu_1 = 0x48, 255 DBG_CLIENT_BLKID_smu_2 = 0x49, 256 DBG_CLIENT_BLKID_cb1 = 0x4a, 257 DBG_CLIENT_BLKID_ia0 = 0x4b, 258 DBG_CLIENT_BLKID_wd = 0x4c, 259 DBG_CLIENT_BLKID_ia1 = 0x4d, 260 DBG_CLIENT_BLKID_vcec1_0 = 0x4e, 261 DBG_CLIENT_BLKID_scf0 = 0x4f, 262 DBG_CLIENT_BLKID_vgt1 = 0x50, 263 DBG_CLIENT_BLKID_pc1 = 0x51, 264 DBG_CLIENT_BLKID_cb0 = 0x52, 265 DBG_CLIENT_BLKID_gdc_one_0 = 0x53, 266 DBG_CLIENT_BLKID_gdc_one_1 = 0x54, 267 DBG_CLIENT_BLKID_gdc_one_2 = 0x55, 268 DBG_CLIENT_BLKID_gdc_one_3 = 0x56, 269 DBG_CLIENT_BLKID_gdc_one_4 = 0x57, 270 DBG_CLIENT_BLKID_gdc_one_5 = 0x58, 271 DBG_CLIENT_BLKID_gdc_one_6 = 0x59, 272 DBG_CLIENT_BLKID_gdc_one_7 = 0x5a, 273 DBG_CLIENT_BLKID_gdc_one_8 = 0x5b, 274 DBG_CLIENT_BLKID_gdc_one_9 = 0x5c, 275 DBG_CLIENT_BLKID_gdc_one_10 = 0x5d, 276 DBG_CLIENT_BLKID_gdc_one_11 = 0x5e, 277 DBG_CLIENT_BLKID_gdc_one_12 = 0x5f, 278 DBG_CLIENT_BLKID_gdc_one_13 = 0x60, 279 DBG_CLIENT_BLKID_gdc_one_14 = 0x61, 280 DBG_CLIENT_BLKID_gdc_one_15 = 0x62, 281 DBG_CLIENT_BLKID_gdc_one_16 = 0x63, 282 DBG_CLIENT_BLKID_gdc_one_17 = 0x64, 283 DBG_CLIENT_BLKID_gdc_one_18 = 0x65, 284 DBG_CLIENT_BLKID_gdc_one_19 = 0x66, 285 DBG_CLIENT_BLKID_gdc_one_20 = 0x67, 286 DBG_CLIENT_BLKID_gdc_one_21 = 0x68, 287 DBG_CLIENT_BLKID_gdc_one_22 = 0x69, 288 DBG_CLIENT_BLKID_gdc_one_23 = 0x6a, 289 DBG_CLIENT_BLKID_gdc_one_24 = 0x6b, 290 DBG_CLIENT_BLKID_gdc_one_25 = 0x6c, 291 DBG_CLIENT_BLKID_gdc_one_26 = 0x6d, 292 DBG_CLIENT_BLKID_gdc_one_27 = 0x6e, 293 DBG_CLIENT_BLKID_gdc_one_28 = 0x6f, 294 DBG_CLIENT_BLKID_gdc_one_29 = 0x70, 295 DBG_CLIENT_BLKID_gdc_one_30 = 0x71, 296 DBG_CLIENT_BLKID_gdc_one_31 = 0x72, 297 DBG_CLIENT_BLKID_gdc_one_32 = 0x73, 298 DBG_CLIENT_BLKID_gdc_one_33 = 0x74, 299 DBG_CLIENT_BLKID_gdc_one_34 = 0x75, 300 DBG_CLIENT_BLKID_gdc_one_35 = 0x76, 301 DBG_CLIENT_BLKID_vceb0_0 = 0x77, 302 DBG_CLIENT_BLKID_vgt3 = 0x78, 303 DBG_CLIENT_BLKID_pc3 = 0x79, 304 DBG_CLIENT_BLKID_mcd3 = 0x7a, 305 DBG_CLIENT_BLKID_uvdu_0 = 0x7b, 306 DBG_CLIENT_BLKID_uvdu_1 = 0x7c, 307 DBG_CLIENT_BLKID_uvdu_2 = 0x7d, 308 DBG_CLIENT_BLKID_uvdu_3 = 0x7e, 309 DBG_CLIENT_BLKID_uvdu_4 = 0x7f, 310 DBG_CLIENT_BLKID_uvdu_5 = 0x80, 311 DBG_CLIENT_BLKID_uvdu_6 = 0x81, 312 DBG_CLIENT_BLKID_cb300 = 0x82, 313 DBG_CLIENT_BLKID_mcd1 = 0x83, 314 DBG_CLIENT_BLKID_sx00 = 0x84, 315 DBG_CLIENT_BLKID_uvdc_0 = 0x85, 316 DBG_CLIENT_BLKID_uvdc_1 = 0x86, 317 DBG_CLIENT_BLKID_mcc3 = 0x87, 318 DBG_CLIENT_BLKID_cpg_0 = 0x88, 319 DBG_CLIENT_BLKID_cpg_1 = 0x89, 320 DBG_CLIENT_BLKID_gck = 0x8a, 321 DBG_CLIENT_BLKID_mcc1 = 0x8b, 322 DBG_CLIENT_BLKID_cpf_0 = 0x8c, 323 DBG_CLIENT_BLKID_cpf_1 = 0x8d, 324 DBG_CLIENT_BLKID_rlc = 0x8e, 325 DBG_CLIENT_BLKID_grbm = 0x8f, 326 DBG_CLIENT_BLKID_sammsp = 0x90, 327 DBG_CLIENT_BLKID_dci_pg = 0x91, 328 DBG_CLIENT_BLKID_dci_0 = 0x92, 329 DBG_CLIENT_BLKID_dccg0_0 = 0x93, 330 DBG_CLIENT_BLKID_dccg0_1 = 0x94, 331 DBG_CLIENT_BLKID_dcfe01_0 = 0x95, 332 DBG_CLIENT_BLKID_dcfe02_0 = 0x96, 333 DBG_CLIENT_BLKID_dcfe03_0 = 0x97, 334 DBG_CLIENT_BLKID_dcfe04_0 = 0x98, 335 DBG_CLIENT_BLKID_dcfe05_0 = 0x99, 336 DBG_CLIENT_BLKID_dcfe06_0 = 0x9a, 337 DBG_CLIENT_BLKID_RESERVED_LAST = 0x9b, 338} DebugBlockId; 339typedef enum DebugBlockId_OLD { 340 DBG_BLOCK_ID_RESERVED = 0x0, 341 DBG_BLOCK_ID_DBG = 0x1, 342 DBG_BLOCK_ID_VMC = 0x2, 343 DBG_BLOCK_ID_PDMA = 0x3, 344 DBG_BLOCK_ID_CG = 0x4, 345 DBG_BLOCK_ID_SRBM = 0x5, 346 DBG_BLOCK_ID_GRBM = 0x6, 347 DBG_BLOCK_ID_RLC = 0x7, 348 DBG_BLOCK_ID_CSC = 0x8, 349 DBG_BLOCK_ID_SEM = 0x9, 350 DBG_BLOCK_ID_IH = 0xa, 351 DBG_BLOCK_ID_SC = 0xb, 352 DBG_BLOCK_ID_SQ = 0xc, 353 DBG_BLOCK_ID_AVP = 0xd, 354 DBG_BLOCK_ID_GMCON = 0xe, 355 DBG_BLOCK_ID_SMU = 0xf, 356 DBG_BLOCK_ID_DMA0 = 0x10, 357 DBG_BLOCK_ID_DMA1 = 0x11, 358 DBG_BLOCK_ID_SPIM = 0x12, 359 DBG_BLOCK_ID_GDS = 0x13, 360 DBG_BLOCK_ID_SPIS = 0x14, 361 DBG_BLOCK_ID_UNUSED0 = 0x15, 362 DBG_BLOCK_ID_PA0 = 0x16, 363 DBG_BLOCK_ID_PA1 = 0x17, 364 DBG_BLOCK_ID_CP0 = 0x18, 365 DBG_BLOCK_ID_CP1 = 0x19, 366 DBG_BLOCK_ID_CP2 = 0x1a, 367 DBG_BLOCK_ID_UNUSED1 = 0x1b, 368 DBG_BLOCK_ID_UVDU = 0x1c, 369 DBG_BLOCK_ID_UVDM = 0x1d, 370 DBG_BLOCK_ID_VCE = 0x1e, 371 DBG_BLOCK_ID_UNUSED2 = 0x1f, 372 DBG_BLOCK_ID_VGT0 = 0x20, 373 DBG_BLOCK_ID_VGT1 = 0x21, 374 DBG_BLOCK_ID_IA = 0x22, 375 DBG_BLOCK_ID_UNUSED3 = 0x23, 376 DBG_BLOCK_ID_SCT0 = 0x24, 377 DBG_BLOCK_ID_SCT1 = 0x25, 378 DBG_BLOCK_ID_SPM0 = 0x26, 379 DBG_BLOCK_ID_SPM1 = 0x27, 380 DBG_BLOCK_ID_TCAA = 0x28, 381 DBG_BLOCK_ID_TCAB = 0x29, 382 DBG_BLOCK_ID_TCCA = 0x2a, 383 DBG_BLOCK_ID_TCCB = 0x2b, 384 DBG_BLOCK_ID_MCC0 = 0x2c, 385 DBG_BLOCK_ID_MCC1 = 0x2d, 386 DBG_BLOCK_ID_MCC2 = 0x2e, 387 DBG_BLOCK_ID_MCC3 = 0x2f, 388 DBG_BLOCK_ID_SX0 = 0x30, 389 DBG_BLOCK_ID_SX1 = 0x31, 390 DBG_BLOCK_ID_SX2 = 0x32, 391 DBG_BLOCK_ID_SX3 = 0x33, 392 DBG_BLOCK_ID_UNUSED4 = 0x34, 393 DBG_BLOCK_ID_UNUSED5 = 0x35, 394 DBG_BLOCK_ID_UNUSED6 = 0x36, 395 DBG_BLOCK_ID_UNUSED7 = 0x37, 396 DBG_BLOCK_ID_PC0 = 0x38, 397 DBG_BLOCK_ID_PC1 = 0x39, 398 DBG_BLOCK_ID_UNUSED8 = 0x3a, 399 DBG_BLOCK_ID_UNUSED9 = 0x3b, 400 DBG_BLOCK_ID_UNUSED10 = 0x3c, 401 DBG_BLOCK_ID_UNUSED11 = 0x3d, 402 DBG_BLOCK_ID_MCB = 0x3e, 403 DBG_BLOCK_ID_UNUSED12 = 0x3f, 404 DBG_BLOCK_ID_SCB0 = 0x40, 405 DBG_BLOCK_ID_SCB1 = 0x41, 406 DBG_BLOCK_ID_UNUSED13 = 0x42, 407 DBG_BLOCK_ID_UNUSED14 = 0x43, 408 DBG_BLOCK_ID_SCF0 = 0x44, 409 DBG_BLOCK_ID_SCF1 = 0x45, 410 DBG_BLOCK_ID_UNUSED15 = 0x46, 411 DBG_BLOCK_ID_UNUSED16 = 0x47, 412 DBG_BLOCK_ID_BCI0 = 0x48, 413 DBG_BLOCK_ID_BCI1 = 0x49, 414 DBG_BLOCK_ID_BCI2 = 0x4a, 415 DBG_BLOCK_ID_BCI3 = 0x4b, 416 DBG_BLOCK_ID_UNUSED17 = 0x4c, 417 DBG_BLOCK_ID_UNUSED18 = 0x4d, 418 DBG_BLOCK_ID_UNUSED19 = 0x4e, 419 DBG_BLOCK_ID_UNUSED20 = 0x4f, 420 DBG_BLOCK_ID_CB00 = 0x50, 421 DBG_BLOCK_ID_CB01 = 0x51, 422 DBG_BLOCK_ID_CB02 = 0x52, 423 DBG_BLOCK_ID_CB03 = 0x53, 424 DBG_BLOCK_ID_CB04 = 0x54, 425 DBG_BLOCK_ID_UNUSED21 = 0x55, 426 DBG_BLOCK_ID_UNUSED22 = 0x56, 427 DBG_BLOCK_ID_UNUSED23 = 0x57, 428 DBG_BLOCK_ID_CB10 = 0x58, 429 DBG_BLOCK_ID_CB11 = 0x59, 430 DBG_BLOCK_ID_CB12 = 0x5a, 431 DBG_BLOCK_ID_CB13 = 0x5b, 432 DBG_BLOCK_ID_CB14 = 0x5c, 433 DBG_BLOCK_ID_UNUSED24 = 0x5d, 434 DBG_BLOCK_ID_UNUSED25 = 0x5e, 435 DBG_BLOCK_ID_UNUSED26 = 0x5f, 436 DBG_BLOCK_ID_TCP0 = 0x60, 437 DBG_BLOCK_ID_TCP1 = 0x61, 438 DBG_BLOCK_ID_TCP2 = 0x62, 439 DBG_BLOCK_ID_TCP3 = 0x63, 440 DBG_BLOCK_ID_TCP4 = 0x64, 441 DBG_BLOCK_ID_TCP5 = 0x65, 442 DBG_BLOCK_ID_TCP6 = 0x66, 443 DBG_BLOCK_ID_TCP7 = 0x67, 444 DBG_BLOCK_ID_TCP8 = 0x68, 445 DBG_BLOCK_ID_TCP9 = 0x69, 446 DBG_BLOCK_ID_TCP10 = 0x6a, 447 DBG_BLOCK_ID_TCP11 = 0x6b, 448 DBG_BLOCK_ID_TCP12 = 0x6c, 449 DBG_BLOCK_ID_TCP13 = 0x6d, 450 DBG_BLOCK_ID_TCP14 = 0x6e, 451 DBG_BLOCK_ID_TCP15 = 0x6f, 452 DBG_BLOCK_ID_TCP16 = 0x70, 453 DBG_BLOCK_ID_TCP17 = 0x71, 454 DBG_BLOCK_ID_TCP18 = 0x72, 455 DBG_BLOCK_ID_TCP19 = 0x73, 456 DBG_BLOCK_ID_TCP20 = 0x74, 457 DBG_BLOCK_ID_TCP21 = 0x75, 458 DBG_BLOCK_ID_TCP22 = 0x76, 459 DBG_BLOCK_ID_TCP23 = 0x77, 460 DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, 461 DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, 462 DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, 463 DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, 464 DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, 465 DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, 466 DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, 467 DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, 468 DBG_BLOCK_ID_DB00 = 0x80, 469 DBG_BLOCK_ID_DB01 = 0x81, 470 DBG_BLOCK_ID_DB02 = 0x82, 471 DBG_BLOCK_ID_DB03 = 0x83, 472 DBG_BLOCK_ID_DB04 = 0x84, 473 DBG_BLOCK_ID_UNUSED27 = 0x85, 474 DBG_BLOCK_ID_UNUSED28 = 0x86, 475 DBG_BLOCK_ID_UNUSED29 = 0x87, 476 DBG_BLOCK_ID_DB10 = 0x88, 477 DBG_BLOCK_ID_DB11 = 0x89, 478 DBG_BLOCK_ID_DB12 = 0x8a, 479 DBG_BLOCK_ID_DB13 = 0x8b, 480 DBG_BLOCK_ID_DB14 = 0x8c, 481 DBG_BLOCK_ID_UNUSED30 = 0x8d, 482 DBG_BLOCK_ID_UNUSED31 = 0x8e, 483 DBG_BLOCK_ID_UNUSED32 = 0x8f, 484 DBG_BLOCK_ID_TCC0 = 0x90, 485 DBG_BLOCK_ID_TCC1 = 0x91, 486 DBG_BLOCK_ID_TCC2 = 0x92, 487 DBG_BLOCK_ID_TCC3 = 0x93, 488 DBG_BLOCK_ID_TCC4 = 0x94, 489 DBG_BLOCK_ID_TCC5 = 0x95, 490 DBG_BLOCK_ID_TCC6 = 0x96, 491 DBG_BLOCK_ID_TCC7 = 0x97, 492 DBG_BLOCK_ID_SPS00 = 0x98, 493 DBG_BLOCK_ID_SPS01 = 0x99, 494 DBG_BLOCK_ID_SPS02 = 0x9a, 495 DBG_BLOCK_ID_SPS10 = 0x9b, 496 DBG_BLOCK_ID_SPS11 = 0x9c, 497 DBG_BLOCK_ID_SPS12 = 0x9d, 498 DBG_BLOCK_ID_UNUSED33 = 0x9e, 499 DBG_BLOCK_ID_UNUSED34 = 0x9f, 500 DBG_BLOCK_ID_TA00 = 0xa0, 501 DBG_BLOCK_ID_TA01 = 0xa1, 502 DBG_BLOCK_ID_TA02 = 0xa2, 503 DBG_BLOCK_ID_TA03 = 0xa3, 504 DBG_BLOCK_ID_TA04 = 0xa4, 505 DBG_BLOCK_ID_TA05 = 0xa5, 506 DBG_BLOCK_ID_TA06 = 0xa6, 507 DBG_BLOCK_ID_TA07 = 0xa7, 508 DBG_BLOCK_ID_TA08 = 0xa8, 509 DBG_BLOCK_ID_TA09 = 0xa9, 510 DBG_BLOCK_ID_TA0A = 0xaa, 511 DBG_BLOCK_ID_TA0B = 0xab, 512 DBG_BLOCK_ID_UNUSED35 = 0xac, 513 DBG_BLOCK_ID_UNUSED36 = 0xad, 514 DBG_BLOCK_ID_UNUSED37 = 0xae, 515 DBG_BLOCK_ID_UNUSED38 = 0xaf, 516 DBG_BLOCK_ID_TA10 = 0xb0, 517 DBG_BLOCK_ID_TA11 = 0xb1, 518 DBG_BLOCK_ID_TA12 = 0xb2, 519 DBG_BLOCK_ID_TA13 = 0xb3, 520 DBG_BLOCK_ID_TA14 = 0xb4, 521 DBG_BLOCK_ID_TA15 = 0xb5, 522 DBG_BLOCK_ID_TA16 = 0xb6, 523 DBG_BLOCK_ID_TA17 = 0xb7, 524 DBG_BLOCK_ID_TA18 = 0xb8, 525 DBG_BLOCK_ID_TA19 = 0xb9, 526 DBG_BLOCK_ID_TA1A = 0xba, 527 DBG_BLOCK_ID_TA1B = 0xbb, 528 DBG_BLOCK_ID_UNUSED39 = 0xbc, 529 DBG_BLOCK_ID_UNUSED40 = 0xbd, 530 DBG_BLOCK_ID_UNUSED41 = 0xbe, 531 DBG_BLOCK_ID_UNUSED42 = 0xbf, 532 DBG_BLOCK_ID_TD00 = 0xc0, 533 DBG_BLOCK_ID_TD01 = 0xc1, 534 DBG_BLOCK_ID_TD02 = 0xc2, 535 DBG_BLOCK_ID_TD03 = 0xc3, 536 DBG_BLOCK_ID_TD04 = 0xc4, 537 DBG_BLOCK_ID_TD05 = 0xc5, 538 DBG_BLOCK_ID_TD06 = 0xc6, 539 DBG_BLOCK_ID_TD07 = 0xc7, 540 DBG_BLOCK_ID_TD08 = 0xc8, 541 DBG_BLOCK_ID_TD09 = 0xc9, 542 DBG_BLOCK_ID_TD0A = 0xca, 543 DBG_BLOCK_ID_TD0B = 0xcb, 544 DBG_BLOCK_ID_UNUSED43 = 0xcc, 545 DBG_BLOCK_ID_UNUSED44 = 0xcd, 546 DBG_BLOCK_ID_UNUSED45 = 0xce, 547 DBG_BLOCK_ID_UNUSED46 = 0xcf, 548 DBG_BLOCK_ID_TD10 = 0xd0, 549 DBG_BLOCK_ID_TD11 = 0xd1, 550 DBG_BLOCK_ID_TD12 = 0xd2, 551 DBG_BLOCK_ID_TD13 = 0xd3, 552 DBG_BLOCK_ID_TD14 = 0xd4, 553 DBG_BLOCK_ID_TD15 = 0xd5, 554 DBG_BLOCK_ID_TD16 = 0xd6, 555 DBG_BLOCK_ID_TD17 = 0xd7, 556 DBG_BLOCK_ID_TD18 = 0xd8, 557 DBG_BLOCK_ID_TD19 = 0xd9, 558 DBG_BLOCK_ID_TD1A = 0xda, 559 DBG_BLOCK_ID_TD1B = 0xdb, 560 DBG_BLOCK_ID_UNUSED47 = 0xdc, 561 DBG_BLOCK_ID_UNUSED48 = 0xdd, 562 DBG_BLOCK_ID_UNUSED49 = 0xde, 563 DBG_BLOCK_ID_UNUSED50 = 0xdf, 564 DBG_BLOCK_ID_MCD0 = 0xe0, 565 DBG_BLOCK_ID_MCD1 = 0xe1, 566 DBG_BLOCK_ID_MCD2 = 0xe2, 567 DBG_BLOCK_ID_MCD3 = 0xe3, 568 DBG_BLOCK_ID_MCD4 = 0xe4, 569 DBG_BLOCK_ID_MCD5 = 0xe5, 570 DBG_BLOCK_ID_UNUSED51 = 0xe6, 571 DBG_BLOCK_ID_UNUSED52 = 0xe7, 572} DebugBlockId_OLD; 573typedef enum DebugBlockId_BY2 { 574 DBG_BLOCK_ID_RESERVED_BY2 = 0x0, 575 DBG_BLOCK_ID_VMC_BY2 = 0x1, 576 DBG_BLOCK_ID_CG_BY2 = 0x2, 577 DBG_BLOCK_ID_GRBM_BY2 = 0x3, 578 DBG_BLOCK_ID_CSC_BY2 = 0x4, 579 DBG_BLOCK_ID_IH_BY2 = 0x5, 580 DBG_BLOCK_ID_SQ_BY2 = 0x6, 581 DBG_BLOCK_ID_GMCON_BY2 = 0x7, 582 DBG_BLOCK_ID_DMA0_BY2 = 0x8, 583 DBG_BLOCK_ID_SPIM_BY2 = 0x9, 584 DBG_BLOCK_ID_SPIS_BY2 = 0xa, 585 DBG_BLOCK_ID_PA0_BY2 = 0xb, 586 DBG_BLOCK_ID_CP0_BY2 = 0xc, 587 DBG_BLOCK_ID_CP2_BY2 = 0xd, 588 DBG_BLOCK_ID_UVDU_BY2 = 0xe, 589 DBG_BLOCK_ID_VCE_BY2 = 0xf, 590 DBG_BLOCK_ID_VGT0_BY2 = 0x10, 591 DBG_BLOCK_ID_IA_BY2 = 0x11, 592 DBG_BLOCK_ID_SCT0_BY2 = 0x12, 593 DBG_BLOCK_ID_SPM0_BY2 = 0x13, 594 DBG_BLOCK_ID_TCAA_BY2 = 0x14, 595 DBG_BLOCK_ID_TCCA_BY2 = 0x15, 596 DBG_BLOCK_ID_MCC0_BY2 = 0x16, 597 DBG_BLOCK_ID_MCC2_BY2 = 0x17, 598 DBG_BLOCK_ID_SX0_BY2 = 0x18, 599 DBG_BLOCK_ID_SX2_BY2 = 0x19, 600 DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, 601 DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, 602 DBG_BLOCK_ID_PC0_BY2 = 0x1c, 603 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, 604 DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, 605 DBG_BLOCK_ID_MCB_BY2 = 0x1f, 606 DBG_BLOCK_ID_SCB0_BY2 = 0x20, 607 DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, 608 DBG_BLOCK_ID_SCF0_BY2 = 0x22, 609 DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, 610 DBG_BLOCK_ID_BCI0_BY2 = 0x24, 611 DBG_BLOCK_ID_BCI2_BY2 = 0x25, 612 DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, 613 DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, 614 DBG_BLOCK_ID_CB00_BY2 = 0x28, 615 DBG_BLOCK_ID_CB02_BY2 = 0x29, 616 DBG_BLOCK_ID_CB04_BY2 = 0x2a, 617 DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, 618 DBG_BLOCK_ID_CB10_BY2 = 0x2c, 619 DBG_BLOCK_ID_CB12_BY2 = 0x2d, 620 DBG_BLOCK_ID_CB14_BY2 = 0x2e, 621 DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, 622 DBG_BLOCK_ID_TCP0_BY2 = 0x30, 623 DBG_BLOCK_ID_TCP2_BY2 = 0x31, 624 DBG_BLOCK_ID_TCP4_BY2 = 0x32, 625 DBG_BLOCK_ID_TCP6_BY2 = 0x33, 626 DBG_BLOCK_ID_TCP8_BY2 = 0x34, 627 DBG_BLOCK_ID_TCP10_BY2 = 0x35, 628 DBG_BLOCK_ID_TCP12_BY2 = 0x36, 629 DBG_BLOCK_ID_TCP14_BY2 = 0x37, 630 DBG_BLOCK_ID_TCP16_BY2 = 0x38, 631 DBG_BLOCK_ID_TCP18_BY2 = 0x39, 632 DBG_BLOCK_ID_TCP20_BY2 = 0x3a, 633 DBG_BLOCK_ID_TCP22_BY2 = 0x3b, 634 DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, 635 DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, 636 DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, 637 DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, 638 DBG_BLOCK_ID_DB00_BY2 = 0x40, 639 DBG_BLOCK_ID_DB02_BY2 = 0x41, 640 DBG_BLOCK_ID_DB04_BY2 = 0x42, 641 DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, 642 DBG_BLOCK_ID_DB10_BY2 = 0x44, 643 DBG_BLOCK_ID_DB12_BY2 = 0x45, 644 DBG_BLOCK_ID_DB14_BY2 = 0x46, 645 DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, 646 DBG_BLOCK_ID_TCC0_BY2 = 0x48, 647 DBG_BLOCK_ID_TCC2_BY2 = 0x49, 648 DBG_BLOCK_ID_TCC4_BY2 = 0x4a, 649 DBG_BLOCK_ID_TCC6_BY2 = 0x4b, 650 DBG_BLOCK_ID_SPS00_BY2 = 0x4c, 651 DBG_BLOCK_ID_SPS02_BY2 = 0x4d, 652 DBG_BLOCK_ID_SPS11_BY2 = 0x4e, 653 DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, 654 DBG_BLOCK_ID_TA00_BY2 = 0x50, 655 DBG_BLOCK_ID_TA02_BY2 = 0x51, 656 DBG_BLOCK_ID_TA04_BY2 = 0x52, 657 DBG_BLOCK_ID_TA06_BY2 = 0x53, 658 DBG_BLOCK_ID_TA08_BY2 = 0x54, 659 DBG_BLOCK_ID_TA0A_BY2 = 0x55, 660 DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, 661 DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, 662 DBG_BLOCK_ID_TA10_BY2 = 0x58, 663 DBG_BLOCK_ID_TA12_BY2 = 0x59, 664 DBG_BLOCK_ID_TA14_BY2 = 0x5a, 665 DBG_BLOCK_ID_TA16_BY2 = 0x5b, 666 DBG_BLOCK_ID_TA18_BY2 = 0x5c, 667 DBG_BLOCK_ID_TA1A_BY2 = 0x5d, 668 DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, 669 DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, 670 DBG_BLOCK_ID_TD00_BY2 = 0x60, 671 DBG_BLOCK_ID_TD02_BY2 = 0x61, 672 DBG_BLOCK_ID_TD04_BY2 = 0x62, 673 DBG_BLOCK_ID_TD06_BY2 = 0x63, 674 DBG_BLOCK_ID_TD08_BY2 = 0x64, 675 DBG_BLOCK_ID_TD0A_BY2 = 0x65, 676 DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, 677 DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, 678 DBG_BLOCK_ID_TD10_BY2 = 0x68, 679 DBG_BLOCK_ID_TD12_BY2 = 0x69, 680 DBG_BLOCK_ID_TD14_BY2 = 0x6a, 681 DBG_BLOCK_ID_TD16_BY2 = 0x6b, 682 DBG_BLOCK_ID_TD18_BY2 = 0x6c, 683 DBG_BLOCK_ID_TD1A_BY2 = 0x6d, 684 DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, 685 DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, 686 DBG_BLOCK_ID_MCD0_BY2 = 0x70, 687 DBG_BLOCK_ID_MCD2_BY2 = 0x71, 688 DBG_BLOCK_ID_MCD4_BY2 = 0x72, 689 DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, 690} DebugBlockId_BY2; 691typedef enum DebugBlockId_BY4 { 692 DBG_BLOCK_ID_RESERVED_BY4 = 0x0, 693 DBG_BLOCK_ID_CG_BY4 = 0x1, 694 DBG_BLOCK_ID_CSC_BY4 = 0x2, 695 DBG_BLOCK_ID_SQ_BY4 = 0x3, 696 DBG_BLOCK_ID_DMA0_BY4 = 0x4, 697 DBG_BLOCK_ID_SPIS_BY4 = 0x5, 698 DBG_BLOCK_ID_CP0_BY4 = 0x6, 699 DBG_BLOCK_ID_UVDU_BY4 = 0x7, 700 DBG_BLOCK_ID_VGT0_BY4 = 0x8, 701 DBG_BLOCK_ID_SCT0_BY4 = 0x9, 702 DBG_BLOCK_ID_TCAA_BY4 = 0xa, 703 DBG_BLOCK_ID_MCC0_BY4 = 0xb, 704 DBG_BLOCK_ID_SX0_BY4 = 0xc, 705 DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, 706 DBG_BLOCK_ID_PC0_BY4 = 0xe, 707 DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, 708 DBG_BLOCK_ID_SCB0_BY4 = 0x10, 709 DBG_BLOCK_ID_SCF0_BY4 = 0x11, 710 DBG_BLOCK_ID_BCI0_BY4 = 0x12, 711 DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, 712 DBG_BLOCK_ID_CB00_BY4 = 0x14, 713 DBG_BLOCK_ID_CB04_BY4 = 0x15, 714 DBG_BLOCK_ID_CB10_BY4 = 0x16, 715 DBG_BLOCK_ID_CB14_BY4 = 0x17, 716 DBG_BLOCK_ID_TCP0_BY4 = 0x18, 717 DBG_BLOCK_ID_TCP4_BY4 = 0x19, 718 DBG_BLOCK_ID_TCP8_BY4 = 0x1a, 719 DBG_BLOCK_ID_TCP12_BY4 = 0x1b, 720 DBG_BLOCK_ID_TCP16_BY4 = 0x1c, 721 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 722 DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, 723 DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, 724 DBG_BLOCK_ID_DB_BY4 = 0x20, 725 DBG_BLOCK_ID_DB04_BY4 = 0x21, 726 DBG_BLOCK_ID_DB10_BY4 = 0x22, 727 DBG_BLOCK_ID_DB14_BY4 = 0x23, 728 DBG_BLOCK_ID_TCC0_BY4 = 0x24, 729 DBG_BLOCK_ID_TCC4_BY4 = 0x25, 730 DBG_BLOCK_ID_SPS00_BY4 = 0x26, 731 DBG_BLOCK_ID_SPS11_BY4 = 0x27, 732 DBG_BLOCK_ID_TA00_BY4 = 0x28, 733 DBG_BLOCK_ID_TA04_BY4 = 0x29, 734 DBG_BLOCK_ID_TA08_BY4 = 0x2a, 735 DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, 736 DBG_BLOCK_ID_TA10_BY4 = 0x2c, 737 DBG_BLOCK_ID_TA14_BY4 = 0x2d, 738 DBG_BLOCK_ID_TA18_BY4 = 0x2e, 739 DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, 740 DBG_BLOCK_ID_TD00_BY4 = 0x30, 741 DBG_BLOCK_ID_TD04_BY4 = 0x31, 742 DBG_BLOCK_ID_TD08_BY4 = 0x32, 743 DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, 744 DBG_BLOCK_ID_TD10_BY4 = 0x34, 745 DBG_BLOCK_ID_TD14_BY4 = 0x35, 746 DBG_BLOCK_ID_TD18_BY4 = 0x36, 747 DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, 748 DBG_BLOCK_ID_MCD0_BY4 = 0x38, 749 DBG_BLOCK_ID_MCD4_BY4 = 0x39, 750} DebugBlockId_BY4; 751typedef enum DebugBlockId_BY8 { 752 DBG_BLOCK_ID_RESERVED_BY8 = 0x0, 753 DBG_BLOCK_ID_CSC_BY8 = 0x1, 754 DBG_BLOCK_ID_DMA0_BY8 = 0x2, 755 DBG_BLOCK_ID_CP0_BY8 = 0x3, 756 DBG_BLOCK_ID_VGT0_BY8 = 0x4, 757 DBG_BLOCK_ID_TCAA_BY8 = 0x5, 758 DBG_BLOCK_ID_SX0_BY8 = 0x6, 759 DBG_BLOCK_ID_PC0_BY8 = 0x7, 760 DBG_BLOCK_ID_SCB0_BY8 = 0x8, 761 DBG_BLOCK_ID_BCI0_BY8 = 0x9, 762 DBG_BLOCK_ID_CB00_BY8 = 0xa, 763 DBG_BLOCK_ID_CB10_BY8 = 0xb, 764 DBG_BLOCK_ID_TCP0_BY8 = 0xc, 765 DBG_BLOCK_ID_TCP8_BY8 = 0xd, 766 DBG_BLOCK_ID_TCP16_BY8 = 0xe, 767 DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, 768 DBG_BLOCK_ID_DB00_BY8 = 0x10, 769 DBG_BLOCK_ID_DB10_BY8 = 0x11, 770 DBG_BLOCK_ID_TCC0_BY8 = 0x12, 771 DBG_BLOCK_ID_SPS00_BY8 = 0x13, 772 DBG_BLOCK_ID_TA00_BY8 = 0x14, 773 DBG_BLOCK_ID_TA08_BY8 = 0x15, 774 DBG_BLOCK_ID_TA10_BY8 = 0x16, 775 DBG_BLOCK_ID_TA18_BY8 = 0x17, 776 DBG_BLOCK_ID_TD00_BY8 = 0x18, 777 DBG_BLOCK_ID_TD08_BY8 = 0x19, 778 DBG_BLOCK_ID_TD10_BY8 = 0x1a, 779 DBG_BLOCK_ID_TD18_BY8 = 0x1b, 780 DBG_BLOCK_ID_MCD0_BY8 = 0x1c, 781} DebugBlockId_BY8; 782typedef enum DebugBlockId_BY16 { 783 DBG_BLOCK_ID_RESERVED_BY16 = 0x0, 784 DBG_BLOCK_ID_DMA0_BY16 = 0x1, 785 DBG_BLOCK_ID_VGT0_BY16 = 0x2, 786 DBG_BLOCK_ID_SX0_BY16 = 0x3, 787 DBG_BLOCK_ID_SCB0_BY16 = 0x4, 788 DBG_BLOCK_ID_CB00_BY16 = 0x5, 789 DBG_BLOCK_ID_TCP0_BY16 = 0x6, 790 DBG_BLOCK_ID_TCP16_BY16 = 0x7, 791 DBG_BLOCK_ID_DB00_BY16 = 0x8, 792 DBG_BLOCK_ID_TCC0_BY16 = 0x9, 793 DBG_BLOCK_ID_TA00_BY16 = 0xa, 794 DBG_BLOCK_ID_TA10_BY16 = 0xb, 795 DBG_BLOCK_ID_TD00_BY16 = 0xc, 796 DBG_BLOCK_ID_TD10_BY16 = 0xd, 797 DBG_BLOCK_ID_MCD0_BY16 = 0xe, 798} DebugBlockId_BY16; 799typedef enum ColorTransform { 800 DCC_CT_AUTO = 0x0, 801 DCC_CT_NONE = 0x1, 802 ABGR_TO_A_BG_G_RB = 0x2, 803 BGRA_TO_BG_G_RB_A = 0x3, 804} ColorTransform; 805typedef enum CompareRef { 806 REF_NEVER = 0x0, 807 REF_LESS = 0x1, 808 REF_EQUAL = 0x2, 809 REF_LEQUAL = 0x3, 810 REF_GREATER = 0x4, 811 REF_NOTEQUAL = 0x5, 812 REF_GEQUAL = 0x6, 813 REF_ALWAYS = 0x7, 814} CompareRef; 815typedef enum ReadSize { 816 READ_256_BITS = 0x0, 817 READ_512_BITS = 0x1, 818} ReadSize; 819typedef enum DepthFormat { 820 DEPTH_INVALID = 0x0, 821 DEPTH_16 = 0x1, 822 DEPTH_X8_24 = 0x2, 823 DEPTH_8_24 = 0x3, 824 DEPTH_X8_24_FLOAT = 0x4, 825 DEPTH_8_24_FLOAT = 0x5, 826 DEPTH_32_FLOAT = 0x6, 827 DEPTH_X24_8_32_FLOAT = 0x7, 828} DepthFormat; 829typedef enum ZFormat { 830 Z_INVALID = 0x0, 831 Z_16 = 0x1, 832 Z_24 = 0x2, 833 Z_32_FLOAT = 0x3, 834} ZFormat; 835typedef enum StencilFormat { 836 STENCIL_INVALID = 0x0, 837 STENCIL_8 = 0x1, 838} StencilFormat; 839typedef enum CmaskMode { 840 CMASK_CLEAR_NONE = 0x0, 841 CMASK_CLEAR_ONE = 0x1, 842 CMASK_CLEAR_ALL = 0x2, 843 CMASK_ANY_EXPANDED = 0x3, 844 CMASK_ALPHA0_FRAG1 = 0x4, 845 CMASK_ALPHA0_FRAG2 = 0x5, 846 CMASK_ALPHA0_FRAG4 = 0x6, 847 CMASK_ALPHA0_FRAGS = 0x7, 848 CMASK_ALPHA1_FRAG1 = 0x8, 849 CMASK_ALPHA1_FRAG2 = 0x9, 850 CMASK_ALPHA1_FRAG4 = 0xa, 851 CMASK_ALPHA1_FRAGS = 0xb, 852 CMASK_ALPHAX_FRAG1 = 0xc, 853 CMASK_ALPHAX_FRAG2 = 0xd, 854 CMASK_ALPHAX_FRAG4 = 0xe, 855 CMASK_ALPHAX_FRAGS = 0xf, 856} CmaskMode; 857typedef enum QuadExportFormat { 858 EXPORT_UNUSED = 0x0, 859 EXPORT_32_R = 0x1, 860 EXPORT_32_GR = 0x2, 861 EXPORT_32_AR = 0x3, 862 EXPORT_FP16_ABGR = 0x4, 863 EXPORT_UNSIGNED16_ABGR = 0x5, 864 EXPORT_SIGNED16_ABGR = 0x6, 865 EXPORT_32_ABGR = 0x7, 866} QuadExportFormat; 867typedef enum QuadExportFormatOld { 868 EXPORT_4P_32BPC_ABGR = 0x0, 869 EXPORT_4P_16BPC_ABGR = 0x1, 870 EXPORT_4P_32BPC_GR = 0x2, 871 EXPORT_4P_32BPC_AR = 0x3, 872 EXPORT_2P_32BPC_ABGR = 0x4, 873 EXPORT_8P_32BPC_R = 0x5, 874} QuadExportFormatOld; 875typedef enum ColorFormat { 876 COLOR_INVALID = 0x0, 877 COLOR_8 = 0x1, 878 COLOR_16 = 0x2, 879 COLOR_8_8 = 0x3, 880 COLOR_32 = 0x4, 881 COLOR_16_16 = 0x5, 882 COLOR_10_11_11 = 0x6, 883 COLOR_11_11_10 = 0x7, 884 COLOR_10_10_10_2 = 0x8, 885 COLOR_2_10_10_10 = 0x9, 886 COLOR_8_8_8_8 = 0xa, 887 COLOR_32_32 = 0xb, 888 COLOR_16_16_16_16 = 0xc, 889 COLOR_RESERVED_13 = 0xd, 890 COLOR_32_32_32_32 = 0xe, 891 COLOR_RESERVED_15 = 0xf, 892 COLOR_5_6_5 = 0x10, 893 COLOR_1_5_5_5 = 0x11, 894 COLOR_5_5_5_1 = 0x12, 895 COLOR_4_4_4_4 = 0x13, 896 COLOR_8_24 = 0x14, 897 COLOR_24_8 = 0x15, 898 COLOR_X24_8_32_FLOAT = 0x16, 899 COLOR_RESERVED_23 = 0x17, 900} ColorFormat; 901typedef enum SurfaceFormat { 902 FMT_INVALID = 0x0, 903 FMT_8 = 0x1, 904 FMT_16 = 0x2, 905 FMT_8_8 = 0x3, 906 FMT_32 = 0x4, 907 FMT_16_16 = 0x5, 908 FMT_10_11_11 = 0x6, 909 FMT_11_11_10 = 0x7, 910 FMT_10_10_10_2 = 0x8, 911 FMT_2_10_10_10 = 0x9, 912 FMT_8_8_8_8 = 0xa, 913 FMT_32_32 = 0xb, 914 FMT_16_16_16_16 = 0xc, 915 FMT_32_32_32 = 0xd, 916 FMT_32_32_32_32 = 0xe, 917 FMT_RESERVED_4 = 0xf, 918 FMT_5_6_5 = 0x10, 919 FMT_1_5_5_5 = 0x11, 920 FMT_5_5_5_1 = 0x12, 921 FMT_4_4_4_4 = 0x13, 922 FMT_8_24 = 0x14, 923 FMT_24_8 = 0x15, 924 FMT_X24_8_32_FLOAT = 0x16, 925 FMT_RESERVED_33 = 0x17, 926 FMT_11_11_10_FLOAT = 0x18, 927 FMT_16_FLOAT = 0x19, 928 FMT_32_FLOAT = 0x1a, 929 FMT_16_16_FLOAT = 0x1b, 930 FMT_8_24_FLOAT = 0x1c, 931 FMT_24_8_FLOAT = 0x1d, 932 FMT_32_32_FLOAT = 0x1e, 933 FMT_10_11_11_FLOAT = 0x1f, 934 FMT_16_16_16_16_FLOAT = 0x20, 935 FMT_3_3_2 = 0x21, 936 FMT_6_5_5 = 0x22, 937 FMT_32_32_32_32_FLOAT = 0x23, 938 FMT_RESERVED_36 = 0x24, 939 FMT_1 = 0x25, 940 FMT_1_REVERSED = 0x26, 941 FMT_GB_GR = 0x27, 942 FMT_BG_RG = 0x28, 943 FMT_32_AS_8 = 0x29, 944 FMT_32_AS_8_8 = 0x2a, 945 FMT_5_9_9_9_SHAREDEXP = 0x2b, 946 FMT_8_8_8 = 0x2c, 947 FMT_16_16_16 = 0x2d, 948 FMT_16_16_16_FLOAT = 0x2e, 949 FMT_4_4 = 0x2f, 950 FMT_32_32_32_FLOAT = 0x30, 951 FMT_BC1 = 0x31, 952 FMT_BC2 = 0x32, 953 FMT_BC3 = 0x33, 954 FMT_BC4 = 0x34, 955 FMT_BC5 = 0x35, 956 FMT_BC6 = 0x36, 957 FMT_BC7 = 0x37, 958 FMT_32_AS_32_32_32_32 = 0x38, 959 FMT_APC3 = 0x39, 960 FMT_APC4 = 0x3a, 961 FMT_APC5 = 0x3b, 962 FMT_APC6 = 0x3c, 963 FMT_APC7 = 0x3d, 964 FMT_CTX1 = 0x3e, 965 FMT_RESERVED_63 = 0x3f, 966} SurfaceFormat; 967typedef enum BUF_DATA_FORMAT { 968 BUF_DATA_FORMAT_INVALID = 0x0, 969 BUF_DATA_FORMAT_8 = 0x1, 970 BUF_DATA_FORMAT_16 = 0x2, 971 BUF_DATA_FORMAT_8_8 = 0x3, 972 BUF_DATA_FORMAT_32 = 0x4, 973 BUF_DATA_FORMAT_16_16 = 0x5, 974 BUF_DATA_FORMAT_10_11_11 = 0x6, 975 BUF_DATA_FORMAT_11_11_10 = 0x7, 976 BUF_DATA_FORMAT_10_10_10_2 = 0x8, 977 BUF_DATA_FORMAT_2_10_10_10 = 0x9, 978 BUF_DATA_FORMAT_8_8_8_8 = 0xa, 979 BUF_DATA_FORMAT_32_32 = 0xb, 980 BUF_DATA_FORMAT_16_16_16_16 = 0xc, 981 BUF_DATA_FORMAT_32_32_32 = 0xd, 982 BUF_DATA_FORMAT_32_32_32_32 = 0xe, 983 BUF_DATA_FORMAT_RESERVED_15 = 0xf, 984} BUF_DATA_FORMAT; 985typedef enum IMG_DATA_FORMAT { 986 IMG_DATA_FORMAT_INVALID = 0x0, 987 IMG_DATA_FORMAT_8 = 0x1, 988 IMG_DATA_FORMAT_16 = 0x2, 989 IMG_DATA_FORMAT_8_8 = 0x3, 990 IMG_DATA_FORMAT_32 = 0x4, 991 IMG_DATA_FORMAT_16_16 = 0x5, 992 IMG_DATA_FORMAT_10_11_11 = 0x6, 993 IMG_DATA_FORMAT_11_11_10 = 0x7, 994 IMG_DATA_FORMAT_10_10_10_2 = 0x8, 995 IMG_DATA_FORMAT_2_10_10_10 = 0x9, 996 IMG_DATA_FORMAT_8_8_8_8 = 0xa, 997 IMG_DATA_FORMAT_32_32 = 0xb, 998 IMG_DATA_FORMAT_16_16_16_16 = 0xc, 999 IMG_DATA_FORMAT_32_32_32 = 0xd, 1000 IMG_DATA_FORMAT_32_32_32_32 = 0xe, 1001 IMG_DATA_FORMAT_RESERVED_15 = 0xf, 1002 IMG_DATA_FORMAT_5_6_5 = 0x10, 1003 IMG_DATA_FORMAT_1_5_5_5 = 0x11, 1004 IMG_DATA_FORMAT_5_5_5_1 = 0x12, 1005 IMG_DATA_FORMAT_4_4_4_4 = 0x13, 1006 IMG_DATA_FORMAT_8_24 = 0x14, 1007 IMG_DATA_FORMAT_24_8 = 0x15, 1008 IMG_DATA_FORMAT_X24_8_32 = 0x16, 1009 IMG_DATA_FORMAT_RESERVED_23 = 0x17, 1010 IMG_DATA_FORMAT_RESERVED_24 = 0x18, 1011 IMG_DATA_FORMAT_RESERVED_25 = 0x19, 1012 IMG_DATA_FORMAT_RESERVED_26 = 0x1a, 1013 IMG_DATA_FORMAT_RESERVED_27 = 0x1b, 1014 IMG_DATA_FORMAT_RESERVED_28 = 0x1c, 1015 IMG_DATA_FORMAT_RESERVED_29 = 0x1d, 1016 IMG_DATA_FORMAT_RESERVED_30 = 0x1e, 1017 IMG_DATA_FORMAT_RESERVED_31 = 0x1f, 1018 IMG_DATA_FORMAT_GB_GR = 0x20, 1019 IMG_DATA_FORMAT_BG_RG = 0x21, 1020 IMG_DATA_FORMAT_5_9_9_9 = 0x22, 1021 IMG_DATA_FORMAT_BC1 = 0x23, 1022 IMG_DATA_FORMAT_BC2 = 0x24, 1023 IMG_DATA_FORMAT_BC3 = 0x25, 1024 IMG_DATA_FORMAT_BC4 = 0x26, 1025 IMG_DATA_FORMAT_BC5 = 0x27, 1026 IMG_DATA_FORMAT_BC6 = 0x28, 1027 IMG_DATA_FORMAT_BC7 = 0x29, 1028 IMG_DATA_FORMAT_RESERVED_42 = 0x2a, 1029 IMG_DATA_FORMAT_RESERVED_43 = 0x2b, 1030 IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, 1031 IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, 1032 IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, 1033 IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, 1034 IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, 1035 IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, 1036 IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, 1037 IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, 1038 IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, 1039 IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, 1040 IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, 1041 IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, 1042 IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, 1043 IMG_DATA_FORMAT_4_4 = 0x39, 1044 IMG_DATA_FORMAT_6_5_5 = 0x3a, 1045 IMG_DATA_FORMAT_1 = 0x3b, 1046 IMG_DATA_FORMAT_1_REVERSED = 0x3c, 1047 IMG_DATA_FORMAT_32_AS_8 = 0x3d, 1048 IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, 1049 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, 1050} IMG_DATA_FORMAT; 1051typedef enum BUF_NUM_FORMAT { 1052 BUF_NUM_FORMAT_UNORM = 0x0, 1053 BUF_NUM_FORMAT_SNORM = 0x1, 1054 BUF_NUM_FORMAT_USCALED = 0x2, 1055 BUF_NUM_FORMAT_SSCALED = 0x3, 1056 BUF_NUM_FORMAT_UINT = 0x4, 1057 BUF_NUM_FORMAT_SINT = 0x5, 1058 BUF_NUM_FORMAT_RESERVED_6 = 0x6, 1059 BUF_NUM_FORMAT_FLOAT = 0x7, 1060} BUF_NUM_FORMAT; 1061typedef enum IMG_NUM_FORMAT { 1062 IMG_NUM_FORMAT_UNORM = 0x0, 1063 IMG_NUM_FORMAT_SNORM = 0x1, 1064 IMG_NUM_FORMAT_USCALED = 0x2, 1065 IMG_NUM_FORMAT_SSCALED = 0x3, 1066 IMG_NUM_FORMAT_UINT = 0x4, 1067 IMG_NUM_FORMAT_SINT = 0x5, 1068 IMG_NUM_FORMAT_RESERVED_6 = 0x6, 1069 IMG_NUM_FORMAT_FLOAT = 0x7, 1070 IMG_NUM_FORMAT_RESERVED_8 = 0x8, 1071 IMG_NUM_FORMAT_SRGB = 0x9, 1072 IMG_NUM_FORMAT_RESERVED_10 = 0xa, 1073 IMG_NUM_FORMAT_RESERVED_11 = 0xb, 1074 IMG_NUM_FORMAT_RESERVED_12 = 0xc, 1075 IMG_NUM_FORMAT_RESERVED_13 = 0xd, 1076 IMG_NUM_FORMAT_RESERVED_14 = 0xe, 1077 IMG_NUM_FORMAT_RESERVED_15 = 0xf, 1078} IMG_NUM_FORMAT; 1079typedef enum TileType { 1080 ARRAY_COLOR_TILE = 0x0, 1081 ARRAY_DEPTH_TILE = 0x1, 1082} TileType; 1083typedef enum NonDispTilingOrder { 1084 ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 1085 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 1086} NonDispTilingOrder; 1087typedef enum MicroTileMode { 1088 ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, 1089 ADDR_SURF_THIN_MICRO_TILING = 0x1, 1090 ADDR_SURF_DEPTH_MICRO_TILING = 0x2, 1091 ADDR_SURF_ROTATED_MICRO_TILING = 0x3, 1092 ADDR_SURF_THICK_MICRO_TILING = 0x4, 1093} MicroTileMode; 1094typedef enum TileSplit { 1095 ADDR_SURF_TILE_SPLIT_64B = 0x0, 1096 ADDR_SURF_TILE_SPLIT_128B = 0x1, 1097 ADDR_SURF_TILE_SPLIT_256B = 0x2, 1098 ADDR_SURF_TILE_SPLIT_512B = 0x3, 1099 ADDR_SURF_TILE_SPLIT_1KB = 0x4, 1100 ADDR_SURF_TILE_SPLIT_2KB = 0x5, 1101 ADDR_SURF_TILE_SPLIT_4KB = 0x6, 1102} TileSplit; 1103typedef enum SampleSplit { 1104 ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, 1105 ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, 1106 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, 1107 ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, 1108} SampleSplit; 1109typedef enum PipeConfig { 1110 ADDR_SURF_P2 = 0x0, 1111 ADDR_SURF_P2_RESERVED0 = 0x1, 1112 ADDR_SURF_P2_RESERVED1 = 0x2, 1113 ADDR_SURF_P2_RESERVED2 = 0x3, 1114 ADDR_SURF_P4_8x16 = 0x4, 1115 ADDR_SURF_P4_16x16 = 0x5, 1116 ADDR_SURF_P4_16x32 = 0x6, 1117 ADDR_SURF_P4_32x32 = 0x7, 1118 ADDR_SURF_P8_16x16_8x16 = 0x8, 1119 ADDR_SURF_P8_16x32_8x16 = 0x9, 1120 ADDR_SURF_P8_32x32_8x16 = 0xa, 1121 ADDR_SURF_P8_16x32_16x16 = 0xb, 1122 ADDR_SURF_P8_32x32_16x16 = 0xc, 1123 ADDR_SURF_P8_32x32_16x32 = 0xd, 1124 ADDR_SURF_P8_32x64_32x32 = 0xe, 1125 ADDR_SURF_P8_RESERVED0 = 0xf, 1126 ADDR_SURF_P16_32x32_8x16 = 0x10, 1127 ADDR_SURF_P16_32x32_16x16 = 0x11, 1128} PipeConfig; 1129typedef enum NumBanks { 1130 ADDR_SURF_2_BANK = 0x0, 1131 ADDR_SURF_4_BANK = 0x1, 1132 ADDR_SURF_8_BANK = 0x2, 1133 ADDR_SURF_16_BANK = 0x3, 1134} NumBanks; 1135typedef enum BankWidth { 1136 ADDR_SURF_BANK_WIDTH_1 = 0x0, 1137 ADDR_SURF_BANK_WIDTH_2 = 0x1, 1138 ADDR_SURF_BANK_WIDTH_4 = 0x2, 1139 ADDR_SURF_BANK_WIDTH_8 = 0x3, 1140} BankWidth; 1141typedef enum BankHeight { 1142 ADDR_SURF_BANK_HEIGHT_1 = 0x0, 1143 ADDR_SURF_BANK_HEIGHT_2 = 0x1, 1144 ADDR_SURF_BANK_HEIGHT_4 = 0x2, 1145 ADDR_SURF_BANK_HEIGHT_8 = 0x3, 1146} BankHeight; 1147typedef enum BankWidthHeight { 1148 ADDR_SURF_BANK_WH_1 = 0x0, 1149 ADDR_SURF_BANK_WH_2 = 0x1, 1150 ADDR_SURF_BANK_WH_4 = 0x2, 1151 ADDR_SURF_BANK_WH_8 = 0x3, 1152} BankWidthHeight; 1153typedef enum MacroTileAspect { 1154 ADDR_SURF_MACRO_ASPECT_1 = 0x0, 1155 ADDR_SURF_MACRO_ASPECT_2 = 0x1, 1156 ADDR_SURF_MACRO_ASPECT_4 = 0x2, 1157 ADDR_SURF_MACRO_ASPECT_8 = 0x3, 1158} MacroTileAspect; 1159typedef enum GATCL1RequestType { 1160 GATCL1_TYPE_NORMAL = 0x0, 1161 GATCL1_TYPE_SHOOTDOWN = 0x1, 1162 GATCL1_TYPE_BYPASS = 0x2, 1163} GATCL1RequestType; 1164typedef enum TCC_CACHE_POLICIES { 1165 TCC_CACHE_POLICY_LRU = 0x0, 1166 TCC_CACHE_POLICY_STREAM = 0x1, 1167} TCC_CACHE_POLICIES; 1168typedef enum MTYPE { 1169 MTYPE_NC_NV = 0x0, 1170 MTYPE_NC = 0x1, 1171 MTYPE_CC = 0x2, 1172 MTYPE_UC = 0x3, 1173} MTYPE; 1174typedef enum PERFMON_COUNTER_MODE { 1175 PERFMON_COUNTER_MODE_ACCUM = 0x0, 1176 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, 1177 PERFMON_COUNTER_MODE_MAX = 0x2, 1178 PERFMON_COUNTER_MODE_DIRTY = 0x3, 1179 PERFMON_COUNTER_MODE_SAMPLE = 0x4, 1180 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, 1181 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, 1182 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, 1183 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, 1184 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, 1185 PERFMON_COUNTER_MODE_RESERVED = 0xf, 1186} PERFMON_COUNTER_MODE; 1187typedef enum PERFMON_SPM_MODE { 1188 PERFMON_SPM_MODE_OFF = 0x0, 1189 PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, 1190 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, 1191 PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, 1192 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, 1193 PERFMON_SPM_MODE_RESERVED_5 = 0x5, 1194 PERFMON_SPM_MODE_RESERVED_6 = 0x6, 1195 PERFMON_SPM_MODE_RESERVED_7 = 0x7, 1196 PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, 1197 PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, 1198 PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, 1199} PERFMON_SPM_MODE; 1200typedef enum SurfaceTiling { 1201 ARRAY_LINEAR = 0x0, 1202 ARRAY_TILED = 0x1, 1203} SurfaceTiling; 1204typedef enum SurfaceArray { 1205 ARRAY_1D = 0x0, 1206 ARRAY_2D = 0x1, 1207 ARRAY_3D = 0x2, 1208 ARRAY_3D_SLICE = 0x3, 1209} SurfaceArray; 1210typedef enum ColorArray { 1211 ARRAY_2D_ALT_COLOR = 0x0, 1212 ARRAY_2D_COLOR = 0x1, 1213 ARRAY_3D_SLICE_COLOR = 0x3, 1214} ColorArray; 1215typedef enum DepthArray { 1216 ARRAY_2D_ALT_DEPTH = 0x0, 1217 ARRAY_2D_DEPTH = 0x1, 1218} DepthArray; 1219typedef enum ENUM_NUM_SIMD_PER_CU { 1220 NUM_SIMD_PER_CU = 0x4, 1221} ENUM_NUM_SIMD_PER_CU; 1222typedef enum MEM_PWR_FORCE_CTRL { 1223 NO_FORCE_REQUEST = 0x0, 1224 FORCE_LIGHT_SLEEP_REQUEST = 0x1, 1225 FORCE_DEEP_SLEEP_REQUEST = 0x2, 1226 FORCE_SHUT_DOWN_REQUEST = 0x3, 1227} MEM_PWR_FORCE_CTRL; 1228typedef enum MEM_PWR_FORCE_CTRL2 { 1229 NO_FORCE_REQ = 0x0, 1230 FORCE_LIGHT_SLEEP_REQ = 0x1, 1231} MEM_PWR_FORCE_CTRL2; 1232typedef enum MEM_PWR_DIS_CTRL { 1233 ENABLE_MEM_PWR_CTRL = 0x0, 1234 DISABLE_MEM_PWR_CTRL = 0x1, 1235} MEM_PWR_DIS_CTRL; 1236typedef enum MEM_PWR_SEL_CTRL { 1237 DYNAMIC_SHUT_DOWN_ENABLE = 0x0, 1238 DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, 1239 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, 1240} MEM_PWR_SEL_CTRL; 1241typedef enum MEM_PWR_SEL_CTRL2 { 1242 DYNAMIC_DEEP_SLEEP_EN = 0x0, 1243 DYNAMIC_LIGHT_SLEEP_EN = 0x1, 1244} MEM_PWR_SEL_CTRL2; 1245 1246#endif /* SMU_7_1_2_ENUM_H */
~/
Read-only file preview.