FILE
smu_6_0_sh_mask.h
File preview with syntax highlighting.
linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h
1/* 2 * 3 * Copyright (C) 2016 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included 13 * in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23#ifndef SMU_6_0_SH_MASK_H 24#define SMU_6_0_SH_MASK_H 25 26#define CG_AT__CG_R_MASK 0x0000FFFFL 27#define CG_AT__CG_R__SHIFT 0x00000000 28#define CG_AT__CG_L_MASK 0xFFFF0000L 29#define CG_AT__CG_L__SHIFT 0x00000010 30 31#define CG_BSP__BSP_MASK 0x0000FFFFL 32#define CG_BSP__BSP__SHIFT 0x00000000 33#define CG_BSP__BSU_MASK 0x000F0000L 34#define CG_BSP__BSU__SHIFT 0x00000010 35 36#define CG_CAC_CTRL__CAC_WINDOW_MASK 0x00FFFFFFL 37#define CG_CAC_CTRL__CAC_WINDOW__SHIFT 0x00000000 38 39#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x00000002L 40#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x00000001 41#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x00000004L 42#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x00000002 43#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x00000008L 44#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x00000003 45#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x00000100L 46#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x00000008 47 48#define CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK 0x00000003L 49#define CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT 0x00000000 50#define CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK 0x0000000CL 51#define CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT 0x00000002 52#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x0003FFF0L 53#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x00000004 54#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x00700000 55#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x00000014 56#define CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG_MASK 0x03000000L 57#define CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG__SHIFT 0x00000018 58#define CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG_MASK 0x0C000000L 59#define CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG__SHIFT 0x0000001A 60 61#define CG_FFCT_0__UTC_0_MASK 0x000003FFL 62#define CG_FFCT_0__UTC_0__SHIFT 0x00000000 63#define CG_FFCT_0__DTC_0_MASK 0x000FFC00L 64#define CG_FFCT_0__DTC_0__SHIFT 0x0000000A 65 66#define CG_GIT__CG_GICST_MASK 0x0000FFFFL 67#define CG_GIT__CG_GICST__SHIFT 0x00000000 68#define CG_GIT__CG_GIPOT_MASK 0xFFFF0000L 69#define CG_GIT__CG_GIPOT__SHIFT 0x00000010 70 71#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x00000001L 72#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x00000000 73#define CG_SPLL_FUNC_CNTL__SPLL_SLEEP_MASK 0x00000002L 74#define CG_SPLL_FUNC_CNTL__SPLL_SLEEP__SHIFT 0x00000001 75#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x00000008L 76#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x00000003 77#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x000003F0L 78#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x00000004 79#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x007F00000 80#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x00000014 81#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x0000001FF 82#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x00000000 83#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x00800000 84#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x00000017 85#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x04000000 86#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x0000001A 87#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x03FFFFFFL 88#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x00000000 89#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000L 90#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x0000001C 91#define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x00000002L 92#define CG_SPLL_STATUS__SPLL_CHG_STATUS__SHIFT 0x00000001 93#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x00000001L 94#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x00000000 95#define CG_SPLL_SPREAD_SPECTRUM__CLK_S_MASK 0x0000FFF0L 96#define CG_SPLL_SPREAD_SPECTRUM__CLK_S__SHIFT 0x00000004 97#define CG_SPLL_SPREAD_SPECTRUM_2__CLK_V_MASK 0x00000200L 98#define CG_SPLL_SPREAD_SPECTRUM_2__CLK_V__SHIFT 0x00000000 99#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK 0x03FFFFFFL 100#define CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR__SHIFT 0x00000009 101 102#define CG_SSP__SST_MASK 0x0000FFFFL 103#define CG_SSP__SST__SHIFT 0x00000000 104#define CG_SSP__SSTU_MASK 0x000F0000L 105#define CG_SSP__SSTU__SHIFT 0x00000010 106 107#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x00000007L 108#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x00000000 109#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x003FC000 110#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0x0000000E 111#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x0001FE00L 112#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x00000009 113#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0x0000FF00L 114#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x00000008 115#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0x00FF0000L 116#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x00000010 117#define CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK 0x01000000L 118#define CG_THERMAL_INT__THERM_INT_MASK_HIGH__SHIFT 0x00000018 119#define CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK 0x02000000 120#define CG_THERMAL_INT__THERM_INT_MASK_LOW__SHIFT 0x00000019 121 122#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0x0FF00000L 123#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x00000014 124#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x000001FFL 125#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x00000000 126#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x0003fe00L 127#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x00000009 128 129#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0x000000FFL 130#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x00000000 131#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0x000000FFL 132#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x00000000 133#define CG_FDO_CTRL2__TMIN_MASK 0x000000FFL 134#define CG_FDO_CTRL2__TMIN__SHIFT 0x00000000 135#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x00003800L 136#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0x0000000B 137#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xFE000000L 138#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x00000019 139 140#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x00000007L 141#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x00000000 142#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L 143#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x00000003 144#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL 145#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x00000000 146 147#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x00000001L 148#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x00000000 149#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x00000002L 150#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x00000001 151#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x00000004L 152#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x00000002 153#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x00000008L 154#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x00000003 155#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x00000040L 156#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x00000006 157#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x00000400L 158#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0x0000000A 159#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x00800000L 160#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x00000017 161 162#define GPIOPAD_A__GPIO_A_MASK 0x7fffffffL 163#define GPIOPAD_A__GPIO_A__SHIFT 0x00000000 164#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffffL 165#define GPIOPAD_EN__GPIO_EN__SHIFT 0x00000000 166#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x00000020L 167#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x00000005 168#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x00000040L 169#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x00000006 170#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x0000001fL 171#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x00000000 172#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffffL 173#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x00000000 174#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L 175#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x0000001f 176#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffffL 177#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x00000000 178#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L 179#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x0000001f 180#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L 181#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x00000000 182#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L 183#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0x0000000a 184#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L 185#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0x0000000b 186#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L 187#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0x0000000c 188#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L 189#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0x0000000d 190#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L 191#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0x0000000e 192#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L 193#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0x0000000f 194#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L 195#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x00000010 196#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L 197#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x00000011 198#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L 199#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x00000012 200#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L 201#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x00000013 202#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L 203#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x00000001 204#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L 205#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x00000014 206#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L 207#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x00000015 208#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L 209#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x00000016 210#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L 211#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x00000017 212#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L 213#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x00000018 214#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L 215#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x00000019 216#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L 217#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x0000001a 218#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L 219#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x0000001b 220#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L 221#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x0000001c 222#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L 223#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x00000002 224#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L 225#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x00000003 226#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L 227#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x00000004 228#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L 229#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x00000005 230#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L 231#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x00000006 232#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L 233#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x00000007 234#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L 235#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x00000008 236#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L 237#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x00000009 238#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L 239#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x0000001f 240#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffffL 241#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x00000000 242#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L 243#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x0000001f 244#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffffL 245#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x00000000 246#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L 247#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x0000001f 248#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffffL 249#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x00000000 250#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L 251#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x0000001f 252#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffffL 253#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x00000000 254#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffffL 255#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x00000000 256#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L 257#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x00000000 258#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L 259#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0x0000000a 260#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L 261#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0x0000000b 262#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L 263#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0x0000000c 264#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L 265#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0x0000000d 266#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L 267#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0x0000000e 268#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L 269#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0x0000000f 270#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L 271#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x00000010 272#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L 273#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x00000011 274#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L 275#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x00000012 276#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L 277#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x00000013 278#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L 279#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x00000001 280#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L 281#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x00000014 282#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L 283#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x00000015 284#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L 285#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x00000016 286#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L 287#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x00000017 288#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L 289#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x00000018 290#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L 291#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x00000019 292#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L 293#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x0000001a 294#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L 295#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x0000001b 296#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L 297#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x0000001c 298#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L 299#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x0000001d 300#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L 301#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x00000002 302#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L 303#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x0000001e 304#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L 305#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x00000003 306#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L 307#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x00000004 308#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L 309#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x00000005 310#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L 311#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x00000006 312#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L 313#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x00000007 314#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L 315#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x00000008 316#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L 317#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x00000009 318#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffffL 319#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x00000000 320#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffffL 321#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x00000000 322#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0x0000000fL 323#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x00000000 324#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0x000000f0L 325#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x00000004 326#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L 327#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x00000000 328#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffffL 329#define GPIOPAD_Y__GPIO_Y__SHIFT 0x00000000 330 331#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x00000001L 332#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x00000000 333#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x0001fffeL 334#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x00000001 335#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffffL 336#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x00000000 337#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffffL 338#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x00000000 339#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x00000001L 340#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x00000000 341#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x0001fffeL 342#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x00000001 343#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffffL 344#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x00000000 345#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffffL 346#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x00000000 347#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x00000001L 348#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x00000000 349#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x0001fffeL 350#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x00000001 351#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffffL 352#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x00000000 353#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffffL 354#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x00000000 355#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x00000001L 356#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x00000000 357#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x0001fffeL 358#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x00000001 359#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffffL 360#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x00000000 361#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffffL 362#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x00000000 363#define LCAC_MC4_CNTL__MC4_ENABLE_MASK 0x00000001L 364#define LCAC_MC4_CNTL__MC4_ENABLE__SHIFT 0x00000000 365#define LCAC_MC4_CNTL__MC4_THRESHOLD_MASK 0x0001fffeL 366#define LCAC_MC4_CNTL__MC4_THRESHOLD__SHIFT 0x00000001 367#define LCAC_MC4_OVR_SEL__MC4_OVR_SEL_MASK 0xffffffffL 368#define LCAC_MC4_OVR_SEL__MC4_OVR_SEL__SHIFT 0x00000000 369#define LCAC_MC4_OVR_VAL__MC4_OVR_VAL_MASK 0xffffffffL 370#define LCAC_MC4_OVR_VAL__MC4_OVR_VAL__SHIFT 0x00000000 371#define LCAC_MC5_CNTL__MC5_ENABLE_MASK 0x00000001L 372#define LCAC_MC5_CNTL__MC5_ENABLE__SHIFT 0x00000000 373#define LCAC_MC5_CNTL__MC5_THRESHOLD_MASK 0x0001fffeL 374#define LCAC_MC5_CNTL__MC5_THRESHOLD__SHIFT 0x00000001 375#define LCAC_MC5_OVR_SEL__MC5_OVR_SEL_MASK 0xffffffffL 376#define LCAC_MC5_OVR_SEL__MC5_OVR_SEL__SHIFT 0x00000000 377#define LCAC_MC5_OVR_VAL__MC5_OVR_VAL_MASK 0xffffffffL 378#define LCAC_MC5_OVR_VAL__MC5_OVR_VAL__SHIFT 0x00000000 379 380#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0x0000FF00L 381#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x00000008 382 383#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x00000001L 384#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x00000000 385#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1_MASK 0x00000002L 386#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1__SHIFT 0x00000001 387#define SCLK_PWRMGT_CNTL__FIR_RESET_MASK 0x00000010L 388#define SCLK_PWRMGT_CNTL__FIR_RESET__SHIFT 0x00000004 389#define SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK 0x00000020L 390#define SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL__SHIFT 0x00000005 391#define SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK 0x00000040L 392#define SCLK_PWRMGT_CNTL__FIR_TREND_MODE__SHIFT 0x00000006 393#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN_MASK 0x00000080L 394#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN__SHIFT 0x00000007 395#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON_MASK 0x00000100L 396#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON__SHIFT 0x00000008 397#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF_MASK 0x00000200L 398#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF__SHIFT 0x00000009 399#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF_MASK 0x00000400L 400#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF__SHIFT 0x0000000A 401#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1_MASK 0x00000800L 402#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1__SHIFT 0x0000000B 403#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2_MASK 0x00001000L 404#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2__SHIFT 0x0000000C 405#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3_MASK 0x00002000L 406#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3__SHIFT 0x0000000D 407#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x00004000L 408#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0x0000000E 409 410#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x00000001L 411#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x00000000 412#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x00000100L 413#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x00000008 414#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x00010000L 415#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x00000010 416#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x01000000L 417#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x00000018 418#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffffL 419#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x00000000 420#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffffL 421#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x00000000 422#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffffL 423#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x00000000 424#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffffL 425#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x00000000 426#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffffL 427#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x00000000 428#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffffL 429#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x00000000 430#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffffL 431#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x00000000 432#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffffL 433#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x00000000 434#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffffL 435#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x00000000 436#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffffL 437#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x00000000 438#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffffffffL 439#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x00000000 440#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffffffffL 441#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x00000000 442#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffffffffL 443#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x00000000 444#define SMC_PC_C__smc_pc_c_MASK 0xffffffffL 445#define SMC_PC_C__smc_pc_c__SHIFT 0x00000000 446#define SMC_RESP_0__SMC_RESP_MASK 0xffffffffL 447#define SMC_RESP_0__SMC_RESP__SHIFT 0x00000000 448#define SMC_RESP_1__SMC_RESP_MASK 0xffffffffL 449#define SMC_RESP_1__SMC_RESP__SHIFT 0x00000000 450#define SMC_RESP_2__SMC_RESP_MASK 0xffffffffL 451#define SMC_RESP_2__SMC_RESP__SHIFT 0x00000000 452 453#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0x000ff000L 454#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0x0000000c 455#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x00000010L 456#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x00000004 457#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x00000008L 458#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x00000003 459#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x00000002L 460#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x00000001 461#define SPLL_CNTL_MODE__SPLL_REFCLK_SEL_MASK 0x0C000000L 462#define SPLL_CNTL_MODE__SPLL_REFCLK_SEL__SHIFT 0x0000001A 463#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000L 464#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x0000001c 465#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x00000001L 466#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x00000000 467#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0x00000c00L 468#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0x0000000a 469#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x00000004L 470#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x00000002 471#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000L 472#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x0000001d 473 474#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0x0f000000L 475#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x00000018 476#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000L 477#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x0000001c 478 479#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK 0x000000F0L 480#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX__SHIFT 0x00000004 481 482#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0x000000FFL 483#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x00000000 484#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0x0000FF00L 485#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x00000008 486 487#define MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL_MASK 0x000000FFL 488#define MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL__SHIFT 0x00000000 489#define MISC_CLK_CNTL__ZCLK_SEL_MASK 0x0000FF00L 490#define MISC_CLK_CNTL__ZCLK_SEL__SHIFT 0x00000008 491 492#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x0000001fL 493#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x00000000 494#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0x0000ffe0L 495#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x00000005 496#define THM_TMON0_INT_DATA__TEMP_MASK 0x00fff000L 497#define THM_TMON0_INT_DATA__TEMP__SHIFT 0x0000000c 498#define THM_TMON0_INT_DATA__VALID_MASK 0x00000800L 499#define THM_TMON0_INT_DATA__VALID__SHIFT 0x0000000b 500#define THM_TMON0_INT_DATA__Z_MASK 0x000007ffL 501#define THM_TMON0_INT_DATA__Z__SHIFT 0x00000000 502#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0x00fff000L 503#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0x0000000c 504#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x00000800L 505#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0x0000000b 506#define THM_TMON0_RDIL0_DATA__Z_MASK 0x000007ffL 507#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x00000000 508#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0x00fff000L 509#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0x0000000c 510#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x00000800L 511#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0x0000000b 512#define THM_TMON0_RDIL10_DATA__Z_MASK 0x000007ffL 513#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x00000000 514#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0x00fff000L 515#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0x0000000c 516#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x00000800L 517#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0x0000000b 518#define THM_TMON0_RDIL11_DATA__Z_MASK 0x000007ffL 519#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x00000000 520#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0x00fff000L 521#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0x0000000c 522#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x00000800L 523#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0x0000000b 524#define THM_TMON0_RDIL12_DATA__Z_MASK 0x000007ffL 525#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x00000000 526#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0x00fff000L 527#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0x0000000c 528#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x00000800L 529#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0x0000000b 530#define THM_TMON0_RDIL13_DATA__Z_MASK 0x000007ffL 531#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x00000000 532#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0x00fff000L 533#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0x0000000c 534#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x00000800L 535#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0x0000000b 536#define THM_TMON0_RDIL14_DATA__Z_MASK 0x000007ffL 537#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x00000000 538#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0x00fff000L 539#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0x0000000c 540#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x00000800L 541#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0x0000000b 542#define THM_TMON0_RDIL15_DATA__Z_MASK 0x000007ffL 543#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x00000000 544#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0x00fff000L 545#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0x0000000c 546#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x00000800L 547#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0x0000000b 548#define THM_TMON0_RDIL1_DATA__Z_MASK 0x000007ffL 549#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x00000000 550#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0x00fff000L 551#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0x0000000c 552#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x00000800L 553#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0x0000000b 554#define THM_TMON0_RDIL2_DATA__Z_MASK 0x000007ffL 555#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x00000000 556#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0x00fff000L 557#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0x0000000c 558#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x00000800L 559#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0x0000000b 560#define THM_TMON0_RDIL3_DATA__Z_MASK 0x000007ffL 561#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x00000000 562#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0x00fff000L 563#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0x0000000c 564#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x00000800L 565#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0x0000000b 566#define THM_TMON0_RDIL4_DATA__Z_MASK 0x000007ffL 567#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x00000000 568#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0x00fff000L 569#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0x0000000c 570#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x00000800L 571#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0x0000000b 572#define THM_TMON0_RDIL5_DATA__Z_MASK 0x000007ffL 573#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x00000000 574#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0x00fff000L 575#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0x0000000c 576#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x00000800L 577#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0x0000000b 578#define THM_TMON0_RDIL6_DATA__Z_MASK 0x000007ffL 579#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x00000000 580#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0x00fff000L 581#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0x0000000c 582#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x00000800L 583#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0x0000000b 584#define THM_TMON0_RDIL7_DATA__Z_MASK 0x000007ffL 585#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x00000000 586#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0x00fff000L 587#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0x0000000c 588#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x00000800L 589#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0x0000000b 590#define THM_TMON0_RDIL8_DATA__Z_MASK 0x000007ffL 591#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x00000000 592#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0x00fff000L 593#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0x0000000c 594#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x00000800L 595#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0x0000000b 596#define THM_TMON0_RDIL9_DATA__Z_MASK 0x000007ffL 597#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x00000000 598#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0x00fff000L 599#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0x0000000c 600#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x00000800L 601#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0x0000000b 602#define THM_TMON0_RDIR0_DATA__Z_MASK 0x000007ffL 603#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x00000000 604#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0x00fff000L 605#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0x0000000c 606#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x00000800L 607#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0x0000000b 608#define THM_TMON0_RDIR10_DATA__Z_MASK 0x000007ffL 609#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x00000000 610#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0x00fff000L 611#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0x0000000c 612#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x00000800L 613#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0x0000000b 614#define THM_TMON0_RDIR11_DATA__Z_MASK 0x000007ffL 615#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x00000000 616#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0x00fff000L 617#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0x0000000c 618#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x00000800L 619#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0x0000000b 620#define THM_TMON0_RDIR12_DATA__Z_MASK 0x000007ffL 621#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x00000000 622#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0x00fff000L 623#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0x0000000c 624#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x00000800L 625#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0x0000000b 626#define THM_TMON0_RDIR13_DATA__Z_MASK 0x000007ffL 627#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x00000000 628#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0x00fff000L 629#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0x0000000c 630#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x00000800L 631#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0x0000000b 632#define THM_TMON0_RDIR14_DATA__Z_MASK 0x000007ffL 633#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x00000000 634#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0x00fff000L 635#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0x0000000c 636#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x00000800L 637#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0x0000000b 638#define THM_TMON0_RDIR15_DATA__Z_MASK 0x000007ffL 639#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x00000000 640#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0x00fff000L 641#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0x0000000c 642#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x00000800L 643#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0x0000000b 644#define THM_TMON0_RDIR1_DATA__Z_MASK 0x000007ffL 645#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x00000000 646#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0x00fff000L 647#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0x0000000c 648#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x00000800L 649#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0x0000000b 650#define THM_TMON0_RDIR2_DATA__Z_MASK 0x000007ffL 651#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x00000000 652#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0x00fff000L 653#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0x0000000c 654#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x00000800L 655#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0x0000000b 656#define THM_TMON0_RDIR3_DATA__Z_MASK 0x000007ffL 657#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x00000000 658#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0x00fff000L 659#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0x0000000c 660#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x00000800L 661#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0x0000000b 662#define THM_TMON0_RDIR4_DATA__Z_MASK 0x000007ffL 663#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x00000000 664#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0x00fff000L 665#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0x0000000c 666#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x00000800L 667#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0x0000000b 668#define THM_TMON0_RDIR5_DATA__Z_MASK 0x000007ffL 669#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x00000000 670#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0x00fff000L 671#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0x0000000c 672#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x00000800L 673#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0x0000000b 674#define THM_TMON0_RDIR6_DATA__Z_MASK 0x000007ffL 675#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x00000000 676#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0x00fff000L 677#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0x0000000c 678#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x00000800L 679#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0x0000000b 680#define THM_TMON0_RDIR7_DATA__Z_MASK 0x000007ffL 681#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x00000000 682#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0x00fff000L 683#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0x0000000c 684#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x00000800L 685#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0x0000000b 686#define THM_TMON0_RDIR8_DATA__Z_MASK 0x000007ffL 687#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x00000000 688#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0x00fff000L 689#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0x0000000c 690#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x00000800L 691#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0x0000000b 692#define THM_TMON0_RDIR9_DATA__Z_MASK 0x000007ffL 693#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x00000000 694#define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x0000001fL 695#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x00000000 696#define THM_TMON1_DEBUG__DEBUG_Z_MASK 0x0000ffe0L 697#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x00000005 698#define THM_TMON1_INT_DATA__TEMP_MASK 0x00fff000L 699#define THM_TMON1_INT_DATA__TEMP__SHIFT 0x0000000c 700#define THM_TMON1_INT_DATA__VALID_MASK 0x00000800L 701#define THM_TMON1_INT_DATA__VALID__SHIFT 0x0000000b 702#define THM_TMON1_INT_DATA__Z_MASK 0x000007ffL 703#define THM_TMON1_INT_DATA__Z__SHIFT 0x00000000 704#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0x00fff000L 705#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0x0000000c 706#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x00000800L 707#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0x0000000b 708#define THM_TMON1_RDIL0_DATA__Z_MASK 0x000007ffL 709#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x00000000 710#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0x00fff000L 711#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0x0000000c 712#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x00000800L 713#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0x0000000b 714#define THM_TMON1_RDIL10_DATA__Z_MASK 0x000007ffL 715#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x00000000 716#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0x00fff000L 717#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0x0000000c 718#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x00000800L 719#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0x0000000b 720#define THM_TMON1_RDIL11_DATA__Z_MASK 0x000007ffL 721#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x00000000 722#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0x00fff000L 723#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0x0000000c 724#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x00000800L 725#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0x0000000b 726#define THM_TMON1_RDIL12_DATA__Z_MASK 0x000007ffL 727#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x00000000 728#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0x00fff000L 729#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0x0000000c 730#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x00000800L 731#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0x0000000b 732#define THM_TMON1_RDIL13_DATA__Z_MASK 0x000007ffL 733#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x00000000 734#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0x00fff000L 735#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0x0000000c 736#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x00000800L 737#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0x0000000b 738#define THM_TMON1_RDIL14_DATA__Z_MASK 0x000007ffL 739#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x00000000 740#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0x00fff000L 741#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0x0000000c 742#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x00000800L 743#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0x0000000b 744#define THM_TMON1_RDIL15_DATA__Z_MASK 0x000007ffL 745#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x00000000 746#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0x00fff000L 747#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0x0000000c 748#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x00000800L 749#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0x0000000b 750#define THM_TMON1_RDIL1_DATA__Z_MASK 0x000007ffL 751#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x00000000 752#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0x00fff000L 753#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0x0000000c 754#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x00000800L 755#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0x0000000b 756#define THM_TMON1_RDIL2_DATA__Z_MASK 0x000007ffL 757#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x00000000 758#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0x00fff000L 759#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0x0000000c 760#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x00000800L 761#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0x0000000b 762#define THM_TMON1_RDIL3_DATA__Z_MASK 0x000007ffL 763#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x00000000 764#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0x00fff000L 765#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0x0000000c 766#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x00000800L 767#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0x0000000b 768#define THM_TMON1_RDIL4_DATA__Z_MASK 0x000007ffL 769#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x00000000 770#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0x00fff000L 771#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0x0000000c 772#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x00000800L 773#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0x0000000b 774#define THM_TMON1_RDIL5_DATA__Z_MASK 0x000007ffL 775#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x00000000 776#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0x00fff000L 777#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0x0000000c 778#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x00000800L 779#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0x0000000b 780#define THM_TMON1_RDIL6_DATA__Z_MASK 0x000007ffL 781#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x00000000 782#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0x00fff000L 783#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0x0000000c 784#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x00000800L 785#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0x0000000b 786#define THM_TMON1_RDIL7_DATA__Z_MASK 0x000007ffL 787#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x00000000 788#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0x00fff000L 789#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0x0000000c 790#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x00000800L 791#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0x0000000b 792#define THM_TMON1_RDIL8_DATA__Z_MASK 0x000007ffL 793#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x00000000 794#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0x00fff000L 795#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0x0000000c 796#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x00000800L 797#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0x0000000b 798#define THM_TMON1_RDIL9_DATA__Z_MASK 0x000007ffL 799#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x00000000 800#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0x00fff000L 801#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0x0000000c 802#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x00000800L 803#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0x0000000b 804#define THM_TMON1_RDIR0_DATA__Z_MASK 0x000007ffL 805#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x00000000 806#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0x00fff000L 807#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0x0000000c 808#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x00000800L 809#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0x0000000b 810#define THM_TMON1_RDIR10_DATA__Z_MASK 0x000007ffL 811#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x00000000 812#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0x00fff000L 813#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0x0000000c 814#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x00000800L 815#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0x0000000b 816#define THM_TMON1_RDIR11_DATA__Z_MASK 0x000007ffL 817#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x00000000 818#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0x00fff000L 819#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0x0000000c 820#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x00000800L 821#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0x0000000b 822#define THM_TMON1_RDIR12_DATA__Z_MASK 0x000007ffL 823#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x00000000 824#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0x00fff000L 825#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0x0000000c 826#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x00000800L 827#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0x0000000b 828#define THM_TMON1_RDIR13_DATA__Z_MASK 0x000007ffL 829#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x00000000 830#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0x00fff000L 831#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0x0000000c 832#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x00000800L 833#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0x0000000b 834#define THM_TMON1_RDIR14_DATA__Z_MASK 0x000007ffL 835#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x00000000 836#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0x00fff000L 837#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0x0000000c 838#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x00000800L 839#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0x0000000b 840#define THM_TMON1_RDIR15_DATA__Z_MASK 0x000007ffL 841#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x00000000 842#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0x00fff000L 843#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0x0000000c 844#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x00000800L 845#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0x0000000b 846#define THM_TMON1_RDIR1_DATA__Z_MASK 0x000007ffL 847#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x00000000 848#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0x00fff000L 849#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0x0000000c 850#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x00000800L 851#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0x0000000b 852#define THM_TMON1_RDIR2_DATA__Z_MASK 0x000007ffL 853#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x00000000 854#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0x00fff000L 855#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0x0000000c 856#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x00000800L 857#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0x0000000b 858#define THM_TMON1_RDIR3_DATA__Z_MASK 0x000007ffL 859#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x00000000 860#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0x00fff000L 861#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0x0000000c 862#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x00000800L 863#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0x0000000b 864#define THM_TMON1_RDIR4_DATA__Z_MASK 0x000007ffL 865#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x00000000 866#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0x00fff000L 867#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0x0000000c 868#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x00000800L 869#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0x0000000b 870#define THM_TMON1_RDIR5_DATA__Z_MASK 0x000007ffL 871#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x00000000 872#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0x00fff000L 873#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0x0000000c 874#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x00000800L 875#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0x0000000b 876#define THM_TMON1_RDIR6_DATA__Z_MASK 0x000007ffL 877#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x00000000 878#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0x00fff000L 879#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0x0000000c 880#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x00000800L 881#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0x0000000b 882#define THM_TMON1_RDIR7_DATA__Z_MASK 0x000007ffL 883#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x00000000 884#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0x00fff000L 885#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0x0000000c 886#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x00000800L 887#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0x0000000b 888#define THM_TMON1_RDIR8_DATA__Z_MASK 0x000007ffL 889#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x00000000 890#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0x00fff000L 891#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0x0000000c 892#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x00000800L 893#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0x0000000b 894#define THM_TMON1_RDIR9_DATA__Z_MASK 0x000007ffL 895#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x00000000 896 897#endif
~/
Read-only file preview.