FILE
sdma1_4_2_sh_mask.h
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linux-6.19.14/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h
1/* 2 * Copyright (C) 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _sdma1_4_2_0_SH_MASK_HEADER 22#define _sdma1_4_2_0_SH_MASK_HEADER 23 24 25// addressBlock: sdma1_sdma1dec 26//SDMA1_UCODE_ADDR 27#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 28#define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL 29//SDMA1_UCODE_DATA 30#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 31#define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 32//SDMA1_VM_CNTL 33#define SDMA1_VM_CNTL__CMD__SHIFT 0x0 34#define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL 35//SDMA1_VM_CTX_LO 36#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 37#define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 38//SDMA1_VM_CTX_HI 39#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 40#define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 41//SDMA1_ACTIVE_FCN_ID 42#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 43#define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 44#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f 45#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 46#define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 47#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L 48//SDMA1_VM_CTX_CNTL 49#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 50#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 51#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L 52#define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L 53//SDMA1_VIRT_RESET_REQ 54#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 55#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f 56#define SDMA1_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 57#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L 58//SDMA1_VF_ENABLE 59#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 60#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 61//SDMA1_CONTEXT_REG_TYPE0 62#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 63#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 64#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 65#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 66#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4 67#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5 68#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6 69#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 70#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 71#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 72#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa 73#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb 74#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc 75#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd 76#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe 77#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf 78#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 79#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 80#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 81#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 82#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L 83#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L 84#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L 85#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L 86#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L 87#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L 88#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L 89#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 90#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 91#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 92#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L 93#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L 94#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L 95#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L 96#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L 97#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L 98#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L 99#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L 100#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L 101#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L 102//SDMA1_CONTEXT_REG_TYPE1 103#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8 104#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 105#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa 106#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb 107#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc 108#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd 109#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 110#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf 111#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 112#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 113#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 114#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 115#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14 116#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 117#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 118#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L 119#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x00000200L 120#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L 121#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L 122#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L 123#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L 124#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 125#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L 126#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L 127#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L 128#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 129#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 130#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L 131#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 132#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 133//SDMA1_CONTEXT_REG_TYPE2 134#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 135#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 136#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 137#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 138#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 139#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 140#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6 141#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7 142#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8 143#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9 144#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 145#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L 146#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L 147#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L 148#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L 149#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L 150#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L 151#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L 152#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L 153#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L 154#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L 155#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 156//SDMA1_CONTEXT_REG_TYPE3 157#define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 158#define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 159//SDMA1_PUB_REG_TYPE0 160#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 161#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 162#define SDMA1_PUB_REG_TYPE0__SDMA1_REGISTER_SECURITY_CNTL__SHIFT 0x2 163#define SDMA1_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 164#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT 0x4 165#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT 0x5 166#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT 0x6 167#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT 0x7 168#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT 0x8 169#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT 0x9 170#define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 171#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT 0xb 172#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT 0xc 173#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT 0xd 174#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT 0xe 175#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT 0xf 176#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT 0x10 177#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT 0x11 178#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT 0x12 179#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL__SHIFT 0x13 180#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 181#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 182#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x1a 183#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x1b 184#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x1c 185#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d 186#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x1e 187#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x1f 188#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L 189#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L 190#define SDMA1_PUB_REG_TYPE0__SDMA1_REGISTER_SECURITY_CNTL_MASK 0x00000004L 191#define SDMA1_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 192#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK 0x00000010L 193#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK 0x00000020L 194#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK 0x00000040L 195#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK 0x00000080L 196#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK 0x00000100L 197#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK 0x00000200L 198#define SDMA1_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 199#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK 0x00000800L 200#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK 0x00001000L 201#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK 0x00002000L 202#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK 0x00004000L 203#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK 0x00008000L 204#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK 0x00010000L 205#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK 0x00020000L 206#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK 0x00040000L 207#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL_MASK 0x00080000L 208#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L 209#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 210#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L 211#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x08000000L 212#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L 213#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L 214#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L 215#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L 216//SDMA1_PUB_REG_TYPE1 217#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x0 218#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 219#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x2 220#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x3 221#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x4 222#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x5 223#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x6 224#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT 0x7 225#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x8 226#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x9 227#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa 228#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0xb 229#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT 0xc 230#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT 0xd 231#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 232#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 233#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 234#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 235#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x12 236#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x13 237#define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x14 238#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x15 239#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x16 240#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x17 241#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x18 242#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x19 243#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x1a 244#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x1b 245#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x1c 246#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d 247#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT 0x1e 248#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT 0x1f 249#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000001L 250#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 251#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000004L 252#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L 253#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L 254#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L 255#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L 256#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK 0x00000080L 257#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L 258#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L 259#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK 0x00000400L 260#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L 261#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK 0x00001000L 262#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK 0x00002000L 263#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 264#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 265#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 266#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 267#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L 268#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L 269#define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L 270#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L 271#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L 272#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L 273#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L 274#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L 275#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L 276#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L 277#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L 278#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L 279#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK 0x40000000L 280#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK 0x80000000L 281//SDMA1_PUB_REG_TYPE2 282#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x0 283#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x1 284#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x2 285#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x3 286#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x4 287#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x5 288#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x6 289#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT 0x7 290#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT 0x8 291#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE__SHIFT 0x9 292#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa 293#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0xb 294#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0xc 295#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0xd 296#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0xe 297#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT 0xf 298#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x10 299#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x11 300#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x12 301#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x13 302#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x14 303#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x15 304#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL__SHIFT 0x17 305#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x18 306#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x19 307#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 308#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x1b 309#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 310#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL__SHIFT 0x1e 311#define SDMA1_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 312#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000001L 313#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000002L 314#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000004L 315#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000008L 316#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000010L 317#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000020L 318#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000040L 319#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK 0x00000080L 320#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK 0x00000100L 321#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE_MASK 0x00000200L 322#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L 323#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L 324#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L 325#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L 326#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L 327#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK 0x00008000L 328#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L 329#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L 330#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L 331#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L 332#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L 333#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L 334#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL_MASK 0x00800000L 335#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT_MASK 0x01000000L 336#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT_MASK 0x02000000L 337#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 338#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L 339#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 340#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL_MASK 0x40000000L 341#define SDMA1_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 342//SDMA1_PUB_REG_TYPE3 343#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x0 344#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x1 345#define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 346#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L 347#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 348#define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL 349//SDMA1_MMHUB_CNTL 350#define SDMA1_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 351#define SDMA1_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 352//SDMA1_CONTEXT_GROUP_BOUNDARY 353#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 354#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 355//SDMA1_POWER_CNTL 356#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 357#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 358#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 359#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 360#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 361#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 362#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 363#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 364#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 365#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 366//SDMA1_CLK_CTRL 367#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 368#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 369#define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc 370#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 371#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 372#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 373#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 374#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 375#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 376#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 377#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 378#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 379#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 380#define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L 381#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 382#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 383#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 384#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 385#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 386#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 387#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 388#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 389//SDMA1_CNTL 390#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 391#define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1 392#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 393#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 394#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 395#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 396#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 397#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 398#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 399#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 400#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 401#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L 402#define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 403#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 404#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 405#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 406#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 407#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 408#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 409#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 410#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 411#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 412//SDMA1_CHICKEN_BITS 413#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 414#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 415#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 416#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 417#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 418#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 419#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 420#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 421#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 422#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 423#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 424#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 425#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 426#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 427#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 428#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 429#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 430#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 431#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 432#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 433#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 434#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 435#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 436#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 437#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 438#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 439//SDMA1_GB_ADDR_CONFIG 440#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 441#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 442#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 443#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 444#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 445#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 446#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 447#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 448#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 449#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 450//SDMA1_GB_ADDR_CONFIG_READ 451#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 452#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 453#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 454#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 455#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 456#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 457#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 458#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 459#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 460#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 461//SDMA1_RB_RPTR_FETCH_HI 462#define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 463#define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 464//SDMA1_SEM_WAIT_FAIL_TIMER_CNTL 465#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 466#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 467//SDMA1_RB_RPTR_FETCH 468#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 469#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 470//SDMA1_IB_OFFSET_FETCH 471#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 472#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 473//SDMA1_PROGRAM 474#define SDMA1_PROGRAM__STREAM__SHIFT 0x0 475#define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL 476//SDMA1_STATUS_REG 477#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 478#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 479#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 480#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 481#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 482#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 483#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 484#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 485#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 486#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 487#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa 488#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 489#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc 490#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 491#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe 492#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 493#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 494#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 495#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 496#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 497#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 498#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 499#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 500#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 501#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a 502#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 503#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 504#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e 505#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 506#define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L 507#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L 508#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L 509#define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L 510#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 511#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 512#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 513#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 514#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 515#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L 516#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L 517#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 518#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L 519#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 520#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 521#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 522#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 523#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 524#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 525#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 526#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 527#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 528#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 529#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 530#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L 531#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 532#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 533#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L 534#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 535//SDMA1_STATUS1_REG 536#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 537#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 538#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 539#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 540#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 541#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 542#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 543#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 544#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 545#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 546#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 547#define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf 548#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 549#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 550#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 551#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 552#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 553#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 554#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 555#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 556#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 557#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 558#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 559#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 560#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 561#define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L 562#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 563#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 564//SDMA1_RD_BURST_CNTL 565#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 566#define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 567#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 568#define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 569//SDMA1_HBM_PAGE_CONFIG 570#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 571#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L 572//SDMA1_UCODE_CHECKSUM 573#define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 574#define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 575//SDMA1_F32_CNTL 576#define SDMA1_F32_CNTL__HALT__SHIFT 0x0 577#define SDMA1_F32_CNTL__STEP__SHIFT 0x1 578#define SDMA1_F32_CNTL__HALT_MASK 0x00000001L 579#define SDMA1_F32_CNTL__STEP_MASK 0x00000002L 580//SDMA1_FREEZE 581#define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 582#define SDMA1_FREEZE__FREEZE__SHIFT 0x4 583#define SDMA1_FREEZE__FROZEN__SHIFT 0x5 584#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 585#define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L 586#define SDMA1_FREEZE__FREEZE_MASK 0x00000010L 587#define SDMA1_FREEZE__FROZEN_MASK 0x00000020L 588#define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L 589//SDMA1_PHASE0_QUANTUM 590#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 591#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 592#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 593#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 594#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 595#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 596//SDMA1_PHASE1_QUANTUM 597#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 598#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 599#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 600#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 601#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 602#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 603//SDMA1_EDC_CONFIG 604#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 605#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 606#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 607#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 608//SDMA1_BA_THRESHOLD 609#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 610#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 611#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 612#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 613//SDMA1_ID 614#define SDMA1_ID__DEVICE_ID__SHIFT 0x0 615#define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL 616//SDMA1_VERSION 617#define SDMA1_VERSION__MINVER__SHIFT 0x0 618#define SDMA1_VERSION__MAJVER__SHIFT 0x8 619#define SDMA1_VERSION__REV__SHIFT 0x10 620#define SDMA1_VERSION__MINVER_MASK 0x0000007FL 621#define SDMA1_VERSION__MAJVER_MASK 0x00007F00L 622#define SDMA1_VERSION__REV_MASK 0x003F0000L 623//SDMA1_EDC_COUNTER 624#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 625#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 626#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 627#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 628#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 629#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 630#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 631#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 632#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 633#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 634#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 635#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 636#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 637#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 638#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf 639#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 640#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 641#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 642#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 643#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 644#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 645#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 646#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 647#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 648#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L 649#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 650#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 651#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 652#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 653#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 654#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 655#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 656#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 657#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 658#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 659#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 660#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 661#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 662#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L 663#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L 664#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L 665#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L 666#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L 667#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L 668#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L 669#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L 670#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L 671#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L 672//SDMA1_EDC_COUNTER_CLEAR 673#define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 674#define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 675//SDMA1_STATUS2_REG 676#define SDMA1_STATUS2_REG__ID__SHIFT 0x0 677#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 678#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 679#define SDMA1_STATUS2_REG__ID_MASK 0x00000003L 680#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL 681#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 682//SDMA1_ATOMIC_CNTL 683#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 684#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 685#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 686#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 687//SDMA1_ATOMIC_PREOP_LO 688#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 689#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 690//SDMA1_ATOMIC_PREOP_HI 691#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 692#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 693//SDMA1_UTCL1_CNTL 694#define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 695#define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 696#define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 697#define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 698#define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 699#define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 700#define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 701#define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 702#define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 703#define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 704#define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 705#define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 706//SDMA1_UTCL1_WATERMK 707#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 708#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 709#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 710#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 711#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL 712#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L 713#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L 714#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L 715//SDMA1_UTCL1_RD_STATUS 716#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 717#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 718#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 719#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 720#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 721#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 722#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 723#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 724#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 725#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 726#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 727#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 728#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 729#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 730#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 731#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 732#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 733#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 734#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 735#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 736#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 737#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 738#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 739#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 740#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 741#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 742#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 743#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 744#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 745#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 746#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 747#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 748#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 749#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 750#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 751#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 752#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 753#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 754#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 755#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 756#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 757#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 758#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 759#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 760#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 761#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 762#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 763#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 764#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 765#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 766#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 767#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 768#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 769#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 770//SDMA1_UTCL1_WR_STATUS 771#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 772#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 773#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 774#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 775#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 776#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 777#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 778#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 779#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 780#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 781#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 782#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 783#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 784#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 785#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 786#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 787#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 788#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 789#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 790#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 791#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 792#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 793#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 794#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 795#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 796#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 797#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 798#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 799#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 800#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 801#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 802#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 803#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 804#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 805#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 806#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 807#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 808#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 809#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 810#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 811#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 812#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 813#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 814#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 815#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 816#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 817#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 818#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 819#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 820#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 821#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 822#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 823#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 824#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 825#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 826#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 827//SDMA1_UTCL1_INV0 828#define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 829#define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 830#define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 831#define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 832#define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 833#define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 834#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 835#define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 836#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 837#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 838#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 839#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 840#define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 841#define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 842#define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 843#define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 844#define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 845#define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 846#define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 847#define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 848#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 849#define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 850#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 851#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 852#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 853#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 854#define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 855#define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 856//SDMA1_UTCL1_INV1 857#define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 858#define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 859//SDMA1_UTCL1_INV2 860#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 861#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 862//SDMA1_UTCL1_RD_XNACK0 863#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 864#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 865//SDMA1_UTCL1_RD_XNACK1 866#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 867#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 868#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 869#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 870#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 871#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 872#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 873#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 874//SDMA1_UTCL1_WR_XNACK0 875#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 876#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 877//SDMA1_UTCL1_WR_XNACK1 878#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 879#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 880#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 881#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 882#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 883#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 884#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 885#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 886//SDMA1_UTCL1_TIMEOUT 887#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 888#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 889#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 890#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 891//SDMA1_UTCL1_PAGE 892#define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 893#define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 894#define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 895#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 896#define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 897#define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 898#define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 899#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 900//SDMA1_POWER_CNTL_IDLE 901#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 902#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 903#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 904#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 905#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 906#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 907//SDMA1_RELAX_ORDERING_LUT 908#define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 909#define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 910#define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 911#define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 912#define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 913#define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 914#define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 915#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 916#define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 917#define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 918#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 919#define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 920#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 921#define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 922#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 923#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 924#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 925#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 926#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 927#define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 928#define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 929#define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 930#define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 931#define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 932#define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 933#define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 934#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 935#define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 936#define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 937#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 938#define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 939#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 940#define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 941#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 942#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 943#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 944#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 945#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 946//SDMA1_CHICKEN_BITS_2 947#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 948#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 949//SDMA1_STATUS3_REG 950#define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 951#define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 952#define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 953#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 954#define SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 955#define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 956#define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 957#define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 958#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 959#define SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 960//SDMA1_PHYSICAL_ADDR_LO 961#define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 962#define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 963#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 964#define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 965#define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 966#define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 967#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 968#define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 969//SDMA1_PHYSICAL_ADDR_HI 970#define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 971#define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 972//SDMA1_PHASE2_QUANTUM 973#define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0 974#define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8 975#define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 976#define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 977#define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 978#define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 979//SDMA1_ERROR_LOG 980#define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0 981#define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10 982#define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 983#define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L 984//SDMA1_PUB_DUMMY_REG0 985#define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 986#define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 987//SDMA1_PUB_DUMMY_REG1 988#define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 989#define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 990//SDMA1_PUB_DUMMY_REG2 991#define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 992#define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 993//SDMA1_PUB_DUMMY_REG3 994#define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 995#define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 996//SDMA1_F32_COUNTER 997#define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 998#define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 999//SDMA1_PERFMON_CNTL 1000#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1001#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1002#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1003#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 1004#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 1005#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 1006#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 1007#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 1008#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 1009#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 1010#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 1011#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 1012//SDMA1_PERFCOUNTER0_RESULT 1013#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1014#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1015//SDMA1_PERFCOUNTER1_RESULT 1016#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1017#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1018//SDMA1_PERFCOUNTER_TAG_DELAY_RANGE 1019#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1020#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1021#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1022#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1023#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1024#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1025//SDMA1_CRD_CNTL 1026#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1027#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1028#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1029#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1030//SDMA1_GPU_IOV_VIOLATION_LOG 1031#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1032#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1033#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1034#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 1035#define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1036#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 1037#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1038#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1039#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1040#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1041#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L 1042#define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1043#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 1044#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1045//SDMA1_ULV_CNTL 1046#define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1047#define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 1048#define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 1049#define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1050#define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1051#define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1052#define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1053#define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 1054#define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 1055#define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1056#define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1057#define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1058//SDMA1_EA_DBIT_ADDR_DATA 1059#define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1060#define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1061//SDMA1_EA_DBIT_ADDR_INDEX 1062#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1063#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1064//SDMA1_GFX_RB_CNTL 1065#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1066#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1067#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1068#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1069#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1070#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1071#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1072#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1073#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1074#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1075#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1076#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1077#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1078#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1079#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1080#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1081//SDMA1_GFX_RB_BASE 1082#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 1083#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1084//SDMA1_GFX_RB_BASE_HI 1085#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1086#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1087//SDMA1_GFX_RB_RPTR 1088#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1089#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1090//SDMA1_GFX_RB_RPTR_HI 1091#define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1092#define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1093//SDMA1_GFX_RB_WPTR 1094#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1095#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1096//SDMA1_GFX_RB_WPTR_HI 1097#define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1098#define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1099//SDMA1_GFX_RB_WPTR_POLL_CNTL 1100#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1101#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1102#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1103#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1104#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1105#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1106#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1107#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1108#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1109#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1110//SDMA1_GFX_RB_RPTR_ADDR_HI 1111#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1112#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1113//SDMA1_GFX_RB_RPTR_ADDR_LO 1114#define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1115#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1116#define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1117#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1118//SDMA1_GFX_IB_CNTL 1119#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1120#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1121#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1122#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1123#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1124#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1125#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1126#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1127//SDMA1_GFX_IB_RPTR 1128#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1129#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1130//SDMA1_GFX_IB_OFFSET 1131#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1132#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1133//SDMA1_GFX_IB_BASE_LO 1134#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1135#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1136//SDMA1_GFX_IB_BASE_HI 1137#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1138#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1139//SDMA1_GFX_IB_SIZE 1140#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 1141#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1142//SDMA1_GFX_SKIP_CNTL 1143#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1144#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1145//SDMA1_GFX_CONTEXT_STATUS 1146#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1147#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1148#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1149#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1150#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1151#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1152#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1153#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1154#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1155#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1156#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1157#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1158#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1159#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1160#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1161#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1162//SDMA1_GFX_DOORBELL 1163#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1164#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1165#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1166#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1167//SDMA1_GFX_CONTEXT_CNTL 1168#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1169#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1170//SDMA1_GFX_STATUS 1171#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1172#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1173#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1174#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1175//SDMA1_GFX_DOORBELL_LOG 1176#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1177#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1178#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1179#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1180//SDMA1_GFX_WATERMARK 1181#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1182#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1183#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1184#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1185//SDMA1_GFX_DOORBELL_OFFSET 1186#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1187#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1188//SDMA1_GFX_CSA_ADDR_LO 1189#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1190#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1191//SDMA1_GFX_CSA_ADDR_HI 1192#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1193#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1194//SDMA1_GFX_IB_SUB_REMAIN 1195#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1196#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1197//SDMA1_GFX_PREEMPT 1198#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1199#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1200//SDMA1_GFX_DUMMY_REG 1201#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1202#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1203//SDMA1_GFX_RB_WPTR_POLL_ADDR_HI 1204#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1205#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1206//SDMA1_GFX_RB_WPTR_POLL_ADDR_LO 1207#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1208#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1209//SDMA1_GFX_RB_AQL_CNTL 1210#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1211#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1212#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1213#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1214#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1215#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1216//SDMA1_GFX_MINOR_PTR_UPDATE 1217#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1218#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1219//SDMA1_GFX_MIDCMD_DATA0 1220#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1221#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1222//SDMA1_GFX_MIDCMD_DATA1 1223#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1224#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1225//SDMA1_GFX_MIDCMD_DATA2 1226#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1227#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1228//SDMA1_GFX_MIDCMD_DATA3 1229#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1230#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1231//SDMA1_GFX_MIDCMD_DATA4 1232#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1233#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1234//SDMA1_GFX_MIDCMD_DATA5 1235#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1236#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1237//SDMA1_GFX_MIDCMD_DATA6 1238#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1239#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1240//SDMA1_GFX_MIDCMD_DATA7 1241#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1242#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1243//SDMA1_GFX_MIDCMD_DATA8 1244#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1245#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1246//SDMA1_GFX_MIDCMD_CNTL 1247#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1248#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1249#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1250#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1251#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1252#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1253#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1254#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1255//SDMA1_PAGE_RB_CNTL 1256#define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1257#define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1258#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1259#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1260#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1261#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1262#define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1263#define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1264#define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1265#define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1266#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1267#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1268#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1269#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1270#define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1271#define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1272//SDMA1_PAGE_RB_BASE 1273#define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0 1274#define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1275//SDMA1_PAGE_RB_BASE_HI 1276#define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1277#define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1278//SDMA1_PAGE_RB_RPTR 1279#define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1280#define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1281//SDMA1_PAGE_RB_RPTR_HI 1282#define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1283#define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1284//SDMA1_PAGE_RB_WPTR 1285#define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1286#define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1287//SDMA1_PAGE_RB_WPTR_HI 1288#define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1289#define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1290//SDMA1_PAGE_RB_WPTR_POLL_CNTL 1291#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1292#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1293#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1294#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1295#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1296#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1297#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1298#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1299#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1300#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1301//SDMA1_PAGE_RB_RPTR_ADDR_HI 1302#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1303#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1304//SDMA1_PAGE_RB_RPTR_ADDR_LO 1305#define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1306#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1307#define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1308#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1309//SDMA1_PAGE_IB_CNTL 1310#define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1311#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1312#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1313#define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1314#define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1315#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1316#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1317#define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1318//SDMA1_PAGE_IB_RPTR 1319#define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1320#define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1321//SDMA1_PAGE_IB_OFFSET 1322#define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1323#define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1324//SDMA1_PAGE_IB_BASE_LO 1325#define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1326#define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1327//SDMA1_PAGE_IB_BASE_HI 1328#define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1329#define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1330//SDMA1_PAGE_IB_SIZE 1331#define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1332#define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1333//SDMA1_PAGE_SKIP_CNTL 1334#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1335#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1336//SDMA1_PAGE_CONTEXT_STATUS 1337#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1338#define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1339#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1340#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1341#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1342#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1343#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1344#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1345#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1346#define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1347#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1348#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1349#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1350#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1351#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1352#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1353//SDMA1_PAGE_DOORBELL 1354#define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1355#define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1356#define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1357#define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1358//SDMA1_PAGE_STATUS 1359#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1360#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1361#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1362#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1363//SDMA1_PAGE_DOORBELL_LOG 1364#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1365#define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1366#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1367#define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1368//SDMA1_PAGE_WATERMARK 1369#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1370#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1371#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1372#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1373//SDMA1_PAGE_DOORBELL_OFFSET 1374#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1375#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1376//SDMA1_PAGE_CSA_ADDR_LO 1377#define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1378#define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1379//SDMA1_PAGE_CSA_ADDR_HI 1380#define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1381#define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1382//SDMA1_PAGE_IB_SUB_REMAIN 1383#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1384#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1385//SDMA1_PAGE_PREEMPT 1386#define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1387#define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1388//SDMA1_PAGE_DUMMY_REG 1389#define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1390#define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1391//SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 1392#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1393#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1394//SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 1395#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1396#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1397//SDMA1_PAGE_RB_AQL_CNTL 1398#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1399#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1400#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1401#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1402#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1403#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1404//SDMA1_PAGE_MINOR_PTR_UPDATE 1405#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1406#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1407//SDMA1_PAGE_MIDCMD_DATA0 1408#define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1409#define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1410//SDMA1_PAGE_MIDCMD_DATA1 1411#define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1412#define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1413//SDMA1_PAGE_MIDCMD_DATA2 1414#define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1415#define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1416//SDMA1_PAGE_MIDCMD_DATA3 1417#define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1418#define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1419//SDMA1_PAGE_MIDCMD_DATA4 1420#define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1421#define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1422//SDMA1_PAGE_MIDCMD_DATA5 1423#define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1424#define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1425//SDMA1_PAGE_MIDCMD_DATA6 1426#define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1427#define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1428//SDMA1_PAGE_MIDCMD_DATA7 1429#define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1430#define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1431//SDMA1_PAGE_MIDCMD_DATA8 1432#define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1433#define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1434//SDMA1_PAGE_MIDCMD_CNTL 1435#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1436#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1437#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1438#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1439#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1440#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1441#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1442#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1443//SDMA1_RLC0_RB_CNTL 1444#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1445#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1446#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1447#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1448#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1449#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1450#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1451#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1452#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1453#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1454#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1455#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1456#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1457#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1458#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1459#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1460//SDMA1_RLC0_RB_BASE 1461#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 1462#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1463//SDMA1_RLC0_RB_BASE_HI 1464#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1465#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1466//SDMA1_RLC0_RB_RPTR 1467#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1468#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1469//SDMA1_RLC0_RB_RPTR_HI 1470#define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1471#define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1472//SDMA1_RLC0_RB_WPTR 1473#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1474#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1475//SDMA1_RLC0_RB_WPTR_HI 1476#define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1477#define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1478//SDMA1_RLC0_RB_WPTR_POLL_CNTL 1479#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1480#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1481#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1482#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1483#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1484#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1485#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1486#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1487#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1488#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1489//SDMA1_RLC0_RB_RPTR_ADDR_HI 1490#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1491#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1492//SDMA1_RLC0_RB_RPTR_ADDR_LO 1493#define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1494#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1495#define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1496#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1497//SDMA1_RLC0_IB_CNTL 1498#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1499#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1500#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1501#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1502#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1503#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1504#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1505#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1506//SDMA1_RLC0_IB_RPTR 1507#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1508#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1509//SDMA1_RLC0_IB_OFFSET 1510#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1511#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1512//SDMA1_RLC0_IB_BASE_LO 1513#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1514#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1515//SDMA1_RLC0_IB_BASE_HI 1516#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1517#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1518//SDMA1_RLC0_IB_SIZE 1519#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1520#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1521//SDMA1_RLC0_SKIP_CNTL 1522#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1523#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1524//SDMA1_RLC0_CONTEXT_STATUS 1525#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1526#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1527#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1528#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1529#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1530#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1531#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1532#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1533#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1534#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1535#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1536#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1537#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1538#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1539#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1540#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1541//SDMA1_RLC0_DOORBELL 1542#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1543#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1544#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1545#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1546//SDMA1_RLC0_STATUS 1547#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1548#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1549#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1550#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1551//SDMA1_RLC0_DOORBELL_LOG 1552#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1553#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1554#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1555#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1556//SDMA1_RLC0_WATERMARK 1557#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1558#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1559#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1560#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1561//SDMA1_RLC0_DOORBELL_OFFSET 1562#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1563#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1564//SDMA1_RLC0_CSA_ADDR_LO 1565#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1566#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1567//SDMA1_RLC0_CSA_ADDR_HI 1568#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1569#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1570//SDMA1_RLC0_IB_SUB_REMAIN 1571#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1572#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1573//SDMA1_RLC0_PREEMPT 1574#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1575#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1576//SDMA1_RLC0_DUMMY_REG 1577#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1578#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1579//SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 1580#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1581#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1582//SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 1583#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1584#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1585//SDMA1_RLC0_RB_AQL_CNTL 1586#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1587#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1588#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1589#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1590#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1591#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1592//SDMA1_RLC0_MINOR_PTR_UPDATE 1593#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1594#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1595//SDMA1_RLC0_MIDCMD_DATA0 1596#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1597#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1598//SDMA1_RLC0_MIDCMD_DATA1 1599#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1600#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1601//SDMA1_RLC0_MIDCMD_DATA2 1602#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1603#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1604//SDMA1_RLC0_MIDCMD_DATA3 1605#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1606#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1607//SDMA1_RLC0_MIDCMD_DATA4 1608#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1609#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1610//SDMA1_RLC0_MIDCMD_DATA5 1611#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1612#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1613//SDMA1_RLC0_MIDCMD_DATA6 1614#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1615#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1616//SDMA1_RLC0_MIDCMD_DATA7 1617#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1618#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1619//SDMA1_RLC0_MIDCMD_DATA8 1620#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1621#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1622//SDMA1_RLC0_MIDCMD_CNTL 1623#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1624#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1625#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1626#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1627#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1628#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1629#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1630#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1631//SDMA1_RLC1_RB_CNTL 1632#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1633#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1634#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1635#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1636#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1637#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1638#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1639#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1640#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1641#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1642#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1643#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1644#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1645#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1646#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1647#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1648//SDMA1_RLC1_RB_BASE 1649#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 1650#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1651//SDMA1_RLC1_RB_BASE_HI 1652#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1653#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1654//SDMA1_RLC1_RB_RPTR 1655#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1656#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1657//SDMA1_RLC1_RB_RPTR_HI 1658#define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1659#define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1660//SDMA1_RLC1_RB_WPTR 1661#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1662#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1663//SDMA1_RLC1_RB_WPTR_HI 1664#define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1665#define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1666//SDMA1_RLC1_RB_WPTR_POLL_CNTL 1667#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1668#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1669#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1670#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1671#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1672#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1673#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1674#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1675#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1676#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1677//SDMA1_RLC1_RB_RPTR_ADDR_HI 1678#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1679#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1680//SDMA1_RLC1_RB_RPTR_ADDR_LO 1681#define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1682#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1683#define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1684#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1685//SDMA1_RLC1_IB_CNTL 1686#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1687#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1688#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1689#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1690#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1691#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1692#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1693#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1694//SDMA1_RLC1_IB_RPTR 1695#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1696#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1697//SDMA1_RLC1_IB_OFFSET 1698#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1699#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1700//SDMA1_RLC1_IB_BASE_LO 1701#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1702#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1703//SDMA1_RLC1_IB_BASE_HI 1704#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1705#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1706//SDMA1_RLC1_IB_SIZE 1707#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1708#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1709//SDMA1_RLC1_SKIP_CNTL 1710#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1711#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1712//SDMA1_RLC1_CONTEXT_STATUS 1713#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1714#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1715#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1716#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1717#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1718#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1719#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1720#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1721#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1722#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1723#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1724#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1725#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1726#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1727#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1728#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1729//SDMA1_RLC1_DOORBELL 1730#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1731#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1732#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1733#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1734//SDMA1_RLC1_STATUS 1735#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1736#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1737#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1738#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1739//SDMA1_RLC1_DOORBELL_LOG 1740#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1741#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1742#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1743#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1744//SDMA1_RLC1_WATERMARK 1745#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1746#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1747#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1748#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1749//SDMA1_RLC1_DOORBELL_OFFSET 1750#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1751#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1752//SDMA1_RLC1_CSA_ADDR_LO 1753#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1754#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1755//SDMA1_RLC1_CSA_ADDR_HI 1756#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1757#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1758//SDMA1_RLC1_IB_SUB_REMAIN 1759#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1760#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1761//SDMA1_RLC1_PREEMPT 1762#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1763#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1764//SDMA1_RLC1_DUMMY_REG 1765#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1766#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1767//SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 1768#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1769#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1770//SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 1771#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1772#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1773//SDMA1_RLC1_RB_AQL_CNTL 1774#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1775#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1776#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1777#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1778#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1779#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1780//SDMA1_RLC1_MINOR_PTR_UPDATE 1781#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1782#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1783//SDMA1_RLC1_MIDCMD_DATA0 1784#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1785#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1786//SDMA1_RLC1_MIDCMD_DATA1 1787#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1788#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1789//SDMA1_RLC1_MIDCMD_DATA2 1790#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1791#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1792//SDMA1_RLC1_MIDCMD_DATA3 1793#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1794#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1795//SDMA1_RLC1_MIDCMD_DATA4 1796#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1797#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1798//SDMA1_RLC1_MIDCMD_DATA5 1799#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1800#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1801//SDMA1_RLC1_MIDCMD_DATA6 1802#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1803#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1804//SDMA1_RLC1_MIDCMD_DATA7 1805#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1806#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1807//SDMA1_RLC1_MIDCMD_DATA8 1808#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1809#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1810//SDMA1_RLC1_MIDCMD_CNTL 1811#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1812#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1813#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1814#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1815#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1816#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1817#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1818#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1819//SDMA1_RLC2_RB_CNTL 1820#define SDMA1_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 1821#define SDMA1_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 1822#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1823#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1824#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1825#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1826#define SDMA1_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 1827#define SDMA1_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 1828#define SDMA1_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1829#define SDMA1_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1830#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1831#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1832#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1833#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1834#define SDMA1_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L 1835#define SDMA1_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L 1836//SDMA1_RLC2_RB_BASE 1837#define SDMA1_RLC2_RB_BASE__ADDR__SHIFT 0x0 1838#define SDMA1_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1839//SDMA1_RLC2_RB_BASE_HI 1840#define SDMA1_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 1841#define SDMA1_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1842//SDMA1_RLC2_RB_RPTR 1843#define SDMA1_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 1844#define SDMA1_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1845//SDMA1_RLC2_RB_RPTR_HI 1846#define SDMA1_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 1847#define SDMA1_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1848//SDMA1_RLC2_RB_WPTR 1849#define SDMA1_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 1850#define SDMA1_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1851//SDMA1_RLC2_RB_WPTR_HI 1852#define SDMA1_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 1853#define SDMA1_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1854//SDMA1_RLC2_RB_WPTR_POLL_CNTL 1855#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1856#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1857#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1858#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1859#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1860#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1861#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1862#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1863#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1864#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1865//SDMA1_RLC2_RB_RPTR_ADDR_HI 1866#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1867#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1868//SDMA1_RLC2_RB_RPTR_ADDR_LO 1869#define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1870#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1871#define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1872#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1873//SDMA1_RLC2_IB_CNTL 1874#define SDMA1_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 1875#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1876#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1877#define SDMA1_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 1878#define SDMA1_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1879#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1880#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1881#define SDMA1_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1882//SDMA1_RLC2_IB_RPTR 1883#define SDMA1_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 1884#define SDMA1_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1885//SDMA1_RLC2_IB_OFFSET 1886#define SDMA1_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 1887#define SDMA1_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1888//SDMA1_RLC2_IB_BASE_LO 1889#define SDMA1_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 1890#define SDMA1_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1891//SDMA1_RLC2_IB_BASE_HI 1892#define SDMA1_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 1893#define SDMA1_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1894//SDMA1_RLC2_IB_SIZE 1895#define SDMA1_RLC2_IB_SIZE__SIZE__SHIFT 0x0 1896#define SDMA1_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL 1897//SDMA1_RLC2_SKIP_CNTL 1898#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1899#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1900//SDMA1_RLC2_CONTEXT_STATUS 1901#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1902#define SDMA1_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 1903#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1904#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1905#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1906#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1907#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1908#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1909#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1910#define SDMA1_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1911#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1912#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1913#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1914#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1915#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1916#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1917//SDMA1_RLC2_DOORBELL 1918#define SDMA1_RLC2_DOORBELL__ENABLE__SHIFT 0x1c 1919#define SDMA1_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e 1920#define SDMA1_RLC2_DOORBELL__ENABLE_MASK 0x10000000L 1921#define SDMA1_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L 1922//SDMA1_RLC2_STATUS 1923#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1924#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1925#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1926#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1927//SDMA1_RLC2_DOORBELL_LOG 1928#define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1929#define SDMA1_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 1930#define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1931#define SDMA1_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1932//SDMA1_RLC2_WATERMARK 1933#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1934#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1935#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1936#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1937//SDMA1_RLC2_DOORBELL_OFFSET 1938#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1939#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1940//SDMA1_RLC2_CSA_ADDR_LO 1941#define SDMA1_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 1942#define SDMA1_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1943//SDMA1_RLC2_CSA_ADDR_HI 1944#define SDMA1_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 1945#define SDMA1_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1946//SDMA1_RLC2_IB_SUB_REMAIN 1947#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1948#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1949//SDMA1_RLC2_PREEMPT 1950#define SDMA1_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 1951#define SDMA1_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1952//SDMA1_RLC2_DUMMY_REG 1953#define SDMA1_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 1954#define SDMA1_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1955//SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI 1956#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1957#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1958//SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO 1959#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1960#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1961//SDMA1_RLC2_RB_AQL_CNTL 1962#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1963#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1964#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1965#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1966#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1967#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1968//SDMA1_RLC2_MINOR_PTR_UPDATE 1969#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1970#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1971//SDMA1_RLC2_MIDCMD_DATA0 1972#define SDMA1_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 1973#define SDMA1_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1974//SDMA1_RLC2_MIDCMD_DATA1 1975#define SDMA1_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 1976#define SDMA1_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1977//SDMA1_RLC2_MIDCMD_DATA2 1978#define SDMA1_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 1979#define SDMA1_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1980//SDMA1_RLC2_MIDCMD_DATA3 1981#define SDMA1_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 1982#define SDMA1_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1983//SDMA1_RLC2_MIDCMD_DATA4 1984#define SDMA1_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 1985#define SDMA1_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1986//SDMA1_RLC2_MIDCMD_DATA5 1987#define SDMA1_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 1988#define SDMA1_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1989//SDMA1_RLC2_MIDCMD_DATA6 1990#define SDMA1_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 1991#define SDMA1_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1992//SDMA1_RLC2_MIDCMD_DATA7 1993#define SDMA1_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 1994#define SDMA1_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1995//SDMA1_RLC2_MIDCMD_DATA8 1996#define SDMA1_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 1997#define SDMA1_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1998//SDMA1_RLC2_MIDCMD_CNTL 1999#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2000#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2001#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2002#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2003#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2004#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2005#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2006#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2007//SDMA1_RLC3_RB_CNTL 2008#define SDMA1_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 2009#define SDMA1_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 2010#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2011#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2012#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2013#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2014#define SDMA1_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 2015#define SDMA1_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 2016#define SDMA1_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2017#define SDMA1_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2018#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2019#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2020#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2021#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2022#define SDMA1_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L 2023#define SDMA1_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L 2024//SDMA1_RLC3_RB_BASE 2025#define SDMA1_RLC3_RB_BASE__ADDR__SHIFT 0x0 2026#define SDMA1_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2027//SDMA1_RLC3_RB_BASE_HI 2028#define SDMA1_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 2029#define SDMA1_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2030//SDMA1_RLC3_RB_RPTR 2031#define SDMA1_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 2032#define SDMA1_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2033//SDMA1_RLC3_RB_RPTR_HI 2034#define SDMA1_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 2035#define SDMA1_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2036//SDMA1_RLC3_RB_WPTR 2037#define SDMA1_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 2038#define SDMA1_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2039//SDMA1_RLC3_RB_WPTR_HI 2040#define SDMA1_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 2041#define SDMA1_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2042//SDMA1_RLC3_RB_WPTR_POLL_CNTL 2043#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2044#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2045#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2046#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2047#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2048#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2049#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2050#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2051#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2052#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2053//SDMA1_RLC3_RB_RPTR_ADDR_HI 2054#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2055#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2056//SDMA1_RLC3_RB_RPTR_ADDR_LO 2057#define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2058#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2059#define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2060#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2061//SDMA1_RLC3_IB_CNTL 2062#define SDMA1_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 2063#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2064#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2065#define SDMA1_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 2066#define SDMA1_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2067#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2068#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2069#define SDMA1_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2070//SDMA1_RLC3_IB_RPTR 2071#define SDMA1_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 2072#define SDMA1_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2073//SDMA1_RLC3_IB_OFFSET 2074#define SDMA1_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 2075#define SDMA1_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2076//SDMA1_RLC3_IB_BASE_LO 2077#define SDMA1_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 2078#define SDMA1_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2079//SDMA1_RLC3_IB_BASE_HI 2080#define SDMA1_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 2081#define SDMA1_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2082//SDMA1_RLC3_IB_SIZE 2083#define SDMA1_RLC3_IB_SIZE__SIZE__SHIFT 0x0 2084#define SDMA1_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL 2085//SDMA1_RLC3_SKIP_CNTL 2086#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2087#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2088//SDMA1_RLC3_CONTEXT_STATUS 2089#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2090#define SDMA1_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 2091#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2092#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2093#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2094#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2095#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2096#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2097#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2098#define SDMA1_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2099#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2100#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2101#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2102#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2103#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2104#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2105//SDMA1_RLC3_DOORBELL 2106#define SDMA1_RLC3_DOORBELL__ENABLE__SHIFT 0x1c 2107#define SDMA1_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e 2108#define SDMA1_RLC3_DOORBELL__ENABLE_MASK 0x10000000L 2109#define SDMA1_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L 2110//SDMA1_RLC3_STATUS 2111#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2112#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2113#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2114#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2115//SDMA1_RLC3_DOORBELL_LOG 2116#define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2117#define SDMA1_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 2118#define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2119#define SDMA1_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2120//SDMA1_RLC3_WATERMARK 2121#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2122#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2123#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2124#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2125//SDMA1_RLC3_DOORBELL_OFFSET 2126#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2127#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2128//SDMA1_RLC3_CSA_ADDR_LO 2129#define SDMA1_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 2130#define SDMA1_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2131//SDMA1_RLC3_CSA_ADDR_HI 2132#define SDMA1_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 2133#define SDMA1_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2134//SDMA1_RLC3_IB_SUB_REMAIN 2135#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2136#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2137//SDMA1_RLC3_PREEMPT 2138#define SDMA1_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 2139#define SDMA1_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2140//SDMA1_RLC3_DUMMY_REG 2141#define SDMA1_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 2142#define SDMA1_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2143//SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI 2144#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2145#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2146//SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO 2147#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2148#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2149//SDMA1_RLC3_RB_AQL_CNTL 2150#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2151#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2152#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2153#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2154#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2155#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2156//SDMA1_RLC3_MINOR_PTR_UPDATE 2157#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2158#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2159//SDMA1_RLC3_MIDCMD_DATA0 2160#define SDMA1_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 2161#define SDMA1_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2162//SDMA1_RLC3_MIDCMD_DATA1 2163#define SDMA1_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 2164#define SDMA1_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2165//SDMA1_RLC3_MIDCMD_DATA2 2166#define SDMA1_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 2167#define SDMA1_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2168//SDMA1_RLC3_MIDCMD_DATA3 2169#define SDMA1_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 2170#define SDMA1_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2171//SDMA1_RLC3_MIDCMD_DATA4 2172#define SDMA1_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 2173#define SDMA1_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2174//SDMA1_RLC3_MIDCMD_DATA5 2175#define SDMA1_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 2176#define SDMA1_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2177//SDMA1_RLC3_MIDCMD_DATA6 2178#define SDMA1_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 2179#define SDMA1_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2180//SDMA1_RLC3_MIDCMD_DATA7 2181#define SDMA1_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 2182#define SDMA1_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2183//SDMA1_RLC3_MIDCMD_DATA8 2184#define SDMA1_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 2185#define SDMA1_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2186//SDMA1_RLC3_MIDCMD_CNTL 2187#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2188#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2189#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2190#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2191#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2192#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2193#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2194#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2195//SDMA1_RLC4_RB_CNTL 2196#define SDMA1_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 2197#define SDMA1_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 2198#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2199#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2200#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2201#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2202#define SDMA1_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 2203#define SDMA1_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 2204#define SDMA1_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2205#define SDMA1_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2206#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2207#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2208#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2209#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2210#define SDMA1_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L 2211#define SDMA1_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L 2212//SDMA1_RLC4_RB_BASE 2213#define SDMA1_RLC4_RB_BASE__ADDR__SHIFT 0x0 2214#define SDMA1_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2215//SDMA1_RLC4_RB_BASE_HI 2216#define SDMA1_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 2217#define SDMA1_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2218//SDMA1_RLC4_RB_RPTR 2219#define SDMA1_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 2220#define SDMA1_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2221//SDMA1_RLC4_RB_RPTR_HI 2222#define SDMA1_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 2223#define SDMA1_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2224//SDMA1_RLC4_RB_WPTR 2225#define SDMA1_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 2226#define SDMA1_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2227//SDMA1_RLC4_RB_WPTR_HI 2228#define SDMA1_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 2229#define SDMA1_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2230//SDMA1_RLC4_RB_WPTR_POLL_CNTL 2231#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2232#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2233#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2234#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2235#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2236#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2237#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2238#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2239#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2240#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2241//SDMA1_RLC4_RB_RPTR_ADDR_HI 2242#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2243#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2244//SDMA1_RLC4_RB_RPTR_ADDR_LO 2245#define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2246#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2247#define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2248#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2249//SDMA1_RLC4_IB_CNTL 2250#define SDMA1_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 2251#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2252#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2253#define SDMA1_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 2254#define SDMA1_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2255#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2256#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2257#define SDMA1_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2258//SDMA1_RLC4_IB_RPTR 2259#define SDMA1_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 2260#define SDMA1_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2261//SDMA1_RLC4_IB_OFFSET 2262#define SDMA1_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 2263#define SDMA1_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2264//SDMA1_RLC4_IB_BASE_LO 2265#define SDMA1_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 2266#define SDMA1_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2267//SDMA1_RLC4_IB_BASE_HI 2268#define SDMA1_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 2269#define SDMA1_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2270//SDMA1_RLC4_IB_SIZE 2271#define SDMA1_RLC4_IB_SIZE__SIZE__SHIFT 0x0 2272#define SDMA1_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL 2273//SDMA1_RLC4_SKIP_CNTL 2274#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2275#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2276//SDMA1_RLC4_CONTEXT_STATUS 2277#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2278#define SDMA1_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 2279#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2280#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2281#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2282#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2283#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2284#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2285#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2286#define SDMA1_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2287#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2288#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2289#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2290#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2291#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2292#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2293//SDMA1_RLC4_DOORBELL 2294#define SDMA1_RLC4_DOORBELL__ENABLE__SHIFT 0x1c 2295#define SDMA1_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e 2296#define SDMA1_RLC4_DOORBELL__ENABLE_MASK 0x10000000L 2297#define SDMA1_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L 2298//SDMA1_RLC4_STATUS 2299#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2300#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2301#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2302#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2303//SDMA1_RLC4_DOORBELL_LOG 2304#define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2305#define SDMA1_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 2306#define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2307#define SDMA1_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2308//SDMA1_RLC4_WATERMARK 2309#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2310#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2311#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2312#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2313//SDMA1_RLC4_DOORBELL_OFFSET 2314#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2315#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2316//SDMA1_RLC4_CSA_ADDR_LO 2317#define SDMA1_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 2318#define SDMA1_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2319//SDMA1_RLC4_CSA_ADDR_HI 2320#define SDMA1_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 2321#define SDMA1_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2322//SDMA1_RLC4_IB_SUB_REMAIN 2323#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2324#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2325//SDMA1_RLC4_PREEMPT 2326#define SDMA1_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 2327#define SDMA1_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2328//SDMA1_RLC4_DUMMY_REG 2329#define SDMA1_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 2330#define SDMA1_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2331//SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI 2332#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2333#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2334//SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO 2335#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2336#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2337//SDMA1_RLC4_RB_AQL_CNTL 2338#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2339#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2340#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2341#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2342#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2343#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2344//SDMA1_RLC4_MINOR_PTR_UPDATE 2345#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2346#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2347//SDMA1_RLC4_MIDCMD_DATA0 2348#define SDMA1_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 2349#define SDMA1_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2350//SDMA1_RLC4_MIDCMD_DATA1 2351#define SDMA1_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 2352#define SDMA1_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2353//SDMA1_RLC4_MIDCMD_DATA2 2354#define SDMA1_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 2355#define SDMA1_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2356//SDMA1_RLC4_MIDCMD_DATA3 2357#define SDMA1_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 2358#define SDMA1_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2359//SDMA1_RLC4_MIDCMD_DATA4 2360#define SDMA1_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 2361#define SDMA1_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2362//SDMA1_RLC4_MIDCMD_DATA5 2363#define SDMA1_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 2364#define SDMA1_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2365//SDMA1_RLC4_MIDCMD_DATA6 2366#define SDMA1_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 2367#define SDMA1_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2368//SDMA1_RLC4_MIDCMD_DATA7 2369#define SDMA1_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 2370#define SDMA1_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2371//SDMA1_RLC4_MIDCMD_DATA8 2372#define SDMA1_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 2373#define SDMA1_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2374//SDMA1_RLC4_MIDCMD_CNTL 2375#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2376#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2377#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2378#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2379#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2380#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2381#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2382#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2383//SDMA1_RLC5_RB_CNTL 2384#define SDMA1_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 2385#define SDMA1_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 2386#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2387#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2388#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2389#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2390#define SDMA1_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 2391#define SDMA1_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 2392#define SDMA1_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2393#define SDMA1_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2394#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2395#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2396#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2397#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2398#define SDMA1_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L 2399#define SDMA1_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L 2400//SDMA1_RLC5_RB_BASE 2401#define SDMA1_RLC5_RB_BASE__ADDR__SHIFT 0x0 2402#define SDMA1_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2403//SDMA1_RLC5_RB_BASE_HI 2404#define SDMA1_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 2405#define SDMA1_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2406//SDMA1_RLC5_RB_RPTR 2407#define SDMA1_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 2408#define SDMA1_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2409//SDMA1_RLC5_RB_RPTR_HI 2410#define SDMA1_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 2411#define SDMA1_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2412//SDMA1_RLC5_RB_WPTR 2413#define SDMA1_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 2414#define SDMA1_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2415//SDMA1_RLC5_RB_WPTR_HI 2416#define SDMA1_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 2417#define SDMA1_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2418//SDMA1_RLC5_RB_WPTR_POLL_CNTL 2419#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2420#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2421#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2422#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2423#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2424#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2425#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2426#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2427#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2428#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2429//SDMA1_RLC5_RB_RPTR_ADDR_HI 2430#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2431#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2432//SDMA1_RLC5_RB_RPTR_ADDR_LO 2433#define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2434#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2435#define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2436#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2437//SDMA1_RLC5_IB_CNTL 2438#define SDMA1_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 2439#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2440#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2441#define SDMA1_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 2442#define SDMA1_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2443#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2444#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2445#define SDMA1_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2446//SDMA1_RLC5_IB_RPTR 2447#define SDMA1_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 2448#define SDMA1_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2449//SDMA1_RLC5_IB_OFFSET 2450#define SDMA1_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 2451#define SDMA1_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2452//SDMA1_RLC5_IB_BASE_LO 2453#define SDMA1_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 2454#define SDMA1_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2455//SDMA1_RLC5_IB_BASE_HI 2456#define SDMA1_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 2457#define SDMA1_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2458//SDMA1_RLC5_IB_SIZE 2459#define SDMA1_RLC5_IB_SIZE__SIZE__SHIFT 0x0 2460#define SDMA1_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL 2461//SDMA1_RLC5_SKIP_CNTL 2462#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2463#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2464//SDMA1_RLC5_CONTEXT_STATUS 2465#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2466#define SDMA1_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 2467#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2468#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2469#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2470#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2471#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2472#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2473#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2474#define SDMA1_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2475#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2476#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2477#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2478#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2479#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2480#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2481//SDMA1_RLC5_DOORBELL 2482#define SDMA1_RLC5_DOORBELL__ENABLE__SHIFT 0x1c 2483#define SDMA1_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e 2484#define SDMA1_RLC5_DOORBELL__ENABLE_MASK 0x10000000L 2485#define SDMA1_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L 2486//SDMA1_RLC5_STATUS 2487#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2488#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2489#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2490#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2491//SDMA1_RLC5_DOORBELL_LOG 2492#define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2493#define SDMA1_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 2494#define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2495#define SDMA1_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2496//SDMA1_RLC5_WATERMARK 2497#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2498#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2499#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2500#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2501//SDMA1_RLC5_DOORBELL_OFFSET 2502#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2503#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2504//SDMA1_RLC5_CSA_ADDR_LO 2505#define SDMA1_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 2506#define SDMA1_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2507//SDMA1_RLC5_CSA_ADDR_HI 2508#define SDMA1_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 2509#define SDMA1_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2510//SDMA1_RLC5_IB_SUB_REMAIN 2511#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2512#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2513//SDMA1_RLC5_PREEMPT 2514#define SDMA1_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 2515#define SDMA1_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2516//SDMA1_RLC5_DUMMY_REG 2517#define SDMA1_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 2518#define SDMA1_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2519//SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI 2520#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2521#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2522//SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO 2523#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2524#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2525//SDMA1_RLC5_RB_AQL_CNTL 2526#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2527#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2528#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2529#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2530#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2531#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2532//SDMA1_RLC5_MINOR_PTR_UPDATE 2533#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2534#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2535//SDMA1_RLC5_MIDCMD_DATA0 2536#define SDMA1_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 2537#define SDMA1_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2538//SDMA1_RLC5_MIDCMD_DATA1 2539#define SDMA1_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 2540#define SDMA1_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2541//SDMA1_RLC5_MIDCMD_DATA2 2542#define SDMA1_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 2543#define SDMA1_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2544//SDMA1_RLC5_MIDCMD_DATA3 2545#define SDMA1_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 2546#define SDMA1_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2547//SDMA1_RLC5_MIDCMD_DATA4 2548#define SDMA1_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 2549#define SDMA1_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2550//SDMA1_RLC5_MIDCMD_DATA5 2551#define SDMA1_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 2552#define SDMA1_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2553//SDMA1_RLC5_MIDCMD_DATA6 2554#define SDMA1_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 2555#define SDMA1_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2556//SDMA1_RLC5_MIDCMD_DATA7 2557#define SDMA1_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 2558#define SDMA1_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2559//SDMA1_RLC5_MIDCMD_DATA8 2560#define SDMA1_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 2561#define SDMA1_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2562//SDMA1_RLC5_MIDCMD_CNTL 2563#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2564#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2565#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2566#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2567#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2568#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2569#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2570#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2571//SDMA1_RLC6_RB_CNTL 2572#define SDMA1_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 2573#define SDMA1_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 2574#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2575#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2576#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2577#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2578#define SDMA1_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 2579#define SDMA1_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 2580#define SDMA1_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2581#define SDMA1_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2582#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2583#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2584#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2585#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2586#define SDMA1_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L 2587#define SDMA1_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L 2588//SDMA1_RLC6_RB_BASE 2589#define SDMA1_RLC6_RB_BASE__ADDR__SHIFT 0x0 2590#define SDMA1_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2591//SDMA1_RLC6_RB_BASE_HI 2592#define SDMA1_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 2593#define SDMA1_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2594//SDMA1_RLC6_RB_RPTR 2595#define SDMA1_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 2596#define SDMA1_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2597//SDMA1_RLC6_RB_RPTR_HI 2598#define SDMA1_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 2599#define SDMA1_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2600//SDMA1_RLC6_RB_WPTR 2601#define SDMA1_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 2602#define SDMA1_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2603//SDMA1_RLC6_RB_WPTR_HI 2604#define SDMA1_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 2605#define SDMA1_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2606//SDMA1_RLC6_RB_WPTR_POLL_CNTL 2607#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2608#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2609#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2610#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2611#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2612#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2613#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2614#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2615#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2616#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2617//SDMA1_RLC6_RB_RPTR_ADDR_HI 2618#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2619#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2620//SDMA1_RLC6_RB_RPTR_ADDR_LO 2621#define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2622#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2623#define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2624#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2625//SDMA1_RLC6_IB_CNTL 2626#define SDMA1_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 2627#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2628#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2629#define SDMA1_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 2630#define SDMA1_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2631#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2632#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2633#define SDMA1_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2634//SDMA1_RLC6_IB_RPTR 2635#define SDMA1_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 2636#define SDMA1_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2637//SDMA1_RLC6_IB_OFFSET 2638#define SDMA1_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 2639#define SDMA1_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2640//SDMA1_RLC6_IB_BASE_LO 2641#define SDMA1_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 2642#define SDMA1_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2643//SDMA1_RLC6_IB_BASE_HI 2644#define SDMA1_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 2645#define SDMA1_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2646//SDMA1_RLC6_IB_SIZE 2647#define SDMA1_RLC6_IB_SIZE__SIZE__SHIFT 0x0 2648#define SDMA1_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL 2649//SDMA1_RLC6_SKIP_CNTL 2650#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2651#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2652//SDMA1_RLC6_CONTEXT_STATUS 2653#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2654#define SDMA1_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 2655#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2656#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2657#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2658#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2659#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2660#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2661#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2662#define SDMA1_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2663#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2664#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2665#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2666#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2667#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2668#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2669//SDMA1_RLC6_DOORBELL 2670#define SDMA1_RLC6_DOORBELL__ENABLE__SHIFT 0x1c 2671#define SDMA1_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e 2672#define SDMA1_RLC6_DOORBELL__ENABLE_MASK 0x10000000L 2673#define SDMA1_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L 2674//SDMA1_RLC6_STATUS 2675#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2676#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2677#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2678#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2679//SDMA1_RLC6_DOORBELL_LOG 2680#define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2681#define SDMA1_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 2682#define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2683#define SDMA1_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2684//SDMA1_RLC6_WATERMARK 2685#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2686#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2687#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2688#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2689//SDMA1_RLC6_DOORBELL_OFFSET 2690#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2691#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2692//SDMA1_RLC6_CSA_ADDR_LO 2693#define SDMA1_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 2694#define SDMA1_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2695//SDMA1_RLC6_CSA_ADDR_HI 2696#define SDMA1_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 2697#define SDMA1_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2698//SDMA1_RLC6_IB_SUB_REMAIN 2699#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2700#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2701//SDMA1_RLC6_PREEMPT 2702#define SDMA1_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 2703#define SDMA1_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2704//SDMA1_RLC6_DUMMY_REG 2705#define SDMA1_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 2706#define SDMA1_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2707//SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI 2708#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2709#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2710//SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO 2711#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2712#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2713//SDMA1_RLC6_RB_AQL_CNTL 2714#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2715#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2716#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2717#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2718#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2719#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2720//SDMA1_RLC6_MINOR_PTR_UPDATE 2721#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2722#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2723//SDMA1_RLC6_MIDCMD_DATA0 2724#define SDMA1_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 2725#define SDMA1_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2726//SDMA1_RLC6_MIDCMD_DATA1 2727#define SDMA1_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 2728#define SDMA1_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2729//SDMA1_RLC6_MIDCMD_DATA2 2730#define SDMA1_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 2731#define SDMA1_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2732//SDMA1_RLC6_MIDCMD_DATA3 2733#define SDMA1_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 2734#define SDMA1_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2735//SDMA1_RLC6_MIDCMD_DATA4 2736#define SDMA1_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 2737#define SDMA1_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2738//SDMA1_RLC6_MIDCMD_DATA5 2739#define SDMA1_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 2740#define SDMA1_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2741//SDMA1_RLC6_MIDCMD_DATA6 2742#define SDMA1_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 2743#define SDMA1_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2744//SDMA1_RLC6_MIDCMD_DATA7 2745#define SDMA1_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 2746#define SDMA1_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2747//SDMA1_RLC6_MIDCMD_DATA8 2748#define SDMA1_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 2749#define SDMA1_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2750//SDMA1_RLC6_MIDCMD_CNTL 2751#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2752#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2753#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2754#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2755#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2756#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2757#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2758#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2759//SDMA1_RLC7_RB_CNTL 2760#define SDMA1_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 2761#define SDMA1_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 2762#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2763#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2764#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2765#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2766#define SDMA1_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 2767#define SDMA1_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 2768#define SDMA1_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2769#define SDMA1_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2770#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2771#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2772#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2773#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2774#define SDMA1_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L 2775#define SDMA1_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L 2776//SDMA1_RLC7_RB_BASE 2777#define SDMA1_RLC7_RB_BASE__ADDR__SHIFT 0x0 2778#define SDMA1_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2779//SDMA1_RLC7_RB_BASE_HI 2780#define SDMA1_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 2781#define SDMA1_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2782//SDMA1_RLC7_RB_RPTR 2783#define SDMA1_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 2784#define SDMA1_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2785//SDMA1_RLC7_RB_RPTR_HI 2786#define SDMA1_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 2787#define SDMA1_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2788//SDMA1_RLC7_RB_WPTR 2789#define SDMA1_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 2790#define SDMA1_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2791//SDMA1_RLC7_RB_WPTR_HI 2792#define SDMA1_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 2793#define SDMA1_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2794//SDMA1_RLC7_RB_WPTR_POLL_CNTL 2795#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2796#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2797#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2798#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2799#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2800#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2801#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2802#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2803#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2804#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2805//SDMA1_RLC7_RB_RPTR_ADDR_HI 2806#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2807#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2808//SDMA1_RLC7_RB_RPTR_ADDR_LO 2809#define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2810#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2811#define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2812#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2813//SDMA1_RLC7_IB_CNTL 2814#define SDMA1_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 2815#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2816#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2817#define SDMA1_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 2818#define SDMA1_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2819#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2820#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2821#define SDMA1_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2822//SDMA1_RLC7_IB_RPTR 2823#define SDMA1_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 2824#define SDMA1_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2825//SDMA1_RLC7_IB_OFFSET 2826#define SDMA1_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 2827#define SDMA1_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2828//SDMA1_RLC7_IB_BASE_LO 2829#define SDMA1_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 2830#define SDMA1_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2831//SDMA1_RLC7_IB_BASE_HI 2832#define SDMA1_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 2833#define SDMA1_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2834//SDMA1_RLC7_IB_SIZE 2835#define SDMA1_RLC7_IB_SIZE__SIZE__SHIFT 0x0 2836#define SDMA1_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL 2837//SDMA1_RLC7_SKIP_CNTL 2838#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2839#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2840//SDMA1_RLC7_CONTEXT_STATUS 2841#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2842#define SDMA1_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 2843#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2844#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2845#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2846#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2847#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2848#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2849#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2850#define SDMA1_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2851#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2852#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2853#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2854#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2855#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2856#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2857//SDMA1_RLC7_DOORBELL 2858#define SDMA1_RLC7_DOORBELL__ENABLE__SHIFT 0x1c 2859#define SDMA1_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e 2860#define SDMA1_RLC7_DOORBELL__ENABLE_MASK 0x10000000L 2861#define SDMA1_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L 2862//SDMA1_RLC7_STATUS 2863#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2864#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2865#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2866#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2867//SDMA1_RLC7_DOORBELL_LOG 2868#define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2869#define SDMA1_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 2870#define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2871#define SDMA1_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2872//SDMA1_RLC7_WATERMARK 2873#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2874#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2875#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2876#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2877//SDMA1_RLC7_DOORBELL_OFFSET 2878#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2879#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2880//SDMA1_RLC7_CSA_ADDR_LO 2881#define SDMA1_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 2882#define SDMA1_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2883//SDMA1_RLC7_CSA_ADDR_HI 2884#define SDMA1_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 2885#define SDMA1_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2886//SDMA1_RLC7_IB_SUB_REMAIN 2887#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2888#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2889//SDMA1_RLC7_PREEMPT 2890#define SDMA1_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 2891#define SDMA1_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2892//SDMA1_RLC7_DUMMY_REG 2893#define SDMA1_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 2894#define SDMA1_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2895//SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI 2896#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2897#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2898//SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO 2899#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2900#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2901//SDMA1_RLC7_RB_AQL_CNTL 2902#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2903#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2904#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2905#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2906#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2907#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2908//SDMA1_RLC7_MINOR_PTR_UPDATE 2909#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2910#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2911//SDMA1_RLC7_MIDCMD_DATA0 2912#define SDMA1_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 2913#define SDMA1_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2914//SDMA1_RLC7_MIDCMD_DATA1 2915#define SDMA1_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 2916#define SDMA1_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2917//SDMA1_RLC7_MIDCMD_DATA2 2918#define SDMA1_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 2919#define SDMA1_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2920//SDMA1_RLC7_MIDCMD_DATA3 2921#define SDMA1_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 2922#define SDMA1_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2923//SDMA1_RLC7_MIDCMD_DATA4 2924#define SDMA1_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 2925#define SDMA1_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2926//SDMA1_RLC7_MIDCMD_DATA5 2927#define SDMA1_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 2928#define SDMA1_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2929//SDMA1_RLC7_MIDCMD_DATA6 2930#define SDMA1_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 2931#define SDMA1_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2932//SDMA1_RLC7_MIDCMD_DATA7 2933#define SDMA1_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 2934#define SDMA1_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2935//SDMA1_RLC7_MIDCMD_DATA8 2936#define SDMA1_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 2937#define SDMA1_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2938//SDMA1_RLC7_MIDCMD_CNTL 2939#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2940#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2941#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2942#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2943#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2944#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2945#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2946#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2947 2948#endif
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